1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2022 Scott Long 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Thunderbolt3/USB4 config space register definitions 29 */ 30 31 #ifndef _TBCFG_REG_H 32 #define _TBCFG_REG_H 33 34 /* Config space read request, 6.4.2.3 */ 35 struct tb_cfg_read { 36 tb_route_t route; 37 uint32_t addr_attrs; 38 #define TB_CFG_ADDR_SHIFT 0 39 #define TB_CFG_ADDR_MASK GENMASK(12,0) 40 #define TB_CFG_SIZE_SHIFT 13 41 #define TB_CFG_SIZE_MASK GENMASK(18,13) 42 #define TB_CFG_ADAPTER_SHIFT 19 43 #define TB_CFG_ADAPTER_MASK GENMASK(24,19) 44 #define TB_CFG_CS_PATH (0x00 << 25) 45 #define TB_CFG_CS_ADAPTER (0x01 << 25) 46 #define TB_CFG_CS_ROUTER (0x02 << 25) 47 #define TB_CFG_CS_COUNTERS (0x03 << 25) 48 #define TB_CFG_SEQ_SHIFT 27 49 #define TB_CFG_SEQ_MASK (28,27) 50 uint32_t crc; 51 }; 52 53 /* Config space read response, 6.4.2.4 */ 54 struct tb_cfg_read_resp { 55 tb_route_t route; 56 uint32_t addr_attrs; 57 uint32_t data[0]; /* Up to 60 dwords */ 58 /* uint32_t crc is at the end */ 59 } __packed; 60 61 /* Config space write request, 6.4.2.5 */ 62 struct tb_cfg_write { 63 tb_route_t route; 64 uint32_t addr_attrs; 65 uint32_t data[0]; /* Up to 60 dwords */ 66 /* uint32_t crc is at the end */ 67 } __packed; 68 69 /* Config space write response, 6.4.2.6 */ 70 struct tb_cfg_write_resp { 71 tb_route_t route; 72 uint32_t addr_attrs; 73 uint32_t crc; 74 } __packed; 75 76 /* Config space event, 6.4.2.7 */ 77 struct tb_cfg_notify { 78 tb_route_t route; 79 uint32_t event_adap; 80 #define TB_CFG_EVENT_MASK GENMASK(7,0) 81 #define GET_NOTIFY_EVENT(n) ((n)->event_adap & TB_CFG_EVENT_MASK) 82 #define TB_CFG_ERR_CONN 0x00 83 #define TB_CFG_ERR_LINK 0x01 84 #define TB_CFG_ERR_ADDR 0x02 85 #define TB_CFG_ERR_ADP 0x04 86 #define TB_CFG_ERR_ENUM 0x08 87 #define TB_CFG_ERR_NUA 0x09 88 #define TB_CFG_ERR_LEN 0x0b 89 #define TB_CFG_ERR_HEC 0x0c 90 #define TB_CFG_ERR_FC 0x0d 91 #define TB_CFG_ERR_PLUG 0x0e 92 #define TB_CFG_ERR_LOCK 0x0f 93 #define TB_CFG_HP_ACK 0x07 94 #define TB_CFG_DP_BW 0x20 95 #define TB_CFG_EVENT_ADAPTER_SHIFT 8 96 #define TB_CFG_EVENT_ADAPTER_MASK GENMASK(13,8) 97 #define GET_NOTIFY_ADAPTER(n) (((n)->event_adap & \ 98 TB_CFG_EVENT_ADAPTER_MASK) >> \ 99 TB_CFG_EVENT_ADAPTER_SHIFT) 100 #define TB_CFG_PG_NONE 0x00000000 101 #define TB_CFG_PG_PLUG 0x80000000 102 #define TB_CFG_PG_UNPLUG 0xc0000000 103 uint32_t crc; 104 } __packed; 105 106 /* Config space event acknowledgement, 6.4.2.8 */ 107 struct tb_cfg_notify_ack { 108 tb_route_t route; 109 uint32_t crc; 110 } __packed; 111 112 /* Config space hot plug event, 6.4.2.10 */ 113 struct tb_cfg_hotplug { 114 tb_route_t route; 115 uint32_t adapter_attrs; 116 #define TB_CFG_ADPT_MASK GENMASK(5,0) 117 #define TB_CFG_UPG_PLUG (0x0 << 31) 118 #define TB_CFG_UPG_UNPLUG (0x1 << 31) 119 uint32_t crc; 120 } __packed; 121 122 /* Config space inter-domain request, 6.4.2.11 */ 123 struct tb_cfg_xdomain { 124 tb_route_t route; 125 uint32_t data[0]; 126 /* uint32_t crc is at the end */ 127 } __packed; 128 129 /* Config space inter-domain response, 6.4.2.12 */ 130 struct tb_cfg_xdomain_resp { 131 tb_route_t route; 132 uint32_t data[0]; 133 /* uint32_t crc is at the end */ 134 } __packed; 135 136 /* Config space router basic registers 8.2.1.1 */ 137 struct tb_cfg_router { 138 uint16_t vendor_id; /* ROUTER_CS_0 */ 139 uint16_t product_id; 140 uint32_t router_cs_1; /* ROUTER_CS_1 */ 141 #define ROUTER_CS1_NEXT_CAP_MASK GENMASK(7,0) 142 #define GET_ROUTER_CS_NEXT_CAP(r) (r->router_cs_1 & \ 143 ROUTER_CS1_NEXT_CAP_MASK) 144 #define ROUTER_CS1_UPSTREAM_SHIFT 8 145 #define ROUTER_CS1_UPSTREAM_MASK GENMASK(13,8) 146 #define GET_ROUTER_CS_UPSTREAM_ADAP(r) ((r->router_cs_1 & \ 147 ROUTER_CS1_UPSTREAM_MASK) >> \ 148 ROUTER_CS1_UPSTREAM_SHIFT) 149 #define ROUTER_CS1_MAX_SHIFT 14 150 #define ROUTER_CS1_MAX_MASK GENMASK(19,14) 151 #define GET_ROUTER_CS_MAX_ADAP(r) ((r->router_cs_1 & \ 152 ROUTER_CS1_MAX_MASK) >> \ 153 ROUTER_CS1_MAX_SHIFT) 154 #define ROUTER_CS1_MAX_ADAPTERS 64 155 #define ROUTER_CS1_DEPTH_SHIFT 20 156 #define ROUTER_CS1_DEPTH_MASK GENMASK(22,20) 157 #define GET_ROUTER_CS_DEPTH(r) ((r->router_cs_1 & \ 158 ROUTER_CS1_DEPTH_MASK) >> \ 159 ROUTER_CS1_DEPTH_SHIFT) 160 #define ROUTER_CS1_REVISION_SHIFT 24 161 #define ROUTER_CS1_REVISION_MASK GENMASK(31,24) 162 #define GET_ROUTER_CS_REVISION ((r->router_cs_1 & \ 163 ROUTER_CS1_REVISION_MASK) >> \ 164 ROUTER_CS1_REVISION_SHIFT) 165 uint32_t topology_lo; /* ROUTER_CS_2 */ 166 uint32_t topology_hi; /* ROUTER_CS_3 */ 167 #define CFG_TOPOLOGY_VALID (1 << 31) 168 uint8_t notification_timeout; /* ROUTER_CS_4 */ 169 uint8_t cm_version; 170 #define CFG_CM_USB4 0x10 171 uint8_t rsrvd1; 172 uint8_t usb4_version; 173 #define CFG_USB4_V1_0 0x10 174 uint32_t flags_cs5; /* ROUTER_CS_5 */ 175 #define CFG_CS5_SLP (1 << 0) 176 #define CFG_CS5_WOP (1 << 1) 177 #define CFG_CS5_WOU (1 << 2) 178 #define CFG_CS5_DP (1 << 3) 179 #define CFG_CS5_C3S (1 << 23) 180 #define CFG_CS5_PTO (1 << 24) 181 #define CFG_CS5_UTO (1 << 25) 182 #define CFG_CS5_HCO (1 << 26) 183 #define CFG_CS5_CV (1 << 31) 184 uint32_t flags_cs6; /* ROUTER_CS_6 */ 185 #define CFG_CS6_SLPR (1 << 0) 186 #define CFG_CS6_TNS (1 << 1) 187 #define CFG_CS6_WAKE_PCIE (1 << 2) 188 #define CFG_CS6_WAKE_USB3 (1 << 3) 189 #define CFG_CS6_WAKE_DP (1 << 4) 190 #define CFG_CS6_HCI (1 << 18) 191 #define CFG_CS6_RR (1 << 24) 192 #define CFG_CS6_CR (1 << 25) 193 uint32_t uuid_hi; /* ROUTER_CS_7 */ 194 uint32_t uuid_lo; /* ROUTER_CS_8 */ 195 uint32_t data[16]; /* ROUTER_CS_9-24 */ 196 uint32_t metadata; /* ROUTER_CS_25 */ 197 uint32_t opcode_status; /* ROUTER_CS_26 */ 198 /* TBD: Opcodes and status */ 199 #define CFG_ONS (1 << 30) 200 #define CFG_OV (1 << 31) 201 } __packed; 202 203 #define TB_CFG_CAP_OFFSET_MAX 0xfff 204 205 /* Config space router capability header 8.2.1.3/8.2.1.4 */ 206 struct tb_cfg_cap_hdr { 207 uint8_t next_cap; 208 uint8_t cap_id; 209 } __packed; 210 211 /* Config space router TMU registers 8.2.1.2 */ 212 struct tb_cfg_cap_tmu { 213 struct tb_cfg_cap_hdr hdr; 214 #define TB_CFG_CAP_TMU 0x03 215 } __packed; 216 217 struct tb_cfg_vsc_cap { 218 struct tb_cfg_cap_hdr hdr; 219 #define TB_CFG_CAP_VSC 0x05 220 uint8_t vsc_id; 221 uint8_t len; 222 } __packed; 223 224 struct tb_cfg_vsec_cap { 225 struct tb_cfg_cap_hdr hdr; 226 #define TB_CFG_CAP_VSEC 0x05 227 uint8_t vsec_id; 228 uint8_t len; 229 uint16_t vsec_next_cap; 230 uint16_t vsec_len; 231 } __packed; 232 233 union tb_cfg_cap { 234 struct tb_cfg_cap_hdr hdr; 235 struct tb_cfg_cap_tmu tmu; 236 struct tb_cfg_vsc_cap vsc; 237 struct tb_cfg_vsec_cap vsec; 238 } __packed; 239 240 #define TB_CFG_VSC_PLUG 0x01 /* Hot Plug and DROM */ 241 242 #define TB_CFG_VSEC_LC 0x06 /* Link Controller */ 243 #define TB_LC_DESC 0x02 /* LC Descriptor fields */ 244 #define TB_LC_DESC_NUM_LC_MASK GENMASK(3, 0) 245 #define TB_LC_DESC_SIZE_SHIFT 8 246 #define TB_LC_DESC_SIZE_MASK GENMASK(15, 8) 247 #define TB_LC_DESC_PORT_SHIFT 16 248 #define TB_LC_DESC_PORT_MASK GENMASK(27, 16) 249 #define TB_LC_UUID 0x03 250 #define TB_LC_DP_SINK 0x10 /* Display Port config */ 251 #define TB_LC_PORT_ATTR 0x8d /* Port attributes */ 252 #define TB_LC_PORT_ATTR_BE (1 << 12) /* Bonding enabled */ 253 #define TB_LC_SX_CTRL 0x96 /* Sleep control */ 254 #define TB_LC_SX_CTRL_WOC (1 << 1) 255 #define TB_LC_SX_CTRL_WOD (1 << 2) 256 #define TB_LC_SX_CTRL_WOU4 (1 << 5) 257 #define TB_LC_SX_CTRL_WOP (1 << 6) 258 #define TB_LC_SX_CTRL_L1C (1 << 16) 259 #define TB_LC_SX_CTRL_L1D (1 << 17) 260 #define TB_LC_SX_CTRL_L2C (1 << 20) 261 #define TB_LC_SX_CTRL_L2D (1 << 21) 262 #define TB_LC_SX_CTRL_UFP (1 << 30) 263 #define TB_LC_SX_CTRL_SLP (1 << 31) 264 #define TB_LC_POWER 0x740 265 266 /* Config space adapter basic registers 8.2.2.1 */ 267 struct tb_cfg_adapter { 268 uint16_t vendor_id; /* ADP CS0 */ 269 uint16_t product_id; 270 uint32_t adp_cs1; /* ADP CS1 */ 271 #define ADP_CS1_NEXT_CAP_MASK GENMASK(7,0) 272 #define GET_ADP_CS_NEXT_CAP(a) (a->adp_cs1 & \ 273 ADP_CS1_NEXT_CAP_MASK) 274 #define ADP_CS1_COUNTER_SHIFT 8 275 #define ADP_CS1_COUNTER_MASK GENMASK(18,8) 276 #define GET_ADP_CS_MAX_COUNTERS(a) ((a->adp_cs1 & \ 277 ADP_CS1_COUNTER_MASK) >> \ 278 ADP_CS1_COUNTER_SHIFT) 279 #define CFG_COUNTER_CONFIG_FLAG (1 << 19) 280 uint32_t adp_cs2; /* ADP CS2 */ 281 #define ADP_CS2_TYPE_MASK GENMASK(23,0) 282 #define GET_ADP_CS_TYPE(a) (a->adp_cs2 & ADP_CS2_TYPE_MASK) 283 #define ADP_CS2_UNSUPPORTED 0x000000 284 #define ADP_CS2_LANE 0x000001 285 #define ADP_CS2_HOSTIF 0x000002 286 #define ADP_CS2_PCIE_DFP 0x100101 287 #define ADP_CS2_PCIE_UFP 0x100102 288 #define ADP_CS2_DP_OUT 0x0e0102 289 #define ADP_CS2_DP_IN 0x0e0101 290 #define ADP_CS2_USB3_DFP 0x200101 291 #define ADP_CS2_USB3_UFP 0x200102 292 uint32_t adp_cs3; /* ADP CS 3 */ 293 #define ADP_CS3_ADP_NUM_SHIFT 20 294 #define ADP_CS3_ADP_NUM_MASK GENMASK(25,20) 295 #define GET_ADP_CS_ADP_NUM(a) ((a->adp_cs3 & \ 296 ADP_CS3_ADP_NUM_MASK) >> \ 297 ADP_CS3_ADP_NUM_SHIFT) 298 #define CFG_ADP_HEC_ERROR (1 << 29) 299 #define CFG_ADP_FC_ERROR (1 << 30) 300 #define CFG_ADP_SBC (1 << 31) 301 } __packed; 302 303 /* Config space lane adapter capability 8.2.2.3 */ 304 struct tb_cfg_cap_lane { 305 struct tb_cfg_cap_hdr hdr; /* LANE_ADP_CS_0 */ 306 #define TB_CFG_CAP_LANE 0x01 307 /* Supported link/width/power */ 308 uint16_t supp_lwp; 309 #define CAP_LANE_LINK_MASK GENMASK(3,0) 310 #define CAP_LANE_LINK_GEN3 0x0004 311 #define CAP_LANE_LINK_GEN2 0x0008 312 #define CAP_LANE_WIDTH_MASK GENMASK(9,4) 313 #define CAP_LANE_WIDTH_1X 0x0010 314 #define CAP_LANE_WIDTH_2X 0x0020 315 #define CAP_LANE_POWER_CL0 0x0400 316 #define CAP_LANE_POWER_CL1 0x0800 317 #define CAP_LANE_POWER_CL2 0x1000 318 /* Target link/width/power */ 319 uint16_t targ_lwp; /* LANE_ADP_CS_1 */ 320 #define CAP_LANE_TARGET_GEN2 0x0008 321 #define CAP_LANE_TARGET_GEN3 0x000c 322 #define CAP_LANE_TARGET_SINGLE 0x0010 323 #define CAP_LANE_TARGET_DUAL 0x0030 324 #define CAP_LANE_DISABLE 0x4000 325 #define CAP_LANE_BONDING 0x8000 326 /* Current link/width/state */ 327 uint16_t current_lws; 328 /* Same definitions a supp_lwp for bits 0 - 9 */ 329 #define CAP_LANE_STATE_SHIFT 10 330 #define CAP_LANE_STATE_MASK GENMASK(13,10) 331 #define CAP_LANE_STATE_DISABLE (0x0 << CAP_LANE_STATE_SHIFT) 332 #define CAP_LANE_STATE_TRAINING (0x1 << CAP_LANE_STATE_SHIFT) 333 #define CAP_LANE_STATE_CL0 (0x2 << CAP_LANE_STATE_SHIFT) 334 #define CAP_LANE_STATE_TXCL0 (0x3 << CAP_LANE_STATE_SHIFT) 335 #define CAP_LANE_STATE_RXCL0 (0x4 << CAP_LANE_STATE_SHIFT) 336 #define CAP_LANE_STATE_CL1 (0x5 << CAP_LANE_STATE_SHIFT) 337 #define CAP_LANE_STATE_CL2 (0x6 << CAP_LANE_STATE_SHIFT) 338 #define CAP_LANE_STATE_CLD (0x7 << CAP_LANE_STATE_SHIFT) 339 #define CAP_LANE_PMS 0x4000 340 /* Logical Layer Errors */ 341 uint16_t lle; /* LANE_ADP_CS_2 */ 342 #define CAP_LANE_LLE_MASK GENMASK(6,0) 343 #define CAP_LANE_LLE_ALE 0x01 344 #define CAP_LANE_LLE_OSE 0x02 345 #define CAP_LANE_LLE_TE 0x04 346 #define CAP_LANE_LLE_EBE 0x08 347 #define CAP_LANE_LLE_DBE 0x10 348 #define CAP_LANE_LLE_RDE 0x20 349 #define CAP_LANE_LLE_RST 0x40 350 uint16_t lle_enable; 351 } __packed; 352 353 /* Config space path registers 8.2.3.1 */ 354 struct tb_cfg_path { 355 } __packed; 356 357 /* Config space counter registers 8.2.4 */ 358 struct tb_cfg_counters { 359 } __packed; 360 361 #endif /* _TBCFG_REG_H */ 362