1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2022 Scott Long 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_thunderbolt.h" 30 31 /* PCIe interface for Thunderbolt Native Host Interface (nhi) */ 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/conf.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/sysctl.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/taskqueue.h> 45 #include <sys/gsb_crc32.h> 46 #include <sys/endian.h> 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 50 #include <machine/bus.h> 51 #include <machine/stdarg.h> 52 53 #include <dev/thunderbolt/nhi_reg.h> 54 #include <dev/thunderbolt/nhi_var.h> 55 #include <dev/thunderbolt/tb_reg.h> 56 #include <dev/thunderbolt/tb_var.h> 57 #include <dev/thunderbolt/tb_debug.h> 58 #include <dev/thunderbolt/hcm_var.h> 59 #include <dev/thunderbolt/tbcfg_reg.h> 60 #include <dev/thunderbolt/router_var.h> 61 #include <dev/thunderbolt/tb_dev.h> 62 #include "tb_if.h" 63 64 static int nhi_alloc_ring(struct nhi_softc *, int, int, int, 65 struct nhi_ring_pair **); 66 static void nhi_free_ring(struct nhi_ring_pair *); 67 static void nhi_free_rings(struct nhi_softc *); 68 static int nhi_configure_ring(struct nhi_softc *, struct nhi_ring_pair *); 69 static int nhi_activate_ring(struct nhi_ring_pair *); 70 static int nhi_deactivate_ring(struct nhi_ring_pair *); 71 static int nhi_alloc_ring0(struct nhi_softc *); 72 static void nhi_free_ring0(struct nhi_softc *); 73 static void nhi_fill_rx_ring(struct nhi_softc *, struct nhi_ring_pair *); 74 static int nhi_init(struct nhi_softc *); 75 static void nhi_post_init(void *); 76 static int nhi_tx_enqueue(struct nhi_ring_pair *, struct nhi_cmd_frame *); 77 static int nhi_setup_sysctl(struct nhi_softc *); 78 79 SYSCTL_NODE(_hw, OID_AUTO, nhi, CTLFLAG_RD, 0, "NHI Driver Parameters"); 80 81 MALLOC_DEFINE(M_NHI, "nhi", "nhi driver memory"); 82 83 #ifndef NHI_DEBUG_LEVEL 84 #define NHI_DEBUG_LEVEL 0 85 #endif 86 87 /* 0 = default, 1 = force-on, 2 = force-off */ 88 #ifndef NHI_FORCE_HCM 89 #define NHI_FORCE_HCM 0 90 #endif 91 92 void 93 nhi_get_tunables(struct nhi_softc *sc) 94 { 95 devclass_t dc; 96 device_t ufp; 97 char tmpstr[80], oid[80]; 98 u_int val; 99 100 /* Set local defaults */ 101 sc->debug = NHI_DEBUG_LEVEL; 102 sc->max_ring_count = NHI_DEFAULT_NUM_RINGS; 103 sc->force_hcm = NHI_FORCE_HCM; 104 105 /* Inherit setting from the upstream thunderbolt switch node */ 106 val = TB_GET_DEBUG(sc->dev, &sc->debug); 107 if (val != 0) { 108 dc = devclass_find("tbolt"); 109 if (dc != NULL) { 110 ufp = devclass_get_device(dc, device_get_unit(sc->dev)); 111 if (ufp != NULL) 112 TB_GET_DEBUG(ufp, &sc->debug); 113 } else { 114 if (TUNABLE_STR_FETCH("hw.tbolt.debug_level", oid, 115 80) != 0) 116 tb_parse_debug(&sc->debug, oid); 117 } 118 } 119 120 /* 121 * Grab global variables. Allow nhi debug flags to override 122 * thunderbolt debug flags, if present. 123 */ 124 bzero(oid, 80); 125 if (TUNABLE_STR_FETCH("hw.nhi.debug_level", oid, 80) != 0) 126 tb_parse_debug(&sc->debug, oid); 127 if (TUNABLE_INT_FETCH("hw.nhi.max_rings", &val) != 0) { 128 val = min(val, NHI_MAX_NUM_RINGS); 129 sc->max_ring_count = max(val, 1); 130 } 131 if (TUNABLE_INT_FETCH("hw.nhi.force_hcm", &val) != 0) 132 sc->force_hcm = val; 133 134 /* Grab instance variables */ 135 bzero(oid, 80); 136 snprintf(tmpstr, sizeof(tmpstr), "dev.nhi.%d.debug_level", 137 device_get_unit(sc->dev)); 138 if (TUNABLE_STR_FETCH(tmpstr, oid, 80) != 0) 139 tb_parse_debug(&sc->debug, oid); 140 snprintf(tmpstr, sizeof(tmpstr), "dev.nhi.%d.max_rings", 141 device_get_unit(sc->dev)); 142 if (TUNABLE_INT_FETCH(tmpstr, &val) != 0) { 143 val = min(val, NHI_MAX_NUM_RINGS); 144 sc->max_ring_count = max(val, 1); 145 } 146 snprintf(tmpstr, sizeof(tmpstr), "dev, nhi.%d.force_hcm", 147 device_get_unit(sc->dev)); 148 if (TUNABLE_INT_FETCH(tmpstr, &val) != 0) 149 sc->force_hcm = val; 150 151 return; 152 } 153 154 static void 155 nhi_configure_caps(struct nhi_softc *sc) 156 { 157 158 if (NHI_IS_USB4(sc) || (sc->force_hcm == NHI_FORCE_HCM_ON)) 159 sc->caps |= NHI_CAP_HCM; 160 if (sc->force_hcm == NHI_FORCE_HCM_OFF) 161 sc->caps &= ~NHI_CAP_HCM; 162 } 163 164 struct nhi_cmd_frame * 165 nhi_alloc_tx_frame(struct nhi_ring_pair *r) 166 { 167 struct nhi_cmd_frame *cmd; 168 169 mtx_lock(&r->mtx); 170 cmd = nhi_alloc_tx_frame_locked(r); 171 mtx_unlock(&r->mtx); 172 173 return (cmd); 174 } 175 176 void 177 nhi_free_tx_frame(struct nhi_ring_pair *r, struct nhi_cmd_frame *cmd) 178 { 179 mtx_lock(&r->mtx); 180 nhi_free_tx_frame_locked(r, cmd); 181 mtx_unlock(&r->mtx); 182 } 183 184 /* 185 * Push a command and data dword through the mailbox to the firmware. 186 * Response is either good, error, or timeout. Commands that return data 187 * do so by reading OUTMAILDATA. 188 */ 189 int 190 nhi_inmail_cmd(struct nhi_softc *sc, uint32_t cmd, uint32_t data) 191 { 192 uint32_t val; 193 u_int error, timeout; 194 195 mtx_lock(&sc->nhi_mtx); 196 /* 197 * XXX Should a defer/reschedule happen here, or is it not worth 198 * worrying about? 199 */ 200 if (sc->hwflags & NHI_MBOX_BUSY) { 201 mtx_unlock(&sc->nhi_mtx); 202 tb_debug(sc, DBG_MBOX, "Driver busy with mailbox\n"); 203 return (EBUSY); 204 } 205 sc->hwflags |= NHI_MBOX_BUSY; 206 207 val = nhi_read_reg(sc, TBT_INMAILCMD); 208 tb_debug(sc, DBG_MBOX|DBG_FULL, "Reading INMAILCMD= 0x%08x\n", val); 209 if (val & INMAILCMD_ERROR) 210 tb_debug(sc, DBG_MBOX, "Error already set in INMAILCMD\n"); 211 if (val & INMAILCMD_OPREQ) { 212 mtx_unlock(&sc->nhi_mtx); 213 tb_debug(sc, DBG_MBOX, 214 "INMAILCMD request already in progress\n"); 215 return (EBUSY); 216 } 217 218 nhi_write_reg(sc, TBT_INMAILDATA, data); 219 nhi_write_reg(sc, TBT_INMAILCMD, cmd | INMAILCMD_OPREQ); 220 221 /* Poll at 1s intervals */ 222 timeout = NHI_MAILBOX_TIMEOUT; 223 while (timeout--) { 224 DELAY(1000000); 225 val = nhi_read_reg(sc, TBT_INMAILCMD); 226 tb_debug(sc, DBG_MBOX|DBG_EXTRA, 227 "Polling INMAILCMD= 0x%08x\n", val); 228 if ((val & INMAILCMD_OPREQ) == 0) 229 break; 230 } 231 sc->hwflags &= ~NHI_MBOX_BUSY; 232 mtx_unlock(&sc->nhi_mtx); 233 234 error = 0; 235 if (val & INMAILCMD_OPREQ) { 236 tb_printf(sc, "Timeout waiting for mailbox\n"); 237 error = ETIMEDOUT; 238 } 239 if (val & INMAILCMD_ERROR) { 240 tb_printf(sc, "Firmware reports error in mailbox\n"); 241 error = EINVAL; 242 } 243 244 return (error); 245 } 246 247 /* 248 * Pull command status and data from the firmware mailbox. 249 */ 250 int 251 nhi_outmail_cmd(struct nhi_softc *sc, uint32_t *val) 252 { 253 254 if (val == NULL) 255 return (EINVAL); 256 *val = nhi_read_reg(sc, TBT_OUTMAILCMD); 257 return (0); 258 } 259 260 int 261 nhi_attach(struct nhi_softc *sc) 262 { 263 uint32_t val; 264 int error = 0; 265 266 if ((error = nhi_setup_sysctl(sc)) != 0) 267 return (error); 268 269 mtx_init(&sc->nhi_mtx, "nhimtx", "NHI Control Mutex", MTX_DEF); 270 271 nhi_configure_caps(sc); 272 273 /* 274 * Get the number of TX/RX paths. This sizes some of the register 275 * arrays during allocation and initialization. USB4 spec says that 276 * the max is 21. Alpine Ridge appears to default to 12. 277 */ 278 val = GET_HOST_CAPS_PATHS(nhi_read_reg(sc, NHI_HOST_CAPS)); 279 tb_debug(sc, DBG_INIT|DBG_NOISY, "Total Paths= %d\n", val); 280 if ((val == 0) || (val > 21) || ((NHI_IS_AR(sc) && val != 12))) { 281 tb_printf(sc, "WARN: unexpected number of paths: %d\n", val); 282 /* return (ENXIO); */ 283 } 284 sc->path_count = val; 285 286 SLIST_INIT(&sc->ring_list); 287 288 error = nhi_pci_configure_interrupts(sc); 289 if (error == 0) 290 error = nhi_alloc_ring0(sc); 291 if (error == 0) { 292 nhi_configure_ring(sc, sc->ring0); 293 nhi_activate_ring(sc->ring0); 294 nhi_fill_rx_ring(sc, sc->ring0); 295 } 296 297 if (error == 0) 298 error = tbdev_add_interface(sc); 299 300 if ((error == 0) && (NHI_USE_ICM(sc))) 301 tb_printf(sc, "WARN: device uses an internal connection manager\n"); 302 if ((error == 0) && (NHI_USE_HCM(sc))) 303 ; 304 error = hcm_attach(sc); 305 306 if (error == 0) 307 error = nhi_init(sc); 308 309 return (error); 310 } 311 312 int 313 nhi_detach(struct nhi_softc *sc) 314 { 315 316 if (NHI_USE_HCM(sc)) 317 hcm_detach(sc); 318 319 if (sc->root_rsc != NULL) 320 tb_router_detach(sc->root_rsc); 321 322 tbdev_remove_interface(sc); 323 324 nhi_pci_disable_interrupts(sc); 325 nhi_pci_free_interrupts(sc); 326 327 nhi_free_ring0(sc); 328 329 /* XXX Should the rings be marked as !VALID in the descriptors? */ 330 nhi_free_rings(sc); 331 332 mtx_destroy(&sc->nhi_mtx); 333 334 return (0); 335 } 336 337 static void 338 nhi_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 339 { 340 bus_addr_t *addr; 341 342 addr = arg; 343 if (error == 0 && nsegs == 1) { 344 *addr = segs[0].ds_addr; 345 } else 346 *addr = 0; 347 } 348 349 static int 350 nhi_alloc_ring(struct nhi_softc *sc, int ringnum, int tx_depth, int rx_depth, 351 struct nhi_ring_pair **rp) 352 { 353 bus_dma_template_t t; 354 bus_addr_t ring_busaddr; 355 struct nhi_ring_pair *r; 356 int ring_size, error; 357 u_int rxring_len, txring_len; 358 char *ring; 359 360 if (ringnum >= sc->max_ring_count) { 361 tb_debug(sc, DBG_INIT, "Tried to allocate ring number %d\n", 362 ringnum); 363 return (EINVAL); 364 } 365 366 /* Allocate the ring structure and the RX ring tacker together. */ 367 rxring_len = rx_depth * sizeof(void *); 368 txring_len = tx_depth * sizeof(void *); 369 r = malloc(sizeof(struct nhi_ring_pair) + rxring_len + txring_len, 370 M_NHI, M_NOWAIT|M_ZERO); 371 if (r == NULL) { 372 tb_printf(sc, "ERROR: Cannot allocate ring memory\n"); 373 return (ENOMEM); 374 } 375 376 r->sc = sc; 377 TAILQ_INIT(&r->tx_head); 378 TAILQ_INIT(&r->rx_head); 379 r->ring_num = ringnum; 380 r->tx_ring_depth = tx_depth; 381 r->tx_ring_mask = tx_depth - 1; 382 r->rx_ring_depth = rx_depth; 383 r->rx_ring_mask = rx_depth - 1; 384 r->rx_pici_reg = NHI_RX_RING_PICI + ringnum * 16; 385 r->tx_pici_reg = NHI_TX_RING_PICI + ringnum * 16; 386 r->rx_cmd_ring = (struct nhi_cmd_frame **)((uint8_t *)r + sizeof (*r)); 387 r->tx_cmd_ring = (struct nhi_cmd_frame **)((uint8_t *)r->rx_cmd_ring + 388 rxring_len); 389 390 snprintf(r->name, NHI_RING_NAMELEN, "nhiring%d\n", ringnum); 391 mtx_init(&r->mtx, r->name, "NHI Ring Lock", MTX_DEF); 392 tb_debug(sc, DBG_INIT | DBG_FULL, "Allocated ring context at %p, " 393 "mutex %p\n", r, &r->mtx); 394 395 /* Allocate the RX and TX buffer descriptor rings */ 396 ring_size = sizeof(struct nhi_tx_buffer_desc) * r->tx_ring_depth; 397 ring_size += sizeof(struct nhi_rx_buffer_desc) * r->rx_ring_depth; 398 tb_debug(sc, DBG_INIT | DBG_FULL, "Ring %d ring_size= %d\n", 399 ringnum, ring_size); 400 401 bus_dma_template_init(&t, sc->parent_dmat); 402 t.alignment = 4; 403 t.maxsize = t.maxsegsize = ring_size; 404 t.nsegments = 1; 405 if ((error = bus_dma_template_tag(&t, &r->ring_dmat)) != 0) { 406 tb_printf(sc, "Cannot allocate ring %d DMA tag: %d\n", 407 ringnum, error); 408 return (ENOMEM); 409 } 410 if (bus_dmamem_alloc(r->ring_dmat, (void **)&ring, BUS_DMA_NOWAIT, 411 &r->ring_map)) { 412 tb_printf(sc, "Cannot allocate ring memory\n"); 413 return (ENOMEM); 414 } 415 bzero(ring, ring_size); 416 bus_dmamap_load(r->ring_dmat, r->ring_map, ring, ring_size, 417 nhi_memaddr_cb, &ring_busaddr, 0); 418 419 r->ring = ring; 420 421 r->tx_ring = (union nhi_ring_desc *)(ring); 422 r->tx_ring_busaddr = ring_busaddr; 423 ring += sizeof(struct nhi_tx_buffer_desc) * r->tx_ring_depth; 424 ring_busaddr += sizeof(struct nhi_tx_buffer_desc) * r->tx_ring_depth; 425 426 r->rx_ring = (union nhi_ring_desc *)(ring); 427 r->rx_ring_busaddr = ring_busaddr; 428 429 tb_debug(sc, DBG_INIT | DBG_EXTRA, "Ring %d: RX %p [0x%jx] " 430 "TX %p [0x%jx]\n", ringnum, r->tx_ring, r->tx_ring_busaddr, 431 r->rx_ring, r->rx_ring_busaddr); 432 433 *rp = r; 434 return (0); 435 } 436 437 static void 438 nhi_free_ring(struct nhi_ring_pair *r) 439 { 440 441 tb_debug(r->sc, DBG_INIT, "Freeing ring %d resources\n", r->ring_num); 442 nhi_deactivate_ring(r); 443 444 if (r->tx_ring_busaddr != 0) { 445 bus_dmamap_unload(r->ring_dmat, r->ring_map); 446 r->tx_ring_busaddr = 0; 447 } 448 if (r->ring != NULL) { 449 bus_dmamem_free(r->ring_dmat, r->ring, r->ring_map); 450 r->ring = NULL; 451 } 452 if (r->ring_dmat != NULL) { 453 bus_dma_tag_destroy(r->ring_dmat); 454 r->ring_dmat = NULL; 455 } 456 mtx_destroy(&r->mtx); 457 } 458 459 static void 460 nhi_free_rings(struct nhi_softc *sc) 461 { 462 struct nhi_ring_pair *r; 463 464 while ((r = SLIST_FIRST(&sc->ring_list)) != NULL) { 465 nhi_free_ring(r); 466 mtx_lock(&sc->nhi_mtx); 467 SLIST_REMOVE_HEAD(&sc->ring_list, ring_link); 468 mtx_unlock(&sc->nhi_mtx); 469 free(r, M_NHI); 470 } 471 472 return; 473 } 474 475 static int 476 nhi_configure_ring(struct nhi_softc *sc, struct nhi_ring_pair *ring) 477 { 478 bus_addr_t busaddr; 479 uint32_t val; 480 int idx; 481 482 idx = ring->ring_num * 16; 483 484 /* Program the TX ring address and size */ 485 busaddr = ring->tx_ring_busaddr; 486 nhi_write_reg(sc, NHI_TX_RING_ADDR_LO + idx, busaddr & 0xffffffff); 487 nhi_write_reg(sc, NHI_TX_RING_ADDR_HI + idx, busaddr >> 32); 488 nhi_write_reg(sc, NHI_TX_RING_SIZE + idx, ring->tx_ring_depth); 489 nhi_write_reg(sc, NHI_TX_RING_TABLE_TIMESTAMP + idx, 0x0); 490 tb_debug(sc, DBG_INIT, "TX Ring %d TX_RING_SIZE= 0x%x\n", 491 ring->ring_num, ring->tx_ring_depth); 492 493 /* Program the RX ring address and size */ 494 busaddr = ring->rx_ring_busaddr; 495 val = (ring->rx_buffer_size << 16) | ring->rx_ring_depth; 496 nhi_write_reg(sc, NHI_RX_RING_ADDR_LO + idx, busaddr & 0xffffffff); 497 nhi_write_reg(sc, NHI_RX_RING_ADDR_HI + idx, busaddr >> 32); 498 nhi_write_reg(sc, NHI_RX_RING_SIZE + idx, val); 499 nhi_write_reg(sc, NHI_RX_RING_TABLE_BASE1 + idx, 0xffffffff); 500 tb_debug(sc, DBG_INIT, "RX Ring %d RX_RING_SIZE= 0x%x\n", 501 ring->ring_num, val); 502 503 return (0); 504 } 505 506 static int 507 nhi_activate_ring(struct nhi_ring_pair *ring) 508 { 509 struct nhi_softc *sc = ring->sc; 510 int idx; 511 512 nhi_pci_enable_interrupt(ring); 513 514 idx = ring->ring_num * 32; 515 tb_debug(sc, DBG_INIT, "Activating ring %d at idx %d\n", 516 ring->ring_num, idx); 517 nhi_write_reg(sc, NHI_TX_RING_TABLE_BASE0 + idx, 518 TX_TABLE_RAW | TX_TABLE_VALID); 519 nhi_write_reg(sc, NHI_RX_RING_TABLE_BASE0 + idx, 520 RX_TABLE_RAW | RX_TABLE_VALID); 521 522 return (0); 523 } 524 525 static int 526 nhi_deactivate_ring(struct nhi_ring_pair *r) 527 { 528 struct nhi_softc *sc = r->sc; 529 int idx; 530 531 idx = r->ring_num * 32; 532 tb_debug(sc, DBG_INIT, "Deactiving ring %d at idx %d\n", 533 r->ring_num, idx); 534 nhi_write_reg(sc, NHI_TX_RING_TABLE_BASE0 + idx, 0); 535 nhi_write_reg(sc, NHI_RX_RING_TABLE_BASE0 + idx, 0); 536 537 idx = r->ring_num * 16; 538 tb_debug(sc, DBG_INIT, "Setting ring %d sizes to 0\n", r->ring_num); 539 nhi_write_reg(sc, NHI_TX_RING_SIZE + idx, 0); 540 nhi_write_reg(sc, NHI_RX_RING_SIZE + idx, 0); 541 542 return (0); 543 } 544 545 static int 546 nhi_alloc_ring0(struct nhi_softc *sc) 547 { 548 bus_addr_t frames_busaddr; 549 bus_dma_template_t t; 550 struct nhi_intr_tracker *trkr; 551 struct nhi_ring_pair *r; 552 struct nhi_cmd_frame *cmd; 553 char *frames; 554 int error, size, i; 555 556 if ((error = nhi_alloc_ring(sc, 0, NHI_RING0_TX_DEPTH, 557 NHI_RING0_RX_DEPTH, &r)) != 0) { 558 tb_printf(sc, "Error allocating control ring\n"); 559 return (error); 560 } 561 562 r->rx_buffer_size = NHI_RING0_FRAME_SIZE;/* Control packets are small */ 563 564 /* Allocate the RX and TX buffers that are used for Ring0 comms */ 565 size = r->tx_ring_depth * NHI_RING0_FRAME_SIZE; 566 size += r->rx_ring_depth * NHI_RING0_FRAME_SIZE; 567 568 bus_dma_template_init(&t, sc->parent_dmat); 569 t.maxsize = t.maxsegsize = size; 570 t.nsegments = 1; 571 if (bus_dma_template_tag(&t, &sc->ring0_dmat)) { 572 tb_printf(sc, "Error allocating control ring buffer tag\n"); 573 return (ENOMEM); 574 } 575 576 if (bus_dmamem_alloc(sc->ring0_dmat, (void **)&frames, BUS_DMA_NOWAIT, 577 &sc->ring0_map) != 0) { 578 tb_printf(sc, "Error allocating control ring memory\n"); 579 return (ENOMEM); 580 } 581 bzero(frames, size); 582 bus_dmamap_load(sc->ring0_dmat, sc->ring0_map, frames, size, 583 nhi_memaddr_cb, &frames_busaddr, 0); 584 sc->ring0_frames_busaddr = frames_busaddr; 585 sc->ring0_frames = frames; 586 587 /* Allocate the driver command trackers */ 588 sc->ring0_cmds = malloc(sizeof(struct nhi_cmd_frame) * 589 (r->tx_ring_depth + r->rx_ring_depth), M_NHI, M_NOWAIT | M_ZERO); 590 if (sc->ring0_cmds == NULL) 591 return (ENOMEM); 592 593 /* Initialize the RX frames so they can be used */ 594 mtx_lock(&r->mtx); 595 for (i = 0; i < r->rx_ring_depth; i++) { 596 cmd = &sc->ring0_cmds[i]; 597 cmd->data = (uint32_t *)(frames + NHI_RING0_FRAME_SIZE * i); 598 cmd->data_busaddr = frames_busaddr + NHI_RING0_FRAME_SIZE * i; 599 cmd->flags = CMD_MAPPED; 600 cmd->idx = i; 601 TAILQ_INSERT_TAIL(&r->rx_head, cmd, cm_link); 602 } 603 604 /* Inititalize the TX frames */ 605 for ( ; i < r->tx_ring_depth + r->rx_ring_depth - 1; i++) { 606 cmd = &sc->ring0_cmds[i]; 607 cmd->data = (uint32_t *)(frames + NHI_RING0_FRAME_SIZE * i); 608 cmd->data_busaddr = frames_busaddr + NHI_RING0_FRAME_SIZE * i; 609 cmd->flags = CMD_MAPPED; 610 cmd->idx = i; 611 nhi_free_tx_frame_locked(r, cmd); 612 } 613 mtx_unlock(&r->mtx); 614 615 /* Do a 1:1 mapping of rings to interrupt vectors. */ 616 /* XXX Should be abstracted */ 617 trkr = &sc->intr_trackers[0]; 618 trkr->ring = r; 619 r->tracker = trkr; 620 621 /* XXX Should be an array */ 622 sc->ring0 = r; 623 SLIST_INSERT_HEAD(&sc->ring_list, r, ring_link); 624 625 return (0); 626 } 627 628 static void 629 nhi_free_ring0(struct nhi_softc *sc) 630 { 631 if (sc->ring0_cmds != NULL) { 632 free(sc->ring0_cmds, M_NHI); 633 sc->ring0_cmds = NULL; 634 } 635 636 if (sc->ring0_frames_busaddr != 0) { 637 bus_dmamap_unload(sc->ring0_dmat, sc->ring0_map); 638 sc->ring0_frames_busaddr = 0; 639 } 640 641 if (sc->ring0_frames != NULL) { 642 bus_dmamem_free(sc->ring0_dmat, sc->ring0_frames, 643 sc->ring0_map); 644 sc->ring0_frames = NULL; 645 } 646 647 if (sc->ring0_dmat != NULL) 648 bus_dma_tag_destroy(sc->ring0_dmat); 649 650 return; 651 } 652 653 static void 654 nhi_fill_rx_ring(struct nhi_softc *sc, struct nhi_ring_pair *rp) 655 { 656 struct nhi_cmd_frame *cmd; 657 struct nhi_rx_buffer_desc *desc; 658 u_int ci; 659 660 /* Assume that we never grow or shrink the ring population */ 661 rp->rx_ci = ci = 0; 662 rp->rx_pi = 0; 663 664 do { 665 cmd = TAILQ_FIRST(&rp->rx_head); 666 if (cmd == NULL) 667 break; 668 TAILQ_REMOVE(&rp->rx_head, cmd, cm_link); 669 desc = &rp->rx_ring[ci].rx; 670 if ((cmd->flags & CMD_MAPPED) == 0) 671 panic("Need rx buffer mapping code"); 672 673 desc->addr_lo = cmd->data_busaddr & 0xffffffff; 674 desc->addr_hi = (cmd->data_busaddr >> 32) & 0xffffffff; 675 desc->offset = 0; 676 desc->flags = RX_BUFFER_DESC_RS | RX_BUFFER_DESC_IE; 677 rp->rx_ci = ci; 678 rp->rx_cmd_ring[ci] = cmd; 679 tb_debug(sc, DBG_RXQ | DBG_FULL, 680 "Updating ring%d ci= %d cmd= %p, busaddr= 0x%jx\n", 681 rp->ring_num, ci, cmd, cmd->data_busaddr); 682 683 ci = (rp->rx_ci + 1) & rp->rx_ring_mask; 684 } while (ci != rp->rx_pi); 685 686 /* Update the CI in one shot */ 687 tb_debug(sc, DBG_RXQ, "Writing RX CI= %d\n", rp->rx_ci); 688 nhi_write_reg(sc, rp->rx_pici_reg, rp->rx_ci); 689 690 return; 691 } 692 693 static int 694 nhi_init(struct nhi_softc *sc) 695 { 696 tb_route_t root_route = {0x0, 0x0}; 697 uint32_t val; 698 int error; 699 700 tb_debug(sc, DBG_INIT, "Initializing NHI\n"); 701 702 /* Set interrupt Auto-ACK */ 703 val = nhi_read_reg(sc, NHI_DMA_MISC); 704 tb_debug(sc, DBG_INIT|DBG_FULL, "Read NHI_DMA_MISC= 0x%08x\n", val); 705 val |= DMA_MISC_INT_AUTOCLEAR; 706 tb_debug(sc, DBG_INIT, "Setting interrupt auto-ACK, 0x%08x\n", val); 707 nhi_write_reg(sc, NHI_DMA_MISC, val); 708 709 if (NHI_IS_AR(sc) || NHI_IS_TR(sc) || NHI_IS_ICL(sc)) 710 tb_printf(sc, "WARN: device uses an internal connection manager\n"); 711 712 /* 713 * Populate the controller (local) UUID, necessary for cross-domain 714 * communications. 715 if (NHI_IS_ICL(sc)) 716 nhi_pci_get_uuid(sc); 717 */ 718 719 /* 720 * Attach the router to the root thunderbolt bridge now that the DMA 721 * channel is configured and ready. 722 * The root router always has a route of 0x0...0, so set it statically 723 * here. 724 */ 725 if ((error = tb_router_attach_root(sc, root_route)) != 0) 726 tb_printf(sc, "tb_router_attach_root() error." 727 " The driver should be loaded at boot\n"); 728 729 if (error == 0) { 730 sc->ich.ich_func = nhi_post_init; 731 sc->ich.ich_arg = sc; 732 error = config_intrhook_establish(&sc->ich); 733 if (error) 734 tb_printf(sc, "Failed to establish config hook\n"); 735 } 736 737 return (error); 738 } 739 740 static void 741 nhi_post_init(void *arg) 742 { 743 struct nhi_softc *sc; 744 uint8_t *u; 745 int error; 746 747 sc = (struct nhi_softc *)arg; 748 tb_debug(sc, DBG_INIT | DBG_EXTRA, "nhi_post_init\n"); 749 750 bzero(sc->lc_uuid, 16); 751 error = tb_config_get_lc_uuid(sc->root_rsc, sc->lc_uuid); 752 if (error == 0) { 753 u = sc->lc_uuid; 754 tb_printf(sc, "Root Router LC UUID: %02x%02x%02x%02x-" 755 "%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x\n", 756 u[15], u[14], u[13], u[12], u[11], u[10], u[9], u[8], u[7], 757 u[6], u[5], u[4], u[3], u[2], u[1], u[0]); 758 } else 759 tb_printf(sc, "Error finding LC registers: %d\n", error); 760 761 u = sc->uuid; 762 tb_printf(sc, "Root Router UUID: %02x%02x%02x%02x-" 763 "%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x\n", 764 u[15], u[14], u[13], u[12], u[11], u[10], u[9], u[8], u[7], 765 u[6], u[5], u[4], u[3], u[2], u[1], u[0]); 766 767 config_intrhook_disestablish(&sc->ich); 768 } 769 770 static int 771 nhi_tx_enqueue(struct nhi_ring_pair *r, struct nhi_cmd_frame *cmd) 772 { 773 struct nhi_softc *sc; 774 struct nhi_tx_buffer_desc *desc; 775 uint16_t pi; 776 777 sc = r->sc; 778 779 /* A length of 0 means 4096. Can't have longer lengths */ 780 if (cmd->req_len > TX_BUFFER_DESC_LEN_MASK + 1) { 781 tb_debug(sc, DBG_TXQ, "Error: TX frame too big\n"); 782 return (EINVAL); 783 } 784 cmd->req_len &= TX_BUFFER_DESC_LEN_MASK; 785 786 mtx_lock(&r->mtx); 787 desc = &r->tx_ring[r->tx_pi].tx; 788 pi = (r->tx_pi + 1) & r->tx_ring_mask; 789 if (pi == r->tx_ci) { 790 mtx_unlock(&r->mtx); 791 return (EBUSY); 792 } 793 r->tx_cmd_ring[r->tx_pi] = cmd; 794 r->tx_pi = pi; 795 796 desc->addr_lo = htole32(cmd->data_busaddr & 0xffffffff); 797 desc->addr_hi = htole32(cmd->data_busaddr >> 32); 798 desc->eof_len = htole16((cmd->pdf << TX_BUFFER_DESC_EOF_SHIFT) | 799 cmd->req_len); 800 desc->flags_sof = cmd->pdf | TX_BUFFER_DESC_IE | TX_BUFFER_DESC_RS; 801 desc->offset = 0; 802 desc->payload_time = 0; 803 804 tb_debug(sc, DBG_TXQ, "enqueue TXdescIdx= %d cmdidx= %d len= %d, " 805 "busaddr= 0x%jx\n", r->tx_pi, cmd->idx, cmd->req_len, 806 cmd->data_busaddr); 807 808 nhi_write_reg(sc, r->tx_pici_reg, pi << TX_RING_PI_SHIFT | r->tx_ci); 809 mtx_unlock(&r->mtx); 810 return (0); 811 } 812 813 /* 814 * No scheduling happens for now. Ring0 scheduling is done in the TB 815 * layer. 816 */ 817 int 818 nhi_tx_schedule(struct nhi_ring_pair *r, struct nhi_cmd_frame *cmd) 819 { 820 int error; 821 822 error = nhi_tx_enqueue(r, cmd); 823 if (error == EBUSY) 824 nhi_write_reg(r->sc, r->tx_pici_reg, r->tx_pi << TX_RING_PI_SHIFT | r->tx_ci); 825 return (error); 826 } 827 828 int 829 nhi_tx_synchronous(struct nhi_ring_pair *r, struct nhi_cmd_frame *cmd) 830 { 831 int error, count; 832 833 if ((error = nhi_tx_schedule(r, cmd)) != 0) 834 return (error); 835 836 if (cmd->flags & CMD_POLLED) { 837 error = 0; 838 count = cmd->timeout * 100; 839 840 /* Enter the loop at least once */ 841 while ((count-- > 0) && (cmd->flags & CMD_REQ_COMPLETE) == 0) { 842 DELAY(10000); 843 rmb(); 844 nhi_intr(r->tracker); 845 } 846 } else { 847 error = msleep(cmd, &r->mtx, PCATCH, "nhi_tx", cmd->timeout); 848 if ((error == 0) && (cmd->flags & CMD_REQ_COMPLETE) != 0) 849 error = EWOULDBLOCK; 850 } 851 852 if ((cmd->flags & CMD_REQ_COMPLETE) == 0) 853 error = ETIMEDOUT; 854 855 tb_debug(r->sc, DBG_TXQ|DBG_FULL, "tx_synchronous done waiting, " 856 "err= %d, TX_COMPLETE= %d\n", error, 857 !!(cmd->flags & CMD_REQ_COMPLETE)); 858 859 if (error == ERESTART) { 860 tb_printf(r->sc, "TX command interrupted\n"); 861 } else if ((error == EWOULDBLOCK) || (error == ETIMEDOUT)) { 862 tb_printf(r->sc, "TX command timed out\n"); 863 } else if (error != 0) { 864 tb_printf(r->sc, "TX command failed error= %d\n", error); 865 } 866 867 return (error); 868 } 869 870 static int 871 nhi_tx_complete(struct nhi_ring_pair *r, struct nhi_tx_buffer_desc *desc, 872 struct nhi_cmd_frame *cmd) 873 { 874 struct nhi_softc *sc; 875 struct nhi_pdf_dispatch *txpdf; 876 u_int sof; 877 878 sc = r->sc; 879 sof = desc->flags_sof & TX_BUFFER_DESC_SOF_MASK; 880 tb_debug(sc, DBG_TXQ, "Recovered TX pdf= %s cmdidx= %d flags= 0x%x\n", 881 tb_get_string(sof, nhi_frame_pdf), cmd->idx, desc->flags_sof); 882 883 if ((desc->flags_sof & TX_BUFFER_DESC_DONE) == 0) 884 tb_debug(sc, DBG_TXQ, 885 "warning, TX descriptor DONE flag not set\n"); 886 887 /* XXX Atomics */ 888 cmd->flags |= CMD_REQ_COMPLETE; 889 890 txpdf = &r->tracker->txpdf[sof]; 891 if (txpdf->cb != NULL) { 892 tb_debug(sc, DBG_INTR|DBG_TXQ, "Calling PDF TX callback\n"); 893 txpdf->cb(txpdf->context, (union nhi_ring_desc *)desc, cmd); 894 return (0); 895 } 896 897 tb_debug(sc, DBG_TXQ, "Unhandled TX complete %s\n", 898 tb_get_string(sof, nhi_frame_pdf)); 899 nhi_free_tx_frame(r, cmd); 900 901 return (0); 902 } 903 904 static int 905 nhi_rx_complete(struct nhi_ring_pair *r, struct nhi_rx_post_desc *desc, 906 struct nhi_cmd_frame *cmd) 907 { 908 struct nhi_softc *sc; 909 struct nhi_pdf_dispatch *rxpdf; 910 u_int eof, len; 911 912 sc = r->sc; 913 eof = desc->eof_len >> RX_BUFFER_DESC_EOF_SHIFT; 914 len = desc->eof_len & RX_BUFFER_DESC_LEN_MASK; 915 tb_debug(sc, DBG_INTR|DBG_RXQ, 916 "Recovered RX pdf= %s len= %d cmdidx= %d, busaddr= 0x%jx\n", 917 tb_get_string(eof, nhi_frame_pdf), len, cmd->idx, 918 cmd->data_busaddr); 919 920 rxpdf = &r->tracker->rxpdf[eof]; 921 if (rxpdf->cb != NULL) { 922 tb_debug(sc, DBG_INTR|DBG_RXQ, "Calling PDF RX callback\n"); 923 rxpdf->cb(rxpdf->context, (union nhi_ring_desc *)desc, cmd); 924 return (0); 925 } 926 927 tb_debug(sc, DBG_INTR, "Unhandled RX frame %s\n", 928 tb_get_string(eof, nhi_frame_pdf)); 929 930 return (0); 931 } 932 933 int 934 nhi_register_pdf(struct nhi_ring_pair *rp, struct nhi_dispatch *tx, 935 struct nhi_dispatch *rx) 936 { 937 struct nhi_intr_tracker *trkr; 938 struct nhi_pdf_dispatch *slot; 939 940 KASSERT(rp != NULL, ("ring_pair is null\n")); 941 tb_debug(rp->sc, DBG_INTR|DBG_EXTRA, "nhi_register_pdf called\n"); 942 943 trkr = rp->tracker; 944 if (trkr == NULL) { 945 tb_debug(rp->sc, DBG_INTR, "Invalid tracker\n"); 946 return (EINVAL); 947 } 948 949 tb_debug(rp->sc, DBG_INTR|DBG_EXTRA, "Registering TX interrupts\n"); 950 if (tx != NULL) { 951 while (tx->cb != NULL) { 952 if ((tx->pdf < 0) || (tx->pdf > 15)) 953 return (EINVAL); 954 slot = &trkr->txpdf[tx->pdf]; 955 if (slot->cb != NULL) { 956 tb_debug(rp->sc, DBG_INTR, 957 "Attempted to register busy callback\n"); 958 return (EBUSY); 959 } 960 slot->cb = tx->cb; 961 slot->context = tx->context; 962 tb_debug(rp->sc, DBG_INTR, 963 "Registered TX callback for PDF %d\n", tx->pdf); 964 tx++; 965 } 966 } 967 968 tb_debug(rp->sc, DBG_INTR|DBG_EXTRA, "Registering RX interrupts\n"); 969 if (rx != NULL) { 970 while (rx->cb != NULL) { 971 if ((rx->pdf < 0) || (rx->pdf > 15)) 972 return (EINVAL); 973 slot = &trkr->rxpdf[rx->pdf]; 974 if (slot->cb != NULL) { 975 tb_debug(rp->sc, DBG_INTR, 976 "Attempted to register busy callback\n"); 977 return (EBUSY); 978 } 979 slot->cb = rx->cb; 980 slot->context = rx->context; 981 tb_debug(rp->sc, DBG_INTR, 982 "Registered RX callback for PDF %d\n", rx->pdf); 983 rx++; 984 } 985 } 986 987 return (0); 988 } 989 990 int 991 nhi_deregister_pdf(struct nhi_ring_pair *rp, struct nhi_dispatch *tx, 992 struct nhi_dispatch *rx) 993 { 994 struct nhi_intr_tracker *trkr; 995 struct nhi_pdf_dispatch *slot; 996 997 tb_debug(rp->sc, DBG_INTR|DBG_EXTRA, "nhi_register_pdf called\n"); 998 999 trkr = rp->tracker; 1000 1001 if (tx != NULL) { 1002 while (tx->cb != NULL) { 1003 if ((tx->pdf < 0) || (tx->pdf > 15)) 1004 return (EINVAL); 1005 slot = &trkr->txpdf[tx->pdf]; 1006 slot->cb = NULL; 1007 slot->context = NULL; 1008 tx++; 1009 } 1010 } 1011 1012 if (rx != NULL) { 1013 while (rx->cb != NULL) { 1014 if ((rx->pdf < 0) || (rx->pdf > 15)) 1015 return (EINVAL); 1016 slot = &trkr->rxpdf[rx->pdf]; 1017 slot->cb = NULL; 1018 slot->context = NULL; 1019 rx++; 1020 } 1021 } 1022 1023 return (0); 1024 } 1025 1026 /* 1027 * The CI and PI indexes are not read from the hardware. We track them in 1028 * software, so we know where in the ring to start a scan on an interrupt. 1029 * All we have to do is check for the appropriate Done bit in the next 1030 * descriptor, and we know if we have reached the last descriptor that the 1031 * hardware touched. This technique saves at least 2 MEMIO reads per 1032 * interrupt. 1033 */ 1034 void 1035 nhi_intr(void *data) 1036 { 1037 union nhi_ring_desc *rxd; 1038 struct nhi_cmd_frame *cmd; 1039 struct nhi_intr_tracker *trkr = data; 1040 struct nhi_softc *sc; 1041 struct nhi_ring_pair *r; 1042 struct nhi_tx_buffer_desc *txd; 1043 uint32_t val, old_ci; 1044 u_int count; 1045 1046 sc = trkr->sc; 1047 1048 tb_debug(sc, DBG_INTR|DBG_FULL, "Interrupt @ vector %d\n", 1049 trkr->vector); 1050 if ((r = trkr->ring) == NULL) 1051 return; 1052 1053 /* 1054 * Process TX completions from the adapter. Only go through 1055 * the ring once to prevent unbounded looping. 1056 */ 1057 count = r->tx_ring_depth; 1058 while (count-- > 0) { 1059 txd = &r->tx_ring[r->tx_ci].tx; 1060 if ((txd->flags_sof & TX_BUFFER_DESC_DONE) == 0) 1061 break; 1062 cmd = r->tx_cmd_ring[r->tx_ci]; 1063 tb_debug(sc, DBG_INTR|DBG_TXQ|DBG_FULL, 1064 "Found tx cmdidx= %d cmd= %p\n", r->tx_ci, cmd); 1065 1066 /* Pass the completion up the stack */ 1067 nhi_tx_complete(r, txd, cmd); 1068 1069 /* 1070 * Advance to the next item in the ring via the cached 1071 * copy of the CI. Clear the flags so we can detect 1072 * a new done condition the next time the ring wraps 1073 * around. Anything higher up the stack that needs this 1074 * field should have already copied it. 1075 * 1076 * XXX is a memory barrier needed? 1077 */ 1078 txd->flags_sof = 0; 1079 r->tx_ci = (r->tx_ci + 1) & r->tx_ring_mask; 1080 } 1081 1082 /* Process RX packets from the adapter */ 1083 count = r->rx_ring_depth; 1084 old_ci = r->rx_ci; 1085 1086 while (count-- > 0) { 1087 tb_debug(sc, DBG_INTR|DBG_RXQ|DBG_FULL, 1088 "Checking RX descriptor at %d\n", r->rx_pi); 1089 1090 /* Look up RX descriptor and cmd */ 1091 rxd = &r->rx_ring[r->rx_pi]; 1092 tb_debug(sc, DBG_INTR|DBG_RXQ|DBG_FULL, 1093 "rx desc len= 0x%04x flags= 0x%04x\n", rxd->rxpost.eof_len, 1094 rxd->rxpost.flags_sof); 1095 if ((rxd->rxpost.flags_sof & RX_BUFFER_DESC_DONE) == 0) 1096 break; 1097 cmd = r->rx_cmd_ring[r->rx_pi]; 1098 tb_debug(sc, DBG_INTR|DBG_RXQ|DBG_FULL, 1099 "Found rx cmdidx= %d cmd= %p\n", r->rx_pi, cmd); 1100 1101 /* 1102 * Pass the RX frame up the stack. RX frames are re-used 1103 * in-place, so their contents must be copied before this 1104 * function returns. 1105 * 1106 * XXX Rings other than Ring0 might want to have a different 1107 * re-use and re-populate policy 1108 */ 1109 nhi_rx_complete(r, &rxd->rxpost, cmd); 1110 1111 /* 1112 * Advance the CI and move forward to the next item in the 1113 * ring via our cached copy of the PI. Clear out the 1114 * length field so we can detect a new RX frame when the 1115 * ring wraps around. Reset the flags of the descriptor. 1116 */ 1117 rxd->rxpost.eof_len = 0; 1118 rxd->rx.flags = RX_BUFFER_DESC_RS | RX_BUFFER_DESC_IE; 1119 r->rx_ci = (r->rx_ci + 1) & r->rx_ring_mask; 1120 r->rx_pi = (r->rx_pi + 1) & r->rx_ring_mask; 1121 } 1122 1123 /* 1124 * Tell the firmware about the new RX CI 1125 * 1126 * XXX There's a chance this will overwrite an update to the PI. 1127 * Is that OK? We keep our own copy of the PI and never read it from 1128 * hardware. However, will overwriting it result in a missed 1129 * interrupt? 1130 */ 1131 if (r->rx_ci != old_ci) { 1132 val = r->rx_pi << RX_RING_PI_SHIFT | r->rx_ci; 1133 tb_debug(sc, DBG_INTR | DBG_RXQ, 1134 "Writing new RX PICI= 0x%08x\n", val); 1135 nhi_write_reg(sc, r->rx_pici_reg, val); 1136 } 1137 } 1138 1139 static int 1140 nhi_setup_sysctl(struct nhi_softc *sc) 1141 { 1142 struct sysctl_ctx_list *ctx = NULL; 1143 struct sysctl_oid *tree = NULL; 1144 1145 ctx = device_get_sysctl_ctx(sc->dev); 1146 if (ctx != NULL) 1147 tree = device_get_sysctl_tree(sc->dev); 1148 1149 /* 1150 * Not being able to create sysctls is going to hamper other 1151 * parts of the driver. 1152 */ 1153 if (tree == NULL) { 1154 tb_printf(sc, "Error: cannot create sysctl nodes\n"); 1155 return (EINVAL); 1156 } 1157 sc->sysctl_tree = tree; 1158 sc->sysctl_ctx = ctx; 1159 1160 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 1161 OID_AUTO, "debug_level", CTLTYPE_STRING|CTLFLAG_RW|CTLFLAG_MPSAFE, 1162 &sc->debug, 0, tb_debug_sysctl, "A", "Thunderbolt debug level"); 1163 SYSCTL_ADD_U16(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1164 "max_rings", CTLFLAG_RD, &sc->max_ring_count, 0, 1165 "Max number of rings available"); 1166 SYSCTL_ADD_U8(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1167 "force_hcm", CTLFLAG_RD, &sc->force_hcm, 0, 1168 "Force on/off the function of the host connection manager"); 1169 1170 return (0); 1171 } 1172