1 /*- 2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 3 * PCI-SCSI controllers. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * 7 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 10 * 11 * 12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 13 * Copyright (C) 1998-1999 Gerard Roudier 14 * 15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 16 * a port of the FreeBSD ncr driver to Linux-1.2.13. 17 * 18 * The original ncr driver has been written for 386bsd and FreeBSD by 19 * Wolfgang Stanglmeier <wolf@cologne.de> 20 * Stefan Esser <se@mi.Uni-Koeln.de> 21 * Copyright (C) 1994 Wolfgang Stanglmeier 22 * 23 * The initialisation code, and part of the code that addresses 24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 25 * written by Justin T. Gibbs. 26 * 27 * Other major contributions: 28 * 29 * NVRAM detection and reading. 30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 31 * 32 *----------------------------------------------------------------------------- 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 /* $FreeBSD$ */ 59 60 /* 61 * Scripts for SYMBIOS-Processor 62 * 63 * We have to know the offsets of all labels before we reach 64 * them (for forward jumps). Therefore we declare a struct 65 * here. If you make changes inside the script, 66 * 67 * DONT FORGET TO CHANGE THE LENGTHS HERE! 68 */ 69 70 /* 71 * Script fragments which are loaded into the on-chip RAM 72 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips. 73 * Must not exceed 4K bytes. 74 */ 75 struct SYM_FWA_SCR { 76 u32 start [ 14]; 77 u32 getjob_begin [ 4]; 78 u32 getjob_end [ 4]; 79 u32 select [ 8]; 80 u32 wf_sel_done [ 2]; 81 u32 sel_done [ 2]; 82 u32 send_ident [ 2]; 83 #ifdef SYM_CONF_IARB_SUPPORT 84 u32 select2 [ 8]; 85 #else 86 u32 select2 [ 2]; 87 #endif 88 u32 command [ 2]; 89 u32 dispatch [ 28]; 90 u32 sel_no_cmd [ 10]; 91 u32 init [ 6]; 92 u32 clrack [ 4]; 93 u32 disp_status [ 4]; 94 u32 datai_done [ 26]; 95 u32 datao_done [ 12]; 96 u32 datai_phase [ 2]; 97 u32 datao_phase [ 4]; 98 u32 msg_in [ 2]; 99 u32 msg_in2 [ 10]; 100 #ifdef SYM_CONF_IARB_SUPPORT 101 u32 status [ 14]; 102 #else 103 u32 status [ 10]; 104 #endif 105 u32 complete [ 8]; 106 u32 complete2 [ 12]; 107 u32 complete_error [ 4]; 108 u32 done [ 14]; 109 u32 done_end [ 2]; 110 u32 save_dp [ 8]; 111 u32 restore_dp [ 4]; 112 u32 disconnect [ 20]; 113 #ifdef SYM_CONF_IARB_SUPPORT 114 u32 idle [ 4]; 115 #else 116 u32 idle [ 2]; 117 #endif 118 #ifdef SYM_CONF_IARB_SUPPORT 119 u32 ungetjob [ 6]; 120 #else 121 u32 ungetjob [ 4]; 122 #endif 123 u32 reselect [ 4]; 124 u32 reselected [ 22]; 125 u32 resel_scntl4 [ 20]; 126 u32 resel_lun0 [ 6]; 127 #if SYM_CONF_MAX_TASK*4 > 512 128 u32 resel_tag [ 26]; 129 #elif SYM_CONF_MAX_TASK*4 > 256 130 u32 resel_tag [ 20]; 131 #else 132 u32 resel_tag [ 16]; 133 #endif 134 u32 resel_dsa [ 2]; 135 u32 resel_dsa1 [ 6]; 136 u32 resel_no_tag [ 6]; 137 u32 data_in [SYM_CONF_MAX_SG * 2]; 138 u32 data_in2 [ 4]; 139 u32 data_out [SYM_CONF_MAX_SG * 2]; 140 u32 data_out2 [ 4]; 141 u32 pm0_data [ 12]; 142 u32 pm0_data_out [ 6]; 143 u32 pm0_data_end [ 6]; 144 u32 pm1_data [ 12]; 145 u32 pm1_data_out [ 6]; 146 u32 pm1_data_end [ 6]; 147 }; 148 149 /* 150 * Script fragments which stay in main memory for all chips 151 * except for chips that support 8K on-chip RAM. 152 */ 153 struct SYM_FWB_SCR { 154 u32 start64 [ 2]; 155 u32 no_data [ 2]; 156 u32 sel_for_abort [ 18]; 157 u32 sel_for_abort_1 [ 2]; 158 u32 msg_in_etc [ 12]; 159 u32 msg_received [ 4]; 160 u32 msg_weird_seen [ 4]; 161 u32 msg_extended [ 20]; 162 u32 msg_bad [ 6]; 163 u32 msg_weird [ 4]; 164 u32 msg_weird1 [ 8]; 165 166 u32 wdtr_resp [ 6]; 167 u32 send_wdtr [ 4]; 168 u32 sdtr_resp [ 6]; 169 u32 send_sdtr [ 4]; 170 u32 ppr_resp [ 6]; 171 u32 send_ppr [ 4]; 172 u32 nego_bad_phase [ 4]; 173 u32 msg_out [ 4]; 174 u32 msg_out_done [ 4]; 175 u32 data_ovrun [ 2]; 176 u32 data_ovrun1 [ 22]; 177 u32 data_ovrun2 [ 8]; 178 u32 abort_resel [ 16]; 179 u32 resend_ident [ 4]; 180 u32 ident_break [ 4]; 181 u32 ident_break_atn [ 4]; 182 u32 sdata_in [ 6]; 183 u32 resel_bad_lun [ 4]; 184 u32 bad_i_t_l [ 4]; 185 u32 bad_i_t_l_q [ 4]; 186 u32 bad_status [ 6]; 187 u32 pm_handle [ 20]; 188 u32 pm_handle1 [ 4]; 189 u32 pm_save [ 4]; 190 u32 pm0_save [ 14]; 191 u32 pm1_save [ 14]; 192 193 /* WSR handling */ 194 u32 pm_wsr_handle [ 42]; 195 u32 wsr_ma_helper [ 4]; 196 197 /* Data area */ 198 u32 zero [ 1]; 199 u32 scratch [ 1]; 200 u32 pm0_data_addr [ 1]; 201 u32 pm1_data_addr [ 1]; 202 u32 saved_dsa [ 1]; 203 u32 saved_drs [ 1]; 204 u32 done_pos [ 1]; 205 u32 startpos [ 1]; 206 u32 targtbl [ 1]; 207 /* End of data area */ 208 209 u32 snooptest [ 6]; 210 u32 snoopend [ 2]; 211 }; 212 213 static const struct SYM_FWA_SCR SYM_FWA_SCR = { 214 /*--------------------------< START >----------------------------*/ { 215 /* 216 * Switch the LED on. 217 * Will be patched with a NO_OP if LED 218 * not needed or not desired. 219 */ 220 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 221 0, 222 /* 223 * Clear SIGP. 224 */ 225 SCR_FROM_REG (ctest2), 226 0, 227 /* 228 * Stop here if the C code wants to perform 229 * some error recovery procedure manually. 230 * (Indicate this by setting SEM in ISTAT) 231 */ 232 SCR_FROM_REG (istat), 233 0, 234 /* 235 * Report to the C code the next position in 236 * the start queue the SCRIPTS will schedule. 237 * The C code must not change SCRATCHA. 238 */ 239 SCR_LOAD_ABS (scratcha, 4), 240 PADDR_B (startpos), 241 SCR_INT ^ IFTRUE (MASK (SEM, SEM)), 242 SIR_SCRIPT_STOPPED, 243 /* 244 * Start the next job. 245 * 246 * @DSA = start point for this job. 247 * SCRATCHA = address of this job in the start queue. 248 * 249 * We will restore startpos with SCRATCHA if we fails the 250 * arbitration or if it is the idle job. 251 * 252 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 253 * is a critical path. If it is partially executed, it then 254 * may happen that the job address is not yet in the DSA 255 * and the next queue position points to the next JOB. 256 */ 257 SCR_LOAD_ABS (dsa, 4), 258 PADDR_B (startpos), 259 SCR_LOAD_REL (temp, 4), 260 4, 261 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{ 262 SCR_STORE_ABS (temp, 4), 263 PADDR_B (startpos), 264 SCR_LOAD_REL (dsa, 4), 265 0, 266 }/*-------------------------< GETJOB_END >-----------------------*/,{ 267 SCR_LOAD_REL (temp, 4), 268 0, 269 SCR_RETURN, 270 0, 271 }/*-------------------------< SELECT >---------------------------*/,{ 272 /* 273 * DSA contains the address of a scheduled 274 * data structure. 275 * 276 * SCRATCHA contains the address of the start queue 277 * entry which points to the next job. 278 * 279 * Set Initiator mode. 280 * 281 * (Target mode is left as an exercise for the reader) 282 */ 283 SCR_CLR (SCR_TRG), 284 0, 285 /* 286 * And try to select this target. 287 */ 288 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select), 289 PADDR_A (ungetjob), 290 /* 291 * Now there are 4 possibilities: 292 * 293 * (1) The chip loses arbitration. 294 * This is ok, because it will try again, 295 * when the bus becomes idle. 296 * (But beware of the timeout function!) 297 * 298 * (2) The chip is reselected. 299 * Then the script processor takes the jump 300 * to the RESELECT label. 301 * 302 * (3) The chip wins arbitration. 303 * Then it will execute SCRIPTS instruction until 304 * the next instruction that checks SCSI phase. 305 * Then will stop and wait for selection to be 306 * complete or selection time-out to occur. 307 * 308 * After having won arbitration, the SCRIPTS 309 * processor is able to execute instructions while 310 * the SCSI core is performing SCSI selection. 311 */ 312 /* 313 * load the savep (saved data pointer) into 314 * the actual data pointer. 315 */ 316 SCR_LOAD_REL (temp, 4), 317 offsetof (struct sym_ccb, phys.head.savep), 318 /* 319 * Initialize the status registers 320 */ 321 SCR_LOAD_REL (scr0, 4), 322 offsetof (struct sym_ccb, phys.head.status), 323 }/*-------------------------< WF_SEL_DONE >----------------------*/,{ 324 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 325 SIR_SEL_ATN_NO_MSG_OUT, 326 }/*-------------------------< SEL_DONE >-------------------------*/,{ 327 /* 328 * C1010-33 errata work-around. 329 * Due to a race, the SCSI core may not have 330 * loaded SCNTL3 on SEL_TBL instruction. 331 * We reload it once phase is stable. 332 * Patched with a NOOP for other chips. 333 */ 334 SCR_LOAD_REL (scntl3, 1), 335 offsetof(struct sym_dsb, select.sel_scntl3), 336 }/*-------------------------< SEND_IDENT >-----------------------*/,{ 337 /* 338 * Selection complete. 339 * Send the IDENTIFY and possibly the TAG message 340 * and negotiation message if present. 341 */ 342 SCR_MOVE_TBL ^ SCR_MSG_OUT, 343 offsetof (struct sym_dsb, smsg), 344 }/*-------------------------< SELECT2 >--------------------------*/,{ 345 #ifdef SYM_CONF_IARB_SUPPORT 346 /* 347 * Set IMMEDIATE ARBITRATION if we have been given 348 * a hint to do so. (Some job to do after this one). 349 */ 350 SCR_FROM_REG (HF_REG), 351 0, 352 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), 353 8, 354 SCR_REG_REG (scntl1, SCR_OR, IARB), 355 0, 356 #endif 357 /* 358 * Anticipate the COMMAND phase. 359 * This is the PHASE we expect at this point. 360 */ 361 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)), 362 PADDR_A (sel_no_cmd), 363 }/*-------------------------< COMMAND >--------------------------*/,{ 364 /* 365 * ... and send the command 366 */ 367 SCR_MOVE_TBL ^ SCR_COMMAND, 368 offsetof (struct sym_dsb, cmd), 369 }/*-------------------------< DISPATCH >-------------------------*/,{ 370 /* 371 * MSG_IN is the only phase that shall be 372 * entered at least once for each (re)selection. 373 * So we test it first. 374 */ 375 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 376 PADDR_A (msg_in), 377 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)), 378 PADDR_A (datao_phase), 379 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)), 380 PADDR_A (datai_phase), 381 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), 382 PADDR_A (status), 383 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), 384 PADDR_A (command), 385 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), 386 PADDR_B (msg_out), 387 /* 388 * Discard as many illegal phases as 389 * required and tell the C code about. 390 */ 391 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)), 392 16, 393 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, 394 HADDR_1 (scratch), 395 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)), 396 -16, 397 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)), 398 16, 399 SCR_MOVE_ABS (1) ^ SCR_ILG_IN, 400 HADDR_1 (scratch), 401 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)), 402 -16, 403 SCR_INT, 404 SIR_BAD_PHASE, 405 SCR_JUMP, 406 PADDR_A (dispatch), 407 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{ 408 /* 409 * The target does not switch to command 410 * phase after IDENTIFY has been sent. 411 * 412 * If it stays in MSG OUT phase send it 413 * the IDENTIFY again. 414 */ 415 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 416 PADDR_B (resend_ident), 417 /* 418 * If target does not switch to MSG IN phase 419 * and we sent a negotiation, assert the 420 * failure immediately. 421 */ 422 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 423 PADDR_A (dispatch), 424 SCR_FROM_REG (HS_REG), 425 0, 426 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 427 SIR_NEGO_FAILED, 428 /* 429 * Jump to dispatcher. 430 */ 431 SCR_JUMP, 432 PADDR_A (dispatch), 433 }/*-------------------------< INIT >-----------------------------*/,{ 434 /* 435 * Wait for the SCSI RESET signal to be 436 * inactive before restarting operations, 437 * since the chip may hang on SEL_ATN 438 * if SCSI RESET is active. 439 */ 440 SCR_FROM_REG (sstat0), 441 0, 442 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), 443 -16, 444 SCR_JUMP, 445 PADDR_A (start), 446 }/*-------------------------< CLRACK >---------------------------*/,{ 447 /* 448 * Terminate possible pending message phase. 449 */ 450 SCR_CLR (SCR_ACK), 451 0, 452 SCR_JUMP, 453 PADDR_A (dispatch), 454 }/*-------------------------< DISP_STATUS >----------------------*/,{ 455 /* 456 * Anticipate STATUS phase. 457 * 458 * Does spare 3 SCRIPTS instructions when we have 459 * completed the INPUT of the data. 460 */ 461 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 462 PADDR_A (status), 463 SCR_JUMP, 464 PADDR_A (dispatch), 465 }/*-------------------------< DATAI_DONE >-----------------------*/,{ 466 /* 467 * If the device still wants to send us data, 468 * we must count the extra bytes. 469 */ 470 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_IN)), 471 PADDR_B (data_ovrun), 472 /* 473 * If the SWIDE is not full, jump to dispatcher. 474 * We anticipate a STATUS phase. 475 */ 476 SCR_FROM_REG (scntl2), 477 0, 478 SCR_JUMP ^ IFFALSE (MASK (WSR, WSR)), 479 PADDR_A (disp_status), 480 /* 481 * The SWIDE is full. 482 * Clear this condition. 483 */ 484 SCR_REG_REG (scntl2, SCR_OR, WSR), 485 0, 486 /* 487 * We are expecting an IGNORE RESIDUE message 488 * from the device, otherwise we are in data 489 * overrun condition. Check against MSG_IN phase. 490 */ 491 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 492 SIR_SWIDE_OVERRUN, 493 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 494 PADDR_A (disp_status), 495 /* 496 * We are in MSG_IN phase, 497 * Read the first byte of the message. 498 * If it is not an IGNORE RESIDUE message, 499 * signal overrun and jump to message 500 * processing. 501 */ 502 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 503 HADDR_1 (msgin[0]), 504 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)), 505 SIR_SWIDE_OVERRUN, 506 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)), 507 PADDR_A (msg_in2), 508 /* 509 * We got the message we expected. 510 * Read the 2nd byte, and jump to dispatcher. 511 */ 512 SCR_CLR (SCR_ACK), 513 0, 514 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 515 HADDR_1 (msgin[1]), 516 SCR_CLR (SCR_ACK), 517 0, 518 SCR_JUMP, 519 PADDR_A (disp_status), 520 }/*-------------------------< DATAO_DONE >-----------------------*/,{ 521 /* 522 * If the device wants us to send more data, 523 * we must count the extra bytes. 524 */ 525 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)), 526 PADDR_B (data_ovrun), 527 /* 528 * If the SODL is not full jump to dispatcher. 529 * We anticipate a STATUS phase. 530 */ 531 SCR_FROM_REG (scntl2), 532 0, 533 SCR_JUMP ^ IFFALSE (MASK (WSS, WSS)), 534 PADDR_A (disp_status), 535 /* 536 * The SODL is full, clear this condition. 537 */ 538 SCR_REG_REG (scntl2, SCR_OR, WSS), 539 0, 540 /* 541 * And signal a DATA UNDERRUN condition 542 * to the C code. 543 */ 544 SCR_INT, 545 SIR_SODL_UNDERRUN, 546 SCR_JUMP, 547 PADDR_A (dispatch), 548 }/*-------------------------< DATAI_PHASE >----------------------*/,{ 549 SCR_RETURN, 550 0, 551 }/*-------------------------< DATAO_PHASE >----------------------*/,{ 552 /* 553 * C1010-66 errata work-around. 554 * Extra clocks of data hold must be inserted 555 * in DATA OUT phase on 33 MHz PCI BUS. 556 * Patched with a NOOP for other chips. 557 */ 558 SCR_REG_REG (scntl4, SCR_OR, (XCLKH_DT|XCLKH_ST)), 559 0, 560 SCR_RETURN, 561 0, 562 }/*-------------------------< MSG_IN >---------------------------*/,{ 563 /* 564 * Get the first byte of the message. 565 * 566 * The script processor doesn't negate the 567 * ACK signal after this transfer. 568 */ 569 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 570 HADDR_1 (msgin[0]), 571 }/*-------------------------< MSG_IN2 >--------------------------*/,{ 572 /* 573 * Check first against 1 byte messages 574 * that we handle from SCRIPTS. 575 */ 576 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)), 577 PADDR_A (complete), 578 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)), 579 PADDR_A (disconnect), 580 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)), 581 PADDR_A (save_dp), 582 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)), 583 PADDR_A (restore_dp), 584 /* 585 * We handle all other messages from the 586 * C code, so no need to waste on-chip RAM 587 * for those ones. 588 */ 589 SCR_JUMP, 590 PADDR_B (msg_in_etc), 591 }/*-------------------------< STATUS >---------------------------*/,{ 592 /* 593 * get the status 594 */ 595 SCR_MOVE_ABS (1) ^ SCR_STATUS, 596 HADDR_1 (scratch), 597 #ifdef SYM_CONF_IARB_SUPPORT 598 /* 599 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION, 600 * since we may have to tamper the start queue from 601 * the C code. 602 */ 603 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)), 604 8, 605 SCR_REG_REG (scntl1, SCR_AND, ~IARB), 606 0, 607 #endif 608 /* 609 * save status to scsi_status. 610 * mark as complete. 611 */ 612 SCR_TO_REG (SS_REG), 613 0, 614 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 615 0, 616 /* 617 * Anticipate the MESSAGE PHASE for 618 * the TASK COMPLETE message. 619 */ 620 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 621 PADDR_A (msg_in), 622 SCR_JUMP, 623 PADDR_A (dispatch), 624 }/*-------------------------< COMPLETE >-------------------------*/,{ 625 /* 626 * Complete message. 627 * 628 * Copy the data pointer to LASTP. 629 */ 630 SCR_STORE_REL (temp, 4), 631 offsetof (struct sym_ccb, phys.head.lastp), 632 /* 633 * When we terminate the cycle by clearing ACK, 634 * the target may disconnect immediately. 635 * 636 * We don't want to be told of an "unexpected disconnect", 637 * so we disable this feature. 638 */ 639 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 640 0, 641 /* 642 * Terminate cycle ... 643 */ 644 SCR_CLR (SCR_ACK|SCR_ATN), 645 0, 646 /* 647 * ... and wait for the disconnect. 648 */ 649 SCR_WAIT_DISC, 650 0, 651 }/*-------------------------< COMPLETE2 >------------------------*/,{ 652 /* 653 * Save host status. 654 */ 655 SCR_STORE_REL (scr0, 4), 656 offsetof (struct sym_ccb, phys.head.status), 657 /* 658 * Some bridges may reorder DMA writes to memory. 659 * We donnot want the CPU to deal with completions 660 * without all the posted write having been flushed 661 * to memory. This DUMMY READ should flush posted 662 * buffers prior to the CPU having to deal with 663 * completions. 664 */ 665 SCR_LOAD_REL (scr0, 4), /* DUMMY READ */ 666 offsetof (struct sym_ccb, phys.head.status), 667 668 /* 669 * If command resulted in not GOOD status, 670 * call the C code if needed. 671 */ 672 SCR_FROM_REG (SS_REG), 673 0, 674 SCR_CALL ^ IFFALSE (DATA (S_GOOD)), 675 PADDR_B (bad_status), 676 /* 677 * If we performed an auto-sense, call 678 * the C code to synchronyze task aborts 679 * with UNIT ATTENTION conditions. 680 */ 681 SCR_FROM_REG (HF_REG), 682 0, 683 SCR_JUMPR ^ IFTRUE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), 684 16, 685 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{ 686 SCR_LOAD_ABS (scratcha, 4), 687 PADDR_B (startpos), 688 SCR_INT, 689 SIR_COMPLETE_ERROR, 690 }/*-------------------------< DONE >-----------------------------*/,{ 691 /* 692 * Copy the DSA to the DONE QUEUE and 693 * signal completion to the host. 694 * If we are interrupted between DONE 695 * and DONE_END, we must reset, otherwise 696 * the completed CCB may be lost. 697 */ 698 SCR_STORE_ABS (dsa, 4), 699 PADDR_B (saved_dsa), 700 SCR_LOAD_ABS (dsa, 4), 701 PADDR_B (done_pos), 702 SCR_LOAD_ABS (scratcha, 4), 703 PADDR_B (saved_dsa), 704 SCR_STORE_REL (scratcha, 4), 705 0, 706 /* 707 * The instruction below reads the DONE QUEUE next 708 * free position from memory. 709 * In addition it ensures that all PCI posted writes 710 * are flushed and so the DSA value of the done 711 * CCB is visible by the CPU before INTFLY is raised. 712 */ 713 SCR_LOAD_REL (temp, 4), 714 4, 715 SCR_INT_FLY, 716 0, 717 SCR_STORE_ABS (temp, 4), 718 PADDR_B (done_pos), 719 }/*-------------------------< DONE_END >-------------------------*/,{ 720 SCR_JUMP, 721 PADDR_A (start), 722 }/*-------------------------< SAVE_DP >--------------------------*/,{ 723 /* 724 * Clear ACK immediately. 725 * No need to delay it. 726 */ 727 SCR_CLR (SCR_ACK), 728 0, 729 /* 730 * Keep track we received a SAVE DP, so 731 * we will switch to the other PM context 732 * on the next PM since the DP may point 733 * to the current PM context. 734 */ 735 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 736 0, 737 /* 738 * SAVE_DP message: 739 * Copy the data pointer to SAVEP. 740 */ 741 SCR_STORE_REL (temp, 4), 742 offsetof (struct sym_ccb, phys.head.savep), 743 SCR_JUMP, 744 PADDR_A (dispatch), 745 }/*-------------------------< RESTORE_DP >-----------------------*/,{ 746 /* 747 * RESTORE_DP message: 748 * Copy SAVEP to actual data pointer. 749 */ 750 SCR_LOAD_REL (temp, 4), 751 offsetof (struct sym_ccb, phys.head.savep), 752 SCR_JUMP, 753 PADDR_A (clrack), 754 }/*-------------------------< DISCONNECT >-----------------------*/,{ 755 /* 756 * DISCONNECTing ... 757 * 758 * disable the "unexpected disconnect" feature, 759 * and remove the ACK signal. 760 */ 761 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 762 0, 763 SCR_CLR (SCR_ACK|SCR_ATN), 764 0, 765 /* 766 * Wait for the disconnect. 767 */ 768 SCR_WAIT_DISC, 769 0, 770 /* 771 * Status is: DISCONNECTED. 772 */ 773 SCR_LOAD_REG (HS_REG, HS_DISCONNECT), 774 0, 775 /* 776 * Save host status. 777 */ 778 SCR_STORE_REL (scr0, 4), 779 offsetof (struct sym_ccb, phys.head.status), 780 /* 781 * If QUIRK_AUTOSAVE is set, 782 * do a "save pointer" operation. 783 */ 784 SCR_FROM_REG (QU_REG), 785 0, 786 SCR_JUMP ^ IFFALSE (MASK (SYM_QUIRK_AUTOSAVE, SYM_QUIRK_AUTOSAVE)), 787 PADDR_A (start), 788 /* 789 * like SAVE_DP message: 790 * Remember we saved the data pointer. 791 * Copy data pointer to SAVEP. 792 */ 793 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 794 0, 795 SCR_STORE_REL (temp, 4), 796 offsetof (struct sym_ccb, phys.head.savep), 797 SCR_JUMP, 798 PADDR_A (start), 799 }/*-------------------------< IDLE >-----------------------------*/,{ 800 /* 801 * Nothing to do? 802 * Switch the LED off and wait for reselect. 803 * Will be patched with a NO_OP if LED 804 * not needed or not desired. 805 */ 806 SCR_REG_REG (gpreg, SCR_OR, 0x01), 807 0, 808 #ifdef SYM_CONF_IARB_SUPPORT 809 SCR_JUMPR, 810 8, 811 #endif 812 }/*-------------------------< UNGETJOB >-------------------------*/,{ 813 #ifdef SYM_CONF_IARB_SUPPORT 814 /* 815 * Set IMMEDIATE ARBITRATION, for the next time. 816 * This will give us better chance to win arbitration 817 * for the job we just wanted to do. 818 */ 819 SCR_REG_REG (scntl1, SCR_OR, IARB), 820 0, 821 #endif 822 /* 823 * We are not able to restart the SCRIPTS if we are 824 * interrupted and these instruction haven't been 825 * all executed. BTW, this is very unlikely to 826 * happen, but we check that from the C code. 827 */ 828 SCR_LOAD_REG (dsa, 0xff), 829 0, 830 SCR_STORE_ABS (scratcha, 4), 831 PADDR_B (startpos), 832 }/*-------------------------< RESELECT >-------------------------*/,{ 833 /* 834 * Make sure we are in initiator mode. 835 */ 836 SCR_CLR (SCR_TRG), 837 0, 838 /* 839 * Sleep waiting for a reselection. 840 */ 841 SCR_WAIT_RESEL, 842 PADDR_A(start), 843 }/*-------------------------< RESELECTED >-----------------------*/,{ 844 /* 845 * Switch the LED on. 846 * Will be patched with a NO_OP if LED 847 * not needed or not desired. 848 */ 849 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 850 0, 851 /* 852 * load the target id into the sdid 853 */ 854 SCR_REG_SFBR (ssid, SCR_AND, 0x8F), 855 0, 856 SCR_TO_REG (sdid), 857 0, 858 /* 859 * Load the target control block address 860 */ 861 SCR_LOAD_ABS (dsa, 4), 862 PADDR_B (targtbl), 863 SCR_SFBR_REG (dsa, SCR_SHL, 0), 864 0, 865 SCR_REG_REG (dsa, SCR_SHL, 0), 866 0, 867 SCR_REG_REG (dsa, SCR_AND, 0x3c), 868 0, 869 SCR_LOAD_REL (dsa, 4), 870 0, 871 /* 872 * We expect MESSAGE IN phase. 873 * If not, get help from the C code. 874 */ 875 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 876 SIR_RESEL_NO_MSG_IN, 877 /* 878 * Load the legacy synchronous transfer registers. 879 */ 880 SCR_LOAD_REL (scntl3, 1), 881 offsetof(struct sym_tcb, head.wval), 882 SCR_LOAD_REL (sxfer, 1), 883 offsetof(struct sym_tcb, head.sval), 884 }/*-------------------------< RESEL_SCNTL4 >---------------------*/,{ 885 /* 886 * The C1010 uses a new synchronous timing scheme. 887 * Will be patched with a NO_OP if not a C1010. 888 */ 889 SCR_LOAD_REL (scntl4, 1), 890 offsetof(struct sym_tcb, head.uval), 891 /* 892 * Get the IDENTIFY message. 893 */ 894 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 895 HADDR_1 (msgin), 896 /* 897 * If IDENTIFY LUN #0, use a faster path 898 * to find the LCB structure. 899 */ 900 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), 901 PADDR_A (resel_lun0), 902 /* 903 * If message isn't an IDENTIFY, 904 * tell the C code about. 905 */ 906 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), 907 SIR_RESEL_NO_IDENTIFY, 908 /* 909 * It is an IDENTIFY message, 910 * Load the LUN control block address. 911 */ 912 SCR_LOAD_REL (dsa, 4), 913 offsetof(struct sym_tcb, head.luntbl_sa), 914 SCR_SFBR_REG (dsa, SCR_SHL, 0), 915 0, 916 SCR_REG_REG (dsa, SCR_SHL, 0), 917 0, 918 SCR_REG_REG (dsa, SCR_AND, 0xfc), 919 0, 920 SCR_LOAD_REL (dsa, 4), 921 0, 922 SCR_JUMPR, 923 8, 924 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{ 925 /* 926 * LUN 0 special case (but usual one :)) 927 */ 928 SCR_LOAD_REL (dsa, 4), 929 offsetof(struct sym_tcb, head.lun0_sa), 930 /* 931 * Jump indirectly to the reselect action for this LUN. 932 */ 933 SCR_LOAD_REL (temp, 4), 934 offsetof(struct sym_lcb, head.resel_sa), 935 SCR_RETURN, 936 0, 937 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */ 938 }/*-------------------------< RESEL_TAG >------------------------*/,{ 939 /* 940 * ACK the IDENTIFY previously received. 941 */ 942 SCR_CLR (SCR_ACK), 943 0, 944 /* 945 * It shall be a tagged command. 946 * Read SIMPLE+TAG. 947 * The C code will deal with errors. 948 * Aggressive optimization, isn't it? :) 949 */ 950 SCR_MOVE_ABS (2) ^ SCR_MSG_IN, 951 HADDR_1 (msgin), 952 /* 953 * Load the pointer to the tagged task 954 * table for this LUN. 955 */ 956 SCR_LOAD_REL (dsa, 4), 957 offsetof(struct sym_lcb, head.itlq_tbl_sa), 958 /* 959 * The SIDL still contains the TAG value. 960 * Aggressive optimization, isn't it? :):) 961 */ 962 SCR_REG_SFBR (sidl, SCR_SHL, 0), 963 0, 964 #if SYM_CONF_MAX_TASK*4 > 512 965 SCR_JUMPR ^ IFFALSE (CARRYSET), 966 8, 967 SCR_REG_REG (dsa1, SCR_OR, 2), 968 0, 969 SCR_REG_REG (sfbr, SCR_SHL, 0), 970 0, 971 SCR_JUMPR ^ IFFALSE (CARRYSET), 972 8, 973 SCR_REG_REG (dsa1, SCR_OR, 1), 974 0, 975 #elif SYM_CONF_MAX_TASK*4 > 256 976 SCR_JUMPR ^ IFFALSE (CARRYSET), 977 8, 978 SCR_REG_REG (dsa1, SCR_OR, 1), 979 0, 980 #endif 981 /* 982 * Retrieve the DSA of this task. 983 * JUMP indirectly to the restart point of the CCB. 984 */ 985 SCR_SFBR_REG (dsa, SCR_AND, 0xfc), 986 0, 987 SCR_LOAD_REL (dsa, 4), 988 0, 989 SCR_LOAD_REL (temp, 4), 990 offsetof(struct sym_ccb, phys.head.go.restart), 991 SCR_RETURN, 992 0, 993 /* In normal situations we branch to RESEL_DSA */ 994 }/*-------------------------< RESEL_DSA >------------------------*/,{ 995 /* 996 * ACK the IDENTIFY or TAG previously received. 997 */ 998 SCR_CLR (SCR_ACK), 999 0, 1000 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{ 1001 /* 1002 * load the savep (saved pointer) into 1003 * the actual data pointer. 1004 */ 1005 SCR_LOAD_REL (temp, 4), 1006 offsetof (struct sym_ccb, phys.head.savep), 1007 /* 1008 * Initialize the status registers 1009 */ 1010 SCR_LOAD_REL (scr0, 4), 1011 offsetof (struct sym_ccb, phys.head.status), 1012 /* 1013 * Jump to dispatcher. 1014 */ 1015 SCR_JUMP, 1016 PADDR_A (dispatch), 1017 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{ 1018 /* 1019 * Load the DSA with the unique ITL task. 1020 */ 1021 SCR_LOAD_REL (dsa, 4), 1022 offsetof(struct sym_lcb, head.itl_task_sa), 1023 /* 1024 * JUMP indirectly to the restart point of the CCB. 1025 */ 1026 SCR_LOAD_REL (temp, 4), 1027 offsetof(struct sym_ccb, phys.head.go.restart), 1028 SCR_RETURN, 1029 0, 1030 /* In normal situations we branch to RESEL_DSA */ 1031 }/*-------------------------< DATA_IN >--------------------------*/,{ 1032 /* 1033 * Because the size depends on the 1034 * #define SYM_CONF_MAX_SG parameter, 1035 * it is filled in at runtime. 1036 * 1037 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1038 * || SCR_CHMOV_TBL ^ SCR_DATA_IN, 1039 * || offsetof (struct sym_dsb, data[ i]), 1040 * ##========================================== 1041 */ 1042 0 1043 }/*-------------------------< DATA_IN2 >-------------------------*/,{ 1044 SCR_CALL, 1045 PADDR_A (datai_done), 1046 SCR_JUMP, 1047 PADDR_B (data_ovrun), 1048 }/*-------------------------< DATA_OUT >-------------------------*/,{ 1049 /* 1050 * Because the size depends on the 1051 * #define SYM_CONF_MAX_SG parameter, 1052 * it is filled in at runtime. 1053 * 1054 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1055 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1056 * || offsetof (struct sym_dsb, data[ i]), 1057 * ##========================================== 1058 */ 1059 0 1060 }/*-------------------------< DATA_OUT2 >------------------------*/,{ 1061 SCR_CALL, 1062 PADDR_A (datao_done), 1063 SCR_JUMP, 1064 PADDR_B (data_ovrun), 1065 }/*-------------------------< PM0_DATA >-------------------------*/,{ 1066 /* 1067 * Read our host flags to SFBR, so we will be able 1068 * to check against the data direction we expect. 1069 */ 1070 SCR_FROM_REG (HF_REG), 1071 0, 1072 /* 1073 * Check against actual DATA PHASE. 1074 */ 1075 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1076 PADDR_A (pm0_data_out), 1077 /* 1078 * Actual phase is DATA IN. 1079 * Check against expected direction. 1080 */ 1081 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1082 PADDR_B (data_ovrun), 1083 /* 1084 * Keep track we are moving data from the 1085 * PM0 DATA mini-script. 1086 */ 1087 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1088 0, 1089 /* 1090 * Move the data to memory. 1091 */ 1092 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1093 offsetof (struct sym_ccb, phys.pm0.sg), 1094 SCR_JUMP, 1095 PADDR_A (pm0_data_end), 1096 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{ 1097 /* 1098 * Actual phase is DATA OUT. 1099 * Check against expected direction. 1100 */ 1101 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1102 PADDR_B (data_ovrun), 1103 /* 1104 * Keep track we are moving data from the 1105 * PM0 DATA mini-script. 1106 */ 1107 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1108 0, 1109 /* 1110 * Move the data from memory. 1111 */ 1112 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1113 offsetof (struct sym_ccb, phys.pm0.sg), 1114 }/*-------------------------< PM0_DATA_END >---------------------*/,{ 1115 /* 1116 * Clear the flag that told we were moving 1117 * data from the PM0 DATA mini-script. 1118 */ 1119 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)), 1120 0, 1121 /* 1122 * Return to the previous DATA script which 1123 * is guaranteed by design (if no bug) to be 1124 * the main DATA script for this transfer. 1125 */ 1126 SCR_LOAD_REL (temp, 4), 1127 offsetof (struct sym_ccb, phys.pm0.ret), 1128 SCR_RETURN, 1129 0, 1130 }/*-------------------------< PM1_DATA >-------------------------*/,{ 1131 /* 1132 * Read our host flags to SFBR, so we will be able 1133 * to check against the data direction we expect. 1134 */ 1135 SCR_FROM_REG (HF_REG), 1136 0, 1137 /* 1138 * Check against actual DATA PHASE. 1139 */ 1140 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1141 PADDR_A (pm1_data_out), 1142 /* 1143 * Actual phase is DATA IN. 1144 * Check against expected direction. 1145 */ 1146 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1147 PADDR_B (data_ovrun), 1148 /* 1149 * Keep track we are moving data from the 1150 * PM1 DATA mini-script. 1151 */ 1152 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1153 0, 1154 /* 1155 * Move the data to memory. 1156 */ 1157 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1158 offsetof (struct sym_ccb, phys.pm1.sg), 1159 SCR_JUMP, 1160 PADDR_A (pm1_data_end), 1161 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{ 1162 /* 1163 * Actual phase is DATA OUT. 1164 * Check against expected direction. 1165 */ 1166 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1167 PADDR_B (data_ovrun), 1168 /* 1169 * Keep track we are moving data from the 1170 * PM1 DATA mini-script. 1171 */ 1172 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1173 0, 1174 /* 1175 * Move the data from memory. 1176 */ 1177 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1178 offsetof (struct sym_ccb, phys.pm1.sg), 1179 }/*-------------------------< PM1_DATA_END >---------------------*/,{ 1180 /* 1181 * Clear the flag that told we were moving 1182 * data from the PM1 DATA mini-script. 1183 */ 1184 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)), 1185 0, 1186 /* 1187 * Return to the previous DATA script which 1188 * is guaranteed by design (if no bug) to be 1189 * the main DATA script for this transfer. 1190 */ 1191 SCR_LOAD_REL (temp, 4), 1192 offsetof (struct sym_ccb, phys.pm1.ret), 1193 SCR_RETURN, 1194 0, 1195 }/*-------------------------<>-----------------------------------*/ 1196 }; 1197 1198 static const struct SYM_FWB_SCR SYM_FWB_SCR = { 1199 /*--------------------------< START64 >--------------------------*/ { 1200 /* 1201 * SCRIPT entry point for the 895A, 896 and 1010. 1202 * For now, there is no specific stuff for those 1203 * chips at this point, but this may come. 1204 */ 1205 SCR_JUMP, 1206 PADDR_A (init), 1207 }/*-------------------------< NO_DATA >--------------------------*/,{ 1208 SCR_JUMP, 1209 PADDR_B (data_ovrun), 1210 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{ 1211 /* 1212 * We are jumped here by the C code, if we have 1213 * some target to reset or some disconnected 1214 * job to abort. Since error recovery is a serious 1215 * busyness, we will really reset the SCSI BUS, if 1216 * case of a SCSI interrupt occurring in this path. 1217 */ 1218 1219 /* 1220 * Set initiator mode. 1221 */ 1222 SCR_CLR (SCR_TRG), 1223 0, 1224 /* 1225 * And try to select this target. 1226 */ 1227 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel), 1228 PADDR_A (reselect), 1229 /* 1230 * Wait for the selection to complete or 1231 * the selection to time out. 1232 */ 1233 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1234 -8, 1235 /* 1236 * Call the C code. 1237 */ 1238 SCR_INT, 1239 SIR_TARGET_SELECTED, 1240 /* 1241 * The C code should let us continue here. 1242 * Send the 'kiss of death' message. 1243 * We expect an immediate disconnect once 1244 * the target has eaten the message. 1245 */ 1246 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1247 0, 1248 SCR_MOVE_TBL ^ SCR_MSG_OUT, 1249 offsetof (struct sym_hcb, abrt_tbl), 1250 SCR_CLR (SCR_ACK|SCR_ATN), 1251 0, 1252 SCR_WAIT_DISC, 1253 0, 1254 /* 1255 * Tell the C code that we are done. 1256 */ 1257 SCR_INT, 1258 SIR_ABORT_SENT, 1259 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{ 1260 /* 1261 * Jump at scheduler. 1262 */ 1263 SCR_JUMP, 1264 PADDR_A (start), 1265 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{ 1266 /* 1267 * If it is an EXTENDED (variable size message) 1268 * Handle it. 1269 */ 1270 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)), 1271 PADDR_B (msg_extended), 1272 /* 1273 * Let the C code handle any other 1274 * 1 byte message. 1275 */ 1276 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), 1277 PADDR_B (msg_received), 1278 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), 1279 PADDR_B (msg_received), 1280 /* 1281 * We donnot handle 2 bytes messages from SCRIPTS. 1282 * So, let the C code deal with these ones too. 1283 */ 1284 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)), 1285 PADDR_B (msg_weird_seen), 1286 SCR_CLR (SCR_ACK), 1287 0, 1288 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1289 HADDR_1 (msgin[1]), 1290 }/*-------------------------< MSG_RECEIVED >---------------------*/,{ 1291 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */ 1292 0, 1293 SCR_INT, 1294 SIR_MSG_RECEIVED, 1295 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{ 1296 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */ 1297 0, 1298 SCR_INT, 1299 SIR_MSG_WEIRD, 1300 }/*-------------------------< MSG_EXTENDED >---------------------*/,{ 1301 /* 1302 * Clear ACK and get the next byte 1303 * assumed to be the message length. 1304 */ 1305 SCR_CLR (SCR_ACK), 1306 0, 1307 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1308 HADDR_1 (msgin[1]), 1309 /* 1310 * Try to catch some unlikely situations as 0 length 1311 * or too large the length. 1312 */ 1313 SCR_JUMP ^ IFTRUE (DATA (0)), 1314 PADDR_B (msg_weird_seen), 1315 SCR_TO_REG (scratcha), 1316 0, 1317 SCR_REG_REG (sfbr, SCR_ADD, (256-8)), 1318 0, 1319 SCR_JUMP ^ IFTRUE (CARRYSET), 1320 PADDR_B (msg_weird_seen), 1321 /* 1322 * We donnot handle extended messages from SCRIPTS. 1323 * Read the amount of data corresponding to the 1324 * message length and call the C code. 1325 */ 1326 SCR_STORE_REL (scratcha, 1), 1327 offsetof (struct sym_dsb, smsg_ext.size), 1328 SCR_CLR (SCR_ACK), 1329 0, 1330 SCR_MOVE_TBL ^ SCR_MSG_IN, 1331 offsetof (struct sym_dsb, smsg_ext), 1332 SCR_JUMP, 1333 PADDR_B (msg_received), 1334 }/*-------------------------< MSG_BAD >--------------------------*/,{ 1335 /* 1336 * unimplemented message - reject it. 1337 */ 1338 SCR_INT, 1339 SIR_REJECT_TO_SEND, 1340 SCR_SET (SCR_ATN), 1341 0, 1342 SCR_JUMP, 1343 PADDR_A (clrack), 1344 }/*-------------------------< MSG_WEIRD >------------------------*/,{ 1345 /* 1346 * weird message received 1347 * ignore all MSG IN phases and reject it. 1348 */ 1349 SCR_INT, 1350 SIR_REJECT_TO_SEND, 1351 SCR_SET (SCR_ATN), 1352 0, 1353 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{ 1354 SCR_CLR (SCR_ACK), 1355 0, 1356 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 1357 PADDR_A (dispatch), 1358 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1359 HADDR_1 (scratch), 1360 SCR_JUMP, 1361 PADDR_B (msg_weird1), 1362 }/*-------------------------< WDTR_RESP >------------------------*/,{ 1363 /* 1364 * let the target fetch our answer. 1365 */ 1366 SCR_SET (SCR_ATN), 1367 0, 1368 SCR_CLR (SCR_ACK), 1369 0, 1370 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1371 PADDR_B (nego_bad_phase), 1372 }/*-------------------------< SEND_WDTR >------------------------*/,{ 1373 /* 1374 * Send the M_X_WIDE_REQ 1375 */ 1376 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, 1377 HADDR_1 (msgout), 1378 SCR_JUMP, 1379 PADDR_B (msg_out_done), 1380 }/*-------------------------< SDTR_RESP >------------------------*/,{ 1381 /* 1382 * let the target fetch our answer. 1383 */ 1384 SCR_SET (SCR_ATN), 1385 0, 1386 SCR_CLR (SCR_ACK), 1387 0, 1388 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1389 PADDR_B (nego_bad_phase), 1390 }/*-------------------------< SEND_SDTR >------------------------*/,{ 1391 /* 1392 * Send the M_X_SYNC_REQ 1393 */ 1394 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, 1395 HADDR_1 (msgout), 1396 SCR_JUMP, 1397 PADDR_B (msg_out_done), 1398 }/*-------------------------< PPR_RESP >-------------------------*/,{ 1399 /* 1400 * let the target fetch our answer. 1401 */ 1402 SCR_SET (SCR_ATN), 1403 0, 1404 SCR_CLR (SCR_ACK), 1405 0, 1406 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1407 PADDR_B (nego_bad_phase), 1408 }/*-------------------------< SEND_PPR >-------------------------*/,{ 1409 /* 1410 * Send the M_X_PPR_REQ 1411 */ 1412 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT, 1413 HADDR_1 (msgout), 1414 SCR_JUMP, 1415 PADDR_B (msg_out_done), 1416 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{ 1417 SCR_INT, 1418 SIR_NEGO_PROTO, 1419 SCR_JUMP, 1420 PADDR_A (dispatch), 1421 }/*-------------------------< MSG_OUT >--------------------------*/,{ 1422 /* 1423 * The target requests a message. 1424 * We donnot send messages that may 1425 * require the device to go to bus free. 1426 */ 1427 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1428 HADDR_1 (msgout), 1429 /* 1430 * ... wait for the next phase 1431 * if it's a message out, send it again, ... 1432 */ 1433 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 1434 PADDR_B (msg_out), 1435 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{ 1436 /* 1437 * Let the C code be aware of the 1438 * sent message and clear the message. 1439 */ 1440 SCR_INT, 1441 SIR_MSG_OUT_DONE, 1442 /* 1443 * ... and process the next phase 1444 */ 1445 SCR_JUMP, 1446 PADDR_A (dispatch), 1447 }/*-------------------------< DATA_OVRUN >-----------------------*/,{ 1448 /* 1449 * Use scratcha to count the extra bytes. 1450 */ 1451 SCR_LOAD_ABS (scratcha, 4), 1452 PADDR_B (zero), 1453 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{ 1454 /* 1455 * The target may want to transfer too much data. 1456 * 1457 * If phase is DATA OUT write 1 byte and count it. 1458 */ 1459 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), 1460 16, 1461 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT, 1462 HADDR_1 (scratch), 1463 SCR_JUMP, 1464 PADDR_B (data_ovrun2), 1465 /* 1466 * If WSR is set, clear this condition, and 1467 * count this byte. 1468 */ 1469 SCR_FROM_REG (scntl2), 1470 0, 1471 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), 1472 16, 1473 SCR_REG_REG (scntl2, SCR_OR, WSR), 1474 0, 1475 SCR_JUMP, 1476 PADDR_B (data_ovrun2), 1477 /* 1478 * Finally check against DATA IN phase. 1479 * Signal data overrun to the C code 1480 * and jump to dispatcher if not so. 1481 * Read 1 byte otherwise and count it. 1482 */ 1483 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)), 1484 16, 1485 SCR_INT, 1486 SIR_DATA_OVERRUN, 1487 SCR_JUMP, 1488 PADDR_A (dispatch), 1489 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN, 1490 HADDR_1 (scratch), 1491 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{ 1492 /* 1493 * Count this byte. 1494 * This will allow to return a negative 1495 * residual to user. 1496 */ 1497 SCR_REG_REG (scratcha, SCR_ADD, 0x01), 1498 0, 1499 SCR_REG_REG (scratcha1, SCR_ADDC, 0), 1500 0, 1501 SCR_REG_REG (scratcha2, SCR_ADDC, 0), 1502 0, 1503 /* 1504 * .. and repeat as required. 1505 */ 1506 SCR_JUMP, 1507 PADDR_B (data_ovrun1), 1508 }/*-------------------------< ABORT_RESEL >----------------------*/,{ 1509 SCR_SET (SCR_ATN), 1510 0, 1511 SCR_CLR (SCR_ACK), 1512 0, 1513 /* 1514 * send the abort/abortag/reset message 1515 * we expect an immediate disconnect 1516 */ 1517 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1518 0, 1519 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1520 HADDR_1 (msgout), 1521 SCR_CLR (SCR_ACK|SCR_ATN), 1522 0, 1523 SCR_WAIT_DISC, 1524 0, 1525 SCR_INT, 1526 SIR_RESEL_ABORTED, 1527 SCR_JUMP, 1528 PADDR_A (start), 1529 }/*-------------------------< RESEND_IDENT >---------------------*/,{ 1530 /* 1531 * The target stays in MSG OUT phase after having acked 1532 * Identify [+ Tag [+ Extended message ]]. Targets shall 1533 * behave this way on parity error. 1534 * We must send it again all the messages. 1535 */ 1536 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */ 1537 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */ 1538 SCR_JUMP, 1539 PADDR_A (send_ident), 1540 }/*-------------------------< IDENT_BREAK >----------------------*/,{ 1541 SCR_CLR (SCR_ATN), 1542 0, 1543 SCR_JUMP, 1544 PADDR_A (select2), 1545 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{ 1546 SCR_SET (SCR_ATN), 1547 0, 1548 SCR_JUMP, 1549 PADDR_A (select2), 1550 }/*-------------------------< SDATA_IN >-------------------------*/,{ 1551 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1552 offsetof (struct sym_dsb, sense), 1553 SCR_CALL, 1554 PADDR_A (datai_done), 1555 SCR_JUMP, 1556 PADDR_B (data_ovrun), 1557 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{ 1558 /* 1559 * Message is an IDENTIFY, but lun is unknown. 1560 * Signal problem to C code for logging the event. 1561 * Send a M_ABORT to clear all pending tasks. 1562 */ 1563 SCR_INT, 1564 SIR_RESEL_BAD_LUN, 1565 SCR_JUMP, 1566 PADDR_B (abort_resel), 1567 }/*-------------------------< BAD_I_T_L >------------------------*/,{ 1568 /* 1569 * We donnot have a task for that I_T_L. 1570 * Signal problem to C code for logging the event. 1571 * Send a M_ABORT message. 1572 */ 1573 SCR_INT, 1574 SIR_RESEL_BAD_I_T_L, 1575 SCR_JUMP, 1576 PADDR_B (abort_resel), 1577 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{ 1578 /* 1579 * We donnot have a task that matches the tag. 1580 * Signal problem to C code for logging the event. 1581 * Send a M_ABORTTAG message. 1582 */ 1583 SCR_INT, 1584 SIR_RESEL_BAD_I_T_L_Q, 1585 SCR_JUMP, 1586 PADDR_B (abort_resel), 1587 }/*-------------------------< BAD_STATUS >-----------------------*/,{ 1588 /* 1589 * Anything different from INTERMEDIATE 1590 * CONDITION MET should be a bad SCSI status, 1591 * given that GOOD status has already been tested. 1592 * Call the C code. 1593 */ 1594 SCR_LOAD_ABS (scratcha, 4), 1595 PADDR_B (startpos), 1596 SCR_INT ^ IFFALSE (DATA (S_COND_MET)), 1597 SIR_BAD_SCSI_STATUS, 1598 SCR_RETURN, 1599 0, 1600 }/*-------------------------< PM_HANDLE >------------------------*/,{ 1601 /* 1602 * Phase mismatch handling. 1603 * 1604 * Since we have to deal with 2 SCSI data pointers 1605 * (current and saved), we need at least 2 contexts. 1606 * Each context (pm0 and pm1) has a saved area, a 1607 * SAVE mini-script and a DATA phase mini-script. 1608 */ 1609 /* 1610 * Get the PM handling flags. 1611 */ 1612 SCR_FROM_REG (HF_REG), 1613 0, 1614 /* 1615 * If no flags (1rst PM for example), avoid 1616 * all the below heavy flags testing. 1617 * This makes the normal case a bit faster. 1618 */ 1619 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))), 1620 PADDR_B (pm_handle1), 1621 /* 1622 * If we received a SAVE DP, switch to the 1623 * other PM context since the savep may point 1624 * to the current PM context. 1625 */ 1626 SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)), 1627 8, 1628 SCR_REG_REG (sfbr, SCR_XOR, HF_ACT_PM), 1629 0, 1630 /* 1631 * If we have been interrupt in a PM DATA mini-script, 1632 * we take the return address from the corresponding 1633 * saved area. 1634 * This ensure the return address always points to the 1635 * main DATA script for this transfer. 1636 */ 1637 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))), 1638 PADDR_B (pm_handle1), 1639 SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)), 1640 16, 1641 SCR_LOAD_REL (ia, 4), 1642 offsetof(struct sym_ccb, phys.pm0.ret), 1643 SCR_JUMP, 1644 PADDR_B (pm_save), 1645 SCR_LOAD_REL (ia, 4), 1646 offsetof(struct sym_ccb, phys.pm1.ret), 1647 SCR_JUMP, 1648 PADDR_B (pm_save), 1649 }/*-------------------------< PM_HANDLE1 >-----------------------*/,{ 1650 /* 1651 * Normal case. 1652 * Update the return address so that it 1653 * will point after the interrupted MOVE. 1654 */ 1655 SCR_REG_REG (ia, SCR_ADD, 8), 1656 0, 1657 SCR_REG_REG (ia1, SCR_ADDC, 0), 1658 0, 1659 }/*-------------------------< PM_SAVE >--------------------------*/,{ 1660 /* 1661 * Clear all the flags that told us if we were 1662 * interrupted in a PM DATA mini-script and/or 1663 * we received a SAVE DP. 1664 */ 1665 SCR_SFBR_REG (HF_REG, SCR_AND, (~(HF_IN_PM0|HF_IN_PM1|HF_DP_SAVED))), 1666 0, 1667 /* 1668 * Choose the current PM context. 1669 */ 1670 SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)), 1671 PADDR_B (pm1_save), 1672 }/*-------------------------< PM0_SAVE >-------------------------*/,{ 1673 SCR_STORE_REL (ia, 4), 1674 offsetof(struct sym_ccb, phys.pm0.ret), 1675 /* 1676 * If WSR bit is set, either UA and RBC may 1677 * have to be changed whether the device wants 1678 * to ignore this residue or not. 1679 */ 1680 SCR_FROM_REG (scntl2), 1681 0, 1682 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), 1683 PADDR_B (pm_wsr_handle), 1684 /* 1685 * Save the remaining byte count, the updated 1686 * address and the return address. 1687 */ 1688 SCR_STORE_REL (rbc, 4), 1689 offsetof(struct sym_ccb, phys.pm0.sg.size), 1690 SCR_STORE_REL (ua, 4), 1691 offsetof(struct sym_ccb, phys.pm0.sg.addr), 1692 /* 1693 * Set the current pointer at the PM0 DATA mini-script. 1694 */ 1695 SCR_LOAD_ABS (temp, 4), 1696 PADDR_B (pm0_data_addr), 1697 SCR_JUMP, 1698 PADDR_A (dispatch), 1699 }/*-------------------------< PM1_SAVE >-------------------------*/,{ 1700 SCR_STORE_REL (ia, 4), 1701 offsetof(struct sym_ccb, phys.pm1.ret), 1702 /* 1703 * If WSR bit is set, either UA and RBC may 1704 * have to be changed whether the device wants 1705 * to ignore this residue or not. 1706 */ 1707 SCR_FROM_REG (scntl2), 1708 0, 1709 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), 1710 PADDR_B (pm_wsr_handle), 1711 /* 1712 * Save the remaining byte count, the updated 1713 * address and the return address. 1714 */ 1715 SCR_STORE_REL (rbc, 4), 1716 offsetof(struct sym_ccb, phys.pm1.sg.size), 1717 SCR_STORE_REL (ua, 4), 1718 offsetof(struct sym_ccb, phys.pm1.sg.addr), 1719 /* 1720 * Set the current pointer at the PM1 DATA mini-script. 1721 */ 1722 SCR_LOAD_ABS (temp, 4), 1723 PADDR_B (pm1_data_addr), 1724 SCR_JUMP, 1725 PADDR_A (dispatch), 1726 }/*-------------------------< PM_WSR_HANDLE >--------------------*/,{ 1727 /* 1728 * Phase mismatch handling from SCRIPT with WSR set. 1729 * Such a condition can occur if the chip wants to 1730 * execute a CHMOV(size > 1) when the WSR bit is 1731 * set and the target changes PHASE. 1732 * 1733 * We must move the residual byte to memory. 1734 * 1735 * UA contains bit 0..31 of the address to 1736 * move the residual byte. 1737 * Move it to the table indirect. 1738 */ 1739 SCR_STORE_REL (ua, 4), 1740 offsetof (struct sym_ccb, phys.wresid.addr), 1741 /* 1742 * Increment UA (move address to next position). 1743 */ 1744 SCR_REG_REG (ua, SCR_ADD, 1), 1745 0, 1746 SCR_REG_REG (ua1, SCR_ADDC, 0), 1747 0, 1748 SCR_REG_REG (ua2, SCR_ADDC, 0), 1749 0, 1750 SCR_REG_REG (ua3, SCR_ADDC, 0), 1751 0, 1752 /* 1753 * Compute SCRATCHA as: 1754 * - size to transfer = 1 byte. 1755 * - bit 24..31 = high address bit [32...39]. 1756 */ 1757 SCR_LOAD_ABS (scratcha, 4), 1758 PADDR_B (zero), 1759 SCR_REG_REG (scratcha, SCR_OR, 1), 1760 0, 1761 SCR_FROM_REG (rbc3), 1762 0, 1763 SCR_TO_REG (scratcha3), 1764 0, 1765 /* 1766 * Move this value to the table indirect. 1767 */ 1768 SCR_STORE_REL (scratcha, 4), 1769 offsetof (struct sym_ccb, phys.wresid.size), 1770 /* 1771 * Wait for a valid phase. 1772 * While testing with bogus QUANTUM drives, the C1010 1773 * sometimes raised a spurious phase mismatch with 1774 * WSR and the CHMOV(1) triggered another PM. 1775 * Waiting explicitely for the PHASE seemed to avoid 1776 * the nested phase mismatch. Btw, this didn't happen 1777 * using my IBM drives. 1778 */ 1779 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_IN)), 1780 0, 1781 /* 1782 * Perform the move of the residual byte. 1783 */ 1784 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1785 offsetof (struct sym_ccb, phys.wresid), 1786 /* 1787 * We can now handle the phase mismatch with UA fixed. 1788 * RBC[0..23]=0 is a special case that does not require 1789 * a PM context. The C code also checks against this. 1790 */ 1791 SCR_FROM_REG (rbc), 1792 0, 1793 SCR_RETURN ^ IFFALSE (DATA (0)), 1794 0, 1795 SCR_FROM_REG (rbc1), 1796 0, 1797 SCR_RETURN ^ IFFALSE (DATA (0)), 1798 0, 1799 SCR_FROM_REG (rbc2), 1800 0, 1801 SCR_RETURN ^ IFFALSE (DATA (0)), 1802 0, 1803 /* 1804 * RBC[0..23]=0. 1805 * Not only we donnot need a PM context, but this would 1806 * lead to a bogus CHMOV(0). This condition means that 1807 * the residual was the last byte to move from this CHMOV. 1808 * So, we just have to move the current data script pointer 1809 * (i.e. TEMP) to the SCRIPTS address following the 1810 * interrupted CHMOV and jump to dispatcher. 1811 */ 1812 SCR_STORE_ABS (ia, 4), 1813 PADDR_B (scratch), 1814 SCR_LOAD_ABS (temp, 4), 1815 PADDR_B (scratch), 1816 SCR_JUMP, 1817 PADDR_A (dispatch), 1818 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{ 1819 /* 1820 * Helper for the C code when WSR bit is set. 1821 * Perform the move of the residual byte. 1822 */ 1823 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1824 offsetof (struct sym_ccb, phys.wresid), 1825 SCR_JUMP, 1826 PADDR_A (dispatch), 1827 }/*-------------------------< ZERO >-----------------------------*/,{ 1828 SCR_DATA_ZERO, 1829 }/*-------------------------< SCRATCH >--------------------------*/,{ 1830 SCR_DATA_ZERO, 1831 }/*-------------------------< PM0_DATA_ADDR >--------------------*/,{ 1832 SCR_DATA_ZERO, 1833 }/*-------------------------< PM1_DATA_ADDR >--------------------*/,{ 1834 SCR_DATA_ZERO, 1835 }/*-------------------------< SAVED_DSA >------------------------*/,{ 1836 SCR_DATA_ZERO, 1837 }/*-------------------------< SAVED_DRS >------------------------*/,{ 1838 SCR_DATA_ZERO, 1839 }/*-------------------------< DONE_POS >-------------------------*/,{ 1840 SCR_DATA_ZERO, 1841 }/*-------------------------< STARTPOS >-------------------------*/,{ 1842 SCR_DATA_ZERO, 1843 }/*-------------------------< TARGTBL >--------------------------*/,{ 1844 SCR_DATA_ZERO, 1845 1846 }/*-------------------------< SNOOPTEST >------------------------*/,{ 1847 /* 1848 * Read the variable from memory. 1849 */ 1850 SCR_LOAD_REL (scratcha, 4), 1851 offsetof(struct sym_hcb, cache), 1852 /* 1853 * Write the variable to memory. 1854 */ 1855 SCR_STORE_REL (temp, 4), 1856 offsetof(struct sym_hcb, cache), 1857 /* 1858 * Read back the variable from memory. 1859 */ 1860 SCR_LOAD_REL (temp, 4), 1861 offsetof(struct sym_hcb, cache), 1862 }/*-------------------------< SNOOPEND >-------------------------*/,{ 1863 /* 1864 * And stop. 1865 */ 1866 SCR_INT, 1867 99, 1868 }/*-------------------------<>-----------------------------------*/ 1869 }; 1870