1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 5 * PCI-SCSI controllers. 6 * 7 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 8 * 9 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 10 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 11 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 12 * 13 * 14 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 15 * Copyright (C) 1998-1999 Gerard Roudier 16 * 17 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 18 * a port of the FreeBSD ncr driver to Linux-1.2.13. 19 * 20 * The original ncr driver has been written for 386bsd and FreeBSD by 21 * Wolfgang Stanglmeier <wolf@cologne.de> 22 * Stefan Esser <se@mi.Uni-Koeln.de> 23 * Copyright (C) 1994 Wolfgang Stanglmeier 24 * 25 * The initialisation code, and part of the code that addresses 26 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 27 * written by Justin T. Gibbs. 28 * 29 * Other major contributions: 30 * 31 * NVRAM detection and reading. 32 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 33 * 34 *----------------------------------------------------------------------------- 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 51 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 */ 59 60 61 #ifndef SYM_DEFS_H 62 #define SYM_DEFS_H 63 64 /* 65 * Vendor. 66 */ 67 #define PCI_VENDOR_NCR 0x1000 68 69 /* 70 * PCI device identifier of SYMBIOS chips. 71 */ 72 #define PCI_ID_SYM53C810 1 73 #define PCI_ID_SYM53C810AP 5 74 #define PCI_ID_SYM53C815 4 75 #define PCI_ID_SYM53C820 2 76 #define PCI_ID_SYM53C825 3 77 #define PCI_ID_SYM53C860 6 78 #define PCI_ID_SYM53C875 0xf 79 #define PCI_ID_SYM53C875_2 0x8f 80 #define PCI_ID_SYM53C885 0xd 81 #define PCI_ID_SYM53C895 0xc 82 #define PCI_ID_SYM53C896 0xb 83 #define PCI_ID_SYM53C895A 0x12 84 #define PCI_ID_LSI53C1010 0x20 85 #define PCI_ID_LSI53C1010_2 0x21 86 #define PCI_ID_LSI53C1510D 0xa 87 88 /* 89 * SYM53C8XX device features descriptor. 90 */ 91 struct sym_pci_chip { 92 u_short device_id; 93 unsigned short revision_id; 94 const char *name; 95 u_char burst_max; /* log-base-2 of max burst */ 96 u_char offset_max; 97 u_char nr_divisor; 98 u_char lp_probe_bit; 99 u_int features; 100 #define FE_LED0 (1<<0) 101 #define FE_WIDE (1<<1) /* Wide data transfers */ 102 #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */ 103 #define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */ 104 #define FE_DBLR (1<<4) /* Clock doubler present */ 105 #define FE_QUAD (1<<5) /* Clock quadrupler present */ 106 #define FE_ERL (1<<6) /* Enable read line */ 107 #define FE_CLSE (1<<7) /* Cache line size enable */ 108 #define FE_WRIE (1<<8) /* Write & Invalidate enable */ 109 #define FE_ERMP (1<<9) /* Enable read multiple */ 110 #define FE_BOF (1<<10) /* Burst opcode fetch */ 111 #define FE_DFS (1<<11) /* DMA fifo size */ 112 #define FE_PFEN (1<<12) /* Prefetch enable */ 113 #define FE_LDSTR (1<<13) /* Load/Store supported */ 114 #define FE_RAM (1<<14) /* On chip RAM present */ 115 #define FE_CLK80 (1<<15) /* Board clock is 80 MHz */ 116 #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */ 117 #define FE_64BIT (1<<17) /* 64-bit PCI BUS interface */ 118 #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */ 119 #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */ 120 #define FE_LEDC (1<<20) /* Hardware control of LED */ 121 #define FE_ULTRA3 (1<<21) /* Ultra 3 - 80 Mtrans/sec DT */ 122 #define FE_66MHZ (1<<22) /* 66MHz PCI support */ 123 #define FE_CRC (1<<23) /* CRC support */ 124 #define FE_DIFF (1<<24) /* SCSI HVD support */ 125 #define FE_DFBC (1<<25) /* Have DFBC register */ 126 #define FE_LCKFRQ (1<<26) /* Have LCKFRQ */ 127 #define FE_C10 (1<<27) /* Various C10 core (mis)features */ 128 #define FE_U3EN (1<<28) /* U3EN bit usable */ 129 #define FE_DAC (1<<29) /* Support PCI DAC (64 bit addressing) */ 130 131 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP) 132 #define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL) 133 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM) 134 }; 135 136 /* 137 * Symbios NVRAM data format 138 */ 139 #define SYMBIOS_NVRAM_SIZE 368 140 #define SYMBIOS_NVRAM_ADDRESS 0x100 141 142 struct Symbios_nvram { 143 /* Header 6 bytes */ 144 u_short type; /* 0x0000 */ 145 u_short byte_count; /* excluding header/trailer */ 146 u_short checksum; 147 148 /* Controller set up 20 bytes */ 149 u_char v_major; /* 0x00 */ 150 u_char v_minor; /* 0x30 */ 151 u32 boot_crc; 152 u_short flags; 153 #define SYMBIOS_SCAM_ENABLE (1) 154 #define SYMBIOS_PARITY_ENABLE (1<<1) 155 #define SYMBIOS_VERBOSE_MSGS (1<<2) 156 #define SYMBIOS_CHS_MAPPING (1<<3) 157 #define SYMBIOS_NO_NVRAM (1<<3) /* ??? */ 158 u_short flags1; 159 #define SYMBIOS_SCAN_HI_LO (1) 160 u_short term_state; 161 #define SYMBIOS_TERM_CANT_PROGRAM (0) 162 #define SYMBIOS_TERM_ENABLED (1) 163 #define SYMBIOS_TERM_DISABLED (2) 164 u_short rmvbl_flags; 165 #define SYMBIOS_RMVBL_NO_SUPPORT (0) 166 #define SYMBIOS_RMVBL_BOOT_DEVICE (1) 167 #define SYMBIOS_RMVBL_MEDIA_INSTALLED (2) 168 u_char host_id; 169 u_char num_hba; /* 0x04 */ 170 u_char num_devices; /* 0x10 */ 171 u_char max_scam_devices; /* 0x04 */ 172 u_char num_valid_scam_devices; /* 0x00 */ 173 u_char flags2; 174 #define SYMBIOS_AVOID_BUS_RESET (1<<2) 175 176 /* Boot order 14 bytes * 4 */ 177 struct Symbios_host{ 178 u_short type; /* 4:8xx / 0:nok */ 179 u_short device_id; /* PCI device id */ 180 u_short vendor_id; /* PCI vendor id */ 181 u_char bus_nr; /* PCI bus number */ 182 u_char device_fn; /* PCI device/function number << 3*/ 183 u_short word8; 184 u_short flags; 185 #define SYMBIOS_INIT_SCAN_AT_BOOT (1) 186 u_short io_port; /* PCI io_port address */ 187 } host[4]; 188 189 /* Targets 8 bytes * 16 */ 190 struct Symbios_target { 191 u_char flags; 192 #define SYMBIOS_DISCONNECT_ENABLE (1) 193 #define SYMBIOS_SCAN_AT_BOOT_TIME (1<<1) 194 #define SYMBIOS_SCAN_LUNS (1<<2) 195 #define SYMBIOS_QUEUE_TAGS_ENABLED (1<<3) 196 u_char rsvd; 197 u_char bus_width; /* 0x08/0x10 */ 198 u_char sync_offset; 199 u_short sync_period; /* 4*period factor */ 200 u_short timeout; 201 } target[16]; 202 /* Scam table 8 bytes * 4 */ 203 struct Symbios_scam { 204 u_short id; 205 u_short method; 206 #define SYMBIOS_SCAM_DEFAULT_METHOD (0) 207 #define SYMBIOS_SCAM_DONT_ASSIGN (1) 208 #define SYMBIOS_SCAM_SET_SPECIFIC_ID (2) 209 #define SYMBIOS_SCAM_USE_ORDER_GIVEN (3) 210 u_short status; 211 #define SYMBIOS_SCAM_UNKNOWN (0) 212 #define SYMBIOS_SCAM_DEVICE_NOT_FOUND (1) 213 #define SYMBIOS_SCAM_ID_NOT_SET (2) 214 #define SYMBIOS_SCAM_ID_VALID (3) 215 u_char target_id; 216 u_char rsvd; 217 } scam[4]; 218 219 u_char spare_devices[15*8]; 220 u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */ 221 }; 222 typedef struct Symbios_nvram Symbios_nvram; 223 typedef struct Symbios_host Symbios_host; 224 typedef struct Symbios_target Symbios_target; 225 typedef struct Symbios_scam Symbios_scam; 226 227 /* 228 * Tekram NvRAM data format. 229 */ 230 #define TEKRAM_NVRAM_SIZE 64 231 #define TEKRAM_93C46_NVRAM_ADDRESS 0 232 #define TEKRAM_24C16_NVRAM_ADDRESS 0x40 233 234 struct Tekram_nvram { 235 struct Tekram_target { 236 u_char flags; 237 #define TEKRAM_PARITY_CHECK (1) 238 #define TEKRAM_SYNC_NEGO (1<<1) 239 #define TEKRAM_DISCONNECT_ENABLE (1<<2) 240 #define TEKRAM_START_CMD (1<<3) 241 #define TEKRAM_TAGGED_COMMANDS (1<<4) 242 #define TEKRAM_WIDE_NEGO (1<<5) 243 u_char sync_index; 244 u_short word2; 245 } target[16]; 246 u_char host_id; 247 u_char flags; 248 #define TEKRAM_MORE_THAN_2_DRIVES (1) 249 #define TEKRAM_DRIVES_SUP_1GB (1<<1) 250 #define TEKRAM_RESET_ON_POWER_ON (1<<2) 251 #define TEKRAM_ACTIVE_NEGATION (1<<3) 252 #define TEKRAM_IMMEDIATE_SEEK (1<<4) 253 #define TEKRAM_SCAN_LUNS (1<<5) 254 #define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; 1: boot device; 2:all */ 255 u_char boot_delay_index; 256 u_char max_tags_index; 257 u_short flags1; 258 #define TEKRAM_F2_F6_ENABLED (1) 259 u_short spare[29]; 260 }; 261 typedef struct Tekram_nvram Tekram_nvram; 262 typedef struct Tekram_target Tekram_target; 263 264 /* 265 * SYM53C8XX IO register data structure. 266 */ 267 struct sym_reg { 268 /*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */ 269 270 /*01*/ u8 nc_scntl1; /* no reset */ 271 #define ISCON 0x10 /* connected to scsi */ 272 #define CRST 0x08 /* force reset */ 273 #define IARB 0x02 /* immediate arbitration */ 274 275 /*02*/ u8 nc_scntl2; /* no disconnect expected */ 276 #define SDU 0x80 /* cmd: disconnect will raise error */ 277 #define CHM 0x40 /* sta: chained mode */ 278 #define WSS 0x08 /* sta: wide scsi send [W]*/ 279 #define WSR 0x01 /* sta: wide scsi received [W]*/ 280 281 /*03*/ u8 nc_scntl3; /* cnf system clock dependent */ 282 #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 283 #define ULTRA 0x80 /* cmd: ULTRA enable */ 284 /* bits 0-2, 7 rsvd for C1010 */ 285 286 /*04*/ u8 nc_scid; /* cnf host adapter scsi address */ 287 #define RRE 0x40 /* r/w:e enable response to resel. */ 288 #define SRE 0x20 /* r/w:e enable response to select */ 289 290 /*05*/ u8 nc_sxfer; /* ### Sync speed and count */ 291 /* bits 6-7 rsvd for C1010 */ 292 293 /*06*/ u8 nc_sdid; /* ### Destination-ID */ 294 295 /*07*/ u8 nc_gpreg; /* ??? IO-Pins */ 296 297 /*08*/ u8 nc_sfbr; /* ### First byte received */ 298 299 /*09*/ u8 nc_socl; 300 #define CREQ 0x80 /* r/w: SCSI-REQ */ 301 #define CACK 0x40 /* r/w: SCSI-ACK */ 302 #define CBSY 0x20 /* r/w: SCSI-BSY */ 303 #define CSEL 0x10 /* r/w: SCSI-SEL */ 304 #define CATN 0x08 /* r/w: SCSI-ATN */ 305 #define CMSG 0x04 /* r/w: SCSI-MSG */ 306 #define CC_D 0x02 /* r/w: SCSI-C_D */ 307 #define CI_O 0x01 /* r/w: SCSI-I_O */ 308 309 /*0a*/ u8 nc_ssid; 310 311 /*0b*/ u8 nc_sbcl; 312 313 /*0c*/ u8 nc_dstat; 314 #define DFE 0x80 /* sta: dma fifo empty */ 315 #define MDPE 0x40 /* int: master data parity error */ 316 #define BF 0x20 /* int: script: bus fault */ 317 #define ABRT 0x10 /* int: script: command aborted */ 318 #define SSI 0x08 /* int: script: single step */ 319 #define SIR 0x04 /* int: script: interrupt instruct. */ 320 #define IID 0x01 /* int: script: illegal instruct. */ 321 322 /*0d*/ u8 nc_sstat0; 323 #define ILF 0x80 /* sta: data in SIDL register lsb */ 324 #define ORF 0x40 /* sta: data in SODR register lsb */ 325 #define OLF 0x20 /* sta: data in SODL register lsb */ 326 #define AIP 0x10 /* sta: arbitration in progress */ 327 #define LOA 0x08 /* sta: arbitration lost */ 328 #define WOA 0x04 /* sta: arbitration won */ 329 #define IRST 0x02 /* sta: scsi reset signal */ 330 #define SDP 0x01 /* sta: scsi parity signal */ 331 332 /*0e*/ u8 nc_sstat1; 333 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 334 335 /*0f*/ u8 nc_sstat2; 336 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 337 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 338 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 339 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ 340 #define LDSC 0x02 /* sta: disconnect & reconnect */ 341 342 /*10*/ u8 nc_dsa; /* --> Base page */ 343 /*11*/ u8 nc_dsa1; 344 /*12*/ u8 nc_dsa2; 345 /*13*/ u8 nc_dsa3; 346 347 /*14*/ u8 nc_istat; /* --> Main Command and status */ 348 #define CABRT 0x80 /* cmd: abort current operation */ 349 #define SRST 0x40 /* mod: reset chip */ 350 #define SIGP 0x20 /* r/w: message from host to script */ 351 #define SEM 0x10 /* r/w: message between host + script */ 352 #define CON 0x08 /* sta: connected to scsi */ 353 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 354 #define SIP 0x02 /* sta: scsi-interrupt */ 355 #define DIP 0x01 /* sta: host/script interrupt */ 356 357 /*15*/ u8 nc_istat1; /* 896 only */ 358 /*16*/ u8 nc_mbox0; /* 896 only */ 359 /*17*/ u8 nc_mbox1; /* 896 only */ 360 361 /*18*/ u8 nc_ctest0; 362 /*19*/ u8 nc_ctest1; 363 364 /*1a*/ u8 nc_ctest2; 365 #define CSIGP 0x40 366 /* bits 0-2,7 rsvd for C1010 */ 367 368 /*1b*/ u8 nc_ctest3; 369 #define FLF 0x08 /* cmd: flush dma fifo */ 370 #define CLF 0x04 /* cmd: clear dma fifo */ 371 #define FM 0x02 /* mod: fetch pin mode */ 372 #define WRIE 0x01 /* mod: write and invalidate enable */ 373 /* bits 4-7 rsvd for C1010 */ 374 375 /*1c*/ u32 nc_temp; /* ### Temporary stack */ 376 377 /*20*/ u8 nc_dfifo; 378 /*21*/ u8 nc_ctest4; 379 #define BDIS 0x80 /* mod: burst disable */ 380 #define MPEE 0x08 /* mod: master parity error enable */ 381 382 /*22*/ u8 nc_ctest5; 383 #define DFS 0x20 /* mod: dma fifo size */ 384 /* bits 0-1, 3-7 rsvd for C1010 */ 385 386 /*23*/ u8 nc_ctest6; 387 388 /*24*/ u32 nc_dbc; /* ### Byte count and command */ 389 /*28*/ u32 nc_dnad; /* ### Next command register */ 390 /*2c*/ u32 nc_dsp; /* --> Script Pointer */ 391 /*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */ 392 393 /*34*/ u8 nc_scratcha; /* Temporary register a */ 394 /*35*/ u8 nc_scratcha1; 395 /*36*/ u8 nc_scratcha2; 396 /*37*/ u8 nc_scratcha3; 397 398 /*38*/ u8 nc_dmode; 399 #define BL_2 0x80 /* mod: burst length shift value +2 */ 400 #define BL_1 0x40 /* mod: burst length shift value +1 */ 401 #define ERL 0x08 /* mod: enable read line */ 402 #define ERMP 0x04 /* mod: enable read multiple */ 403 #define BOF 0x02 /* mod: burst op code fetch */ 404 405 /*39*/ u8 nc_dien; 406 /*3a*/ u8 nc_sbr; 407 408 /*3b*/ u8 nc_dcntl; /* --> Script execution control */ 409 #define CLSE 0x80 /* mod: cache line size enable */ 410 #define PFF 0x40 /* cmd: pre-fetch flush */ 411 #define PFEN 0x20 /* mod: pre-fetch enable */ 412 #define SSM 0x10 /* mod: single step mode */ 413 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 414 #define STD 0x04 /* cmd: start dma mode */ 415 #define IRQD 0x02 /* mod: irq disable */ 416 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 417 /* bits 0-1 rsvd for C1010 */ 418 419 /*3c*/ u32 nc_adder; 420 421 /*40*/ u16 nc_sien; /* -->: interrupt enable */ 422 /*42*/ u16 nc_sist; /* <--: interrupt status */ 423 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ 424 #define STO 0x0400/* sta: timeout (select) */ 425 #define GEN 0x0200/* sta: timeout (general) */ 426 #define HTH 0x0100/* sta: timeout (handshake) */ 427 #define MA 0x80 /* sta: phase mismatch */ 428 #define CMP 0x40 /* sta: arbitration complete */ 429 #define SEL 0x20 /* sta: selected by another device */ 430 #define RSL 0x10 /* sta: reselected by another device*/ 431 #define SGE 0x08 /* sta: gross error (over/underflow)*/ 432 #define UDC 0x04 /* sta: unexpected disconnect */ 433 #define RST 0x02 /* sta: scsi bus reset detected */ 434 #define PAR 0x01 /* sta: scsi parity error */ 435 436 /*44*/ u8 nc_slpar; 437 /*45*/ u8 nc_swide; 438 /*46*/ u8 nc_macntl; 439 /*47*/ u8 nc_gpcntl; 440 /*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/ 441 /*49*/ u8 nc_stime1; /* cmd: timeout user defined */ 442 /*4a*/ u16 nc_respid; /* sta: Reselect-IDs */ 443 444 /*4c*/ u8 nc_stest0; 445 446 /*4d*/ u8 nc_stest1; 447 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ 448 #define DBLEN 0x08 /* clock doubler running */ 449 #define DBLSEL 0x04 /* clock doubler selected */ 450 451 452 /*4e*/ u8 nc_stest2; 453 #define ROF 0x40 /* reset scsi offset (after gross error!) */ 454 #define EXT 0x02 /* extended filtering */ 455 456 /*4f*/ u8 nc_stest3; 457 #define TE 0x80 /* c: tolerAnt enable */ 458 #define HSC 0x20 /* c: Halt SCSI Clock */ 459 #define CSF 0x02 /* c: clear scsi fifo */ 460 461 /*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */ 462 /*52*/ u8 nc_stest4; 463 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 464 #define SMODE_HVD 0x40 /* High Voltage Differential */ 465 #define SMODE_SE 0x80 /* Single Ended */ 466 #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 467 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 468 /* bits 0-5 rsvd for C1010 */ 469 470 /*53*/ u8 nc_53_; 471 /*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */ 472 /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */ 473 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */ 474 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */ 475 #define ENNDJ 0x20 /* Enable Non Data PM Jump */ 476 #define DISFC 0x10 /* Disable Auto FIFO Clear */ 477 #define DILS 0x02 /* Disable Internal Load/Store */ 478 #define DPR 0x01 /* Disable Pipe Req */ 479 480 /*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */ 481 #define ZMOD 0x80 /* High Impedance Mode */ 482 #define DDAC 0x08 /* Disable Dual Address Cycle */ 483 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */ 484 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */ 485 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */ 486 487 /*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */ 488 /*5a*/ u16 nc_5a_; 489 490 /*5c*/ u8 nc_scr0; /* Working register B */ 491 /*5d*/ u8 nc_scr1; 492 /*5e*/ u8 nc_scr2; 493 /*5f*/ u8 nc_scr3; 494 495 /*60*/ u8 nc_scrx[64]; /* Working register C-R */ 496 /*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */ 497 /*a4*/ u32 nc_mmws; /* Memory Move Write Selector */ 498 /*a8*/ u32 nc_sfs; /* Script Fetch Selector */ 499 /*ac*/ u32 nc_drs; /* DSA Relative Selector */ 500 /*b0*/ u32 nc_sbms; /* Static Block Move Selector */ 501 /*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */ 502 /*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */ 503 /*bc*/ u16 nc_scntl4; /* C1010 only */ 504 #define U3EN 0x80 /* Enable Ultra 3 */ 505 #define AIPCKEN 0x40 /* AIP checking enable */ 506 /* Also enable AIP generation on C10-33*/ 507 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT edge */ 508 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST edge */ 509 #define XCLKS_DT 0x02 /* Extra clock of data set on DT edge */ 510 #define XCLKS_ST 0x01 /* Extra clock of data set on ST edge */ 511 /*be*/ u8 nc_aipcntl0; /* AIP Control 0 C1010 only */ 512 /*bf*/ u8 nc_aipcntl1; /* AIP Control 1 C1010 only */ 513 #define DISAIP 0x08 /* Disable AIP generation C10-66 only */ 514 /*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */ 515 /*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */ 516 /*c8*/ u8 nc_rbc; /* Remaining Byte Count */ 517 /*c9*/ u8 nc_rbc1; 518 /*ca*/ u8 nc_rbc2; 519 /*cb*/ u8 nc_rbc3; 520 521 /*cc*/ u8 nc_ua; /* Updated Address */ 522 /*cd*/ u8 nc_ua1; 523 /*ce*/ u8 nc_ua2; 524 /*cf*/ u8 nc_ua3; 525 /*d0*/ u32 nc_esa; /* Entry Storage Address */ 526 /*d4*/ u8 nc_ia; /* Instruction Address */ 527 /*d5*/ u8 nc_ia1; 528 /*d6*/ u8 nc_ia2; 529 /*d7*/ u8 nc_ia3; 530 /*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */ 531 /*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */ 532 /* Following for C1010 only */ 533 /*e0*/ u16 nc_crcpad; /* CRC Value */ 534 /*e2*/ u8 nc_crccntl0; /* CRC control register */ 535 #define SNDCRC 0x10 /* Send CRC Request */ 536 /*e3*/ u8 nc_crccntl1; /* CRC control register */ 537 /*e4*/ u32 nc_crcdata; /* CRC data register */ 538 /*e8*/ u32 nc_e8_; 539 /*ec*/ u32 nc_ec_; 540 /*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */ 541 }; 542 543 /*----------------------------------------------------------- 544 * 545 * Utility macros for the script. 546 * 547 *----------------------------------------------------------- 548 */ 549 550 #define REGJ(p,r) (offsetof(struct sym_reg, p ## r)) 551 #define REG(r) REGJ (nc_, r) 552 553 typedef u32 symcmd; 554 555 /*----------------------------------------------------------- 556 * 557 * SCSI phases 558 * 559 *----------------------------------------------------------- 560 */ 561 562 #define SCR_DATA_OUT 0x00000000 563 #define SCR_DATA_IN 0x01000000 564 #define SCR_COMMAND 0x02000000 565 #define SCR_STATUS 0x03000000 566 #define SCR_DT_DATA_OUT 0x04000000 567 #define SCR_DT_DATA_IN 0x05000000 568 #define SCR_MSG_OUT 0x06000000 569 #define SCR_MSG_IN 0x07000000 570 /* DT phases are illegal for non Ultra3 mode */ 571 #define SCR_ILG_OUT 0x04000000 572 #define SCR_ILG_IN 0x05000000 573 574 /*----------------------------------------------------------- 575 * 576 * Data transfer via SCSI. 577 * 578 *----------------------------------------------------------- 579 * 580 * MOVE_ABS (LEN) 581 * <<start address>> 582 * 583 * MOVE_IND (LEN) 584 * <<dnad_offset>> 585 * 586 * MOVE_TBL 587 * <<dnad_offset>> 588 * 589 *----------------------------------------------------------- 590 */ 591 592 #define OPC_MOVE 0x08000000 593 594 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) 595 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) 596 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) 597 598 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) 599 #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) 600 #define SCR_CHMOV_TBL (0x10000000) 601 602 struct sym_tblmove { 603 u32 size; 604 u32 addr; 605 }; 606 607 /*----------------------------------------------------------- 608 * 609 * Selection 610 * 611 *----------------------------------------------------------- 612 * 613 * SEL_ABS | SCR_ID (0..15) [ | REL_JMP] 614 * <<alternate_address>> 615 * 616 * SEL_TBL | << dnad_offset>> [ | REL_JMP] 617 * <<alternate_address>> 618 * 619 *----------------------------------------------------------- 620 */ 621 622 #define SCR_SEL_ABS 0x40000000 623 #define SCR_SEL_ABS_ATN 0x41000000 624 #define SCR_SEL_TBL 0x42000000 625 #define SCR_SEL_TBL_ATN 0x43000000 626 627 struct sym_tblsel { 628 u_char sel_scntl4; /* C1010 only */ 629 u_char sel_sxfer; 630 u_char sel_id; 631 u_char sel_scntl3; 632 }; 633 634 #define SCR_JMP_REL 0x04000000 635 #define SCR_ID(id) (((u32)(id)) << 16) 636 637 /*----------------------------------------------------------- 638 * 639 * Waiting for Disconnect or Reselect 640 * 641 *----------------------------------------------------------- 642 * 643 * WAIT_DISC 644 * dummy: <<alternate_address>> 645 * 646 * WAIT_RESEL 647 * <<alternate_address>> 648 * 649 *----------------------------------------------------------- 650 */ 651 652 #define SCR_WAIT_DISC 0x48000000 653 #define SCR_WAIT_RESEL 0x50000000 654 655 /*----------------------------------------------------------- 656 * 657 * Bit Set / Reset 658 * 659 *----------------------------------------------------------- 660 * 661 * SET (flags {|.. }) 662 * 663 * CLR (flags {|.. }) 664 * 665 *----------------------------------------------------------- 666 */ 667 668 #define SCR_SET(f) (0x58000000 | (f)) 669 #define SCR_CLR(f) (0x60000000 | (f)) 670 671 #define SCR_CARRY 0x00000400 672 #define SCR_TRG 0x00000200 673 #define SCR_ACK 0x00000040 674 #define SCR_ATN 0x00000008 675 676 /*----------------------------------------------------------- 677 * 678 * Memory to memory move 679 * 680 *----------------------------------------------------------- 681 * 682 * COPY (bytecount) 683 * << source_address >> 684 * << destination_address >> 685 * 686 * SCR_COPY sets the NO FLUSH option by default. 687 * SCR_COPY_F does not set this option. 688 * 689 * For chips which do not support this option, 690 * sym_copy_and_bind() will remove this bit. 691 * 692 *----------------------------------------------------------- 693 */ 694 695 #define SCR_NO_FLUSH 0x01000000 696 697 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 698 #define SCR_COPY_F(n) (0xc0000000 | (n)) 699 700 /*----------------------------------------------------------- 701 * 702 * Register move and binary operations 703 * 704 *----------------------------------------------------------- 705 * 706 * SFBR_REG (reg, op, data) reg = SFBR op data 707 * << 0 >> 708 * 709 * REG_SFBR (reg, op, data) SFBR = reg op data 710 * << 0 >> 711 * 712 * REG_REG (reg, op, data) reg = reg op data 713 * << 0 >> 714 * 715 *----------------------------------------------------------- 716 * 717 * On 825A, 875, 895 and 896 chips the content 718 * of SFBR register can be used as data (SCR_SFBR_DATA). 719 * The 896 has additionnal IO registers starting at 720 * offset 0x80. Bit 7 of register offset is stored in 721 * bit 7 of the SCRIPTS instruction first DWORD. 722 * 723 *----------------------------------------------------------- 724 */ 725 726 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80)) 727 728 #define SCR_SFBR_REG(reg,op,data) \ 729 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 730 731 #define SCR_REG_SFBR(reg,op,data) \ 732 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 733 734 #define SCR_REG_REG(reg,op,data) \ 735 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 736 737 #define SCR_LOAD 0x00000000 738 #define SCR_SHL 0x01000000 739 #define SCR_OR 0x02000000 740 #define SCR_XOR 0x03000000 741 #define SCR_AND 0x04000000 742 #define SCR_SHR 0x05000000 743 #define SCR_ADD 0x06000000 744 #define SCR_ADDC 0x07000000 745 746 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ 747 748 /*----------------------------------------------------------- 749 * 750 * FROM_REG (reg) SFBR = reg 751 * << 0 >> 752 * 753 * TO_REG (reg) reg = SFBR 754 * << 0 >> 755 * 756 * LOAD_REG (reg, data) reg = <data> 757 * << 0 >> 758 * 759 * LOAD_SFBR(data) SFBR = <data> 760 * << 0 >> 761 * 762 *----------------------------------------------------------- 763 */ 764 765 #define SCR_FROM_REG(reg) \ 766 SCR_REG_SFBR(reg,SCR_OR,0) 767 768 #define SCR_TO_REG(reg) \ 769 SCR_SFBR_REG(reg,SCR_OR,0) 770 771 #define SCR_LOAD_REG(reg,data) \ 772 SCR_REG_REG(reg,SCR_LOAD,data) 773 774 #define SCR_LOAD_SFBR(data) \ 775 (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 776 777 /*----------------------------------------------------------- 778 * 779 * LOAD from memory to register. 780 * STORE from register to memory. 781 * 782 * Only supported by 810A, 860, 825A, 875, 895 and 896. 783 * 784 *----------------------------------------------------------- 785 * 786 * LOAD_ABS (LEN) 787 * <<start address>> 788 * 789 * LOAD_REL (LEN) (DSA relative) 790 * <<dsa_offset>> 791 * 792 *----------------------------------------------------------- 793 */ 794 795 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) 796 #define SCR_NO_FLUSH2 0x02000000 797 #define SCR_DSA_REL2 0x10000000 798 799 #define SCR_LOAD_R(reg, how, n) \ 800 (0xe1000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n)) 801 802 #define SCR_STORE_R(reg, how, n) \ 803 (0xe0000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n)) 804 805 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) 806 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) 807 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) 808 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) 809 810 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) 811 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) 812 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) 813 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) 814 815 /*----------------------------------------------------------- 816 * 817 * Waiting for Disconnect or Reselect 818 * 819 *----------------------------------------------------------- 820 * 821 * JUMP [ | IFTRUE/IFFALSE ( ... ) ] 822 * <<address>> 823 * 824 * JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 825 * <<distance>> 826 * 827 * CALL [ | IFTRUE/IFFALSE ( ... ) ] 828 * <<address>> 829 * 830 * CALLR [ | IFTRUE/IFFALSE ( ... ) ] 831 * <<distance>> 832 * 833 * RETURN [ | IFTRUE/IFFALSE ( ... ) ] 834 * <<dummy>> 835 * 836 * INT [ | IFTRUE/IFFALSE ( ... ) ] 837 * <<ident>> 838 * 839 * INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 840 * <<ident>> 841 * 842 * Conditions: 843 * WHEN (phase) 844 * IF (phase) 845 * CARRYSET 846 * DATA (data, mask) 847 * 848 *----------------------------------------------------------- 849 */ 850 851 #define SCR_NO_OP 0x80000000 852 #define SCR_JUMP 0x80080000 853 #define SCR_JUMP64 0x80480000 854 #define SCR_JUMPR 0x80880000 855 #define SCR_CALL 0x88080000 856 #define SCR_CALLR 0x88880000 857 #define SCR_RETURN 0x90080000 858 #define SCR_INT 0x98080000 859 #define SCR_INT_FLY 0x98180000 860 861 #define IFFALSE(arg) (0x00080000 | (arg)) 862 #define IFTRUE(arg) (0x00000000 | (arg)) 863 864 #define WHEN(phase) (0x00030000 | (phase)) 865 #define IF(phase) (0x00020000 | (phase)) 866 867 #define DATA(D) (0x00040000 | ((D) & 0xff)) 868 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 869 870 #define CARRYSET (0x00200000) 871 872 /*----------------------------------------------------------- 873 * 874 * SCSI constants. 875 * 876 *----------------------------------------------------------- 877 */ 878 879 /* 880 * Messages 881 */ 882 883 #define M_COMPLETE (0x00) 884 #define M_EXTENDED (0x01) 885 #define M_SAVE_DP (0x02) 886 #define M_RESTORE_DP (0x03) 887 #define M_DISCONNECT (0x04) 888 #define M_ID_ERROR (0x05) 889 #define M_ABORT (0x06) 890 #define M_REJECT (0x07) 891 #define M_NOOP (0x08) 892 #define M_PARITY (0x09) 893 #define M_LCOMPLETE (0x0a) 894 #define M_FCOMPLETE (0x0b) 895 #define M_RESET (0x0c) 896 #define M_ABORT_TAG (0x0d) 897 #define M_CLEAR_QUEUE (0x0e) 898 #define M_INIT_REC (0x0f) 899 #define M_REL_REC (0x10) 900 #define M_TERMINATE (0x11) 901 #define M_SIMPLE_TAG (0x20) 902 #define M_HEAD_TAG (0x21) 903 #define M_ORDERED_TAG (0x22) 904 #define M_IGN_RESIDUE (0x23) 905 #define M_IDENTIFY (0x80) 906 907 #define M_X_MODIFY_DP (0x00) 908 #define M_X_SYNC_REQ (0x01) 909 #define M_X_WIDE_REQ (0x03) 910 #define M_X_PPR_REQ (0x04) 911 912 /* 913 * PPR protocol options 914 */ 915 #define PPR_OPT_IU (0x01) 916 #define PPR_OPT_DT (0x02) 917 #define PPR_OPT_QAS (0x04) 918 #define PPR_OPT_MASK (0x07) 919 920 /* 921 * Status 922 */ 923 924 #define S_GOOD (0x00) 925 #define S_CHECK_COND (0x02) 926 #define S_COND_MET (0x04) 927 #define S_BUSY (0x08) 928 #define S_INT (0x10) 929 #define S_INT_COND_MET (0x14) 930 #define S_CONFLICT (0x18) 931 #define S_TERMINATED (0x20) 932 #define S_QUEUE_FULL (0x28) 933 #define S_ILLEGAL (0xff) 934 935 #endif /* defined SYM_DEFS_H */ 936