1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2015 Bjoern A. Zeeb 5 * Copyright (c) 2020 Denis Salopek 6 * 7 * This software was developed by SRI International and the University of 8 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 9 * ("MRC2"), as part of the DARPA MRC research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* $FreeBSD$ */ 34 35 #define DEFAULT_ETHER_ADDRESS "\02SUME\00" 36 #define SUME_ETH_DEVICE_NAME "sume" 37 #define MAX_IFC_NAME_LEN 8 38 39 #define SUME_NPORTS 4 40 41 #define SUME_IOCTL_CMD_WRITE_REG (SIOCGPRIVATE_0) 42 #define SUME_IOCTL_CMD_READ_REG (SIOCGPRIVATE_1) 43 44 #define SUME_LOCK(adapter) mtx_lock(&adapter->lock); 45 #define SUME_UNLOCK(adapter) mtx_unlock(&adapter->lock); 46 47 /* Currently SUME only uses 2 fixed channels for all port traffic and regs. */ 48 #define SUME_RIFFA_CHANNEL_DATA 0 49 #define SUME_RIFFA_CHANNEL_REG 1 50 #define SUME_RIFFA_CHANNELS 2 51 52 /* RIFFA constants. */ 53 #define RIFFA_MAX_CHNLS 12 54 #define RIFFA_MAX_BUS_WIDTH_PARAM 4 55 #define RIFFA_SG_BUF_SIZE (4*1024) 56 #define RIFFA_SG_ELEMS 200 57 58 /* RIFFA register offsets. */ 59 #define RIFFA_RX_SG_LEN_REG_OFF 0x0 60 #define RIFFA_RX_SG_ADDR_LO_REG_OFF 0x1 61 #define RIFFA_RX_SG_ADDR_HI_REG_OFF 0x2 62 #define RIFFA_RX_LEN_REG_OFF 0x3 63 #define RIFFA_RX_OFFLAST_REG_OFF 0x4 64 #define RIFFA_TX_SG_LEN_REG_OFF 0x5 65 #define RIFFA_TX_SG_ADDR_LO_REG_OFF 0x6 66 #define RIFFA_TX_SG_ADDR_HI_REG_OFF 0x7 67 #define RIFFA_TX_LEN_REG_OFF 0x8 68 #define RIFFA_TX_OFFLAST_REG_OFF 0x9 69 #define RIFFA_INFO_REG_OFF 0xA 70 #define RIFFA_IRQ_REG0_OFF 0xB 71 #define RIFFA_IRQ_REG1_OFF 0xC 72 #define RIFFA_RX_TNFR_LEN_REG_OFF 0xD 73 #define RIFFA_TX_TNFR_LEN_REG_OFF 0xE 74 75 #define RIFFA_CHNL_REG(c, o) ((c << 4) + o) 76 77 /* 78 * RIFFA state machine; 79 * rather than using complex circular buffers for 1 transaction. 80 */ 81 #define SUME_RIFFA_CHAN_STATE_IDLE 0x01 82 #define SUME_RIFFA_CHAN_STATE_READY 0x02 83 #define SUME_RIFFA_CHAN_STATE_READ 0x04 84 #define SUME_RIFFA_CHAN_STATE_LEN 0x08 85 86 /* Accessor macros. */ 87 #define SUME_OFFLAST ((0 << 1) | (1 & 0x01)) 88 #define SUME_RIFFA_LAST(offlast) ((offlast) & 0x01) 89 #define SUME_RIFFA_OFFSET(offlast) ((uint64_t)((offlast) >> 1) << 2) 90 #define SUME_RIFFA_LEN(len) ((uint64_t)(len) << 2) 91 92 #define SUME_RIFFA_LO_ADDR(addr) (addr & 0xFFFFFFFF) 93 #define SUME_RIFFA_HI_ADDR(addr) ((addr >> 32) & 0xFFFFFFFF) 94 95 /* Vector bits. */ 96 #define SUME_MSI_RXQUE (1 << 0) 97 #define SUME_MSI_RXBUF (1 << 1) 98 #define SUME_MSI_RXDONE (1 << 2) 99 #define SUME_MSI_TXBUF (1 << 3) 100 #define SUME_MSI_TXDONE (1 << 4) 101 102 /* Invalid vector. */ 103 #define SUME_INVALID_VECT 0xc0000000 104 105 /* Module register data (packet counters, link status...) */ 106 #define SUME_MOD0_REG_BASE 0x44040000 107 #define SUME_MOD_REG(port) (SUME_MOD0_REG_BASE + 0x10000 * port) 108 109 #define SUME_RESET_OFFSET 0x8 110 #define SUME_PKTIN_OFFSET 0x18 111 #define SUME_PKTOUT_OFFSET 0x1c 112 #define SUME_STATUS_OFFSET 0x48 113 114 #define SUME_RESET_ADDR(p) (SUME_MOD_REG(p) + SUME_RESET_OFFSET) 115 #define SUME_STAT_RX_ADDR(p) (SUME_MOD_REG(p) + SUME_PKTIN_OFFSET) 116 #define SUME_STAT_TX_ADDR(p) (SUME_MOD_REG(p) + SUME_PKTOUT_OFFSET) 117 #define SUME_STATUS_ADDR(p) (SUME_MOD_REG(p) + SUME_STATUS_OFFSET) 118 119 #define SUME_LINK_STATUS(val) ((val >> 12) & 0x1) 120 121 /* Various bits and pieces. */ 122 #define SUME_RIFFA_MAGIC 0xcafe 123 #define SUME_MR_WRITE 0x1f 124 #define SUME_MR_READ 0x00 125 #define SUME_INIT_RTAG -3 126 #define SUME_DPORT_MASK 0xaa 127 #define SUME_MIN_PKT_SIZE (ETHER_MIN_LEN - ETHER_CRC_LEN) 128 129 struct irq { 130 uint32_t rid; 131 struct resource *res; 132 void *tag; 133 } __aligned(CACHE_LINE_SIZE); 134 135 struct nf_stats { 136 uint64_t hw_rx_packets; 137 uint64_t hw_tx_packets; 138 uint64_t ifc_down_bytes; 139 uint64_t ifc_down_packets; 140 uint64_t rx_bytes; 141 uint64_t rx_dropped; 142 uint64_t rx_packets; 143 uint64_t tx_bytes; 144 uint64_t tx_dropped; 145 uint64_t tx_packets; 146 }; 147 148 struct riffa_chnl_dir { 149 uint32_t state; 150 bus_dma_tag_t ch_tag; 151 bus_dmamap_t ch_map; 152 char *buf_addr; /* bouncebuf addresses+len. */ 153 bus_addr_t buf_hw_addr; /* -- " -- mapped. */ 154 uint32_t num_sg; 155 uint32_t event; /* Used for modreg r/w */ 156 uint32_t len; /* words */ 157 uint32_t offlast; 158 uint32_t recovery; 159 uint32_t rtag; 160 }; 161 162 struct sume_ifreq { 163 uint32_t addr; 164 uint32_t val; 165 }; 166 167 struct nf_priv { 168 struct sume_adapter *adapter; 169 struct ifmedia media; 170 struct nf_stats stats; 171 uint32_t unit; 172 uint32_t port; 173 uint32_t link_up; 174 }; 175 176 struct sume_adapter { 177 struct mtx lock; 178 uint32_t running; 179 uint32_t rid; 180 struct riffa_chnl_dir **recv; 181 struct riffa_chnl_dir **send; 182 device_t dev; 183 struct ifnet *ifp[SUME_NPORTS]; 184 struct resource *bar0_addr; 185 bus_space_tag_t bt; 186 bus_space_handle_t bh; 187 bus_size_t bar0_len; 188 struct irq irq; 189 struct callout timer; 190 struct task stat_task; 191 struct taskqueue *tq; 192 uint64_t bytes_err; 193 uint64_t packets_err; 194 uint32_t last_ifc; 195 uint32_t num_sg; 196 uint32_t sg_buf_size; 197 uint32_t sume_debug; 198 uint32_t wd_counter; 199 }; 200 201 /* SUME metadata: 202 * sport - not used for RX. For TX, set to 0x02, 0x08, 0x20, 0x80, depending on 203 * the sending interface (nf0, nf1, nf2 or nf3). 204 * dport - For RX, is set to 0x02, 0x08, 0x20, 0x80, depending on the receiving 205 * interface (nf0, nf1, nf2 or nf3). For TX, set to 0x01, 0x04, 0x10, 0x40, 206 * depending on the sending HW interface (nf0, nf1, nf2 or nf3). 207 * plen - length of the send/receive packet data (in bytes) 208 * magic - SUME hardcoded magic number which should be 0xcafe 209 * t1, t1 - could be used for timestamping by SUME 210 */ 211 struct nf_metadata { 212 uint16_t sport; 213 uint16_t dport; 214 uint16_t plen; 215 uint16_t magic; 216 uint32_t t1; 217 uint32_t t2; 218 }; 219 220 /* Used for ioctl communication with the rwaxi program used to read/write SUME 221 * internally defined register data. 222 * addr - address of the SUME module register to read/write 223 * val - value to write/read to/from the register 224 * rtag - returned on read: transaction tag, for syncronization 225 * optype - 0x1f when writing, 0x00 for reading 226 */ 227 struct nf_regop_data { 228 uint32_t addr; 229 uint32_t val; 230 uint32_t rtag; 231 uint32_t optype; 232 }; 233 234 /* Our bouncebuffer "descriptor". This holds our physical address (lower and 235 * upper values) of the beginning of the DMA data to RX/TX. The len is number 236 * of words to transmit. 237 */ 238 struct nf_bb_desc { 239 uint32_t lower; 240 uint32_t upper; 241 uint32_t len; 242 }; 243