1 /* $NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* $FreeBSD$ */ 33 34 /* 35 * Sundance Technology PCI vendor ID 36 */ 37 #define VENDOR_SUNDANCETI 0x13f0 38 39 /* 40 * Tamarack Microelectronics PCI vendor ID 41 */ 42 #define VENDOR_TAMARACK 0x143d 43 44 /* 45 * D-Link Systems PCI vendor ID 46 */ 47 #define VENDOR_DLINK 0x1186 48 49 /* 50 * Antares Microsystems PCI vendor ID 51 */ 52 #define VENDOR_ANTARES 0x1754 53 54 /* 55 * Sundance Technology device ID 56 */ 57 #define DEVICEID_SUNDANCETI_ST1023 0x1023 58 #define DEVICEID_SUNDANCETI_ST2021 0x2021 59 #define DEVICEID_TAMARACK_TC9021 0x1021 60 #define DEVICEID_TAMARACK_TC9021_ALT 0x9021 61 62 /* 63 * D-Link Systems device ID 64 */ 65 #define DEVICEID_DLINK_DL4000 0x4000 66 67 /* 68 * Antares Microsystems device ID 69 */ 70 #define DEVICEID_ANTARES_TC9021 0x1021 71 72 /* 73 * Register description for the Sundance Tech. TC9021 10/100/1000 74 * Ethernet controller. 75 * 76 * Note that while DMA addresses are all in 64-bit fields, only 77 * the lower 40 bits of a DMA address are valid. 78 */ 79 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 80 #define STGE_DMA_MAXADDR BUS_SPACE_MAXADDR 81 #else 82 #define STGE_DMA_MAXADDR 0xFFFFFFFFFF 83 #endif 84 85 /* 86 * Register access macros 87 */ 88 #define CSR_WRITE_4(_sc, reg, val) \ 89 bus_write_4((_sc)->sc_res[0], (reg), (val)) 90 #define CSR_WRITE_2(_sc, reg, val) \ 91 bus_write_2((_sc)->sc_res[0], (reg), (val)) 92 #define CSR_WRITE_1(_sc, reg, val) \ 93 bus_write_1((_sc)->sc_res[0], (reg), (val)) 94 95 #define CSR_READ_4(_sc, reg) \ 96 bus_read_4((_sc)->sc_res[0], (reg)) 97 #define CSR_READ_2(_sc, reg) \ 98 bus_read_2((_sc)->sc_res[0], (reg)) 99 #define CSR_READ_1(_sc, reg) \ 100 bus_read_1((_sc)->sc_res[0], (reg)) 101 102 /* 103 * TC9021 buffer fragment descriptor. 104 */ 105 struct stge_frag { 106 uint64_t frag_word0; /* address, length */ 107 }; 108 109 #define FRAG_ADDR(x) (((uint64_t)(x)) << 0) 110 #define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL) 111 #define FRAG_LEN(x) (((uint64_t)(x)) << 48) 112 #define FRAG_LEN_MASK FRAG_LEN(0xffffULL) 113 114 /* 115 * TC9021 Transmit Frame Descriptor. Note the number of fragments 116 * here is arbitrary, but we can't have any more than 15. 117 */ 118 #define STGE_NTXFRAGS 15 119 struct stge_tfd { 120 uint64_t tfd_next; /* next TFD in list */ 121 uint64_t tfd_control; /* control bits */ 122 /* the buffer fragments */ 123 struct stge_frag tfd_frags[STGE_NTXFRAGS]; 124 }; 125 126 #define TFD_FrameId(x) ((x) << 0) 127 #define TFD_FrameId_MAX 0xffff 128 #define TFD_WordAlign(x) ((x) << 16) 129 #define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ 130 #define TFD_WordAlign_word 2 /* align to word in TxFIFO */ 131 #define TFD_WordAlign_disable 1 /* disable alignment */ 132 #define TFD_TCPChecksumEnable (1ULL << 18) 133 #define TFD_UDPChecksumEnable (1ULL << 19) 134 #define TFD_IPChecksumEnable (1ULL << 20) 135 #define TFD_FcsAppendDisable (1ULL << 21) 136 #define TFD_TxIndicate (1ULL << 22) 137 #define TFD_TxDMAIndicate (1ULL << 23) 138 #define TFD_FragCount(x) ((x) << 24) 139 #define TFD_VLANTagInsert (1ULL << 28) 140 #define TFD_TFDDone (1ULL << 31) 141 #define TFD_VID(x) (((uint64_t)(x)) << 32) 142 #define TFD_CFI (1ULL << 44) 143 #define TFD_UserPriority(x) (((uint64_t)(x)) << 45) 144 145 /* 146 * TC9021 Receive Frame Descriptor. Each RFD has a single fragment 147 * in it, and the chip tells us the beginning and end of the frame. 148 */ 149 struct stge_rfd { 150 uint64_t rfd_next; /* next RFD in list */ 151 uint64_t rfd_status; /* status bits */ 152 struct stge_frag rfd_frag; /* the buffer */ 153 }; 154 155 /* Low word of rfd_status */ 156 #define RFD_RxStatus(x) ((x) & 0xffffffff) 157 #define RFD_RxDMAFrameLen(x) ((x) & 0xffff) 158 #define RFD_RxFIFOOverrun 0x00010000 159 #define RFD_RxRuntFrame 0x00020000 160 #define RFD_RxAlignmentError 0x00040000 161 #define RFD_RxFCSError 0x00080000 162 #define RFD_RxOversizedFrame 0x00100000 163 #define RFD_RxLengthError 0x00200000 164 #define RFD_VLANDetected 0x00400000 165 #define RFD_TCPDetected 0x00800000 166 #define RFD_TCPError 0x01000000 167 #define RFD_UDPDetected 0x02000000 168 #define RFD_UDPError 0x04000000 169 #define RFD_IPDetected 0x08000000 170 #define RFD_IPError 0x10000000 171 #define RFD_FrameStart 0x20000000 172 #define RFD_FrameEnd 0x40000000 173 #define RFD_RFDDone 0x80000000 174 /* High word of rfd_status */ 175 #define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff) 176 177 /* 178 * EEPROM offsets. 179 */ 180 #define STGE_EEPROM_ConfigParam 0x00 181 #define STGE_EEPROM_AsicCtrl 0x01 182 #define STGE_EEPROM_SubSystemVendorId 0x02 183 #define STGE_EEPROM_SubSystemId 0x03 184 #define STGE_EEPROM_LEDMode 0x06 185 #define STGE_EEPROM_StationAddress0 0x10 186 #define STGE_EEPROM_StationAddress1 0x11 187 #define STGE_EEPROM_StationAddress2 0x12 188 189 /* 190 * The TC9021 register space. 191 */ 192 193 #define STGE_DMACtrl 0x00 194 #define DMAC_RxDMAComplete (1U << 3) 195 #define DMAC_RxDMAPollNow (1U << 4) 196 #define DMAC_TxDMAComplete (1U << 11) 197 #define DMAC_TxDMAPollNow (1U << 12) 198 #define DMAC_TxDMAInProg (1U << 15) 199 #define DMAC_RxEarlyDisable (1U << 16) 200 #define DMAC_MWIDisable (1U << 18) 201 #define DMAC_TxWriteBackDisable (1U << 19) 202 #define DMAC_TxBurstLimit(x) ((x) << 20) 203 #define DMAC_TargetAbort (1U << 30) 204 #define DMAC_MasterAbort (1U << 31) 205 206 #define STGE_RxDMAStatus 0x08 207 208 #define STGE_TFDListPtrLo 0x10 209 210 #define STGE_TFDListPtrHi 0x14 211 212 #define STGE_TxDMABurstThresh 0x18 /* 8-bit */ 213 214 #define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */ 215 216 #define STGE_TxDMAPollPeriod 0x1a /* 8-bit, 320ns increments */ 217 218 #define STGE_RFDListPtrLo 0x1c 219 220 #define STGE_RFDListPtrHi 0x20 221 222 #define STGE_RxDMABurstThresh 0x24 /* 8-bit */ 223 224 #define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */ 225 226 #define STGE_RxDMAPollPeriod 0x26 /* 8-bit, 320ns increments */ 227 228 #define STGE_RxDMAIntCtrl 0x28 229 #define RDIC_RxFrameCount(x) ((x) & 0xff) 230 #define RDIC_PriorityThresh(x) ((x) << 10) 231 #define RDIC_RxDMAWaitTime(x) ((x) << 16) 232 /* 233 * Number of receive frames transferred via DMA before a Rx interrupt is issued. 234 */ 235 #define STGE_RXINT_NFRAME_DEFAULT 8 236 #define STGE_RXINT_NFRAME_MIN 1 237 #define STGE_RXINT_NFRAME_MAX 255 238 /* 239 * Maximum amount of time (in 64ns increments) to wait before issuing a Rx 240 * interrupt if number of frames recevied is less than STGE_RXINT_NFRAME 241 * (STGE_RXINT_NFRAME_MIN <= STGE_RXINT_NFRAME <= STGE_RXINT_NFRAME_MAX) 242 */ 243 #define STGE_RXINT_DMAWAIT_DEFAULT 30 /* 30us */ 244 #define STGE_RXINT_DMAWAIT_MIN 0 245 #define STGE_RXINT_DMAWAIT_MAX 4194 246 #define STGE_RXINT_USECS2TICK(x) (((x) * 1000)/64) 247 248 #define STGE_DebugCtrl 0x2c /* 16-bit */ 249 #define DC_GPIO0Ctrl (1U << 0) 250 #define DC_GPIO1Ctrl (1U << 1) 251 #define DC_GPIO0 (1U << 2) 252 #define DC_GPIO1 (1U << 3) 253 254 #define STGE_AsicCtrl 0x30 255 #define AC_ExpRomDisable (1U << 0) 256 #define AC_ExpRomSize (1U << 1) 257 #define AC_PhySpeed10 (1U << 4) 258 #define AC_PhySpeed100 (1U << 5) 259 #define AC_PhySpeed1000 (1U << 6) 260 #define AC_PhyMedia (1U << 7) 261 #define AC_ForcedConfig(x) ((x) << 8) 262 #define AC_ForcedConfig_MASK AC_ForcedConfig(7) 263 #define AC_D3ResetDisable (1U << 11) 264 #define AC_SpeedupMode (1U << 13) 265 #define AC_LEDMode (1U << 14) 266 #define AC_RstOutPolarity (1U << 15) 267 #define AC_GlobalReset (1U << 16) 268 #define AC_RxReset (1U << 17) 269 #define AC_TxReset (1U << 18) 270 #define AC_DMA (1U << 19) 271 #define AC_FIFO (1U << 20) 272 #define AC_Network (1U << 21) 273 #define AC_Host (1U << 22) 274 #define AC_AutoInit (1U << 23) 275 #define AC_RstOut (1U << 24) 276 #define AC_InterruptRequest (1U << 25) 277 #define AC_ResetBusy (1U << 26) 278 #define AC_LEDSpeed (1U << 27) 279 #define AC_LEDModeBit1 (1U << 29) 280 281 #define STGE_FIFOCtrl 0x38 /* 16-bit */ 282 #define FC_RAMTestMode (1U << 0) 283 #define FC_Transmitting (1U << 14) 284 #define FC_Receiving (1U << 15) 285 286 #define STGE_RxEarlyThresh 0x3a /* 16-bit */ 287 288 #define STGE_FlowOffThresh 0x3c /* 16-bit */ 289 290 #define STGE_FlowOnTresh 0x3e /* 16-bit */ 291 292 #define STGE_TxStartThresh 0x44 /* 16-bit */ 293 294 #define STGE_EepromData 0x48 /* 16-bit */ 295 296 #define STGE_EepromCtrl 0x4a /* 16-bit */ 297 #define EC_EepromAddress(x) ((x) & 0xff) 298 #define EC_EepromOpcode(x) ((x) << 8) 299 #define EC_OP_WE 0 300 #define EC_OP_WR 1 301 #define EC_OP_RR 2 302 #define EC_OP_ER 3 303 #define EC_EepromBusy (1U << 15) 304 305 #define STGE_ExpRomAddr 0x4c 306 307 #define STGE_ExpRomData 0x50 /* 8-bit */ 308 309 #define STGE_WakeEvent 0x51 /* 8-bit */ 310 #define WE_WakePktEnable (1U << 0) 311 #define WE_MagicPktEnable (1U << 1) 312 #define WE_LinkEventEnable (1U << 2) 313 #define WE_WakePolarity (1U << 3) 314 #define WE_WakePktEvent (1U << 4) 315 #define WE_MagicPktEvent (1U << 5) 316 #define WE_LinkEvent (1U << 6) 317 #define WE_WakeOnLanEnable (1U << 7) 318 319 #define STGE_Countdown 0x54 320 #define CD_Count(x) ((x) & 0xffff) 321 #define CD_CountdownSpeed (1U << 24) 322 #define CD_CountdownMode (1U << 25) 323 #define CD_CountdownIntEnabled (1U << 26) 324 325 #define STGE_IntStatusAck 0x5a /* 16-bit */ 326 327 #define STGE_IntEnable 0x5c /* 16-bit */ 328 329 #define STGE_IntStatus 0x5e /* 16-bit */ 330 331 #define IS_InterruptStatus (1U << 0) 332 #define IS_HostError (1U << 1) 333 #define IS_TxComplete (1U << 2) 334 #define IS_MACControlFrame (1U << 3) 335 #define IS_RxComplete (1U << 4) 336 #define IS_RxEarly (1U << 5) 337 #define IS_InRequested (1U << 6) 338 #define IS_UpdateStats (1U << 7) 339 #define IS_LinkEvent (1U << 8) 340 #define IS_TxDMAComplete (1U << 9) 341 #define IS_RxDMAComplete (1U << 10) 342 #define IS_RFDListEnd (1U << 11) 343 #define IS_RxDMAPriority (1U << 12) 344 345 #define STGE_TxStatus 0x60 346 #define TS_TxError (1U << 0) 347 #define TS_LateCollision (1U << 2) 348 #define TS_MaxCollisions (1U << 3) 349 #define TS_TxUnderrun (1U << 4) 350 #define TS_TxIndicateReqd (1U << 6) 351 #define TS_TxComplete (1U << 7) 352 #define TS_TxFrameId_get(x) ((x) >> 16) 353 354 #define STGE_MACCtrl 0x6c 355 #define MC_IFSSelect(x) ((x) & 3) 356 #define MC_IFS96bit 0 357 #define MC_IFS1024bit 1 358 #define MC_IFS1792bit 2 359 #define MC_IFS4352bit 3 360 361 #define MC_DuplexSelect (1U << 5) 362 #define MC_RcvLargeFrames (1U << 6) 363 #define MC_TxFlowControlEnable (1U << 7) 364 #define MC_RxFlowControlEnable (1U << 8) 365 #define MC_RcvFCS (1U << 9) 366 #define MC_FIFOLoopback (1U << 10) 367 #define MC_MACLoopback (1U << 11) 368 #define MC_AutoVLANtagging (1U << 12) 369 #define MC_AutoVLANuntagging (1U << 13) 370 #define MC_CollisionDetect (1U << 16) 371 #define MC_CarrierSense (1U << 17) 372 #define MC_StatisticsEnable (1U << 21) 373 #define MC_StatisticsDisable (1U << 22) 374 #define MC_StatisticsEnabled (1U << 23) 375 #define MC_TxEnable (1U << 24) 376 #define MC_TxDisable (1U << 25) 377 #define MC_TxEnabled (1U << 26) 378 #define MC_RxEnable (1U << 27) 379 #define MC_RxDisable (1U << 28) 380 #define MC_RxEnabled (1U << 29) 381 #define MC_Paused (1U << 30) 382 #define MC_MASK 0x7fe33fa3 383 384 #define STGE_VLANTag 0x70 385 386 #define STGE_PhySet 0x75 /* 8-bit */ 387 #define PS_MemLenb9b (1U << 0) 388 #define PS_MemLen (1U << 1) 389 #define PS_NonCompdet (1U << 2) 390 391 #define STGE_PhyCtrl 0x76 /* 8-bit */ 392 #define PC_MgmtClk (1U << 0) 393 #define PC_MgmtData (1U << 1) 394 #define PC_MgmtDir (1U << 2) /* MAC->PHY */ 395 #define PC_PhyDuplexPolarity (1U << 3) 396 #define PC_PhyDuplexStatus (1U << 4) 397 #define PC_PhyLnkPolarity (1U << 5) 398 #define PC_LinkSpeed(x) (((x) >> 6) & 3) 399 #define PC_LinkSpeed_Down 0 400 #define PC_LinkSpeed_10 1 401 #define PC_LinkSpeed_100 2 402 #define PC_LinkSpeed_1000 3 403 404 #define STGE_StationAddress0 0x78 /* 16-bit */ 405 406 #define STGE_StationAddress1 0x7a /* 16-bit */ 407 408 #define STGE_StationAddress2 0x7c /* 16-bit */ 409 410 #define STGE_VLANHashTable 0x7e /* 16-bit */ 411 412 #define STGE_VLANId 0x80 413 414 #define STGE_MaxFrameSize 0x86 415 416 #define STGE_ReceiveMode 0x88 /* 16-bit */ 417 #define RM_ReceiveUnicast (1U << 0) 418 #define RM_ReceiveMulticast (1U << 1) 419 #define RM_ReceiveBroadcast (1U << 2) 420 #define RM_ReceiveAllFrames (1U << 3) 421 #define RM_ReceiveMulticastHash (1U << 4) 422 #define RM_ReceiveIPMulticast (1U << 5) 423 #define RM_ReceiveVLANMatch (1U << 8) 424 #define RM_ReceiveVLANHash (1U << 9) 425 426 #define STGE_HashTable0 0x8c 427 428 #define STGE_HashTable1 0x90 429 430 #define STGE_RMONStatisticsMask 0x98 /* set to disable */ 431 432 #define STGE_StatisticsMask 0x9c /* set to disable */ 433 434 #define STGE_RxJumboFrames 0xbc /* 16-bit */ 435 436 #define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */ 437 438 #define STGE_IPCheckSumErrors 0xc2 /* 16-bit */ 439 440 #define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */ 441 442 #define STGE_TxJumboFrames 0xf4 /* 16-bit */ 443 444 /* 445 * TC9021 statistics. Available memory and I/O mapped. 446 */ 447 448 #define STGE_OctetRcvOk 0xa8 449 450 #define STGE_McstOctetRcvdOk 0xac 451 452 #define STGE_BcstOctetRcvdOk 0xb0 453 454 #define STGE_FramesRcvdOk 0xb4 455 456 #define STGE_McstFramesRcvdOk 0xb8 457 458 #define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */ 459 460 #define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */ 461 462 #define STGE_FrameTooLongErrors 0xc8 /* 16-bit */ 463 464 #define STGE_InRangeLengthErrors 0xca /* 16-bit */ 465 466 #define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */ 467 468 #define STGE_FramesLostRxErrors 0xce /* 16-bit */ 469 470 #define STGE_OctetXmtdOk 0xd0 471 472 #define STGE_McstOctetXmtdOk 0xd4 473 474 #define STGE_BcstOctetXmtdOk 0xd8 475 476 #define STGE_FramesXmtdOk 0xdc 477 478 #define STGE_McstFramesXmtdOk 0xe0 479 480 #define STGE_FramesWDeferredXmt 0xe4 481 482 #define STGE_LateCollisions 0xe8 483 484 #define STGE_MultiColFrames 0xec 485 486 #define STGE_SingleColFrames 0xf0 487 488 #define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */ 489 490 #define STGE_CarrierSenseErrors 0xf8 /* 16-bit */ 491 492 #define STGE_MacControlFramesXmtd 0xfa /* 16-bit */ 493 494 #define STGE_FramesAbortXSColls 0xfc /* 16-bit */ 495 496 #define STGE_FramesWEXDeferal 0xfe /* 16-bit */ 497 498 /* 499 * RMON-compatible statistics. Only accessible if memory-mapped. 500 */ 501 502 #define STGE_EtherStatsCollisions 0x100 503 504 #define STGE_EtherStatsOctetsTransmit 0x104 505 506 #define STGE_EtherStatsPktsTransmit 0x108 507 508 #define STGE_EtherStatsPkts64OctetsTransmit 0x10c 509 510 #define STGE_EtherStatsPkts64to127OctetsTransmit 0x110 511 512 #define STGE_EtherStatsPkts128to255OctetsTransmit 0x114 513 514 #define STGE_EtherStatsPkts256to511OctetsTransmit 0x118 515 516 #define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c 517 518 #define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120 519 520 #define STGE_EtherStatsCRCAlignErrors 0x124 521 522 #define STGE_EtherStatsUndersizePkts 0x128 523 524 #define STGE_EtherStatsFragments 0x12c 525 526 #define STGE_EtherStatsJabbers 0x130 527 528 #define STGE_EtherStatsOctets 0x134 529 530 #define STGE_EtherStatsPkts 0x138 531 532 #define STGE_EtherStatsPkts64Octets 0x13c 533 534 #define STGE_EtherStatsPkts65to127Octets 0x140 535 536 #define STGE_EtherStatsPkts128to255Octets 0x144 537 538 #define STGE_EtherStatsPkts256to511Octets 0x148 539 540 #define STGE_EtherStatsPkts512to1023Octets 0x14c 541 542 #define STGE_EtherStatsPkts1024to1518Octets 0x150 543 544 /* 545 * Transmit descriptor list size. 546 */ 547 #define STGE_TX_RING_CNT 256 548 #define STGE_TX_LOWAT (STGE_TX_RING_CNT/32) 549 #define STGE_TX_HIWAT (STGE_TX_RING_CNT - STGE_TX_LOWAT) 550 551 /* 552 * Receive descriptor list size. 553 */ 554 #define STGE_RX_RING_CNT 256 555 556 #define STGE_MAXTXSEGS STGE_NTXFRAGS 557 558 #define STGE_JUMBO_FRAMELEN 9022 559 #define STGE_JUMBO_MTU \ 560 (STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 561 562 struct stge_txdesc { 563 struct mbuf *tx_m; /* head of our mbuf chain */ 564 bus_dmamap_t tx_dmamap; /* our DMA map */ 565 STAILQ_ENTRY(stge_txdesc) tx_q; 566 }; 567 568 STAILQ_HEAD(stge_txdq, stge_txdesc); 569 570 struct stge_rxdesc { 571 struct mbuf *rx_m; 572 bus_dmamap_t rx_dmamap; 573 }; 574 575 #define STGE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 576 #define STGE_ADDR_HI(x) ((u_int64_t) (x) >> 32) 577 578 #define STGE_RING_ALIGN 8 579 580 struct stge_chain_data{ 581 bus_dma_tag_t stge_parent_tag; 582 bus_dma_tag_t stge_tx_tag; 583 struct stge_txdesc stge_txdesc[STGE_TX_RING_CNT]; 584 struct stge_txdq stge_txfreeq; 585 struct stge_txdq stge_txbusyq; 586 bus_dma_tag_t stge_rx_tag; 587 struct stge_rxdesc stge_rxdesc[STGE_RX_RING_CNT]; 588 bus_dma_tag_t stge_tx_ring_tag; 589 bus_dmamap_t stge_tx_ring_map; 590 bus_dma_tag_t stge_rx_ring_tag; 591 bus_dmamap_t stge_rx_ring_map; 592 bus_dmamap_t stge_rx_sparemap; 593 594 int stge_tx_prod; 595 int stge_tx_cons; 596 int stge_tx_cnt; 597 int stge_rx_cons; 598 #ifdef DEVICE_POLLING 599 int stge_rxcycles; 600 #endif 601 int stge_rxlen; 602 struct mbuf *stge_rxhead; 603 struct mbuf *stge_rxtail; 604 }; 605 606 struct stge_ring_data { 607 struct stge_tfd *stge_tx_ring; 608 bus_addr_t stge_tx_ring_paddr; 609 struct stge_rfd *stge_rx_ring; 610 bus_addr_t stge_rx_ring_paddr; 611 }; 612 613 #define STGE_TX_RING_ADDR(sc, i) \ 614 ((sc)->sc_rdata.stge_tx_ring_paddr + sizeof(struct stge_tfd) * (i)) 615 #define STGE_RX_RING_ADDR(sc, i) \ 616 ((sc)->sc_rdata.stge_rx_ring_paddr + sizeof(struct stge_rfd) * (i)) 617 618 #define STGE_TX_RING_SZ \ 619 (sizeof(struct stge_tfd) * STGE_TX_RING_CNT) 620 #define STGE_RX_RING_SZ \ 621 (sizeof(struct stge_rfd) * STGE_RX_RING_CNT) 622 623 /* 624 * Software state per device. 625 */ 626 struct stge_softc { 627 struct ifnet *sc_ifp; /* interface info */ 628 device_t sc_dev; 629 device_t sc_miibus; 630 struct resource *sc_res[2]; 631 struct resource_spec *sc_spec; 632 void *sc_ih; /* interrupt cookie */ 633 int sc_rev; /* silicon revision */ 634 635 struct callout sc_tick_ch; /* tick callout */ 636 637 struct stge_chain_data sc_cdata; 638 struct stge_ring_data sc_rdata; 639 int sc_if_flags; 640 int sc_if_framesize; 641 int sc_txthresh; /* Tx threshold */ 642 uint32_t sc_usefiber:1; /* if we're fiber */ 643 uint32_t sc_stge1023:1; /* are we a 1023 */ 644 uint32_t sc_DMACtrl; /* prototype DMACtrl reg. */ 645 uint32_t sc_MACCtrl; /* prototype MacCtrl reg. */ 646 uint16_t sc_IntEnable; /* prototype IntEnable reg. */ 647 uint16_t sc_led; /* LED conf. from EEPROM */ 648 uint8_t sc_PhyCtrl; /* prototype PhyCtrl reg. */ 649 int sc_suspended; 650 int sc_detach; 651 652 int sc_rxint_nframe; 653 int sc_rxint_dmawait; 654 int sc_nerr; 655 int sc_watchdog_timer; 656 int sc_link; 657 658 struct task sc_link_task; 659 struct mtx sc_mii_mtx; /* MII mutex */ 660 struct mtx sc_mtx; 661 }; 662 663 #define STGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 664 #define STGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 665 #define STGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 666 #define STGE_MII_LOCK(_sc) mtx_lock(&(_sc)->sc_mii_mtx) 667 #define STGE_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mii_mtx) 668 669 #define STGE_MAXERR 5 670 671 #define STGE_RXCHAIN_RESET(_sc) \ 672 do { \ 673 (_sc)->sc_cdata.stge_rxhead = NULL; \ 674 (_sc)->sc_cdata.stge_rxtail = NULL; \ 675 (_sc)->sc_cdata.stge_rxlen = 0; \ 676 } while (/*CONSTCOND*/0) 677 678 #define STGE_TIMEOUT 1000 679 680 struct stge_mii_frame { 681 uint8_t mii_stdelim; 682 uint8_t mii_opcode; 683 uint8_t mii_phyaddr; 684 uint8_t mii_regaddr; 685 uint8_t mii_turnaround; 686 uint16_t mii_data; 687 }; 688 689 /* 690 * MII constants 691 */ 692 #define STGE_MII_STARTDELIM 0x01 693 #define STGE_MII_READOP 0x02 694 #define STGE_MII_WRITEOP 0x01 695 #define STGE_MII_TURNAROUND 0x02 696 697 #define STGE_RESET_NONE 0x00 698 #define STGE_RESET_TX 0x01 699 #define STGE_RESET_RX 0x02 700 #define STGE_RESET_FULL 0x04 701