1 /* $NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause 5 * 6 * Copyright (c) 2001 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Jason R. Thorpe. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * Sundance Technology PCI vendor ID 37 */ 38 #define VENDOR_SUNDANCETI 0x13f0 39 40 /* 41 * Tamarack Microelectronics PCI vendor ID 42 */ 43 #define VENDOR_TAMARACK 0x143d 44 45 /* 46 * D-Link Systems PCI vendor ID 47 */ 48 #define VENDOR_DLINK 0x1186 49 50 /* 51 * Antares Microsystems PCI vendor ID 52 */ 53 #define VENDOR_ANTARES 0x1754 54 55 /* 56 * Sundance Technology device ID 57 */ 58 #define DEVICEID_SUNDANCETI_ST1023 0x1023 59 #define DEVICEID_SUNDANCETI_ST2021 0x2021 60 #define DEVICEID_TAMARACK_TC9021 0x1021 61 #define DEVICEID_TAMARACK_TC9021_ALT 0x9021 62 63 /* 64 * D-Link Systems device ID 65 */ 66 #define DEVICEID_DLINK_DL4000 0x4000 67 68 /* 69 * Antares Microsystems device ID 70 */ 71 #define DEVICEID_ANTARES_TC9021 0x1021 72 73 /* 74 * Register description for the Sundance Tech. TC9021 10/100/1000 75 * Ethernet controller. 76 * 77 * Note that while DMA addresses are all in 64-bit fields, only 78 * the lower 40 bits of a DMA address are valid. 79 */ 80 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 81 #define STGE_DMA_MAXADDR BUS_SPACE_MAXADDR 82 #else 83 #define STGE_DMA_MAXADDR 0xFFFFFFFFFF 84 #endif 85 86 /* 87 * Register access macros 88 */ 89 #define CSR_WRITE_4(_sc, reg, val) \ 90 bus_write_4((_sc)->sc_res[0], (reg), (val)) 91 #define CSR_WRITE_2(_sc, reg, val) \ 92 bus_write_2((_sc)->sc_res[0], (reg), (val)) 93 #define CSR_WRITE_1(_sc, reg, val) \ 94 bus_write_1((_sc)->sc_res[0], (reg), (val)) 95 96 #define CSR_READ_4(_sc, reg) \ 97 bus_read_4((_sc)->sc_res[0], (reg)) 98 #define CSR_READ_2(_sc, reg) \ 99 bus_read_2((_sc)->sc_res[0], (reg)) 100 #define CSR_READ_1(_sc, reg) \ 101 bus_read_1((_sc)->sc_res[0], (reg)) 102 103 #define CSR_BARRIER(_sc, reg, length, flags) \ 104 bus_barrier((_sc)->sc_res[0], reg, length, flags) 105 106 /* 107 * TC9021 buffer fragment descriptor. 108 */ 109 struct stge_frag { 110 uint64_t frag_word0; /* address, length */ 111 }; 112 113 #define FRAG_ADDR(x) (((uint64_t)(x)) << 0) 114 #define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL) 115 #define FRAG_LEN(x) (((uint64_t)(x)) << 48) 116 #define FRAG_LEN_MASK FRAG_LEN(0xffffULL) 117 118 /* 119 * TC9021 Transmit Frame Descriptor. Note the number of fragments 120 * here is arbitrary, but we can't have any more than 15. 121 */ 122 #define STGE_NTXFRAGS 15 123 struct stge_tfd { 124 uint64_t tfd_next; /* next TFD in list */ 125 uint64_t tfd_control; /* control bits */ 126 /* the buffer fragments */ 127 struct stge_frag tfd_frags[STGE_NTXFRAGS]; 128 }; 129 130 #define TFD_FrameId(x) ((x) << 0) 131 #define TFD_FrameId_MAX 0xffff 132 #define TFD_WordAlign(x) ((x) << 16) 133 #define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ 134 #define TFD_WordAlign_word 2 /* align to word in TxFIFO */ 135 #define TFD_WordAlign_disable 1 /* disable alignment */ 136 #define TFD_TCPChecksumEnable (1ULL << 18) 137 #define TFD_UDPChecksumEnable (1ULL << 19) 138 #define TFD_IPChecksumEnable (1ULL << 20) 139 #define TFD_FcsAppendDisable (1ULL << 21) 140 #define TFD_TxIndicate (1ULL << 22) 141 #define TFD_TxDMAIndicate (1ULL << 23) 142 #define TFD_FragCount(x) ((x) << 24) 143 #define TFD_VLANTagInsert (1ULL << 28) 144 #define TFD_TFDDone (1ULL << 31) 145 #define TFD_VID(x) (((uint64_t)(x)) << 32) 146 #define TFD_CFI (1ULL << 44) 147 #define TFD_UserPriority(x) (((uint64_t)(x)) << 45) 148 149 /* 150 * TC9021 Receive Frame Descriptor. Each RFD has a single fragment 151 * in it, and the chip tells us the beginning and end of the frame. 152 */ 153 struct stge_rfd { 154 uint64_t rfd_next; /* next RFD in list */ 155 uint64_t rfd_status; /* status bits */ 156 struct stge_frag rfd_frag; /* the buffer */ 157 }; 158 159 /* Low word of rfd_status */ 160 #define RFD_RxStatus(x) ((x) & 0xffffffff) 161 #define RFD_RxDMAFrameLen(x) ((x) & 0xffff) 162 #define RFD_RxFIFOOverrun 0x00010000 163 #define RFD_RxRuntFrame 0x00020000 164 #define RFD_RxAlignmentError 0x00040000 165 #define RFD_RxFCSError 0x00080000 166 #define RFD_RxOversizedFrame 0x00100000 167 #define RFD_RxLengthError 0x00200000 168 #define RFD_VLANDetected 0x00400000 169 #define RFD_TCPDetected 0x00800000 170 #define RFD_TCPError 0x01000000 171 #define RFD_UDPDetected 0x02000000 172 #define RFD_UDPError 0x04000000 173 #define RFD_IPDetected 0x08000000 174 #define RFD_IPError 0x10000000 175 #define RFD_FrameStart 0x20000000 176 #define RFD_FrameEnd 0x40000000 177 #define RFD_RFDDone 0x80000000 178 /* High word of rfd_status */ 179 #define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff) 180 181 /* 182 * EEPROM offsets. 183 */ 184 #define STGE_EEPROM_ConfigParam 0x00 185 #define STGE_EEPROM_AsicCtrl 0x01 186 #define STGE_EEPROM_SubSystemVendorId 0x02 187 #define STGE_EEPROM_SubSystemId 0x03 188 #define STGE_EEPROM_LEDMode 0x06 189 #define STGE_EEPROM_StationAddress0 0x10 190 #define STGE_EEPROM_StationAddress1 0x11 191 #define STGE_EEPROM_StationAddress2 0x12 192 193 /* 194 * The TC9021 register space. 195 */ 196 197 #define STGE_DMACtrl 0x00 198 #define DMAC_RxDMAComplete (1U << 3) 199 #define DMAC_RxDMAPollNow (1U << 4) 200 #define DMAC_TxDMAComplete (1U << 11) 201 #define DMAC_TxDMAPollNow (1U << 12) 202 #define DMAC_TxDMAInProg (1U << 15) 203 #define DMAC_RxEarlyDisable (1U << 16) 204 #define DMAC_MWIDisable (1U << 18) 205 #define DMAC_TxWriteBackDisable (1U << 19) 206 #define DMAC_TxBurstLimit(x) ((x) << 20) 207 #define DMAC_TargetAbort (1U << 30) 208 #define DMAC_MasterAbort (1U << 31) 209 210 #define STGE_RxDMAStatus 0x08 211 212 #define STGE_TFDListPtrLo 0x10 213 214 #define STGE_TFDListPtrHi 0x14 215 216 #define STGE_TxDMABurstThresh 0x18 /* 8-bit */ 217 218 #define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */ 219 220 #define STGE_TxDMAPollPeriod 0x1a /* 8-bit, 320ns increments */ 221 222 #define STGE_RFDListPtrLo 0x1c 223 224 #define STGE_RFDListPtrHi 0x20 225 226 #define STGE_RxDMABurstThresh 0x24 /* 8-bit */ 227 228 #define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */ 229 230 #define STGE_RxDMAPollPeriod 0x26 /* 8-bit, 320ns increments */ 231 232 #define STGE_RxDMAIntCtrl 0x28 233 #define RDIC_RxFrameCount(x) ((x) & 0xff) 234 #define RDIC_PriorityThresh(x) ((x) << 10) 235 #define RDIC_RxDMAWaitTime(x) ((x) << 16) 236 /* 237 * Number of receive frames transferred via DMA before a Rx interrupt is issued. 238 */ 239 #define STGE_RXINT_NFRAME_DEFAULT 8 240 #define STGE_RXINT_NFRAME_MIN 1 241 #define STGE_RXINT_NFRAME_MAX 255 242 /* 243 * Maximum amount of time (in 64ns increments) to wait before issuing a Rx 244 * interrupt if number of frames recevied is less than STGE_RXINT_NFRAME 245 * (STGE_RXINT_NFRAME_MIN <= STGE_RXINT_NFRAME <= STGE_RXINT_NFRAME_MAX) 246 */ 247 #define STGE_RXINT_DMAWAIT_DEFAULT 30 /* 30us */ 248 #define STGE_RXINT_DMAWAIT_MIN 0 249 #define STGE_RXINT_DMAWAIT_MAX 4194 250 #define STGE_RXINT_USECS2TICK(x) (((x) * 1000)/64) 251 252 #define STGE_DebugCtrl 0x2c /* 16-bit */ 253 #define DC_GPIO0Ctrl (1U << 0) 254 #define DC_GPIO1Ctrl (1U << 1) 255 #define DC_GPIO0 (1U << 2) 256 #define DC_GPIO1 (1U << 3) 257 258 #define STGE_AsicCtrl 0x30 259 #define AC_ExpRomDisable (1U << 0) 260 #define AC_ExpRomSize (1U << 1) 261 #define AC_PhySpeed10 (1U << 4) 262 #define AC_PhySpeed100 (1U << 5) 263 #define AC_PhySpeed1000 (1U << 6) 264 #define AC_PhyMedia (1U << 7) 265 #define AC_ForcedConfig(x) ((x) << 8) 266 #define AC_ForcedConfig_MASK AC_ForcedConfig(7) 267 #define AC_D3ResetDisable (1U << 11) 268 #define AC_SpeedupMode (1U << 13) 269 #define AC_LEDMode (1U << 14) 270 #define AC_RstOutPolarity (1U << 15) 271 #define AC_GlobalReset (1U << 16) 272 #define AC_RxReset (1U << 17) 273 #define AC_TxReset (1U << 18) 274 #define AC_DMA (1U << 19) 275 #define AC_FIFO (1U << 20) 276 #define AC_Network (1U << 21) 277 #define AC_Host (1U << 22) 278 #define AC_AutoInit (1U << 23) 279 #define AC_RstOut (1U << 24) 280 #define AC_InterruptRequest (1U << 25) 281 #define AC_ResetBusy (1U << 26) 282 #define AC_LEDSpeed (1U << 27) 283 #define AC_LEDModeBit1 (1U << 29) 284 285 #define STGE_FIFOCtrl 0x38 /* 16-bit */ 286 #define FC_RAMTestMode (1U << 0) 287 #define FC_Transmitting (1U << 14) 288 #define FC_Receiving (1U << 15) 289 290 #define STGE_RxEarlyThresh 0x3a /* 16-bit */ 291 292 #define STGE_FlowOffThresh 0x3c /* 16-bit */ 293 294 #define STGE_FlowOnTresh 0x3e /* 16-bit */ 295 296 #define STGE_TxStartThresh 0x44 /* 16-bit */ 297 298 #define STGE_EepromData 0x48 /* 16-bit */ 299 300 #define STGE_EepromCtrl 0x4a /* 16-bit */ 301 #define EC_EepromAddress(x) ((x) & 0xff) 302 #define EC_EepromOpcode(x) ((x) << 8) 303 #define EC_OP_WE 0 304 #define EC_OP_WR 1 305 #define EC_OP_RR 2 306 #define EC_OP_ER 3 307 #define EC_EepromBusy (1U << 15) 308 309 #define STGE_ExpRomAddr 0x4c 310 311 #define STGE_ExpRomData 0x50 /* 8-bit */ 312 313 #define STGE_WakeEvent 0x51 /* 8-bit */ 314 #define WE_WakePktEnable (1U << 0) 315 #define WE_MagicPktEnable (1U << 1) 316 #define WE_LinkEventEnable (1U << 2) 317 #define WE_WakePolarity (1U << 3) 318 #define WE_WakePktEvent (1U << 4) 319 #define WE_MagicPktEvent (1U << 5) 320 #define WE_LinkEvent (1U << 6) 321 #define WE_WakeOnLanEnable (1U << 7) 322 323 #define STGE_Countdown 0x54 324 #define CD_Count(x) ((x) & 0xffff) 325 #define CD_CountdownSpeed (1U << 24) 326 #define CD_CountdownMode (1U << 25) 327 #define CD_CountdownIntEnabled (1U << 26) 328 329 #define STGE_IntStatusAck 0x5a /* 16-bit */ 330 331 #define STGE_IntEnable 0x5c /* 16-bit */ 332 333 #define STGE_IntStatus 0x5e /* 16-bit */ 334 335 #define IS_InterruptStatus (1U << 0) 336 #define IS_HostError (1U << 1) 337 #define IS_TxComplete (1U << 2) 338 #define IS_MACControlFrame (1U << 3) 339 #define IS_RxComplete (1U << 4) 340 #define IS_RxEarly (1U << 5) 341 #define IS_InRequested (1U << 6) 342 #define IS_UpdateStats (1U << 7) 343 #define IS_LinkEvent (1U << 8) 344 #define IS_TxDMAComplete (1U << 9) 345 #define IS_RxDMAComplete (1U << 10) 346 #define IS_RFDListEnd (1U << 11) 347 #define IS_RxDMAPriority (1U << 12) 348 349 #define STGE_TxStatus 0x60 350 #define TS_TxError (1U << 0) 351 #define TS_LateCollision (1U << 2) 352 #define TS_MaxCollisions (1U << 3) 353 #define TS_TxUnderrun (1U << 4) 354 #define TS_TxIndicateReqd (1U << 6) 355 #define TS_TxComplete (1U << 7) 356 #define TS_TxFrameId_get(x) ((x) >> 16) 357 358 #define STGE_MACCtrl 0x6c 359 #define MC_IFSSelect(x) ((x) & 3) 360 #define MC_IFS96bit 0 361 #define MC_IFS1024bit 1 362 #define MC_IFS1792bit 2 363 #define MC_IFS4352bit 3 364 365 #define MC_DuplexSelect (1U << 5) 366 #define MC_RcvLargeFrames (1U << 6) 367 #define MC_TxFlowControlEnable (1U << 7) 368 #define MC_RxFlowControlEnable (1U << 8) 369 #define MC_RcvFCS (1U << 9) 370 #define MC_FIFOLoopback (1U << 10) 371 #define MC_MACLoopback (1U << 11) 372 #define MC_AutoVLANtagging (1U << 12) 373 #define MC_AutoVLANuntagging (1U << 13) 374 #define MC_CollisionDetect (1U << 16) 375 #define MC_CarrierSense (1U << 17) 376 #define MC_StatisticsEnable (1U << 21) 377 #define MC_StatisticsDisable (1U << 22) 378 #define MC_StatisticsEnabled (1U << 23) 379 #define MC_TxEnable (1U << 24) 380 #define MC_TxDisable (1U << 25) 381 #define MC_TxEnabled (1U << 26) 382 #define MC_RxEnable (1U << 27) 383 #define MC_RxDisable (1U << 28) 384 #define MC_RxEnabled (1U << 29) 385 #define MC_Paused (1U << 30) 386 #define MC_MASK 0x7fe33fa3 387 388 #define STGE_VLANTag 0x70 389 390 #define STGE_PhySet 0x75 /* 8-bit */ 391 #define PS_MemLenb9b (1U << 0) 392 #define PS_MemLen (1U << 1) 393 #define PS_NonCompdet (1U << 2) 394 395 #define STGE_PhyCtrl 0x76 /* 8-bit */ 396 #define PC_MgmtClk (1U << 0) 397 #define PC_MgmtData (1U << 1) 398 #define PC_MgmtDir (1U << 2) /* MAC->PHY */ 399 #define PC_PhyDuplexPolarity (1U << 3) 400 #define PC_PhyDuplexStatus (1U << 4) 401 #define PC_PhyLnkPolarity (1U << 5) 402 #define PC_LinkSpeed(x) (((x) >> 6) & 3) 403 #define PC_LinkSpeed_Down 0 404 #define PC_LinkSpeed_10 1 405 #define PC_LinkSpeed_100 2 406 #define PC_LinkSpeed_1000 3 407 408 #define STGE_StationAddress0 0x78 /* 16-bit */ 409 410 #define STGE_StationAddress1 0x7a /* 16-bit */ 411 412 #define STGE_StationAddress2 0x7c /* 16-bit */ 413 414 #define STGE_VLANHashTable 0x7e /* 16-bit */ 415 416 #define STGE_VLANId 0x80 417 418 #define STGE_MaxFrameSize 0x86 419 420 #define STGE_ReceiveMode 0x88 /* 16-bit */ 421 #define RM_ReceiveUnicast (1U << 0) 422 #define RM_ReceiveMulticast (1U << 1) 423 #define RM_ReceiveBroadcast (1U << 2) 424 #define RM_ReceiveAllFrames (1U << 3) 425 #define RM_ReceiveMulticastHash (1U << 4) 426 #define RM_ReceiveIPMulticast (1U << 5) 427 #define RM_ReceiveVLANMatch (1U << 8) 428 #define RM_ReceiveVLANHash (1U << 9) 429 430 #define STGE_HashTable0 0x8c 431 432 #define STGE_HashTable1 0x90 433 434 #define STGE_RMONStatisticsMask 0x98 /* set to disable */ 435 436 #define STGE_StatisticsMask 0x9c /* set to disable */ 437 438 #define STGE_RxJumboFrames 0xbc /* 16-bit */ 439 440 #define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */ 441 442 #define STGE_IPCheckSumErrors 0xc2 /* 16-bit */ 443 444 #define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */ 445 446 #define STGE_TxJumboFrames 0xf4 /* 16-bit */ 447 448 /* 449 * TC9021 statistics. Available memory and I/O mapped. 450 */ 451 452 #define STGE_OctetRcvOk 0xa8 453 454 #define STGE_McstOctetRcvdOk 0xac 455 456 #define STGE_BcstOctetRcvdOk 0xb0 457 458 #define STGE_FramesRcvdOk 0xb4 459 460 #define STGE_McstFramesRcvdOk 0xb8 461 462 #define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */ 463 464 #define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */ 465 466 #define STGE_FrameTooLongErrors 0xc8 /* 16-bit */ 467 468 #define STGE_InRangeLengthErrors 0xca /* 16-bit */ 469 470 #define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */ 471 472 #define STGE_FramesLostRxErrors 0xce /* 16-bit */ 473 474 #define STGE_OctetXmtdOk 0xd0 475 476 #define STGE_McstOctetXmtdOk 0xd4 477 478 #define STGE_BcstOctetXmtdOk 0xd8 479 480 #define STGE_FramesXmtdOk 0xdc 481 482 #define STGE_McstFramesXmtdOk 0xe0 483 484 #define STGE_FramesWDeferredXmt 0xe4 485 486 #define STGE_LateCollisions 0xe8 487 488 #define STGE_MultiColFrames 0xec 489 490 #define STGE_SingleColFrames 0xf0 491 492 #define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */ 493 494 #define STGE_CarrierSenseErrors 0xf8 /* 16-bit */ 495 496 #define STGE_MacControlFramesXmtd 0xfa /* 16-bit */ 497 498 #define STGE_FramesAbortXSColls 0xfc /* 16-bit */ 499 500 #define STGE_FramesWEXDeferal 0xfe /* 16-bit */ 501 502 /* 503 * RMON-compatible statistics. Only accessible if memory-mapped. 504 */ 505 506 #define STGE_EtherStatsCollisions 0x100 507 508 #define STGE_EtherStatsOctetsTransmit 0x104 509 510 #define STGE_EtherStatsPktsTransmit 0x108 511 512 #define STGE_EtherStatsPkts64OctetsTransmit 0x10c 513 514 #define STGE_EtherStatsPkts64to127OctetsTransmit 0x110 515 516 #define STGE_EtherStatsPkts128to255OctetsTransmit 0x114 517 518 #define STGE_EtherStatsPkts256to511OctetsTransmit 0x118 519 520 #define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c 521 522 #define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120 523 524 #define STGE_EtherStatsCRCAlignErrors 0x124 525 526 #define STGE_EtherStatsUndersizePkts 0x128 527 528 #define STGE_EtherStatsFragments 0x12c 529 530 #define STGE_EtherStatsJabbers 0x130 531 532 #define STGE_EtherStatsOctets 0x134 533 534 #define STGE_EtherStatsPkts 0x138 535 536 #define STGE_EtherStatsPkts64Octets 0x13c 537 538 #define STGE_EtherStatsPkts65to127Octets 0x140 539 540 #define STGE_EtherStatsPkts128to255Octets 0x144 541 542 #define STGE_EtherStatsPkts256to511Octets 0x148 543 544 #define STGE_EtherStatsPkts512to1023Octets 0x14c 545 546 #define STGE_EtherStatsPkts1024to1518Octets 0x150 547 548 /* 549 * Transmit descriptor list size. 550 */ 551 #define STGE_TX_RING_CNT 256 552 #define STGE_TX_LOWAT (STGE_TX_RING_CNT/32) 553 #define STGE_TX_HIWAT (STGE_TX_RING_CNT - STGE_TX_LOWAT) 554 555 /* 556 * Receive descriptor list size. 557 */ 558 #define STGE_RX_RING_CNT 256 559 560 #define STGE_MAXTXSEGS STGE_NTXFRAGS 561 562 #define STGE_JUMBO_FRAMELEN 9022 563 #define STGE_JUMBO_MTU \ 564 (STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 565 566 struct stge_txdesc { 567 struct mbuf *tx_m; /* head of our mbuf chain */ 568 bus_dmamap_t tx_dmamap; /* our DMA map */ 569 STAILQ_ENTRY(stge_txdesc) tx_q; 570 }; 571 572 STAILQ_HEAD(stge_txdq, stge_txdesc); 573 574 struct stge_rxdesc { 575 struct mbuf *rx_m; 576 bus_dmamap_t rx_dmamap; 577 }; 578 579 #define STGE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 580 #define STGE_ADDR_HI(x) ((u_int64_t) (x) >> 32) 581 582 #define STGE_RING_ALIGN 8 583 584 struct stge_chain_data{ 585 bus_dma_tag_t stge_parent_tag; 586 bus_dma_tag_t stge_tx_tag; 587 struct stge_txdesc stge_txdesc[STGE_TX_RING_CNT]; 588 struct stge_txdq stge_txfreeq; 589 struct stge_txdq stge_txbusyq; 590 bus_dma_tag_t stge_rx_tag; 591 struct stge_rxdesc stge_rxdesc[STGE_RX_RING_CNT]; 592 bus_dma_tag_t stge_tx_ring_tag; 593 bus_dmamap_t stge_tx_ring_map; 594 bus_dma_tag_t stge_rx_ring_tag; 595 bus_dmamap_t stge_rx_ring_map; 596 bus_dmamap_t stge_rx_sparemap; 597 598 int stge_tx_prod; 599 int stge_tx_cons; 600 int stge_tx_cnt; 601 int stge_rx_cons; 602 #ifdef DEVICE_POLLING 603 int stge_rxcycles; 604 #endif 605 int stge_rxlen; 606 struct mbuf *stge_rxhead; 607 struct mbuf *stge_rxtail; 608 }; 609 610 struct stge_ring_data { 611 struct stge_tfd *stge_tx_ring; 612 bus_addr_t stge_tx_ring_paddr; 613 struct stge_rfd *stge_rx_ring; 614 bus_addr_t stge_rx_ring_paddr; 615 }; 616 617 #define STGE_TX_RING_ADDR(sc, i) \ 618 ((sc)->sc_rdata.stge_tx_ring_paddr + sizeof(struct stge_tfd) * (i)) 619 #define STGE_RX_RING_ADDR(sc, i) \ 620 ((sc)->sc_rdata.stge_rx_ring_paddr + sizeof(struct stge_rfd) * (i)) 621 622 #define STGE_TX_RING_SZ \ 623 (sizeof(struct stge_tfd) * STGE_TX_RING_CNT) 624 #define STGE_RX_RING_SZ \ 625 (sizeof(struct stge_rfd) * STGE_RX_RING_CNT) 626 627 /* 628 * Software state per device. 629 */ 630 struct stge_softc { 631 if_t sc_ifp; /* interface info */ 632 device_t sc_dev; 633 device_t sc_miibus; 634 struct resource *sc_res[2]; 635 struct resource_spec *sc_spec; 636 void *sc_ih; /* interrupt cookie */ 637 int sc_rev; /* silicon revision */ 638 639 struct callout sc_tick_ch; /* tick callout */ 640 641 struct stge_chain_data sc_cdata; 642 struct stge_ring_data sc_rdata; 643 int sc_if_flags; 644 int sc_if_framesize; 645 int sc_txthresh; /* Tx threshold */ 646 uint32_t sc_usefiber:1; /* if we're fiber */ 647 uint32_t sc_stge1023:1; /* are we a 1023 */ 648 uint32_t sc_DMACtrl; /* prototype DMACtrl reg. */ 649 uint32_t sc_MACCtrl; /* prototype MacCtrl reg. */ 650 uint16_t sc_IntEnable; /* prototype IntEnable reg. */ 651 uint16_t sc_led; /* LED conf. from EEPROM */ 652 uint8_t sc_PhyCtrl; /* prototype PhyCtrl reg. */ 653 int sc_suspended; 654 int sc_detach; 655 656 int sc_rxint_nframe; 657 int sc_rxint_dmawait; 658 int sc_nerr; 659 int sc_watchdog_timer; 660 int sc_link; 661 662 struct task sc_link_task; 663 struct mtx sc_mii_mtx; /* MII mutex */ 664 struct mtx sc_mtx; 665 }; 666 667 #define STGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 668 #define STGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 669 #define STGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 670 #define STGE_MII_LOCK(_sc) mtx_lock(&(_sc)->sc_mii_mtx) 671 #define STGE_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mii_mtx) 672 673 #define STGE_MAXERR 5 674 675 #define STGE_RXCHAIN_RESET(_sc) \ 676 do { \ 677 (_sc)->sc_cdata.stge_rxhead = NULL; \ 678 (_sc)->sc_cdata.stge_rxtail = NULL; \ 679 (_sc)->sc_cdata.stge_rxlen = 0; \ 680 } while (/*CONSTCOND*/0) 681 682 #define STGE_TIMEOUT 1000 683 684 #define STGE_RESET_NONE 0x00 685 #define STGE_RESET_TX 0x01 686 #define STGE_RESET_RX 0x02 687 #define STGE_RESET_FULL 0x04 688