xref: /freebsd/sys/dev/stge/if_stgereg.h (revision 1e413cf93298b5b97441a21d9a50fdcd0ee9945e)
1 /*	$NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $	*/
2 
3 /*-
4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *	This product includes software developed by the NetBSD
21  *	Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /* $FreeBSD$ */
40 
41 /*
42  * Sundance Technology PCI vendor ID
43  */
44 #define	VENDOR_SUNDANCETI	0x13f0
45 
46 /*
47  * Tamarack Microelectronics PCI vendor ID
48  */
49 #define	VENDOR_TAMARACK		0x143d
50 
51 /*
52  * D-Link Systems PCI vendor ID
53  */
54 #define	VENDOR_DLINK		0x1186
55 
56 /*
57  * Antares Microsystems PCI vendor ID
58  */
59 #define	VENDOR_ANTARES		0x1754
60 
61 /*
62  * Sundance Technology device ID
63  */
64 #define	DEVICEID_SUNDANCETI_ST1023	0x1023
65 #define	DEVICEID_SUNDANCETI_ST2021	0x2021
66 #define	DEVICEID_TAMARACK_TC9021	0x1021
67 #define	DEVICEID_TAMARACK_TC9021_ALT	0x9021
68 
69 /*
70  * D-Link Systems device ID
71  */
72 #define	DEVICEID_DLINK_DL4000		0x4000
73 
74 /*
75  * Antares Microsystems device ID
76  */
77 #define	DEVICEID_ANTARES_TC9021		0x1021
78 
79 /*
80  * Register description for the Sundance Tech. TC9021 10/100/1000
81  * Ethernet controller.
82  *
83  * Note that while DMA addresses are all in 64-bit fields, only
84  * the lower 40 bits of a DMA address are valid.
85  */
86 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
87 #define	STGE_DMA_MAXADDR	BUS_SPACE_MAXADDR
88 #else
89 #define	STGE_DMA_MAXADDR	0xFFFFFFFFFF
90 #endif
91 
92 /*
93  * Register access macros
94  */
95 #define CSR_WRITE_4(_sc, reg, val)	\
96 	bus_write_4((_sc)->sc_res[0], (reg), (val))
97 #define CSR_WRITE_2(_sc, reg, val)	\
98 	bus_write_2((_sc)->sc_res[0], (reg), (val))
99 #define CSR_WRITE_1(_sc, reg, val)	\
100 	bus_write_1((_sc)->sc_res[0], (reg), (val))
101 
102 #define CSR_READ_4(_sc, reg)		\
103 	bus_read_4((_sc)->sc_res[0], (reg))
104 #define CSR_READ_2(_sc, reg)		\
105 	bus_read_2((_sc)->sc_res[0], (reg))
106 #define CSR_READ_1(_sc, reg)		\
107 	bus_read_1((_sc)->sc_res[0], (reg))
108 
109 /*
110  * TC9021 buffer fragment descriptor.
111  */
112 struct stge_frag {
113 	uint64_t	frag_word0;	/* address, length */
114 };
115 
116 #define	FRAG_ADDR(x)	(((uint64_t)(x)) << 0)
117 #define	FRAG_ADDR_MASK	FRAG_ADDR(0xfffffffffULL)
118 #define	FRAG_LEN(x)	(((uint64_t)(x)) << 48)
119 #define	FRAG_LEN_MASK	FRAG_LEN(0xffffULL)
120 
121 /*
122  * TC9021 Transmit Frame Descriptor.  Note the number of fragments
123  * here is arbitrary, but we can't have any more than 15.
124  */
125 #define	STGE_NTXFRAGS	15
126 struct stge_tfd {
127 	uint64_t	tfd_next;	/* next TFD in list */
128 	uint64_t	tfd_control;	/* control bits */
129 					/* the buffer fragments */
130 	struct stge_frag tfd_frags[STGE_NTXFRAGS];
131 };
132 
133 #define	TFD_FrameId(x)		((x) << 0)
134 #define	TFD_FrameId_MAX		0xffff
135 #define	TFD_WordAlign(x)	((x) << 16)
136 #define	TFD_WordAlign_dword	0		/* align to dword in TxFIFO */
137 #define	TFD_WordAlign_word	2		/* align to word in TxFIFO */
138 #define	TFD_WordAlign_disable	1		/* disable alignment */
139 #define	TFD_TCPChecksumEnable	(1ULL << 18)
140 #define	TFD_UDPChecksumEnable	(1ULL << 19)
141 #define	TFD_IPChecksumEnable	(1ULL << 20)
142 #define	TFD_FcsAppendDisable	(1ULL << 21)
143 #define	TFD_TxIndicate		(1ULL << 22)
144 #define	TFD_TxDMAIndicate	(1ULL << 23)
145 #define	TFD_FragCount(x)	((x) << 24)
146 #define	TFD_VLANTagInsert	(1ULL << 28)
147 #define	TFD_TFDDone		(1ULL << 31)
148 #define	TFD_VID(x)		(((uint64_t)(x)) << 32)
149 #define	TFD_CFI			(1ULL << 44)
150 #define	TFD_UserPriority(x)	(((uint64_t)(x)) << 45)
151 
152 /*
153  * TC9021 Receive Frame Descriptor.  Each RFD has a single fragment
154  * in it, and the chip tells us the beginning and end of the frame.
155  */
156 struct stge_rfd {
157 	uint64_t	rfd_next;	/* next RFD in list */
158 	uint64_t	rfd_status;	/* status bits */
159 	struct stge_frag rfd_frag;	/* the buffer */
160 };
161 
162 /* Low word of rfd_status */
163 #define RFD_RxStatus(x)		((x) & 0xffffffff)
164 #define	RFD_RxDMAFrameLen(x)	((x) & 0xffff)
165 #define	RFD_RxFIFOOverrun	0x00010000
166 #define	RFD_RxRuntFrame		0x00020000
167 #define	RFD_RxAlignmentError	0x00040000
168 #define	RFD_RxFCSError		0x00080000
169 #define	RFD_RxOversizedFrame	0x00100000
170 #define	RFD_RxLengthError	0x00200000
171 #define	RFD_VLANDetected	0x00400000
172 #define	RFD_TCPDetected		0x00800000
173 #define	RFD_TCPError		0x01000000
174 #define	RFD_UDPDetected		0x02000000
175 #define	RFD_UDPError		0x04000000
176 #define	RFD_IPDetected		0x08000000
177 #define	RFD_IPError		0x10000000
178 #define	RFD_FrameStart		0x20000000
179 #define	RFD_FrameEnd		0x40000000
180 #define	RFD_RFDDone		0x80000000
181 /* High word of rfd_status */
182 #define	RFD_TCI(x)		((((uint64_t)(x)) >> 32) & 0xffff)
183 
184 /*
185  * EEPROM offsets.
186  */
187 #define	STGE_EEPROM_ConfigParam		0x00
188 #define	STGE_EEPROM_AsicCtrl		0x01
189 #define	STGE_EEPROM_SubSystemVendorId	0x02
190 #define	STGE_EEPROM_SubSystemId		0x03
191 #define	STGE_EEPROM_LEDMode		0x06
192 #define	STGE_EEPROM_StationAddress0	0x10
193 #define	STGE_EEPROM_StationAddress1	0x11
194 #define	STGE_EEPROM_StationAddress2	0x12
195 
196 /*
197  * The TC9021 register space.
198  */
199 
200 #define	STGE_DMACtrl			0x00
201 #define	DMAC_RxDMAComplete		(1U << 3)
202 #define	DMAC_RxDMAPollNow		(1U << 4)
203 #define	DMAC_TxDMAComplete		(1U << 11)
204 #define	DMAC_TxDMAPollNow		(1U << 12)
205 #define	DMAC_TxDMAInProg		(1U << 15)
206 #define	DMAC_RxEarlyDisable		(1U << 16)
207 #define	DMAC_MWIDisable			(1U << 18)
208 #define	DMAC_TxWriteBackDisable		(1U << 19)
209 #define	DMAC_TxBurstLimit(x)		((x) << 20)
210 #define	DMAC_TargetAbort		(1U << 30)
211 #define	DMAC_MasterAbort		(1U << 31)
212 
213 #define	STGE_RxDMAStatus		0x08
214 
215 #define	STGE_TFDListPtrLo		0x10
216 
217 #define	STGE_TFDListPtrHi		0x14
218 
219 #define	STGE_TxDMABurstThresh		0x18	/* 8-bit */
220 
221 #define	STGE_TxDMAUrgentThresh		0x19	/* 8-bit */
222 
223 #define	STGE_TxDMAPollPeriod		0x1a	/* 8-bit, 320ns increments */
224 
225 #define	STGE_RFDListPtrLo		0x1c
226 
227 #define	STGE_RFDListPtrHi		0x20
228 
229 #define	STGE_RxDMABurstThresh		0x24	/* 8-bit */
230 
231 #define	STGE_RxDMAUrgentThresh		0x25	/* 8-bit */
232 
233 #define	STGE_RxDMAPollPeriod		0x26	/* 8-bit, 320ns increments */
234 
235 #define	STGE_RxDMAIntCtrl		0x28
236 #define	RDIC_RxFrameCount(x)		((x) & 0xff)
237 #define	RDIC_PriorityThresh(x)		((x) << 10)
238 #define	RDIC_RxDMAWaitTime(x)		((x) << 16)
239 /*
240  * Number of receive frames transferred via DMA before a Rx interrupt is issued.
241  */
242 #define	STGE_RXINT_NFRAME_DEFAULT	8
243 #define	STGE_RXINT_NFRAME_MIN		1
244 #define	STGE_RXINT_NFRAME_MAX		255
245 /*
246  * Maximum amount of time (in 64ns increments) to wait before issuing a Rx
247  * interrupt if number of frames recevied is less than STGE_RXINT_NFRAME
248  * (STGE_RXINT_NFRAME_MIN <= STGE_RXINT_NFRAME <= STGE_RXINT_NFRAME_MAX)
249  */
250 #define	STGE_RXINT_DMAWAIT_DEFAULT	30	/* 30us */
251 #define	STGE_RXINT_DMAWAIT_MIN		0
252 #define	STGE_RXINT_DMAWAIT_MAX		4194
253 #define	STGE_RXINT_USECS2TICK(x)	(((x) * 1000)/64)
254 
255 #define	STGE_DebugCtrl			0x2c	/* 16-bit */
256 #define	DC_GPIO0Ctrl			(1U << 0)
257 #define	DC_GPIO1Ctrl			(1U << 1)
258 #define	DC_GPIO0			(1U << 2)
259 #define	DC_GPIO1			(1U << 3)
260 
261 #define	STGE_AsicCtrl			0x30
262 #define	AC_ExpRomDisable		(1U << 0)
263 #define	AC_ExpRomSize			(1U << 1)
264 #define	AC_PhySpeed10			(1U << 4)
265 #define	AC_PhySpeed100			(1U << 5)
266 #define	AC_PhySpeed1000			(1U << 6)
267 #define	AC_PhyMedia			(1U << 7)
268 #define	AC_ForcedConfig(x)		((x) << 8)
269 #define	AC_ForcedConfig_MASK		AC_ForcedConfig(7)
270 #define	AC_D3ResetDisable		(1U << 11)
271 #define	AC_SpeedupMode			(1U << 13)
272 #define	AC_LEDMode			(1U << 14)
273 #define	AC_RstOutPolarity		(1U << 15)
274 #define	AC_GlobalReset			(1U << 16)
275 #define	AC_RxReset			(1U << 17)
276 #define	AC_TxReset			(1U << 18)
277 #define	AC_DMA				(1U << 19)
278 #define	AC_FIFO				(1U << 20)
279 #define	AC_Network			(1U << 21)
280 #define	AC_Host				(1U << 22)
281 #define	AC_AutoInit			(1U << 23)
282 #define	AC_RstOut			(1U << 24)
283 #define	AC_InterruptRequest		(1U << 25)
284 #define	AC_ResetBusy			(1U << 26)
285 #define	AC_LEDSpeed			(1U << 27)
286 #define	AC_LEDModeBit1			(1U << 29)
287 
288 #define	STGE_FIFOCtrl			0x38	/* 16-bit */
289 #define	FC_RAMTestMode			(1U << 0)
290 #define	FC_Transmitting			(1U << 14)
291 #define	FC_Receiving			(1U << 15)
292 
293 #define	STGE_RxEarlyThresh		0x3a	/* 16-bit */
294 
295 #define	STGE_FlowOffThresh		0x3c	/* 16-bit */
296 
297 #define	STGE_FlowOnTresh		0x3e	/* 16-bit */
298 
299 #define	STGE_TxStartThresh		0x44	/* 16-bit */
300 
301 #define	STGE_EepromData			0x48	/* 16-bit */
302 
303 #define	STGE_EepromCtrl			0x4a	/* 16-bit */
304 #define	EC_EepromAddress(x)		((x) & 0xff)
305 #define	EC_EepromOpcode(x)		((x) << 8)
306 #define	EC_OP_WE			0
307 #define	EC_OP_WR			1
308 #define	EC_OP_RR			2
309 #define	EC_OP_ER			3
310 #define	EC_EepromBusy			(1U << 15)
311 
312 #define	STGE_ExpRomAddr			0x4c
313 
314 #define	STGE_ExpRomData			0x50	/* 8-bit */
315 
316 #define	STGE_WakeEvent			0x51	/* 8-bit */
317 #define	WE_WakePktEnable		(1U << 0)
318 #define	WE_MagicPktEnable		(1U << 1)
319 #define	WE_LinkEventEnable		(1U << 2)
320 #define	WE_WakePolarity			(1U << 3)
321 #define	WE_WakePktEvent			(1U << 4)
322 #define	WE_MagicPktEvent		(1U << 5)
323 #define	WE_LinkEvent			(1U << 6)
324 #define	WE_WakeOnLanEnable		(1U << 7)
325 
326 #define	STGE_Countdown			0x54
327 #define	CD_Count(x)			((x) & 0xffff)
328 #define	CD_CountdownSpeed		(1U << 24)
329 #define	CD_CountdownMode		(1U << 25)
330 #define	CD_CountdownIntEnabled		(1U << 26)
331 
332 #define	STGE_IntStatusAck		0x5a	/* 16-bit */
333 
334 #define	STGE_IntEnable			0x5c	/* 16-bit */
335 
336 #define	STGE_IntStatus			0x5e	/* 16-bit */
337 
338 #define	IS_InterruptStatus		(1U << 0)
339 #define	IS_HostError			(1U << 1)
340 #define	IS_TxComplete			(1U << 2)
341 #define	IS_MACControlFrame		(1U << 3)
342 #define	IS_RxComplete			(1U << 4)
343 #define	IS_RxEarly			(1U << 5)
344 #define	IS_InRequested			(1U << 6)
345 #define	IS_UpdateStats			(1U << 7)
346 #define	IS_LinkEvent			(1U << 8)
347 #define	IS_TxDMAComplete		(1U << 9)
348 #define	IS_RxDMAComplete		(1U << 10)
349 #define	IS_RFDListEnd			(1U << 11)
350 #define	IS_RxDMAPriority		(1U << 12)
351 
352 #define	STGE_TxStatus			0x60
353 #define	TS_TxError			(1U << 0)
354 #define	TS_LateCollision		(1U << 2)
355 #define	TS_MaxCollisions		(1U << 3)
356 #define	TS_TxUnderrun			(1U << 4)
357 #define	TS_TxIndicateReqd		(1U << 6)
358 #define	TS_TxComplete			(1U << 7)
359 #define	TS_TxFrameId_get(x)		((x) >> 16)
360 
361 #define	STGE_MACCtrl			0x6c
362 #define	MC_IFSSelect(x)			((x) & 3)
363 #define	MC_IFS96bit			0
364 #define	MC_IFS1024bit			1
365 #define	MC_IFS1792bit			2
366 #define	MC_IFS4352bit			3
367 
368 #define	MC_DuplexSelect			(1U << 5)
369 #define	MC_RcvLargeFrames		(1U << 6)
370 #define	MC_TxFlowControlEnable		(1U << 7)
371 #define	MC_RxFlowControlEnable		(1U << 8)
372 #define	MC_RcvFCS			(1U << 9)
373 #define	MC_FIFOLoopback			(1U << 10)
374 #define	MC_MACLoopback			(1U << 11)
375 #define	MC_AutoVLANtagging		(1U << 12)
376 #define	MC_AutoVLANuntagging		(1U << 13)
377 #define	MC_CollisionDetect		(1U << 16)
378 #define	MC_CarrierSense			(1U << 17)
379 #define	MC_StatisticsEnable		(1U << 21)
380 #define	MC_StatisticsDisable		(1U << 22)
381 #define	MC_StatisticsEnabled		(1U << 23)
382 #define	MC_TxEnable			(1U << 24)
383 #define	MC_TxDisable			(1U << 25)
384 #define	MC_TxEnabled			(1U << 26)
385 #define	MC_RxEnable			(1U << 27)
386 #define	MC_RxDisable			(1U << 28)
387 #define	MC_RxEnabled			(1U << 29)
388 #define	MC_Paused			(1U << 30)
389 #define	MC_MASK				0x7fe33fa3
390 
391 #define	STGE_VLANTag			0x70
392 
393 #define STGE_PhySet			0x75	/* 8-bit */
394 #define	PS_MemLenb9b			(1U << 0)
395 #define	PS_MemLen			(1U << 1)
396 #define	PS_NonCompdet			(1U << 2)
397 
398 #define	STGE_PhyCtrl			0x76	/* 8-bit */
399 #define	PC_MgmtClk			(1U << 0)
400 #define	PC_MgmtData			(1U << 1)
401 #define	PC_MgmtDir			(1U << 2)	/* MAC->PHY */
402 #define	PC_PhyDuplexPolarity		(1U << 3)
403 #define	PC_PhyDuplexStatus		(1U << 4)
404 #define	PC_PhyLnkPolarity		(1U << 5)
405 #define	PC_LinkSpeed(x)			(((x) >> 6) & 3)
406 #define	PC_LinkSpeed_Down		0
407 #define	PC_LinkSpeed_10			1
408 #define	PC_LinkSpeed_100		2
409 #define	PC_LinkSpeed_1000		3
410 
411 #define	STGE_StationAddress0		0x78	/* 16-bit */
412 
413 #define	STGE_StationAddress1		0x7a	/* 16-bit */
414 
415 #define	STGE_StationAddress2		0x7c	/* 16-bit */
416 
417 #define	STGE_VLANHashTable		0x7e	/* 16-bit */
418 
419 #define	STGE_VLANId			0x80
420 
421 #define	STGE_MaxFrameSize		0x86
422 
423 #define	STGE_ReceiveMode		0x88	/* 16-bit */
424 #define	RM_ReceiveUnicast		(1U << 0)
425 #define	RM_ReceiveMulticast		(1U << 1)
426 #define	RM_ReceiveBroadcast		(1U << 2)
427 #define	RM_ReceiveAllFrames		(1U << 3)
428 #define	RM_ReceiveMulticastHash		(1U << 4)
429 #define	RM_ReceiveIPMulticast		(1U << 5)
430 #define	RM_ReceiveVLANMatch		(1U << 8)
431 #define	RM_ReceiveVLANHash		(1U << 9)
432 
433 #define	STGE_HashTable0			0x8c
434 
435 #define	STGE_HashTable1			0x90
436 
437 #define	STGE_RMONStatisticsMask		0x98	/* set to disable */
438 
439 #define	STGE_StatisticsMask		0x9c	/* set to disable */
440 
441 #define	STGE_RxJumboFrames		0xbc	/* 16-bit */
442 
443 #define	STGE_TCPCheckSumErrors		0xc0	/* 16-bit */
444 
445 #define	STGE_IPCheckSumErrors		0xc2	/* 16-bit */
446 
447 #define	STGE_UDPCheckSumErrors		0xc4	/* 16-bit */
448 
449 #define	STGE_TxJumboFrames		0xf4	/* 16-bit */
450 
451 /*
452  * TC9021 statistics.  Available memory and I/O mapped.
453  */
454 
455 #define	STGE_OctetRcvOk			0xa8
456 
457 #define	STGE_McstOctetRcvdOk		0xac
458 
459 #define	STGE_BcstOctetRcvdOk		0xb0
460 
461 #define	STGE_FramesRcvdOk		0xb4
462 
463 #define	STGE_McstFramesRcvdOk		0xb8
464 
465 #define	STGE_BcstFramesRcvdOk		0xbe	/* 16-bit */
466 
467 #define	STGE_MacControlFramesRcvd	0xc6	/* 16-bit */
468 
469 #define	STGE_FrameTooLongErrors		0xc8	/* 16-bit */
470 
471 #define	STGE_InRangeLengthErrors	0xca	/* 16-bit */
472 
473 #define	STGE_FramesCheckSeqErrors	0xcc	/* 16-bit */
474 
475 #define	STGE_FramesLostRxErrors		0xce	/* 16-bit */
476 
477 #define	STGE_OctetXmtdOk		0xd0
478 
479 #define	STGE_McstOctetXmtdOk		0xd4
480 
481 #define	STGE_BcstOctetXmtdOk		0xd8
482 
483 #define	STGE_FramesXmtdOk		0xdc
484 
485 #define	STGE_McstFramesXmtdOk		0xe0
486 
487 #define	STGE_FramesWDeferredXmt		0xe4
488 
489 #define	STGE_LateCollisions		0xe8
490 
491 #define	STGE_MultiColFrames		0xec
492 
493 #define	STGE_SingleColFrames		0xf0
494 
495 #define	STGE_BcstFramesXmtdOk		0xf6	/* 16-bit */
496 
497 #define	STGE_CarrierSenseErrors		0xf8	/* 16-bit */
498 
499 #define	STGE_MacControlFramesXmtd	0xfa	/* 16-bit */
500 
501 #define	STGE_FramesAbortXSColls		0xfc	/* 16-bit */
502 
503 #define	STGE_FramesWEXDeferal		0xfe	/* 16-bit */
504 
505 /*
506  * RMON-compatible statistics.  Only accessible if memory-mapped.
507  */
508 
509 #define	STGE_EtherStatsCollisions			0x100
510 
511 #define	STGE_EtherStatsOctetsTransmit			0x104
512 
513 #define	STGE_EtherStatsPktsTransmit			0x108
514 
515 #define	STGE_EtherStatsPkts64OctetsTransmit		0x10c
516 
517 #define	STGE_EtherStatsPkts64to127OctetsTransmit	0x110
518 
519 #define	STGE_EtherStatsPkts128to255OctetsTransmit	0x114
520 
521 #define	STGE_EtherStatsPkts256to511OctetsTransmit	0x118
522 
523 #define	STGE_EtherStatsPkts512to1023OctetsTransmit	0x11c
524 
525 #define	STGE_EtherStatsPkts1024to1518OctetsTransmit	0x120
526 
527 #define	STGE_EtherStatsCRCAlignErrors			0x124
528 
529 #define	STGE_EtherStatsUndersizePkts			0x128
530 
531 #define	STGE_EtherStatsFragments			0x12c
532 
533 #define	STGE_EtherStatsJabbers				0x130
534 
535 #define	STGE_EtherStatsOctets				0x134
536 
537 #define	STGE_EtherStatsPkts				0x138
538 
539 #define	STGE_EtherStatsPkts64Octets			0x13c
540 
541 #define	STGE_EtherStatsPkts65to127Octets		0x140
542 
543 #define	STGE_EtherStatsPkts128to255Octets		0x144
544 
545 #define	STGE_EtherStatsPkts256to511Octets		0x148
546 
547 #define	STGE_EtherStatsPkts512to1023Octets		0x14c
548 
549 #define	STGE_EtherStatsPkts1024to1518Octets		0x150
550 
551 /*
552  * Transmit descriptor list size.
553  */
554 #define	STGE_TX_RING_CNT	256
555 #define	STGE_TX_LOWAT		(STGE_TX_RING_CNT/32)
556 #define	STGE_TX_HIWAT		(STGE_TX_RING_CNT - STGE_TX_LOWAT)
557 
558 /*
559  * Receive descriptor list size.
560  */
561 #define	STGE_RX_RING_CNT	256
562 
563 #define	STGE_MAXTXSEGS		STGE_NTXFRAGS
564 
565 #define STGE_JUMBO_FRAMELEN	9022
566 #define STGE_JUMBO_MTU	\
567 	(STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
568 
569 struct stge_txdesc {
570 	struct mbuf *tx_m;		/* head of our mbuf chain */
571 	bus_dmamap_t tx_dmamap;		/* our DMA map */
572 	STAILQ_ENTRY(stge_txdesc) tx_q;
573 };
574 
575 STAILQ_HEAD(stge_txdq, stge_txdesc);
576 
577 struct stge_rxdesc {
578 	struct mbuf *rx_m;
579 	bus_dmamap_t rx_dmamap;
580 };
581 
582 #define	STGE_ADDR_LO(x)		((u_int64_t) (x) & 0xffffffff)
583 #define	STGE_ADDR_HI(x)		((u_int64_t) (x) >> 32)
584 
585 #define	STGE_RING_ALIGN		8
586 
587 struct stge_chain_data{
588 	bus_dma_tag_t		stge_parent_tag;
589 	bus_dma_tag_t		stge_tx_tag;
590 	struct stge_txdesc	stge_txdesc[STGE_TX_RING_CNT];
591 	struct stge_txdq	stge_txfreeq;
592 	struct stge_txdq	stge_txbusyq;
593 	bus_dma_tag_t		stge_rx_tag;
594 	struct stge_rxdesc	stge_rxdesc[STGE_RX_RING_CNT];
595 	bus_dma_tag_t		stge_tx_ring_tag;
596 	bus_dmamap_t		stge_tx_ring_map;
597 	bus_dma_tag_t		stge_rx_ring_tag;
598 	bus_dmamap_t		stge_rx_ring_map;
599 	bus_dmamap_t		stge_rx_sparemap;
600 
601 	int			stge_tx_prod;
602 	int			stge_tx_cons;
603 	int			stge_tx_cnt;
604 	int			stge_rx_cons;
605 #ifdef DEVICE_POLLING
606 	int			stge_rxcycles;
607 #endif
608 	int			stge_rxlen;
609 	struct mbuf		*stge_rxhead;
610 	struct mbuf		*stge_rxtail;
611 };
612 
613 struct stge_ring_data {
614 	struct stge_tfd		*stge_tx_ring;
615 	bus_addr_t		stge_tx_ring_paddr;
616 	struct stge_rfd		*stge_rx_ring;
617 	bus_addr_t		stge_rx_ring_paddr;
618 };
619 
620 #define STGE_TX_RING_ADDR(sc, i)	\
621     ((sc)->sc_rdata.stge_tx_ring_paddr + sizeof(struct stge_tfd) * (i))
622 #define STGE_RX_RING_ADDR(sc, i)	\
623     ((sc)->sc_rdata.stge_rx_ring_paddr + sizeof(struct stge_rfd) * (i))
624 
625 #define STGE_TX_RING_SZ		\
626     (sizeof(struct stge_tfd) * STGE_TX_RING_CNT)
627 #define STGE_RX_RING_SZ		\
628     (sizeof(struct stge_rfd) * STGE_RX_RING_CNT)
629 
630 /*
631  * Software state per device.
632  */
633 struct stge_softc {
634 	struct ifnet 		*sc_ifp;	/* interface info */
635 	device_t		sc_dev;
636 	device_t		sc_miibus;
637 	struct resource		*sc_res[2];
638 	struct resource_spec	*sc_spec;
639 	void			*sc_ih;		/* interrupt cookie */
640 	int			sc_rev;		/* silicon revision */
641 
642 	struct callout		sc_tick_ch;	/* tick callout */
643 
644 	struct stge_chain_data	sc_cdata;
645 	struct stge_ring_data	sc_rdata;
646 	int			sc_if_flags;
647 	int			sc_if_framesize;
648 	int			sc_txthresh;	/* Tx threshold */
649 	uint32_t		sc_usefiber:1;	/* if we're fiber */
650 	uint32_t		sc_stge1023:1;	/* are we a 1023 */
651 	uint32_t		sc_DMACtrl;	/* prototype DMACtrl reg. */
652 	uint32_t		sc_MACCtrl;	/* prototype MacCtrl reg. */
653 	uint16_t		sc_IntEnable;	/* prototype IntEnable reg. */
654 	uint16_t		sc_led;		/* LED conf. from EEPROM */
655 	uint8_t			sc_PhyCtrl;	/* prototype PhyCtrl reg. */
656 	int			sc_suspended;
657 	int			sc_detach;
658 
659 	int			sc_rxint_nframe;
660 	int			sc_rxint_dmawait;
661 	int			sc_nerr;
662 	int			sc_watchdog_timer;
663 	int			sc_link;
664 
665 	struct task		sc_link_task;
666 	struct mtx		sc_mii_mtx;	/* MII mutex */
667 	struct mtx		sc_mtx;
668 };
669 
670 #define STGE_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
671 #define STGE_UNLOCK(_sc)	mtx_unlock(&(_sc)->sc_mtx)
672 #define STGE_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
673 #define STGE_MII_LOCK(_sc)	mtx_lock(&(_sc)->sc_mii_mtx)
674 #define STGE_MII_UNLOCK(_sc)	mtx_unlock(&(_sc)->sc_mii_mtx)
675 
676 #define	STGE_MAXERR	5
677 
678 #define	STGE_RXCHAIN_RESET(_sc)						\
679 do {									\
680 	(_sc)->sc_cdata.stge_rxhead = NULL;				\
681 	(_sc)->sc_cdata.stge_rxtail = NULL;				\
682 	(_sc)->sc_cdata.stge_rxlen = 0;					\
683 } while (/*CONSTCOND*/0)
684 
685 #define STGE_TIMEOUT 1000
686 
687 struct stge_mii_frame {
688 	uint8_t	mii_stdelim;
689 	uint8_t	mii_opcode;
690 	uint8_t	mii_phyaddr;
691 	uint8_t	mii_regaddr;
692 	uint8_t	mii_turnaround;
693 	uint16_t mii_data;
694 };
695 
696 /*
697  * MII constants
698  */
699 #define STGE_MII_STARTDELIM	0x01
700 #define STGE_MII_READOP		0x02
701 #define STGE_MII_WRITEOP	0x01
702 #define STGE_MII_TURNAROUND	0x02
703 
704 #define	STGE_RESET_NONE	0x00
705 #define	STGE_RESET_TX	0x01
706 #define	STGE_RESET_RX	0x02
707 #define	STGE_RESET_FULL	0x04
708