1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #ifdef HAVE_KERNEL_OPTION_HEADERS 48 #include "opt_device_polling.h" 49 #endif 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/endian.h> 54 #include <sys/mbuf.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #include <sys/module.h> 58 #include <sys/socket.h> 59 #include <sys/sockio.h> 60 #include <sys/sysctl.h> 61 #include <sys/taskqueue.h> 62 63 #include <net/bpf.h> 64 #include <net/ethernet.h> 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_types.h> 69 #include <net/if_vlan_var.h> 70 71 #include <machine/bus.h> 72 #include <machine/resource.h> 73 #include <sys/bus.h> 74 #include <sys/rman.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 82 #include <dev/stge/if_stgereg.h> 83 84 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85 86 MODULE_DEPEND(stge, pci, 1, 1, 1); 87 MODULE_DEPEND(stge, ether, 1, 1, 1); 88 MODULE_DEPEND(stge, miibus, 1, 1, 1); 89 90 /* "device miibus" required. See GENERIC if you get errors here. */ 91 #include "miibus_if.h" 92 93 /* 94 * Devices supported by this driver. 95 */ 96 static struct stge_product { 97 uint16_t stge_vendorid; 98 uint16_t stge_deviceid; 99 const char *stge_name; 100 } stge_products[] = { 101 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023, 102 "Sundance ST-1023 Gigabit Ethernet" }, 103 104 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021, 105 "Sundance ST-2021 Gigabit Ethernet" }, 106 107 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021, 108 "Tamarack TC9021 Gigabit Ethernet" }, 109 110 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT, 111 "Tamarack TC9021 Gigabit Ethernet" }, 112 113 /* 114 * The Sundance sample boards use the Sundance vendor ID, 115 * but the Tamarack product ID. 116 */ 117 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021, 118 "Sundance TC9021 Gigabit Ethernet" }, 119 120 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT, 121 "Sundance TC9021 Gigabit Ethernet" }, 122 123 { VENDOR_DLINK, DEVICEID_DLINK_DL4000, 124 "D-Link DL-4000 Gigabit Ethernet" }, 125 126 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021, 127 "Antares Gigabit Ethernet" } 128 }; 129 130 static int stge_probe(device_t); 131 static int stge_attach(device_t); 132 static int stge_detach(device_t); 133 static int stge_shutdown(device_t); 134 static int stge_suspend(device_t); 135 static int stge_resume(device_t); 136 137 static int stge_encap(struct stge_softc *, struct mbuf **); 138 static void stge_start(struct ifnet *); 139 static void stge_start_locked(struct ifnet *); 140 static void stge_watchdog(struct stge_softc *); 141 static int stge_ioctl(struct ifnet *, u_long, caddr_t); 142 static void stge_init(void *); 143 static void stge_init_locked(struct stge_softc *); 144 static void stge_vlan_setup(struct stge_softc *); 145 static void stge_stop(struct stge_softc *); 146 static void stge_start_tx(struct stge_softc *); 147 static void stge_start_rx(struct stge_softc *); 148 static void stge_stop_tx(struct stge_softc *); 149 static void stge_stop_rx(struct stge_softc *); 150 151 static void stge_reset(struct stge_softc *, uint32_t); 152 static int stge_eeprom_wait(struct stge_softc *); 153 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 154 static void stge_tick(void *); 155 static void stge_stats_update(struct stge_softc *); 156 static void stge_set_filter(struct stge_softc *); 157 static void stge_set_multi(struct stge_softc *); 158 159 static void stge_link_task(void *, int); 160 static void stge_intr(void *); 161 static __inline int stge_tx_error(struct stge_softc *); 162 static void stge_txeof(struct stge_softc *); 163 static int stge_rxeof(struct stge_softc *); 164 static __inline void stge_discard_rxbuf(struct stge_softc *, int); 165 static int stge_newbuf(struct stge_softc *, int); 166 #ifndef __NO_STRICT_ALIGNMENT 167 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *); 168 #endif 169 170 static void stge_mii_sync(struct stge_softc *); 171 static void stge_mii_send(struct stge_softc *, uint32_t, int); 172 static int stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *); 173 static int stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *); 174 static int stge_miibus_readreg(device_t, int, int); 175 static int stge_miibus_writereg(device_t, int, int, int); 176 static void stge_miibus_statchg(device_t); 177 static int stge_mediachange(struct ifnet *); 178 static void stge_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 181 static int stge_dma_alloc(struct stge_softc *); 182 static void stge_dma_free(struct stge_softc *); 183 static void stge_dma_wait(struct stge_softc *); 184 static void stge_init_tx_ring(struct stge_softc *); 185 static int stge_init_rx_ring(struct stge_softc *); 186 #ifdef DEVICE_POLLING 187 static int stge_poll(struct ifnet *, enum poll_cmd, int); 188 #endif 189 190 static void stge_setwol(struct stge_softc *); 191 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 192 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS); 193 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS); 194 195 static device_method_t stge_methods[] = { 196 /* Device interface */ 197 DEVMETHOD(device_probe, stge_probe), 198 DEVMETHOD(device_attach, stge_attach), 199 DEVMETHOD(device_detach, stge_detach), 200 DEVMETHOD(device_shutdown, stge_shutdown), 201 DEVMETHOD(device_suspend, stge_suspend), 202 DEVMETHOD(device_resume, stge_resume), 203 204 /* MII interface */ 205 DEVMETHOD(miibus_readreg, stge_miibus_readreg), 206 DEVMETHOD(miibus_writereg, stge_miibus_writereg), 207 DEVMETHOD(miibus_statchg, stge_miibus_statchg), 208 209 { 0, 0 } 210 211 }; 212 213 static driver_t stge_driver = { 214 "stge", 215 stge_methods, 216 sizeof(struct stge_softc) 217 }; 218 219 static devclass_t stge_devclass; 220 221 DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0); 222 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0); 223 224 static struct resource_spec stge_res_spec_io[] = { 225 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE }, 226 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 227 { -1, 0, 0 } 228 }; 229 230 static struct resource_spec stge_res_spec_mem[] = { 231 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, 232 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 233 { -1, 0, 0 } 234 }; 235 236 #define MII_SET(x) \ 237 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x)) 238 #define MII_CLR(x) \ 239 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x)) 240 241 /* 242 * Sync the PHYs by setting data bit and strobing the clock 32 times. 243 */ 244 static void 245 stge_mii_sync(struct stge_softc *sc) 246 { 247 int i; 248 249 MII_SET(PC_MgmtDir | PC_MgmtData); 250 251 for (i = 0; i < 32; i++) { 252 MII_SET(PC_MgmtClk); 253 DELAY(1); 254 MII_CLR(PC_MgmtClk); 255 DELAY(1); 256 } 257 } 258 259 /* 260 * Clock a series of bits through the MII. 261 */ 262 static void 263 stge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt) 264 { 265 int i; 266 267 MII_CLR(PC_MgmtClk); 268 269 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 270 if (bits & i) 271 MII_SET(PC_MgmtData); 272 else 273 MII_CLR(PC_MgmtData); 274 DELAY(1); 275 MII_CLR(PC_MgmtClk); 276 DELAY(1); 277 MII_SET(PC_MgmtClk); 278 } 279 } 280 281 /* 282 * Read an PHY register through the MII. 283 */ 284 static int 285 stge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame) 286 { 287 int i, ack; 288 289 /* 290 * Set up frame for RX. 291 */ 292 frame->mii_stdelim = STGE_MII_STARTDELIM; 293 frame->mii_opcode = STGE_MII_READOP; 294 frame->mii_turnaround = 0; 295 frame->mii_data = 0; 296 297 CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl); 298 /* 299 * Turn on data xmit. 300 */ 301 MII_SET(PC_MgmtDir); 302 303 stge_mii_sync(sc); 304 305 /* 306 * Send command/address info. 307 */ 308 stge_mii_send(sc, frame->mii_stdelim, 2); 309 stge_mii_send(sc, frame->mii_opcode, 2); 310 stge_mii_send(sc, frame->mii_phyaddr, 5); 311 stge_mii_send(sc, frame->mii_regaddr, 5); 312 313 /* Turn off xmit. */ 314 MII_CLR(PC_MgmtDir); 315 316 /* Idle bit */ 317 MII_CLR((PC_MgmtClk | PC_MgmtData)); 318 DELAY(1); 319 MII_SET(PC_MgmtClk); 320 DELAY(1); 321 322 /* Check for ack */ 323 MII_CLR(PC_MgmtClk); 324 DELAY(1); 325 ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData; 326 MII_SET(PC_MgmtClk); 327 DELAY(1); 328 329 /* 330 * Now try reading data bits. If the ack failed, we still 331 * need to clock through 16 cycles to keep the PHY(s) in sync. 332 */ 333 if (ack) { 334 for(i = 0; i < 16; i++) { 335 MII_CLR(PC_MgmtClk); 336 DELAY(1); 337 MII_SET(PC_MgmtClk); 338 DELAY(1); 339 } 340 goto fail; 341 } 342 343 for (i = 0x8000; i; i >>= 1) { 344 MII_CLR(PC_MgmtClk); 345 DELAY(1); 346 if (!ack) { 347 if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData) 348 frame->mii_data |= i; 349 DELAY(1); 350 } 351 MII_SET(PC_MgmtClk); 352 DELAY(1); 353 } 354 355 fail: 356 MII_CLR(PC_MgmtClk); 357 DELAY(1); 358 MII_SET(PC_MgmtClk); 359 DELAY(1); 360 361 if (ack) 362 return(1); 363 return(0); 364 } 365 366 /* 367 * Write to a PHY register through the MII. 368 */ 369 static int 370 stge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame) 371 { 372 373 /* 374 * Set up frame for TX. 375 */ 376 frame->mii_stdelim = STGE_MII_STARTDELIM; 377 frame->mii_opcode = STGE_MII_WRITEOP; 378 frame->mii_turnaround = STGE_MII_TURNAROUND; 379 380 /* 381 * Turn on data output. 382 */ 383 MII_SET(PC_MgmtDir); 384 385 stge_mii_sync(sc); 386 387 stge_mii_send(sc, frame->mii_stdelim, 2); 388 stge_mii_send(sc, frame->mii_opcode, 2); 389 stge_mii_send(sc, frame->mii_phyaddr, 5); 390 stge_mii_send(sc, frame->mii_regaddr, 5); 391 stge_mii_send(sc, frame->mii_turnaround, 2); 392 stge_mii_send(sc, frame->mii_data, 16); 393 394 /* Idle bit. */ 395 MII_SET(PC_MgmtClk); 396 DELAY(1); 397 MII_CLR(PC_MgmtClk); 398 DELAY(1); 399 400 /* 401 * Turn off xmit. 402 */ 403 MII_CLR(PC_MgmtDir); 404 405 return(0); 406 } 407 408 /* 409 * sc_miibus_readreg: [mii interface function] 410 * 411 * Read a PHY register on the MII of the TC9021. 412 */ 413 static int 414 stge_miibus_readreg(device_t dev, int phy, int reg) 415 { 416 struct stge_softc *sc; 417 struct stge_mii_frame frame; 418 int error; 419 420 sc = device_get_softc(dev); 421 422 if (reg == STGE_PhyCtrl) { 423 /* XXX allow ip1000phy read STGE_PhyCtrl register. */ 424 STGE_MII_LOCK(sc); 425 error = CSR_READ_1(sc, STGE_PhyCtrl); 426 STGE_MII_UNLOCK(sc); 427 return (error); 428 } 429 bzero(&frame, sizeof(frame)); 430 frame.mii_phyaddr = phy; 431 frame.mii_regaddr = reg; 432 433 STGE_MII_LOCK(sc); 434 error = stge_mii_readreg(sc, &frame); 435 STGE_MII_UNLOCK(sc); 436 437 if (error != 0) { 438 /* Don't show errors for PHY probe request */ 439 if (reg != 1) 440 device_printf(sc->sc_dev, "phy read fail\n"); 441 return (0); 442 } 443 return (frame.mii_data); 444 } 445 446 /* 447 * stge_miibus_writereg: [mii interface function] 448 * 449 * Write a PHY register on the MII of the TC9021. 450 */ 451 static int 452 stge_miibus_writereg(device_t dev, int phy, int reg, int val) 453 { 454 struct stge_softc *sc; 455 struct stge_mii_frame frame; 456 int error; 457 458 sc = device_get_softc(dev); 459 460 bzero(&frame, sizeof(frame)); 461 frame.mii_phyaddr = phy; 462 frame.mii_regaddr = reg; 463 frame.mii_data = val; 464 465 STGE_MII_LOCK(sc); 466 error = stge_mii_writereg(sc, &frame); 467 STGE_MII_UNLOCK(sc); 468 469 if (error != 0) 470 device_printf(sc->sc_dev, "phy write fail\n"); 471 return (0); 472 } 473 474 /* 475 * stge_miibus_statchg: [mii interface function] 476 * 477 * Callback from MII layer when media changes. 478 */ 479 static void 480 stge_miibus_statchg(device_t dev) 481 { 482 struct stge_softc *sc; 483 484 sc = device_get_softc(dev); 485 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task); 486 } 487 488 /* 489 * stge_mediastatus: [ifmedia interface function] 490 * 491 * Get the current interface media status. 492 */ 493 static void 494 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 495 { 496 struct stge_softc *sc; 497 struct mii_data *mii; 498 499 sc = ifp->if_softc; 500 mii = device_get_softc(sc->sc_miibus); 501 502 mii_pollstat(mii); 503 ifmr->ifm_status = mii->mii_media_status; 504 ifmr->ifm_active = mii->mii_media_active; 505 } 506 507 /* 508 * stge_mediachange: [ifmedia interface function] 509 * 510 * Set hardware to newly-selected media. 511 */ 512 static int 513 stge_mediachange(struct ifnet *ifp) 514 { 515 struct stge_softc *sc; 516 struct mii_data *mii; 517 518 sc = ifp->if_softc; 519 mii = device_get_softc(sc->sc_miibus); 520 mii_mediachg(mii); 521 522 return (0); 523 } 524 525 static int 526 stge_eeprom_wait(struct stge_softc *sc) 527 { 528 int i; 529 530 for (i = 0; i < STGE_TIMEOUT; i++) { 531 DELAY(1000); 532 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 533 return (0); 534 } 535 return (1); 536 } 537 538 /* 539 * stge_read_eeprom: 540 * 541 * Read data from the serial EEPROM. 542 */ 543 static void 544 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 545 { 546 547 if (stge_eeprom_wait(sc)) 548 device_printf(sc->sc_dev, "EEPROM failed to come ready\n"); 549 550 CSR_WRITE_2(sc, STGE_EepromCtrl, 551 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 552 if (stge_eeprom_wait(sc)) 553 device_printf(sc->sc_dev, "EEPROM read timed out\n"); 554 *data = CSR_READ_2(sc, STGE_EepromData); 555 } 556 557 558 static int 559 stge_probe(device_t dev) 560 { 561 struct stge_product *sp; 562 int i; 563 uint16_t vendor, devid; 564 565 vendor = pci_get_vendor(dev); 566 devid = pci_get_device(dev); 567 sp = stge_products; 568 for (i = 0; i < sizeof(stge_products)/sizeof(stge_products[0]); 569 i++, sp++) { 570 if (vendor == sp->stge_vendorid && 571 devid == sp->stge_deviceid) { 572 device_set_desc(dev, sp->stge_name); 573 return (BUS_PROBE_DEFAULT); 574 } 575 } 576 577 return (ENXIO); 578 } 579 580 static int 581 stge_attach(device_t dev) 582 { 583 struct stge_softc *sc; 584 struct ifnet *ifp; 585 uint8_t enaddr[ETHER_ADDR_LEN]; 586 int error, i; 587 uint16_t cmd; 588 uint32_t val; 589 590 error = 0; 591 sc = device_get_softc(dev); 592 sc->sc_dev = dev; 593 594 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 595 MTX_DEF); 596 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF); 597 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 598 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc); 599 600 /* 601 * Map the device. 602 */ 603 pci_enable_busmaster(dev); 604 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 605 val = pci_read_config(dev, PCIR_BAR(1), 4); 606 if ((val & 0x01) != 0) 607 sc->sc_spec = stge_res_spec_mem; 608 else { 609 val = pci_read_config(dev, PCIR_BAR(0), 4); 610 if ((val & 0x01) == 0) { 611 device_printf(sc->sc_dev, "couldn't locate IO BAR\n"); 612 error = ENXIO; 613 goto fail; 614 } 615 sc->sc_spec = stge_res_spec_io; 616 } 617 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res); 618 if (error != 0) { 619 device_printf(dev, "couldn't allocate %s resources\n", 620 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O"); 621 goto fail; 622 } 623 sc->sc_rev = pci_get_revid(dev); 624 625 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 626 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 627 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0, 628 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe"); 629 630 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 631 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 632 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0, 633 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait"); 634 635 /* Pull in device tunables. */ 636 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 637 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 638 "rxint_nframe", &sc->sc_rxint_nframe); 639 if (error == 0) { 640 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN || 641 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) { 642 device_printf(dev, "rxint_nframe value out of range; " 643 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT); 644 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 645 } 646 } 647 648 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 649 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 650 "rxint_dmawait", &sc->sc_rxint_dmawait); 651 if (error == 0) { 652 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN || 653 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) { 654 device_printf(dev, "rxint_dmawait value out of range; " 655 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT); 656 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 657 } 658 } 659 660 if ((error = stge_dma_alloc(sc) != 0)) 661 goto fail; 662 663 /* 664 * Determine if we're copper or fiber. It affects how we 665 * reset the card. 666 */ 667 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 668 sc->sc_usefiber = 1; 669 else 670 sc->sc_usefiber = 0; 671 672 /* Load LED configuration from EEPROM. */ 673 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led); 674 675 /* 676 * Reset the chip to a known state. 677 */ 678 STGE_LOCK(sc); 679 stge_reset(sc, STGE_RESET_FULL); 680 STGE_UNLOCK(sc); 681 682 /* 683 * Reading the station address from the EEPROM doesn't seem 684 * to work, at least on my sample boards. Instead, since 685 * the reset sequence does AutoInit, read it from the station 686 * address registers. For Sundance 1023 you can only read it 687 * from EEPROM. 688 */ 689 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) { 690 uint16_t v; 691 692 v = CSR_READ_2(sc, STGE_StationAddress0); 693 enaddr[0] = v & 0xff; 694 enaddr[1] = v >> 8; 695 v = CSR_READ_2(sc, STGE_StationAddress1); 696 enaddr[2] = v & 0xff; 697 enaddr[3] = v >> 8; 698 v = CSR_READ_2(sc, STGE_StationAddress2); 699 enaddr[4] = v & 0xff; 700 enaddr[5] = v >> 8; 701 sc->sc_stge1023 = 0; 702 } else { 703 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 704 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 705 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 706 &myaddr[i]); 707 myaddr[i] = le16toh(myaddr[i]); 708 } 709 bcopy(myaddr, enaddr, sizeof(enaddr)); 710 sc->sc_stge1023 = 1; 711 } 712 713 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 714 if (ifp == NULL) { 715 device_printf(sc->sc_dev, "failed to if_alloc()\n"); 716 error = ENXIO; 717 goto fail; 718 } 719 720 ifp->if_softc = sc; 721 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 722 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 723 ifp->if_ioctl = stge_ioctl; 724 ifp->if_start = stge_start; 725 ifp->if_init = stge_init; 726 ifp->if_mtu = ETHERMTU; 727 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1; 728 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 729 IFQ_SET_READY(&ifp->if_snd); 730 /* Revision B3 and earlier chips have checksum bug. */ 731 if (sc->sc_rev >= 0x0c) { 732 ifp->if_hwassist = STGE_CSUM_FEATURES; 733 ifp->if_capabilities = IFCAP_HWCSUM; 734 } else { 735 ifp->if_hwassist = 0; 736 ifp->if_capabilities = 0; 737 } 738 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 739 ifp->if_capenable = ifp->if_capabilities; 740 741 /* 742 * Read some important bits from the PhyCtrl register. 743 */ 744 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 745 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 746 747 /* Set up MII bus. */ 748 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, stge_mediachange, 749 stge_mediastatus)) != 0) { 750 device_printf(sc->sc_dev, "no PHY found!\n"); 751 goto fail; 752 } 753 754 ether_ifattach(ifp, enaddr); 755 756 /* VLAN capability setup */ 757 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 758 if (sc->sc_rev >= 0x0c) 759 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 760 ifp->if_capenable = ifp->if_capabilities; 761 #ifdef DEVICE_POLLING 762 ifp->if_capabilities |= IFCAP_POLLING; 763 #endif 764 /* 765 * Tell the upper layer(s) we support long frames. 766 * Must appear after the call to ether_ifattach() because 767 * ether_ifattach() sets ifi_hdrlen to the default value. 768 */ 769 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 770 771 /* 772 * The manual recommends disabling early transmit, so we 773 * do. It's disabled anyway, if using IP checksumming, 774 * since the entire packet must be in the FIFO in order 775 * for the chip to perform the checksum. 776 */ 777 sc->sc_txthresh = 0x0fff; 778 779 /* 780 * Disable MWI if the PCI layer tells us to. 781 */ 782 sc->sc_DMACtrl = 0; 783 if ((cmd & PCIM_CMD_MWRICEN) == 0) 784 sc->sc_DMACtrl |= DMAC_MWIDisable; 785 786 /* 787 * Hookup IRQ 788 */ 789 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE, 790 NULL, stge_intr, sc, &sc->sc_ih); 791 if (error != 0) { 792 ether_ifdetach(ifp); 793 device_printf(sc->sc_dev, "couldn't set up IRQ\n"); 794 sc->sc_ifp = NULL; 795 goto fail; 796 } 797 798 fail: 799 if (error != 0) 800 stge_detach(dev); 801 802 return (error); 803 } 804 805 static int 806 stge_detach(device_t dev) 807 { 808 struct stge_softc *sc; 809 struct ifnet *ifp; 810 811 sc = device_get_softc(dev); 812 813 ifp = sc->sc_ifp; 814 #ifdef DEVICE_POLLING 815 if (ifp && ifp->if_capenable & IFCAP_POLLING) 816 ether_poll_deregister(ifp); 817 #endif 818 if (device_is_attached(dev)) { 819 STGE_LOCK(sc); 820 /* XXX */ 821 sc->sc_detach = 1; 822 stge_stop(sc); 823 STGE_UNLOCK(sc); 824 callout_drain(&sc->sc_tick_ch); 825 taskqueue_drain(taskqueue_swi, &sc->sc_link_task); 826 ether_ifdetach(ifp); 827 } 828 829 if (sc->sc_miibus != NULL) { 830 device_delete_child(dev, sc->sc_miibus); 831 sc->sc_miibus = NULL; 832 } 833 bus_generic_detach(dev); 834 stge_dma_free(sc); 835 836 if (ifp != NULL) { 837 if_free(ifp); 838 sc->sc_ifp = NULL; 839 } 840 841 if (sc->sc_ih) { 842 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih); 843 sc->sc_ih = NULL; 844 } 845 bus_release_resources(dev, sc->sc_spec, sc->sc_res); 846 847 mtx_destroy(&sc->sc_mii_mtx); 848 mtx_destroy(&sc->sc_mtx); 849 850 return (0); 851 } 852 853 struct stge_dmamap_arg { 854 bus_addr_t stge_busaddr; 855 }; 856 857 static void 858 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 859 { 860 struct stge_dmamap_arg *ctx; 861 862 if (error != 0) 863 return; 864 865 ctx = (struct stge_dmamap_arg *)arg; 866 ctx->stge_busaddr = segs[0].ds_addr; 867 } 868 869 static int 870 stge_dma_alloc(struct stge_softc *sc) 871 { 872 struct stge_dmamap_arg ctx; 873 struct stge_txdesc *txd; 874 struct stge_rxdesc *rxd; 875 int error, i; 876 877 /* create parent tag. */ 878 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */ 879 1, 0, /* algnmnt, boundary */ 880 STGE_DMA_MAXADDR, /* lowaddr */ 881 BUS_SPACE_MAXADDR, /* highaddr */ 882 NULL, NULL, /* filter, filterarg */ 883 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 884 0, /* nsegments */ 885 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 886 0, /* flags */ 887 NULL, NULL, /* lockfunc, lockarg */ 888 &sc->sc_cdata.stge_parent_tag); 889 if (error != 0) { 890 device_printf(sc->sc_dev, "failed to create parent DMA tag\n"); 891 goto fail; 892 } 893 /* create tag for Tx ring. */ 894 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 895 STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 896 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 897 BUS_SPACE_MAXADDR, /* highaddr */ 898 NULL, NULL, /* filter, filterarg */ 899 STGE_TX_RING_SZ, /* maxsize */ 900 1, /* nsegments */ 901 STGE_TX_RING_SZ, /* maxsegsize */ 902 0, /* flags */ 903 NULL, NULL, /* lockfunc, lockarg */ 904 &sc->sc_cdata.stge_tx_ring_tag); 905 if (error != 0) { 906 device_printf(sc->sc_dev, 907 "failed to allocate Tx ring DMA tag\n"); 908 goto fail; 909 } 910 911 /* create tag for Rx ring. */ 912 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 913 STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 914 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 915 BUS_SPACE_MAXADDR, /* highaddr */ 916 NULL, NULL, /* filter, filterarg */ 917 STGE_RX_RING_SZ, /* maxsize */ 918 1, /* nsegments */ 919 STGE_RX_RING_SZ, /* maxsegsize */ 920 0, /* flags */ 921 NULL, NULL, /* lockfunc, lockarg */ 922 &sc->sc_cdata.stge_rx_ring_tag); 923 if (error != 0) { 924 device_printf(sc->sc_dev, 925 "failed to allocate Rx ring DMA tag\n"); 926 goto fail; 927 } 928 929 /* create tag for Tx buffers. */ 930 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 931 1, 0, /* algnmnt, boundary */ 932 BUS_SPACE_MAXADDR, /* lowaddr */ 933 BUS_SPACE_MAXADDR, /* highaddr */ 934 NULL, NULL, /* filter, filterarg */ 935 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */ 936 STGE_MAXTXSEGS, /* nsegments */ 937 MCLBYTES, /* maxsegsize */ 938 0, /* flags */ 939 NULL, NULL, /* lockfunc, lockarg */ 940 &sc->sc_cdata.stge_tx_tag); 941 if (error != 0) { 942 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n"); 943 goto fail; 944 } 945 946 /* create tag for Rx buffers. */ 947 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 948 1, 0, /* algnmnt, boundary */ 949 BUS_SPACE_MAXADDR, /* lowaddr */ 950 BUS_SPACE_MAXADDR, /* highaddr */ 951 NULL, NULL, /* filter, filterarg */ 952 MCLBYTES, /* maxsize */ 953 1, /* nsegments */ 954 MCLBYTES, /* maxsegsize */ 955 0, /* flags */ 956 NULL, NULL, /* lockfunc, lockarg */ 957 &sc->sc_cdata.stge_rx_tag); 958 if (error != 0) { 959 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n"); 960 goto fail; 961 } 962 963 /* allocate DMA'able memory and load the DMA map for Tx ring. */ 964 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag, 965 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 966 &sc->sc_cdata.stge_tx_ring_map); 967 if (error != 0) { 968 device_printf(sc->sc_dev, 969 "failed to allocate DMA'able memory for Tx ring\n"); 970 goto fail; 971 } 972 973 ctx.stge_busaddr = 0; 974 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag, 975 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring, 976 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 977 if (error != 0 || ctx.stge_busaddr == 0) { 978 device_printf(sc->sc_dev, 979 "failed to load DMA'able memory for Tx ring\n"); 980 goto fail; 981 } 982 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr; 983 984 /* allocate DMA'able memory and load the DMA map for Rx ring. */ 985 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag, 986 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 987 &sc->sc_cdata.stge_rx_ring_map); 988 if (error != 0) { 989 device_printf(sc->sc_dev, 990 "failed to allocate DMA'able memory for Rx ring\n"); 991 goto fail; 992 } 993 994 ctx.stge_busaddr = 0; 995 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag, 996 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring, 997 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 998 if (error != 0 || ctx.stge_busaddr == 0) { 999 device_printf(sc->sc_dev, 1000 "failed to load DMA'able memory for Rx ring\n"); 1001 goto fail; 1002 } 1003 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr; 1004 1005 /* create DMA maps for Tx buffers. */ 1006 for (i = 0; i < STGE_TX_RING_CNT; i++) { 1007 txd = &sc->sc_cdata.stge_txdesc[i]; 1008 txd->tx_m = NULL; 1009 txd->tx_dmamap = 0; 1010 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0, 1011 &txd->tx_dmamap); 1012 if (error != 0) { 1013 device_printf(sc->sc_dev, 1014 "failed to create Tx dmamap\n"); 1015 goto fail; 1016 } 1017 } 1018 /* create DMA maps for Rx buffers. */ 1019 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 1020 &sc->sc_cdata.stge_rx_sparemap)) != 0) { 1021 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n"); 1022 goto fail; 1023 } 1024 for (i = 0; i < STGE_RX_RING_CNT; i++) { 1025 rxd = &sc->sc_cdata.stge_rxdesc[i]; 1026 rxd->rx_m = NULL; 1027 rxd->rx_dmamap = 0; 1028 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 1029 &rxd->rx_dmamap); 1030 if (error != 0) { 1031 device_printf(sc->sc_dev, 1032 "failed to create Rx dmamap\n"); 1033 goto fail; 1034 } 1035 } 1036 1037 fail: 1038 return (error); 1039 } 1040 1041 static void 1042 stge_dma_free(struct stge_softc *sc) 1043 { 1044 struct stge_txdesc *txd; 1045 struct stge_rxdesc *rxd; 1046 int i; 1047 1048 /* Tx ring */ 1049 if (sc->sc_cdata.stge_tx_ring_tag) { 1050 if (sc->sc_cdata.stge_tx_ring_map) 1051 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag, 1052 sc->sc_cdata.stge_tx_ring_map); 1053 if (sc->sc_cdata.stge_tx_ring_map && 1054 sc->sc_rdata.stge_tx_ring) 1055 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag, 1056 sc->sc_rdata.stge_tx_ring, 1057 sc->sc_cdata.stge_tx_ring_map); 1058 sc->sc_rdata.stge_tx_ring = NULL; 1059 sc->sc_cdata.stge_tx_ring_map = 0; 1060 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag); 1061 sc->sc_cdata.stge_tx_ring_tag = NULL; 1062 } 1063 /* Rx ring */ 1064 if (sc->sc_cdata.stge_rx_ring_tag) { 1065 if (sc->sc_cdata.stge_rx_ring_map) 1066 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag, 1067 sc->sc_cdata.stge_rx_ring_map); 1068 if (sc->sc_cdata.stge_rx_ring_map && 1069 sc->sc_rdata.stge_rx_ring) 1070 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag, 1071 sc->sc_rdata.stge_rx_ring, 1072 sc->sc_cdata.stge_rx_ring_map); 1073 sc->sc_rdata.stge_rx_ring = NULL; 1074 sc->sc_cdata.stge_rx_ring_map = 0; 1075 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag); 1076 sc->sc_cdata.stge_rx_ring_tag = NULL; 1077 } 1078 /* Tx buffers */ 1079 if (sc->sc_cdata.stge_tx_tag) { 1080 for (i = 0; i < STGE_TX_RING_CNT; i++) { 1081 txd = &sc->sc_cdata.stge_txdesc[i]; 1082 if (txd->tx_dmamap) { 1083 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag, 1084 txd->tx_dmamap); 1085 txd->tx_dmamap = 0; 1086 } 1087 } 1088 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag); 1089 sc->sc_cdata.stge_tx_tag = NULL; 1090 } 1091 /* Rx buffers */ 1092 if (sc->sc_cdata.stge_rx_tag) { 1093 for (i = 0; i < STGE_RX_RING_CNT; i++) { 1094 rxd = &sc->sc_cdata.stge_rxdesc[i]; 1095 if (rxd->rx_dmamap) { 1096 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 1097 rxd->rx_dmamap); 1098 rxd->rx_dmamap = 0; 1099 } 1100 } 1101 if (sc->sc_cdata.stge_rx_sparemap) { 1102 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 1103 sc->sc_cdata.stge_rx_sparemap); 1104 sc->sc_cdata.stge_rx_sparemap = 0; 1105 } 1106 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag); 1107 sc->sc_cdata.stge_rx_tag = NULL; 1108 } 1109 1110 if (sc->sc_cdata.stge_parent_tag) { 1111 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag); 1112 sc->sc_cdata.stge_parent_tag = NULL; 1113 } 1114 } 1115 1116 /* 1117 * stge_shutdown: 1118 * 1119 * Make sure the interface is stopped at reboot time. 1120 */ 1121 static int 1122 stge_shutdown(device_t dev) 1123 { 1124 1125 return (stge_suspend(dev)); 1126 } 1127 1128 static void 1129 stge_setwol(struct stge_softc *sc) 1130 { 1131 struct ifnet *ifp; 1132 uint8_t v; 1133 1134 STGE_LOCK_ASSERT(sc); 1135 1136 ifp = sc->sc_ifp; 1137 v = CSR_READ_1(sc, STGE_WakeEvent); 1138 /* Disable all WOL bits. */ 1139 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 1140 WE_WakeOnLanEnable); 1141 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1142 v |= WE_MagicPktEnable | WE_WakeOnLanEnable; 1143 CSR_WRITE_1(sc, STGE_WakeEvent, v); 1144 /* Reset Tx and prevent transmission. */ 1145 CSR_WRITE_4(sc, STGE_AsicCtrl, 1146 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset); 1147 /* 1148 * TC9021 automatically reset link speed to 100Mbps when it's put 1149 * into sleep so there is no need to try to resetting link speed. 1150 */ 1151 } 1152 1153 static int 1154 stge_suspend(device_t dev) 1155 { 1156 struct stge_softc *sc; 1157 1158 sc = device_get_softc(dev); 1159 1160 STGE_LOCK(sc); 1161 stge_stop(sc); 1162 sc->sc_suspended = 1; 1163 stge_setwol(sc); 1164 STGE_UNLOCK(sc); 1165 1166 return (0); 1167 } 1168 1169 static int 1170 stge_resume(device_t dev) 1171 { 1172 struct stge_softc *sc; 1173 struct ifnet *ifp; 1174 uint8_t v; 1175 1176 sc = device_get_softc(dev); 1177 1178 STGE_LOCK(sc); 1179 /* 1180 * Clear WOL bits, so special frames wouldn't interfere 1181 * normal Rx operation anymore. 1182 */ 1183 v = CSR_READ_1(sc, STGE_WakeEvent); 1184 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 1185 WE_WakeOnLanEnable); 1186 CSR_WRITE_1(sc, STGE_WakeEvent, v); 1187 ifp = sc->sc_ifp; 1188 if (ifp->if_flags & IFF_UP) 1189 stge_init_locked(sc); 1190 1191 sc->sc_suspended = 0; 1192 STGE_UNLOCK(sc); 1193 1194 return (0); 1195 } 1196 1197 static void 1198 stge_dma_wait(struct stge_softc *sc) 1199 { 1200 int i; 1201 1202 for (i = 0; i < STGE_TIMEOUT; i++) { 1203 DELAY(2); 1204 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 1205 break; 1206 } 1207 1208 if (i == STGE_TIMEOUT) 1209 device_printf(sc->sc_dev, "DMA wait timed out\n"); 1210 } 1211 1212 static int 1213 stge_encap(struct stge_softc *sc, struct mbuf **m_head) 1214 { 1215 struct stge_txdesc *txd; 1216 struct stge_tfd *tfd; 1217 struct mbuf *m; 1218 bus_dma_segment_t txsegs[STGE_MAXTXSEGS]; 1219 int error, i, nsegs, si; 1220 uint64_t csum_flags, tfc; 1221 1222 STGE_LOCK_ASSERT(sc); 1223 1224 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL) 1225 return (ENOBUFS); 1226 1227 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1228 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1229 if (error == EFBIG) { 1230 m = m_collapse(*m_head, M_DONTWAIT, STGE_MAXTXSEGS); 1231 if (m == NULL) { 1232 m_freem(*m_head); 1233 *m_head = NULL; 1234 return (ENOMEM); 1235 } 1236 *m_head = m; 1237 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1238 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1239 if (error != 0) { 1240 m_freem(*m_head); 1241 *m_head = NULL; 1242 return (error); 1243 } 1244 } else if (error != 0) 1245 return (error); 1246 if (nsegs == 0) { 1247 m_freem(*m_head); 1248 *m_head = NULL; 1249 return (EIO); 1250 } 1251 1252 m = *m_head; 1253 csum_flags = 0; 1254 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) { 1255 if (m->m_pkthdr.csum_flags & CSUM_IP) 1256 csum_flags |= TFD_IPChecksumEnable; 1257 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1258 csum_flags |= TFD_TCPChecksumEnable; 1259 else if (m->m_pkthdr.csum_flags & CSUM_UDP) 1260 csum_flags |= TFD_UDPChecksumEnable; 1261 } 1262 1263 si = sc->sc_cdata.stge_tx_prod; 1264 tfd = &sc->sc_rdata.stge_tx_ring[si]; 1265 for (i = 0; i < nsegs; i++) 1266 tfd->tfd_frags[i].frag_word0 = 1267 htole64(FRAG_ADDR(txsegs[i].ds_addr) | 1268 FRAG_LEN(txsegs[i].ds_len)); 1269 sc->sc_cdata.stge_tx_cnt++; 1270 1271 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) | 1272 TFD_FragCount(nsegs) | csum_flags; 1273 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) 1274 tfc |= TFD_TxDMAIndicate; 1275 1276 /* Update producer index. */ 1277 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT; 1278 1279 /* Check if we have a VLAN tag to insert. */ 1280 if (m->m_flags & M_VLANTAG) 1281 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag)); 1282 tfd->tfd_control = htole64(tfc); 1283 1284 /* Update Tx Queue. */ 1285 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q); 1286 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q); 1287 txd->tx_m = m; 1288 1289 /* Sync descriptors. */ 1290 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1291 BUS_DMASYNC_PREWRITE); 1292 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1293 sc->sc_cdata.stge_tx_ring_map, 1294 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1295 1296 return (0); 1297 } 1298 1299 /* 1300 * stge_start: [ifnet interface function] 1301 * 1302 * Start packet transmission on the interface. 1303 */ 1304 static void 1305 stge_start(struct ifnet *ifp) 1306 { 1307 struct stge_softc *sc; 1308 1309 sc = ifp->if_softc; 1310 STGE_LOCK(sc); 1311 stge_start_locked(ifp); 1312 STGE_UNLOCK(sc); 1313 } 1314 1315 static void 1316 stge_start_locked(struct ifnet *ifp) 1317 { 1318 struct stge_softc *sc; 1319 struct mbuf *m_head; 1320 int enq; 1321 1322 sc = ifp->if_softc; 1323 1324 STGE_LOCK_ASSERT(sc); 1325 1326 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 1327 IFF_DRV_RUNNING || sc->sc_link == 0) 1328 return; 1329 1330 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1331 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) { 1332 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1333 break; 1334 } 1335 1336 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1337 if (m_head == NULL) 1338 break; 1339 /* 1340 * Pack the data into the transmit ring. If we 1341 * don't have room, set the OACTIVE flag and wait 1342 * for the NIC to drain the ring. 1343 */ 1344 if (stge_encap(sc, &m_head)) { 1345 if (m_head == NULL) 1346 break; 1347 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1348 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1349 break; 1350 } 1351 1352 enq++; 1353 /* 1354 * If there's a BPF listener, bounce a copy of this frame 1355 * to him. 1356 */ 1357 ETHER_BPF_MTAP(ifp, m_head); 1358 } 1359 1360 if (enq > 0) { 1361 /* Transmit */ 1362 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow); 1363 1364 /* Set a timeout in case the chip goes out to lunch. */ 1365 sc->sc_watchdog_timer = 5; 1366 } 1367 } 1368 1369 /* 1370 * stge_watchdog: 1371 * 1372 * Watchdog timer handler. 1373 */ 1374 static void 1375 stge_watchdog(struct stge_softc *sc) 1376 { 1377 struct ifnet *ifp; 1378 1379 STGE_LOCK_ASSERT(sc); 1380 1381 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer) 1382 return; 1383 1384 ifp = sc->sc_ifp; 1385 if_printf(sc->sc_ifp, "device timeout\n"); 1386 ifp->if_oerrors++; 1387 stge_init_locked(sc); 1388 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1389 stge_start_locked(ifp); 1390 } 1391 1392 /* 1393 * stge_ioctl: [ifnet interface function] 1394 * 1395 * Handle control requests from the operator. 1396 */ 1397 static int 1398 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1399 { 1400 struct stge_softc *sc; 1401 struct ifreq *ifr; 1402 struct mii_data *mii; 1403 int error, mask; 1404 1405 sc = ifp->if_softc; 1406 ifr = (struct ifreq *)data; 1407 error = 0; 1408 switch (cmd) { 1409 case SIOCSIFMTU: 1410 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU) 1411 error = EINVAL; 1412 else if (ifp->if_mtu != ifr->ifr_mtu) { 1413 ifp->if_mtu = ifr->ifr_mtu; 1414 STGE_LOCK(sc); 1415 stge_init_locked(sc); 1416 STGE_UNLOCK(sc); 1417 } 1418 break; 1419 case SIOCSIFFLAGS: 1420 STGE_LOCK(sc); 1421 if ((ifp->if_flags & IFF_UP) != 0) { 1422 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1423 if (((ifp->if_flags ^ sc->sc_if_flags) 1424 & IFF_PROMISC) != 0) 1425 stge_set_filter(sc); 1426 } else { 1427 if (sc->sc_detach == 0) 1428 stge_init_locked(sc); 1429 } 1430 } else { 1431 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1432 stge_stop(sc); 1433 } 1434 sc->sc_if_flags = ifp->if_flags; 1435 STGE_UNLOCK(sc); 1436 break; 1437 case SIOCADDMULTI: 1438 case SIOCDELMULTI: 1439 STGE_LOCK(sc); 1440 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1441 stge_set_multi(sc); 1442 STGE_UNLOCK(sc); 1443 break; 1444 case SIOCSIFMEDIA: 1445 case SIOCGIFMEDIA: 1446 mii = device_get_softc(sc->sc_miibus); 1447 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1448 break; 1449 case SIOCSIFCAP: 1450 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1451 #ifdef DEVICE_POLLING 1452 if ((mask & IFCAP_POLLING) != 0) { 1453 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1454 error = ether_poll_register(stge_poll, ifp); 1455 if (error != 0) 1456 break; 1457 STGE_LOCK(sc); 1458 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1459 ifp->if_capenable |= IFCAP_POLLING; 1460 STGE_UNLOCK(sc); 1461 } else { 1462 error = ether_poll_deregister(ifp); 1463 if (error != 0) 1464 break; 1465 STGE_LOCK(sc); 1466 CSR_WRITE_2(sc, STGE_IntEnable, 1467 sc->sc_IntEnable); 1468 ifp->if_capenable &= ~IFCAP_POLLING; 1469 STGE_UNLOCK(sc); 1470 } 1471 } 1472 #endif 1473 if ((mask & IFCAP_HWCSUM) != 0) { 1474 ifp->if_capenable ^= IFCAP_HWCSUM; 1475 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 && 1476 (IFCAP_HWCSUM & ifp->if_capabilities) != 0) 1477 ifp->if_hwassist = STGE_CSUM_FEATURES; 1478 else 1479 ifp->if_hwassist = 0; 1480 } 1481 if ((mask & IFCAP_WOL) != 0 && 1482 (ifp->if_capabilities & IFCAP_WOL) != 0) { 1483 if ((mask & IFCAP_WOL_MAGIC) != 0) 1484 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1485 } 1486 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 1487 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1488 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1489 STGE_LOCK(sc); 1490 stge_vlan_setup(sc); 1491 STGE_UNLOCK(sc); 1492 } 1493 } 1494 VLAN_CAPABILITIES(ifp); 1495 break; 1496 default: 1497 error = ether_ioctl(ifp, cmd, data); 1498 break; 1499 } 1500 1501 return (error); 1502 } 1503 1504 static void 1505 stge_link_task(void *arg, int pending) 1506 { 1507 struct stge_softc *sc; 1508 struct mii_data *mii; 1509 uint32_t v, ac; 1510 int i; 1511 1512 sc = (struct stge_softc *)arg; 1513 STGE_LOCK(sc); 1514 1515 mii = device_get_softc(sc->sc_miibus); 1516 if (mii->mii_media_status & IFM_ACTIVE) { 1517 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1518 sc->sc_link = 1; 1519 } else 1520 sc->sc_link = 0; 1521 1522 sc->sc_MACCtrl = 0; 1523 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 1524 sc->sc_MACCtrl |= MC_DuplexSelect; 1525 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) != 0) 1526 sc->sc_MACCtrl |= MC_RxFlowControlEnable; 1527 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) != 0) 1528 sc->sc_MACCtrl |= MC_TxFlowControlEnable; 1529 /* 1530 * Update STGE_MACCtrl register depending on link status. 1531 * (duplex, flow control etc) 1532 */ 1533 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 1534 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable); 1535 v |= sc->sc_MACCtrl; 1536 CSR_WRITE_4(sc, STGE_MACCtrl, v); 1537 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) { 1538 /* Duplex setting changed, reset Tx/Rx functions. */ 1539 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1540 ac |= AC_TxReset | AC_RxReset; 1541 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1542 for (i = 0; i < STGE_TIMEOUT; i++) { 1543 DELAY(100); 1544 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1545 break; 1546 } 1547 if (i == STGE_TIMEOUT) 1548 device_printf(sc->sc_dev, "reset failed to complete\n"); 1549 } 1550 STGE_UNLOCK(sc); 1551 } 1552 1553 static __inline int 1554 stge_tx_error(struct stge_softc *sc) 1555 { 1556 uint32_t txstat; 1557 int error; 1558 1559 for (error = 0;;) { 1560 txstat = CSR_READ_4(sc, STGE_TxStatus); 1561 if ((txstat & TS_TxComplete) == 0) 1562 break; 1563 /* Tx underrun */ 1564 if ((txstat & TS_TxUnderrun) != 0) { 1565 /* 1566 * XXX 1567 * There should be a more better way to recover 1568 * from Tx underrun instead of a full reset. 1569 */ 1570 if (sc->sc_nerr++ < STGE_MAXERR) 1571 device_printf(sc->sc_dev, "Tx underrun, " 1572 "resetting...\n"); 1573 if (sc->sc_nerr == STGE_MAXERR) 1574 device_printf(sc->sc_dev, "too many errors; " 1575 "not reporting any more\n"); 1576 error = -1; 1577 break; 1578 } 1579 /* Maximum/Late collisions, Re-enable Tx MAC. */ 1580 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0) 1581 CSR_WRITE_4(sc, STGE_MACCtrl, 1582 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | 1583 MC_TxEnable); 1584 } 1585 1586 return (error); 1587 } 1588 1589 /* 1590 * stge_intr: 1591 * 1592 * Interrupt service routine. 1593 */ 1594 static void 1595 stge_intr(void *arg) 1596 { 1597 struct stge_softc *sc; 1598 struct ifnet *ifp; 1599 int reinit; 1600 uint16_t status; 1601 1602 sc = (struct stge_softc *)arg; 1603 ifp = sc->sc_ifp; 1604 1605 STGE_LOCK(sc); 1606 1607 #ifdef DEVICE_POLLING 1608 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1609 goto done_locked; 1610 #endif 1611 status = CSR_READ_2(sc, STGE_IntStatus); 1612 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0) 1613 goto done_locked; 1614 1615 /* Disable interrupts. */ 1616 for (reinit = 0;;) { 1617 status = CSR_READ_2(sc, STGE_IntStatusAck); 1618 status &= sc->sc_IntEnable; 1619 if (status == 0) 1620 break; 1621 /* Host interface errors. */ 1622 if ((status & IS_HostError) != 0) { 1623 device_printf(sc->sc_dev, 1624 "Host interface error, resetting...\n"); 1625 reinit = 1; 1626 goto force_init; 1627 } 1628 1629 /* Receive interrupts. */ 1630 if ((status & IS_RxDMAComplete) != 0) { 1631 stge_rxeof(sc); 1632 if ((status & IS_RFDListEnd) != 0) 1633 CSR_WRITE_4(sc, STGE_DMACtrl, 1634 DMAC_RxDMAPollNow); 1635 } 1636 1637 /* Transmit interrupts. */ 1638 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0) 1639 stge_txeof(sc); 1640 1641 /* Transmission errors.*/ 1642 if ((status & IS_TxComplete) != 0) { 1643 if ((reinit = stge_tx_error(sc)) != 0) 1644 break; 1645 } 1646 } 1647 1648 force_init: 1649 if (reinit != 0) 1650 stge_init_locked(sc); 1651 1652 /* Re-enable interrupts. */ 1653 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1654 1655 /* Try to get more packets going. */ 1656 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1657 stge_start_locked(ifp); 1658 1659 done_locked: 1660 STGE_UNLOCK(sc); 1661 } 1662 1663 /* 1664 * stge_txeof: 1665 * 1666 * Helper; handle transmit interrupts. 1667 */ 1668 static void 1669 stge_txeof(struct stge_softc *sc) 1670 { 1671 struct ifnet *ifp; 1672 struct stge_txdesc *txd; 1673 uint64_t control; 1674 int cons; 1675 1676 STGE_LOCK_ASSERT(sc); 1677 1678 ifp = sc->sc_ifp; 1679 1680 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1681 if (txd == NULL) 1682 return; 1683 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1684 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD); 1685 1686 /* 1687 * Go through our Tx list and free mbufs for those 1688 * frames which have been transmitted. 1689 */ 1690 for (cons = sc->sc_cdata.stge_tx_cons;; 1691 cons = (cons + 1) % STGE_TX_RING_CNT) { 1692 if (sc->sc_cdata.stge_tx_cnt <= 0) 1693 break; 1694 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control); 1695 if ((control & TFD_TFDDone) == 0) 1696 break; 1697 sc->sc_cdata.stge_tx_cnt--; 1698 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1699 1700 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1701 BUS_DMASYNC_POSTWRITE); 1702 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap); 1703 1704 /* Output counter is updated with statistics register */ 1705 m_freem(txd->tx_m); 1706 txd->tx_m = NULL; 1707 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q); 1708 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 1709 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1710 } 1711 sc->sc_cdata.stge_tx_cons = cons; 1712 if (sc->sc_cdata.stge_tx_cnt == 0) 1713 sc->sc_watchdog_timer = 0; 1714 1715 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1716 sc->sc_cdata.stge_tx_ring_map, 1717 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1718 } 1719 1720 static __inline void 1721 stge_discard_rxbuf(struct stge_softc *sc, int idx) 1722 { 1723 struct stge_rfd *rfd; 1724 1725 rfd = &sc->sc_rdata.stge_rx_ring[idx]; 1726 rfd->rfd_status = 0; 1727 } 1728 1729 #ifndef __NO_STRICT_ALIGNMENT 1730 /* 1731 * It seems that TC9021's DMA engine has alignment restrictions in 1732 * DMA scatter operations. The first DMA segment has no address 1733 * alignment restrictins but the rest should be aligned on 4(?) bytes 1734 * boundary. Otherwise it would corrupt random memory. Since we don't 1735 * know which one is used for the first segment in advance we simply 1736 * don't align at all. 1737 * To avoid copying over an entire frame to align, we allocate a new 1738 * mbuf and copy ethernet header to the new mbuf. The new mbuf is 1739 * prepended into the existing mbuf chain. 1740 */ 1741 static __inline struct mbuf * 1742 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m) 1743 { 1744 struct mbuf *n; 1745 1746 n = NULL; 1747 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 1748 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 1749 m->m_data += ETHER_HDR_LEN; 1750 n = m; 1751 } else { 1752 MGETHDR(n, M_DONTWAIT, MT_DATA); 1753 if (n != NULL) { 1754 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 1755 m->m_data += ETHER_HDR_LEN; 1756 m->m_len -= ETHER_HDR_LEN; 1757 n->m_len = ETHER_HDR_LEN; 1758 M_MOVE_PKTHDR(n, m); 1759 n->m_next = m; 1760 } else 1761 m_freem(m); 1762 } 1763 1764 return (n); 1765 } 1766 #endif 1767 1768 /* 1769 * stge_rxeof: 1770 * 1771 * Helper; handle receive interrupts. 1772 */ 1773 static int 1774 stge_rxeof(struct stge_softc *sc) 1775 { 1776 struct ifnet *ifp; 1777 struct stge_rxdesc *rxd; 1778 struct mbuf *mp, *m; 1779 uint64_t status64; 1780 uint32_t status; 1781 int cons, prog, rx_npkts; 1782 1783 STGE_LOCK_ASSERT(sc); 1784 1785 rx_npkts = 0; 1786 ifp = sc->sc_ifp; 1787 1788 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1789 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD); 1790 1791 prog = 0; 1792 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT; 1793 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) { 1794 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status); 1795 status = RFD_RxStatus(status64); 1796 if ((status & RFD_RFDDone) == 0) 1797 break; 1798 #ifdef DEVICE_POLLING 1799 if (ifp->if_capenable & IFCAP_POLLING) { 1800 if (sc->sc_cdata.stge_rxcycles <= 0) 1801 break; 1802 sc->sc_cdata.stge_rxcycles--; 1803 } 1804 #endif 1805 prog++; 1806 rxd = &sc->sc_cdata.stge_rxdesc[cons]; 1807 mp = rxd->rx_m; 1808 1809 /* 1810 * If the packet had an error, drop it. Note we count 1811 * the error later in the periodic stats update. 1812 */ 1813 if ((status & RFD_FrameEnd) != 0 && (status & 1814 (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1815 RFD_RxAlignmentError | RFD_RxFCSError | 1816 RFD_RxLengthError)) != 0) { 1817 stge_discard_rxbuf(sc, cons); 1818 if (sc->sc_cdata.stge_rxhead != NULL) { 1819 m_freem(sc->sc_cdata.stge_rxhead); 1820 STGE_RXCHAIN_RESET(sc); 1821 } 1822 continue; 1823 } 1824 /* 1825 * Add a new receive buffer to the ring. 1826 */ 1827 if (stge_newbuf(sc, cons) != 0) { 1828 ifp->if_iqdrops++; 1829 stge_discard_rxbuf(sc, cons); 1830 if (sc->sc_cdata.stge_rxhead != NULL) { 1831 m_freem(sc->sc_cdata.stge_rxhead); 1832 STGE_RXCHAIN_RESET(sc); 1833 } 1834 continue; 1835 } 1836 1837 if ((status & RFD_FrameEnd) != 0) 1838 mp->m_len = RFD_RxDMAFrameLen(status) - 1839 sc->sc_cdata.stge_rxlen; 1840 sc->sc_cdata.stge_rxlen += mp->m_len; 1841 1842 /* Chain mbufs. */ 1843 if (sc->sc_cdata.stge_rxhead == NULL) { 1844 sc->sc_cdata.stge_rxhead = mp; 1845 sc->sc_cdata.stge_rxtail = mp; 1846 } else { 1847 mp->m_flags &= ~M_PKTHDR; 1848 sc->sc_cdata.stge_rxtail->m_next = mp; 1849 sc->sc_cdata.stge_rxtail = mp; 1850 } 1851 1852 if ((status & RFD_FrameEnd) != 0) { 1853 m = sc->sc_cdata.stge_rxhead; 1854 m->m_pkthdr.rcvif = ifp; 1855 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen; 1856 1857 if (m->m_pkthdr.len > sc->sc_if_framesize) { 1858 m_freem(m); 1859 STGE_RXCHAIN_RESET(sc); 1860 continue; 1861 } 1862 /* 1863 * Set the incoming checksum information for 1864 * the packet. 1865 */ 1866 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1867 if ((status & RFD_IPDetected) != 0) { 1868 m->m_pkthdr.csum_flags |= 1869 CSUM_IP_CHECKED; 1870 if ((status & RFD_IPError) == 0) 1871 m->m_pkthdr.csum_flags |= 1872 CSUM_IP_VALID; 1873 } 1874 if (((status & RFD_TCPDetected) != 0 && 1875 (status & RFD_TCPError) == 0) || 1876 ((status & RFD_UDPDetected) != 0 && 1877 (status & RFD_UDPError) == 0)) { 1878 m->m_pkthdr.csum_flags |= 1879 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1880 m->m_pkthdr.csum_data = 0xffff; 1881 } 1882 } 1883 1884 #ifndef __NO_STRICT_ALIGNMENT 1885 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) { 1886 if ((m = stge_fixup_rx(sc, m)) == NULL) { 1887 STGE_RXCHAIN_RESET(sc); 1888 continue; 1889 } 1890 } 1891 #endif 1892 /* Check for VLAN tagged packets. */ 1893 if ((status & RFD_VLANDetected) != 0 && 1894 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 1895 m->m_pkthdr.ether_vtag = RFD_TCI(status64); 1896 m->m_flags |= M_VLANTAG; 1897 } 1898 1899 STGE_UNLOCK(sc); 1900 /* Pass it on. */ 1901 (*ifp->if_input)(ifp, m); 1902 STGE_LOCK(sc); 1903 rx_npkts++; 1904 1905 STGE_RXCHAIN_RESET(sc); 1906 } 1907 } 1908 1909 if (prog > 0) { 1910 /* Update the consumer index. */ 1911 sc->sc_cdata.stge_rx_cons = cons; 1912 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1913 sc->sc_cdata.stge_rx_ring_map, 1914 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1915 } 1916 return (rx_npkts); 1917 } 1918 1919 #ifdef DEVICE_POLLING 1920 static int 1921 stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1922 { 1923 struct stge_softc *sc; 1924 uint16_t status; 1925 int rx_npkts; 1926 1927 rx_npkts = 0; 1928 sc = ifp->if_softc; 1929 STGE_LOCK(sc); 1930 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1931 STGE_UNLOCK(sc); 1932 return (rx_npkts); 1933 } 1934 1935 sc->sc_cdata.stge_rxcycles = count; 1936 rx_npkts = stge_rxeof(sc); 1937 stge_txeof(sc); 1938 1939 if (cmd == POLL_AND_CHECK_STATUS) { 1940 status = CSR_READ_2(sc, STGE_IntStatus); 1941 status &= sc->sc_IntEnable; 1942 if (status != 0) { 1943 if ((status & IS_HostError) != 0) { 1944 device_printf(sc->sc_dev, 1945 "Host interface error, resetting...\n"); 1946 stge_init_locked(sc); 1947 } 1948 if ((status & IS_TxComplete) != 0) { 1949 if (stge_tx_error(sc) != 0) 1950 stge_init_locked(sc); 1951 } 1952 } 1953 1954 } 1955 1956 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1957 stge_start_locked(ifp); 1958 1959 STGE_UNLOCK(sc); 1960 return (rx_npkts); 1961 } 1962 #endif /* DEVICE_POLLING */ 1963 1964 /* 1965 * stge_tick: 1966 * 1967 * One second timer, used to tick the MII. 1968 */ 1969 static void 1970 stge_tick(void *arg) 1971 { 1972 struct stge_softc *sc; 1973 struct mii_data *mii; 1974 1975 sc = (struct stge_softc *)arg; 1976 1977 STGE_LOCK_ASSERT(sc); 1978 1979 mii = device_get_softc(sc->sc_miibus); 1980 mii_tick(mii); 1981 1982 /* Update statistics counters. */ 1983 stge_stats_update(sc); 1984 1985 /* 1986 * Relcaim any pending Tx descriptors to release mbufs in a 1987 * timely manner as we don't generate Tx completion interrupts 1988 * for every frame. This limits the delay to a maximum of one 1989 * second. 1990 */ 1991 if (sc->sc_cdata.stge_tx_cnt != 0) 1992 stge_txeof(sc); 1993 1994 stge_watchdog(sc); 1995 1996 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1997 } 1998 1999 /* 2000 * stge_stats_update: 2001 * 2002 * Read the TC9021 statistics counters. 2003 */ 2004 static void 2005 stge_stats_update(struct stge_softc *sc) 2006 { 2007 struct ifnet *ifp; 2008 2009 STGE_LOCK_ASSERT(sc); 2010 2011 ifp = sc->sc_ifp; 2012 2013 CSR_READ_4(sc,STGE_OctetRcvOk); 2014 2015 ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk); 2016 2017 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors); 2018 2019 CSR_READ_4(sc, STGE_OctetXmtdOk); 2020 2021 ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk); 2022 2023 ifp->if_collisions += 2024 CSR_READ_4(sc, STGE_LateCollisions) + 2025 CSR_READ_4(sc, STGE_MultiColFrames) + 2026 CSR_READ_4(sc, STGE_SingleColFrames); 2027 2028 ifp->if_oerrors += 2029 CSR_READ_2(sc, STGE_FramesAbortXSColls) + 2030 CSR_READ_2(sc, STGE_FramesWEXDeferal); 2031 } 2032 2033 /* 2034 * stge_reset: 2035 * 2036 * Perform a soft reset on the TC9021. 2037 */ 2038 static void 2039 stge_reset(struct stge_softc *sc, uint32_t how) 2040 { 2041 uint32_t ac; 2042 uint8_t v; 2043 int i, dv; 2044 2045 STGE_LOCK_ASSERT(sc); 2046 2047 dv = 5000; 2048 ac = CSR_READ_4(sc, STGE_AsicCtrl); 2049 switch (how) { 2050 case STGE_RESET_TX: 2051 ac |= AC_TxReset | AC_FIFO; 2052 dv = 100; 2053 break; 2054 case STGE_RESET_RX: 2055 ac |= AC_RxReset | AC_FIFO; 2056 dv = 100; 2057 break; 2058 case STGE_RESET_FULL: 2059 default: 2060 /* 2061 * Only assert RstOut if we're fiber. We need GMII clocks 2062 * to be present in order for the reset to complete on fiber 2063 * cards. 2064 */ 2065 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset | 2066 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 2067 (sc->sc_usefiber ? AC_RstOut : 0); 2068 break; 2069 } 2070 2071 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 2072 2073 /* Account for reset problem at 10Mbps. */ 2074 DELAY(dv); 2075 2076 for (i = 0; i < STGE_TIMEOUT; i++) { 2077 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 2078 break; 2079 DELAY(dv); 2080 } 2081 2082 if (i == STGE_TIMEOUT) 2083 device_printf(sc->sc_dev, "reset failed to complete\n"); 2084 2085 /* Set LED, from Linux IPG driver. */ 2086 ac = CSR_READ_4(sc, STGE_AsicCtrl); 2087 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1); 2088 if ((sc->sc_led & 0x01) != 0) 2089 ac |= AC_LEDMode; 2090 if ((sc->sc_led & 0x03) != 0) 2091 ac |= AC_LEDModeBit1; 2092 if ((sc->sc_led & 0x08) != 0) 2093 ac |= AC_LEDSpeed; 2094 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 2095 2096 /* Set PHY, from Linux IPG driver */ 2097 v = CSR_READ_1(sc, STGE_PhySet); 2098 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet); 2099 v |= ((sc->sc_led & 0x70) >> 4); 2100 CSR_WRITE_1(sc, STGE_PhySet, v); 2101 } 2102 2103 /* 2104 * stge_init: [ ifnet interface function ] 2105 * 2106 * Initialize the interface. 2107 */ 2108 static void 2109 stge_init(void *xsc) 2110 { 2111 struct stge_softc *sc; 2112 2113 sc = (struct stge_softc *)xsc; 2114 STGE_LOCK(sc); 2115 stge_init_locked(sc); 2116 STGE_UNLOCK(sc); 2117 } 2118 2119 static void 2120 stge_init_locked(struct stge_softc *sc) 2121 { 2122 struct ifnet *ifp; 2123 struct mii_data *mii; 2124 uint16_t eaddr[3]; 2125 uint32_t v; 2126 int error; 2127 2128 STGE_LOCK_ASSERT(sc); 2129 2130 ifp = sc->sc_ifp; 2131 mii = device_get_softc(sc->sc_miibus); 2132 2133 /* 2134 * Cancel any pending I/O. 2135 */ 2136 stge_stop(sc); 2137 2138 /* 2139 * Reset the chip to a known state. 2140 */ 2141 stge_reset(sc, STGE_RESET_FULL); 2142 2143 /* Init descriptors. */ 2144 error = stge_init_rx_ring(sc); 2145 if (error != 0) { 2146 device_printf(sc->sc_dev, 2147 "initialization failed: no memory for rx buffers\n"); 2148 stge_stop(sc); 2149 goto out; 2150 } 2151 stge_init_tx_ring(sc); 2152 2153 /* Set the station address. */ 2154 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2155 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0])); 2156 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1])); 2157 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2])); 2158 2159 /* 2160 * Set the statistics masks. Disable all the RMON stats, 2161 * and disable selected stats in the non-RMON stats registers. 2162 */ 2163 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 2164 CSR_WRITE_4(sc, STGE_StatisticsMask, 2165 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 2166 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 2167 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 2168 (1U << 21)); 2169 2170 /* Set up the receive filter. */ 2171 stge_set_filter(sc); 2172 /* Program multicast filter. */ 2173 stge_set_multi(sc); 2174 2175 /* 2176 * Give the transmit and receive ring to the chip. 2177 */ 2178 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 2179 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0))); 2180 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 2181 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0))); 2182 2183 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 2184 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0))); 2185 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 2186 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0))); 2187 2188 /* 2189 * Initialize the Tx auto-poll period. It's OK to make this number 2190 * large (255 is the max, but we use 127) -- we explicitly kick the 2191 * transmit engine when there's actually a packet. 2192 */ 2193 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2194 2195 /* ..and the Rx auto-poll period. */ 2196 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2197 2198 /* Initialize the Tx start threshold. */ 2199 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 2200 2201 /* Rx DMA thresholds, from Linux */ 2202 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 2203 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 2204 2205 /* Rx early threhold, from Linux */ 2206 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 2207 2208 /* Tx DMA thresholds, from Linux */ 2209 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 2210 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 2211 2212 /* 2213 * Initialize the Rx DMA interrupt control register. We 2214 * request an interrupt after every incoming packet, but 2215 * defer it for sc_rxint_dmawait us. When the number of 2216 * interrupts pending reaches STGE_RXINT_NFRAME, we stop 2217 * deferring the interrupt, and signal it immediately. 2218 */ 2219 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 2220 RDIC_RxFrameCount(sc->sc_rxint_nframe) | 2221 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait))); 2222 2223 /* 2224 * Initialize the interrupt mask. 2225 */ 2226 sc->sc_IntEnable = IS_HostError | IS_TxComplete | 2227 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 2228 #ifdef DEVICE_POLLING 2229 /* Disable interrupts if we are polling. */ 2230 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2231 CSR_WRITE_2(sc, STGE_IntEnable, 0); 2232 else 2233 #endif 2234 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 2235 2236 /* 2237 * Configure the DMA engine. 2238 * XXX Should auto-tune TxBurstLimit. 2239 */ 2240 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3)); 2241 2242 /* 2243 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 2244 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 2245 * in the Rx FIFO. 2246 */ 2247 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 2248 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 2249 2250 /* 2251 * Set the maximum frame size. 2252 */ 2253 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2254 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize); 2255 2256 /* 2257 * Initialize MacCtrl -- do it before setting the media, 2258 * as setting the media will actually program the register. 2259 * 2260 * Note: We have to poke the IFS value before poking 2261 * anything else. 2262 */ 2263 /* Tx/Rx MAC should be disabled before programming IFS.*/ 2264 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit)); 2265 2266 stge_vlan_setup(sc); 2267 2268 if (sc->sc_rev >= 6) { /* >= B.2 */ 2269 /* Multi-frag frame bug work-around. */ 2270 CSR_WRITE_2(sc, STGE_DebugCtrl, 2271 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 2272 2273 /* Tx Poll Now bug work-around. */ 2274 CSR_WRITE_2(sc, STGE_DebugCtrl, 2275 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 2276 /* Tx Poll Now bug work-around. */ 2277 CSR_WRITE_2(sc, STGE_DebugCtrl, 2278 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 2279 } 2280 2281 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2282 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 2283 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2284 /* 2285 * It seems that transmitting frames without checking the state of 2286 * Rx/Tx MAC wedge the hardware. 2287 */ 2288 stge_start_tx(sc); 2289 stge_start_rx(sc); 2290 2291 sc->sc_link = 0; 2292 /* 2293 * Set the current media. 2294 */ 2295 mii_mediachg(mii); 2296 2297 /* 2298 * Start the one second MII clock. 2299 */ 2300 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 2301 2302 /* 2303 * ...all done! 2304 */ 2305 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2306 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2307 2308 out: 2309 if (error != 0) 2310 device_printf(sc->sc_dev, "interface not running\n"); 2311 } 2312 2313 static void 2314 stge_vlan_setup(struct stge_softc *sc) 2315 { 2316 struct ifnet *ifp; 2317 uint32_t v; 2318 2319 ifp = sc->sc_ifp; 2320 /* 2321 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl 2322 * MC_AutoVLANuntagging bit. 2323 * MC_AutoVLANtagging bit selects which VLAN source to use 2324 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert 2325 * bit has priority over MC_AutoVLANtagging bit. So we always 2326 * use TFC instead of STGE_VLANTag register. 2327 */ 2328 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2329 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2330 v |= MC_AutoVLANuntagging; 2331 else 2332 v &= ~MC_AutoVLANuntagging; 2333 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2334 } 2335 2336 /* 2337 * Stop transmission on the interface. 2338 */ 2339 static void 2340 stge_stop(struct stge_softc *sc) 2341 { 2342 struct ifnet *ifp; 2343 struct stge_txdesc *txd; 2344 struct stge_rxdesc *rxd; 2345 uint32_t v; 2346 int i; 2347 2348 STGE_LOCK_ASSERT(sc); 2349 /* 2350 * Stop the one second clock. 2351 */ 2352 callout_stop(&sc->sc_tick_ch); 2353 sc->sc_watchdog_timer = 0; 2354 2355 /* 2356 * Disable interrupts. 2357 */ 2358 CSR_WRITE_2(sc, STGE_IntEnable, 0); 2359 2360 /* 2361 * Stop receiver, transmitter, and stats update. 2362 */ 2363 stge_stop_rx(sc); 2364 stge_stop_tx(sc); 2365 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2366 v |= MC_StatisticsDisable; 2367 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2368 2369 /* 2370 * Stop the transmit and receive DMA. 2371 */ 2372 stge_dma_wait(sc); 2373 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 2374 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 2375 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 2376 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 2377 2378 /* 2379 * Free RX and TX mbufs still in the queues. 2380 */ 2381 for (i = 0; i < STGE_RX_RING_CNT; i++) { 2382 rxd = &sc->sc_cdata.stge_rxdesc[i]; 2383 if (rxd->rx_m != NULL) { 2384 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, 2385 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2386 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, 2387 rxd->rx_dmamap); 2388 m_freem(rxd->rx_m); 2389 rxd->rx_m = NULL; 2390 } 2391 } 2392 for (i = 0; i < STGE_TX_RING_CNT; i++) { 2393 txd = &sc->sc_cdata.stge_txdesc[i]; 2394 if (txd->tx_m != NULL) { 2395 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, 2396 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2397 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, 2398 txd->tx_dmamap); 2399 m_freem(txd->tx_m); 2400 txd->tx_m = NULL; 2401 } 2402 } 2403 2404 /* 2405 * Mark the interface down and cancel the watchdog timer. 2406 */ 2407 ifp = sc->sc_ifp; 2408 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2409 sc->sc_link = 0; 2410 } 2411 2412 static void 2413 stge_start_tx(struct stge_softc *sc) 2414 { 2415 uint32_t v; 2416 int i; 2417 2418 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2419 if ((v & MC_TxEnabled) != 0) 2420 return; 2421 v |= MC_TxEnable; 2422 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2423 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2424 for (i = STGE_TIMEOUT; i > 0; i--) { 2425 DELAY(10); 2426 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2427 if ((v & MC_TxEnabled) != 0) 2428 break; 2429 } 2430 if (i == 0) 2431 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n"); 2432 } 2433 2434 static void 2435 stge_start_rx(struct stge_softc *sc) 2436 { 2437 uint32_t v; 2438 int i; 2439 2440 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2441 if ((v & MC_RxEnabled) != 0) 2442 return; 2443 v |= MC_RxEnable; 2444 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2445 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2446 for (i = STGE_TIMEOUT; i > 0; i--) { 2447 DELAY(10); 2448 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2449 if ((v & MC_RxEnabled) != 0) 2450 break; 2451 } 2452 if (i == 0) 2453 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n"); 2454 } 2455 2456 static void 2457 stge_stop_tx(struct stge_softc *sc) 2458 { 2459 uint32_t v; 2460 int i; 2461 2462 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2463 if ((v & MC_TxEnabled) == 0) 2464 return; 2465 v |= MC_TxDisable; 2466 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2467 for (i = STGE_TIMEOUT; i > 0; i--) { 2468 DELAY(10); 2469 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2470 if ((v & MC_TxEnabled) == 0) 2471 break; 2472 } 2473 if (i == 0) 2474 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n"); 2475 } 2476 2477 static void 2478 stge_stop_rx(struct stge_softc *sc) 2479 { 2480 uint32_t v; 2481 int i; 2482 2483 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2484 if ((v & MC_RxEnabled) == 0) 2485 return; 2486 v |= MC_RxDisable; 2487 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2488 for (i = STGE_TIMEOUT; i > 0; i--) { 2489 DELAY(10); 2490 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2491 if ((v & MC_RxEnabled) == 0) 2492 break; 2493 } 2494 if (i == 0) 2495 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n"); 2496 } 2497 2498 static void 2499 stge_init_tx_ring(struct stge_softc *sc) 2500 { 2501 struct stge_ring_data *rd; 2502 struct stge_txdesc *txd; 2503 bus_addr_t addr; 2504 int i; 2505 2506 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq); 2507 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq); 2508 2509 sc->sc_cdata.stge_tx_prod = 0; 2510 sc->sc_cdata.stge_tx_cons = 0; 2511 sc->sc_cdata.stge_tx_cnt = 0; 2512 2513 rd = &sc->sc_rdata; 2514 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ); 2515 for (i = 0; i < STGE_TX_RING_CNT; i++) { 2516 if (i == (STGE_TX_RING_CNT - 1)) 2517 addr = STGE_TX_RING_ADDR(sc, 0); 2518 else 2519 addr = STGE_TX_RING_ADDR(sc, i + 1); 2520 rd->stge_tx_ring[i].tfd_next = htole64(addr); 2521 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone); 2522 txd = &sc->sc_cdata.stge_txdesc[i]; 2523 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 2524 } 2525 2526 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 2527 sc->sc_cdata.stge_tx_ring_map, 2528 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2529 2530 } 2531 2532 static int 2533 stge_init_rx_ring(struct stge_softc *sc) 2534 { 2535 struct stge_ring_data *rd; 2536 bus_addr_t addr; 2537 int i; 2538 2539 sc->sc_cdata.stge_rx_cons = 0; 2540 STGE_RXCHAIN_RESET(sc); 2541 2542 rd = &sc->sc_rdata; 2543 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ); 2544 for (i = 0; i < STGE_RX_RING_CNT; i++) { 2545 if (stge_newbuf(sc, i) != 0) 2546 return (ENOBUFS); 2547 if (i == (STGE_RX_RING_CNT - 1)) 2548 addr = STGE_RX_RING_ADDR(sc, 0); 2549 else 2550 addr = STGE_RX_RING_ADDR(sc, i + 1); 2551 rd->stge_rx_ring[i].rfd_next = htole64(addr); 2552 rd->stge_rx_ring[i].rfd_status = 0; 2553 } 2554 2555 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 2556 sc->sc_cdata.stge_rx_ring_map, 2557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2558 2559 return (0); 2560 } 2561 2562 /* 2563 * stge_newbuf: 2564 * 2565 * Add a receive buffer to the indicated descriptor. 2566 */ 2567 static int 2568 stge_newbuf(struct stge_softc *sc, int idx) 2569 { 2570 struct stge_rxdesc *rxd; 2571 struct stge_rfd *rfd; 2572 struct mbuf *m; 2573 bus_dma_segment_t segs[1]; 2574 bus_dmamap_t map; 2575 int nsegs; 2576 2577 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2578 if (m == NULL) 2579 return (ENOBUFS); 2580 m->m_len = m->m_pkthdr.len = MCLBYTES; 2581 /* 2582 * The hardware requires 4bytes aligned DMA address when JUMBO 2583 * frame is used. 2584 */ 2585 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN)) 2586 m_adj(m, ETHER_ALIGN); 2587 2588 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag, 2589 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2590 m_freem(m); 2591 return (ENOBUFS); 2592 } 2593 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2594 2595 rxd = &sc->sc_cdata.stge_rxdesc[idx]; 2596 if (rxd->rx_m != NULL) { 2597 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2598 BUS_DMASYNC_POSTREAD); 2599 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap); 2600 } 2601 map = rxd->rx_dmamap; 2602 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap; 2603 sc->sc_cdata.stge_rx_sparemap = map; 2604 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2605 BUS_DMASYNC_PREREAD); 2606 rxd->rx_m = m; 2607 2608 rfd = &sc->sc_rdata.stge_rx_ring[idx]; 2609 rfd->rfd_frag.frag_word0 = 2610 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len)); 2611 rfd->rfd_status = 0; 2612 2613 return (0); 2614 } 2615 2616 /* 2617 * stge_set_filter: 2618 * 2619 * Set up the receive filter. 2620 */ 2621 static void 2622 stge_set_filter(struct stge_softc *sc) 2623 { 2624 struct ifnet *ifp; 2625 uint16_t mode; 2626 2627 STGE_LOCK_ASSERT(sc); 2628 2629 ifp = sc->sc_ifp; 2630 2631 mode = CSR_READ_2(sc, STGE_ReceiveMode); 2632 mode |= RM_ReceiveUnicast; 2633 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2634 mode |= RM_ReceiveBroadcast; 2635 else 2636 mode &= ~RM_ReceiveBroadcast; 2637 if ((ifp->if_flags & IFF_PROMISC) != 0) 2638 mode |= RM_ReceiveAllFrames; 2639 else 2640 mode &= ~RM_ReceiveAllFrames; 2641 2642 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2643 } 2644 2645 static void 2646 stge_set_multi(struct stge_softc *sc) 2647 { 2648 struct ifnet *ifp; 2649 struct ifmultiaddr *ifma; 2650 uint32_t crc; 2651 uint32_t mchash[2]; 2652 uint16_t mode; 2653 int count; 2654 2655 STGE_LOCK_ASSERT(sc); 2656 2657 ifp = sc->sc_ifp; 2658 2659 mode = CSR_READ_2(sc, STGE_ReceiveMode); 2660 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2661 if ((ifp->if_flags & IFF_PROMISC) != 0) 2662 mode |= RM_ReceiveAllFrames; 2663 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2664 mode |= RM_ReceiveMulticast; 2665 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2666 return; 2667 } 2668 2669 /* clear existing filters. */ 2670 CSR_WRITE_4(sc, STGE_HashTable0, 0); 2671 CSR_WRITE_4(sc, STGE_HashTable1, 0); 2672 2673 /* 2674 * Set up the multicast address filter by passing all multicast 2675 * addresses through a CRC generator, and then using the low-order 2676 * 6 bits as an index into the 64 bit multicast hash table. The 2677 * high order bits select the register, while the rest of the bits 2678 * select the bit within the register. 2679 */ 2680 2681 bzero(mchash, sizeof(mchash)); 2682 2683 count = 0; 2684 if_maddr_rlock(sc->sc_ifp); 2685 TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) { 2686 if (ifma->ifma_addr->sa_family != AF_LINK) 2687 continue; 2688 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2689 ifma->ifma_addr), ETHER_ADDR_LEN); 2690 2691 /* Just want the 6 least significant bits. */ 2692 crc &= 0x3f; 2693 2694 /* Set the corresponding bit in the hash table. */ 2695 mchash[crc >> 5] |= 1 << (crc & 0x1f); 2696 count++; 2697 } 2698 if_maddr_runlock(ifp); 2699 2700 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames); 2701 if (count > 0) 2702 mode |= RM_ReceiveMulticastHash; 2703 else 2704 mode &= ~RM_ReceiveMulticastHash; 2705 2706 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 2707 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 2708 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2709 } 2710 2711 static int 2712 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2713 { 2714 int error, value; 2715 2716 if (!arg1) 2717 return (EINVAL); 2718 value = *(int *)arg1; 2719 error = sysctl_handle_int(oidp, &value, 0, req); 2720 if (error || !req->newptr) 2721 return (error); 2722 if (value < low || value > high) 2723 return (EINVAL); 2724 *(int *)arg1 = value; 2725 2726 return (0); 2727 } 2728 2729 static int 2730 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS) 2731 { 2732 return (sysctl_int_range(oidp, arg1, arg2, req, 2733 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX)); 2734 } 2735 2736 static int 2737 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS) 2738 { 2739 return (sysctl_int_range(oidp, arg1, arg2, req, 2740 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX)); 2741 } 2742