1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 #ifdef HAVE_KERNEL_OPTION_HEADERS 37 #include "opt_device_polling.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/malloc.h> 47 #include <sys/mbuf.h> 48 #include <sys/module.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 54 #include <net/bpf.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_arp.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #include <machine/bus.h> 65 #include <machine/resource.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/mii_bitbang.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ste/if_stereg.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 MODULE_DEPEND(ste, pci, 1, 1, 1); 80 MODULE_DEPEND(ste, ether, 1, 1, 1); 81 MODULE_DEPEND(ste, miibus, 1, 1, 1); 82 83 /* Define to show Tx error status. */ 84 #define STE_SHOW_TXERRORS 85 86 /* 87 * Various supported device vendors/types and their names. 88 */ 89 static const struct ste_type ste_devs[] = { 90 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 91 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 92 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 93 { 0, 0, NULL } 94 }; 95 96 static int ste_attach(device_t); 97 static int ste_detach(device_t); 98 static int ste_probe(device_t); 99 static int ste_resume(device_t); 100 static int ste_shutdown(device_t); 101 static int ste_suspend(device_t); 102 103 static int ste_dma_alloc(struct ste_softc *); 104 static void ste_dma_free(struct ste_softc *); 105 static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 106 static int ste_eeprom_wait(struct ste_softc *); 107 static int ste_encap(struct ste_softc *, struct mbuf **, 108 struct ste_chain *); 109 static int ste_ifmedia_upd(if_t); 110 static void ste_ifmedia_sts(if_t, struct ifmediareq *); 111 static void ste_init(void *); 112 static void ste_init_locked(struct ste_softc *); 113 static int ste_init_rx_list(struct ste_softc *); 114 static void ste_init_tx_list(struct ste_softc *); 115 static void ste_intr(void *); 116 static int ste_ioctl(if_t, u_long, caddr_t); 117 static uint32_t ste_mii_bitbang_read(device_t); 118 static void ste_mii_bitbang_write(device_t, uint32_t); 119 static int ste_miibus_readreg(device_t, int, int); 120 static void ste_miibus_statchg(device_t); 121 static int ste_miibus_writereg(device_t, int, int, int); 122 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 123 static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int); 124 static void ste_reset(struct ste_softc *); 125 static void ste_restart_tx(struct ste_softc *); 126 static int ste_rxeof(struct ste_softc *, int); 127 static void ste_rxfilter(struct ste_softc *); 128 static void ste_setwol(struct ste_softc *); 129 static void ste_start(if_t); 130 static void ste_start_locked(if_t); 131 static void ste_stats_clear(struct ste_softc *); 132 static void ste_stats_update(struct ste_softc *); 133 static void ste_stop(struct ste_softc *); 134 static void ste_sysctl_node(struct ste_softc *); 135 static void ste_tick(void *); 136 static void ste_txeoc(struct ste_softc *); 137 static void ste_txeof(struct ste_softc *); 138 static void ste_wait(struct ste_softc *); 139 static void ste_watchdog(struct ste_softc *); 140 141 /* 142 * MII bit-bang glue 143 */ 144 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 145 ste_mii_bitbang_read, 146 ste_mii_bitbang_write, 147 { 148 STE_PHYCTL_MDATA, /* MII_BIT_MDO */ 149 STE_PHYCTL_MDATA, /* MII_BIT_MDI */ 150 STE_PHYCTL_MCLK, /* MII_BIT_MDC */ 151 STE_PHYCTL_MDIR, /* MII_BIT_DIR_HOST_PHY */ 152 0, /* MII_BIT_DIR_PHY_HOST */ 153 } 154 }; 155 156 static device_method_t ste_methods[] = { 157 /* Device interface */ 158 DEVMETHOD(device_probe, ste_probe), 159 DEVMETHOD(device_attach, ste_attach), 160 DEVMETHOD(device_detach, ste_detach), 161 DEVMETHOD(device_shutdown, ste_shutdown), 162 DEVMETHOD(device_suspend, ste_suspend), 163 DEVMETHOD(device_resume, ste_resume), 164 165 /* MII interface */ 166 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 167 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 168 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 169 170 DEVMETHOD_END 171 }; 172 173 static driver_t ste_driver = { 174 "ste", 175 ste_methods, 176 sizeof(struct ste_softc) 177 }; 178 179 DRIVER_MODULE(ste, pci, ste_driver, 0, 0); 180 DRIVER_MODULE(miibus, ste, miibus_driver, 0, 0); 181 182 #define STE_SETBIT4(sc, reg, x) \ 183 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 184 185 #define STE_CLRBIT4(sc, reg, x) \ 186 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 187 188 #define STE_SETBIT2(sc, reg, x) \ 189 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 190 191 #define STE_CLRBIT2(sc, reg, x) \ 192 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 193 194 #define STE_SETBIT1(sc, reg, x) \ 195 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 196 197 #define STE_CLRBIT1(sc, reg, x) \ 198 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 199 200 /* 201 * Read the MII serial port for the MII bit-bang module. 202 */ 203 static uint32_t 204 ste_mii_bitbang_read(device_t dev) 205 { 206 struct ste_softc *sc; 207 uint32_t val; 208 209 sc = device_get_softc(dev); 210 211 val = CSR_READ_1(sc, STE_PHYCTL); 212 CSR_BARRIER(sc, STE_PHYCTL, 1, 213 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 214 215 return (val); 216 } 217 218 /* 219 * Write the MII serial port for the MII bit-bang module. 220 */ 221 static void 222 ste_mii_bitbang_write(device_t dev, uint32_t val) 223 { 224 struct ste_softc *sc; 225 226 sc = device_get_softc(dev); 227 228 CSR_WRITE_1(sc, STE_PHYCTL, val); 229 CSR_BARRIER(sc, STE_PHYCTL, 1, 230 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 231 } 232 233 static int 234 ste_miibus_readreg(device_t dev, int phy, int reg) 235 { 236 237 return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg)); 238 } 239 240 static int 241 ste_miibus_writereg(device_t dev, int phy, int reg, int data) 242 { 243 244 mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data); 245 246 return (0); 247 } 248 249 static void 250 ste_miibus_statchg(device_t dev) 251 { 252 struct ste_softc *sc; 253 struct mii_data *mii; 254 if_t ifp; 255 uint16_t cfg; 256 257 sc = device_get_softc(dev); 258 259 mii = device_get_softc(sc->ste_miibus); 260 ifp = sc->ste_ifp; 261 if (mii == NULL || ifp == NULL || 262 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 263 return; 264 265 sc->ste_flags &= ~STE_FLAG_LINK; 266 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 267 (IFM_ACTIVE | IFM_AVALID)) { 268 switch (IFM_SUBTYPE(mii->mii_media_active)) { 269 case IFM_10_T: 270 case IFM_100_TX: 271 case IFM_100_FX: 272 case IFM_100_T4: 273 sc->ste_flags |= STE_FLAG_LINK; 274 default: 275 break; 276 } 277 } 278 279 /* Program MACs with resolved speed/duplex/flow-control. */ 280 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 281 cfg = CSR_READ_2(sc, STE_MACCTL0); 282 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 283 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 284 /* 285 * ST201 data sheet says driver should enable receiving 286 * MAC control frames bit of receive mode register to 287 * receive flow-control frames but the register has no 288 * such bits. In addition the controller has no ability 289 * to send pause frames so it should be handled in 290 * driver. Implementing pause timer handling in driver 291 * layer is not trivial, so don't enable flow-control 292 * here. 293 */ 294 cfg |= STE_MACCTL0_FULLDUPLEX; 295 } 296 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 297 } 298 } 299 300 static int 301 ste_ifmedia_upd(if_t ifp) 302 { 303 struct ste_softc *sc; 304 struct mii_data *mii; 305 struct mii_softc *miisc; 306 int error; 307 308 sc = if_getsoftc(ifp); 309 STE_LOCK(sc); 310 mii = device_get_softc(sc->ste_miibus); 311 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 312 PHY_RESET(miisc); 313 error = mii_mediachg(mii); 314 STE_UNLOCK(sc); 315 316 return (error); 317 } 318 319 static void 320 ste_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 321 { 322 struct ste_softc *sc; 323 struct mii_data *mii; 324 325 sc = if_getsoftc(ifp); 326 mii = device_get_softc(sc->ste_miibus); 327 328 STE_LOCK(sc); 329 if ((if_getflags(ifp) & IFF_UP) == 0) { 330 STE_UNLOCK(sc); 331 return; 332 } 333 mii_pollstat(mii); 334 ifmr->ifm_active = mii->mii_media_active; 335 ifmr->ifm_status = mii->mii_media_status; 336 STE_UNLOCK(sc); 337 } 338 339 static void 340 ste_wait(struct ste_softc *sc) 341 { 342 int i; 343 344 for (i = 0; i < STE_TIMEOUT; i++) { 345 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 346 break; 347 DELAY(1); 348 } 349 350 if (i == STE_TIMEOUT) 351 device_printf(sc->ste_dev, "command never completed!\n"); 352 } 353 354 /* 355 * The EEPROM is slow: give it time to come ready after issuing 356 * it a command. 357 */ 358 static int 359 ste_eeprom_wait(struct ste_softc *sc) 360 { 361 int i; 362 363 DELAY(1000); 364 365 for (i = 0; i < 100; i++) { 366 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 367 DELAY(1000); 368 else 369 break; 370 } 371 372 if (i == 100) { 373 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 374 return (1); 375 } 376 377 return (0); 378 } 379 380 /* 381 * Read a sequence of words from the EEPROM. Note that ethernet address 382 * data is stored in the EEPROM in network byte order. 383 */ 384 static int 385 ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt) 386 { 387 int err = 0, i; 388 389 if (ste_eeprom_wait(sc)) 390 return (1); 391 392 for (i = 0; i < cnt; i++) { 393 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 394 err = ste_eeprom_wait(sc); 395 if (err) 396 break; 397 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA)); 398 dest++; 399 } 400 401 return (err ? 1 : 0); 402 } 403 404 static u_int 405 ste_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 406 { 407 uint32_t *hashes = arg; 408 int h; 409 410 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0x3F; 411 if (h < 32) 412 hashes[0] |= (1 << h); 413 else 414 hashes[1] |= (1 << (h - 32)); 415 416 return (1); 417 } 418 419 static void 420 ste_rxfilter(struct ste_softc *sc) 421 { 422 if_t ifp; 423 uint32_t hashes[2] = { 0, 0 }; 424 uint8_t rxcfg; 425 426 STE_LOCK_ASSERT(sc); 427 428 ifp = sc->ste_ifp; 429 rxcfg = CSR_READ_1(sc, STE_RX_MODE); 430 rxcfg |= STE_RXMODE_UNICAST; 431 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH | 432 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC); 433 if (if_getflags(ifp) & IFF_BROADCAST) 434 rxcfg |= STE_RXMODE_BROADCAST; 435 if ((if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 436 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 437 rxcfg |= STE_RXMODE_ALLMULTI; 438 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 439 rxcfg |= STE_RXMODE_PROMISC; 440 goto chipit; 441 } 442 443 rxcfg |= STE_RXMODE_MULTIHASH; 444 /* Now program new ones. */ 445 if_foreach_llmaddr(ifp, ste_hash_maddr, hashes); 446 447 chipit: 448 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 449 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 450 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 451 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 452 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg); 453 CSR_READ_1(sc, STE_RX_MODE); 454 } 455 456 #ifdef DEVICE_POLLING 457 static poll_handler_t ste_poll, ste_poll_locked; 458 459 static int 460 ste_poll(if_t ifp, enum poll_cmd cmd, int count) 461 { 462 struct ste_softc *sc = if_getsoftc(ifp); 463 int rx_npkts = 0; 464 465 STE_LOCK(sc); 466 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 467 rx_npkts = ste_poll_locked(ifp, cmd, count); 468 STE_UNLOCK(sc); 469 return (rx_npkts); 470 } 471 472 static int 473 ste_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 474 { 475 struct ste_softc *sc = if_getsoftc(ifp); 476 int rx_npkts; 477 478 STE_LOCK_ASSERT(sc); 479 480 rx_npkts = ste_rxeof(sc, count); 481 ste_txeof(sc); 482 ste_txeoc(sc); 483 if (!if_sendq_empty(ifp)) 484 ste_start_locked(ifp); 485 486 if (cmd == POLL_AND_CHECK_STATUS) { 487 uint16_t status; 488 489 status = CSR_READ_2(sc, STE_ISR_ACK); 490 491 if (status & STE_ISR_STATS_OFLOW) 492 ste_stats_update(sc); 493 494 if (status & STE_ISR_HOSTERR) { 495 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 496 ste_init_locked(sc); 497 } 498 } 499 return (rx_npkts); 500 } 501 #endif /* DEVICE_POLLING */ 502 503 static void 504 ste_intr(void *xsc) 505 { 506 struct ste_softc *sc; 507 if_t ifp; 508 uint16_t intrs, status; 509 510 sc = xsc; 511 STE_LOCK(sc); 512 ifp = sc->ste_ifp; 513 514 #ifdef DEVICE_POLLING 515 if (if_getcapenable(ifp) & IFCAP_POLLING) { 516 STE_UNLOCK(sc); 517 return; 518 } 519 #endif 520 /* Reading STE_ISR_ACK clears STE_IMR register. */ 521 status = CSR_READ_2(sc, STE_ISR_ACK); 522 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 523 STE_UNLOCK(sc); 524 return; 525 } 526 527 intrs = STE_INTRS; 528 if (status == 0xFFFF || (status & intrs) == 0) 529 goto done; 530 531 if (sc->ste_int_rx_act > 0) { 532 status &= ~STE_ISR_RX_DMADONE; 533 intrs &= ~STE_IMR_RX_DMADONE; 534 } 535 536 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) { 537 ste_rxeof(sc, -1); 538 /* 539 * The controller has no ability to Rx interrupt 540 * moderation feature. Receiving 64 bytes frames 541 * from wire generates too many interrupts which in 542 * turn make system useless to process other useful 543 * things. Fortunately ST201 supports single shot 544 * timer so use the timer to implement Rx interrupt 545 * moderation in driver. This adds more register 546 * access but it greatly reduces number of Rx 547 * interrupts under high network load. 548 */ 549 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 550 (sc->ste_int_rx_mod != 0)) { 551 if ((status & STE_ISR_RX_DMADONE) != 0) { 552 CSR_WRITE_2(sc, STE_COUNTDOWN, 553 STE_TIMER_USECS(sc->ste_int_rx_mod)); 554 intrs &= ~STE_IMR_RX_DMADONE; 555 sc->ste_int_rx_act = 1; 556 } else { 557 intrs |= STE_IMR_RX_DMADONE; 558 sc->ste_int_rx_act = 0; 559 } 560 } 561 } 562 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 563 if ((status & STE_ISR_TX_DMADONE) != 0) 564 ste_txeof(sc); 565 if ((status & STE_ISR_TX_DONE) != 0) 566 ste_txeoc(sc); 567 if ((status & STE_ISR_STATS_OFLOW) != 0) 568 ste_stats_update(sc); 569 if ((status & STE_ISR_HOSTERR) != 0) { 570 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 571 ste_init_locked(sc); 572 STE_UNLOCK(sc); 573 return; 574 } 575 if (!if_sendq_empty(ifp)) 576 ste_start_locked(ifp); 577 done: 578 /* Re-enable interrupts */ 579 CSR_WRITE_2(sc, STE_IMR, intrs); 580 } 581 STE_UNLOCK(sc); 582 } 583 584 /* 585 * A frame has been uploaded: pass the resulting mbuf chain up to 586 * the higher level protocols. 587 */ 588 static int 589 ste_rxeof(struct ste_softc *sc, int count) 590 { 591 struct mbuf *m; 592 if_t ifp; 593 struct ste_chain_onefrag *cur_rx; 594 uint32_t rxstat; 595 int total_len, rx_npkts; 596 597 ifp = sc->ste_ifp; 598 599 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 600 sc->ste_cdata.ste_rx_list_map, 601 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 602 603 cur_rx = sc->ste_cdata.ste_rx_head; 604 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 605 cur_rx = cur_rx->ste_next) { 606 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 607 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 608 break; 609 #ifdef DEVICE_POLLING 610 if (if_getcapenable(ifp) & IFCAP_POLLING) { 611 if (count == 0) 612 break; 613 count--; 614 } 615 #endif 616 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 617 break; 618 /* 619 * If an error occurs, update stats, clear the 620 * status word and leave the mbuf cluster in place: 621 * it should simply get re-used next time this descriptor 622 * comes up in the ring. 623 */ 624 if (rxstat & STE_RXSTAT_FRAME_ERR) { 625 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 626 cur_rx->ste_ptr->ste_status = 0; 627 continue; 628 } 629 630 /* No errors; receive the packet. */ 631 m = cur_rx->ste_mbuf; 632 total_len = STE_RX_BYTES(rxstat); 633 634 /* 635 * Try to conjure up a new mbuf cluster. If that 636 * fails, it means we have an out of memory condition and 637 * should leave the buffer in place and continue. This will 638 * result in a lost packet, but there's little else we 639 * can do in this situation. 640 */ 641 if (ste_newbuf(sc, cur_rx) != 0) { 642 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 643 cur_rx->ste_ptr->ste_status = 0; 644 continue; 645 } 646 647 m->m_pkthdr.rcvif = ifp; 648 m->m_pkthdr.len = m->m_len = total_len; 649 650 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 651 STE_UNLOCK(sc); 652 if_input(ifp, m); 653 STE_LOCK(sc); 654 } 655 656 if (rx_npkts > 0) { 657 sc->ste_cdata.ste_rx_head = cur_rx; 658 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 659 sc->ste_cdata.ste_rx_list_map, 660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 661 } 662 663 return (rx_npkts); 664 } 665 666 static void 667 ste_txeoc(struct ste_softc *sc) 668 { 669 uint16_t txstat; 670 if_t ifp; 671 672 STE_LOCK_ASSERT(sc); 673 674 ifp = sc->ste_ifp; 675 676 /* 677 * STE_TX_STATUS register implements a queue of up to 31 678 * transmit status byte. Writing an arbitrary value to the 679 * register will advance the queue to the next transmit 680 * status byte. This means if driver does not read 681 * STE_TX_STATUS register after completing sending more 682 * than 31 frames the controller would be stalled so driver 683 * should re-wake the Tx MAC. This is the most severe 684 * limitation of ST201 based controller. 685 */ 686 for (;;) { 687 txstat = CSR_READ_2(sc, STE_TX_STATUS); 688 if ((txstat & STE_TXSTATUS_TXDONE) == 0) 689 break; 690 if ((txstat & (STE_TXSTATUS_UNDERRUN | 691 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR | 692 STE_TXSTATUS_STATSOFLOW)) != 0) { 693 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 694 #ifdef STE_SHOW_TXERRORS 695 device_printf(sc->ste_dev, "TX error : 0x%b\n", 696 txstat & 0xFF, STE_ERR_BITS); 697 #endif 698 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 && 699 sc->ste_tx_thresh < STE_PACKET_SIZE) { 700 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 701 if (sc->ste_tx_thresh > STE_PACKET_SIZE) 702 sc->ste_tx_thresh = STE_PACKET_SIZE; 703 device_printf(sc->ste_dev, 704 "TX underrun, increasing TX" 705 " start threshold to %d bytes\n", 706 sc->ste_tx_thresh); 707 /* Make sure to disable active DMA cycles. */ 708 STE_SETBIT4(sc, STE_DMACTL, 709 STE_DMACTL_TXDMA_STALL); 710 ste_wait(sc); 711 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 712 ste_init_locked(sc); 713 break; 714 } 715 /* Restart Tx. */ 716 ste_restart_tx(sc); 717 } 718 /* 719 * Advance to next status and ACK TxComplete 720 * interrupt. ST201 data sheet was wrong here, to 721 * get next Tx status, we have to write both 722 * STE_TX_STATUS and STE_TX_FRAMEID register. 723 * Otherwise controller returns the same status 724 * as well as not acknowledge Tx completion 725 * interrupt. 726 */ 727 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 728 } 729 } 730 731 static void 732 ste_tick(void *arg) 733 { 734 struct ste_softc *sc; 735 struct mii_data *mii; 736 737 sc = (struct ste_softc *)arg; 738 739 STE_LOCK_ASSERT(sc); 740 741 mii = device_get_softc(sc->ste_miibus); 742 mii_tick(mii); 743 /* 744 * ukphy(4) does not seem to generate CB that reports 745 * resolved link state so if we know we lost a link, 746 * explicitly check the link state. 747 */ 748 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 749 ste_miibus_statchg(sc->ste_dev); 750 /* 751 * Because we are not generating Tx completion 752 * interrupt for every frame, reclaim transmitted 753 * buffers here. 754 */ 755 ste_txeof(sc); 756 ste_txeoc(sc); 757 ste_stats_update(sc); 758 ste_watchdog(sc); 759 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 760 } 761 762 static void 763 ste_txeof(struct ste_softc *sc) 764 { 765 if_t ifp; 766 struct ste_chain *cur_tx; 767 uint32_t txstat; 768 int idx; 769 770 STE_LOCK_ASSERT(sc); 771 772 ifp = sc->ste_ifp; 773 idx = sc->ste_cdata.ste_tx_cons; 774 if (idx == sc->ste_cdata.ste_tx_prod) 775 return; 776 777 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 778 sc->ste_cdata.ste_tx_list_map, 779 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 780 781 while (idx != sc->ste_cdata.ste_tx_prod) { 782 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 783 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 784 if ((txstat & STE_TXCTL_DMADONE) == 0) 785 break; 786 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 787 BUS_DMASYNC_POSTWRITE); 788 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 789 KASSERT(cur_tx->ste_mbuf != NULL, 790 ("%s: freeing NULL mbuf!\n", __func__)); 791 m_freem(cur_tx->ste_mbuf); 792 cur_tx->ste_mbuf = NULL; 793 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 794 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 795 sc->ste_cdata.ste_tx_cnt--; 796 STE_INC(idx, STE_TX_LIST_CNT); 797 } 798 799 sc->ste_cdata.ste_tx_cons = idx; 800 if (sc->ste_cdata.ste_tx_cnt == 0) 801 sc->ste_timer = 0; 802 } 803 804 static void 805 ste_stats_clear(struct ste_softc *sc) 806 { 807 808 STE_LOCK_ASSERT(sc); 809 810 /* Rx stats. */ 811 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); 812 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); 813 CSR_READ_2(sc, STE_STAT_RX_FRAMES); 814 CSR_READ_1(sc, STE_STAT_RX_BCAST); 815 CSR_READ_1(sc, STE_STAT_RX_MCAST); 816 CSR_READ_1(sc, STE_STAT_RX_LOST); 817 /* Tx stats. */ 818 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO); 819 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI); 820 CSR_READ_2(sc, STE_STAT_TX_FRAMES); 821 CSR_READ_1(sc, STE_STAT_TX_BCAST); 822 CSR_READ_1(sc, STE_STAT_TX_MCAST); 823 CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 824 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 825 CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 826 CSR_READ_1(sc, STE_STAT_LATE_COLLS); 827 CSR_READ_1(sc, STE_STAT_TX_DEFER); 828 CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 829 CSR_READ_1(sc, STE_STAT_TX_ABORT); 830 } 831 832 static void 833 ste_stats_update(struct ste_softc *sc) 834 { 835 if_t ifp; 836 struct ste_hw_stats *stats; 837 uint32_t val; 838 839 STE_LOCK_ASSERT(sc); 840 841 ifp = sc->ste_ifp; 842 stats = &sc->ste_stats; 843 /* Rx stats. */ 844 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) | 845 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16; 846 val &= 0x000FFFFF; 847 stats->rx_bytes += val; 848 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES); 849 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST); 850 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST); 851 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST); 852 /* Tx stats. */ 853 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) | 854 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16; 855 val &= 0x000FFFFF; 856 stats->tx_bytes += val; 857 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES); 858 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST); 859 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST); 860 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 861 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 862 stats->tx_single_colls += val; 863 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 864 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 865 stats->tx_multi_colls += val; 866 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 867 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS); 868 stats->tx_late_colls += val; 869 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 870 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER); 871 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 872 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT); 873 } 874 875 /* 876 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 877 * IDs against our list and return a device name if we find a match. 878 */ 879 static int 880 ste_probe(device_t dev) 881 { 882 const struct ste_type *t; 883 884 t = ste_devs; 885 886 while (t->ste_name != NULL) { 887 if ((pci_get_vendor(dev) == t->ste_vid) && 888 (pci_get_device(dev) == t->ste_did)) { 889 device_set_desc(dev, t->ste_name); 890 return (BUS_PROBE_DEFAULT); 891 } 892 t++; 893 } 894 895 return (ENXIO); 896 } 897 898 /* 899 * Attach the interface. Allocate softc structures, do ifmedia 900 * setup and ethernet/BPF attach. 901 */ 902 static int 903 ste_attach(device_t dev) 904 { 905 struct ste_softc *sc; 906 if_t ifp; 907 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 908 int error = 0, phy, pmc, prefer_iomap, rid; 909 910 sc = device_get_softc(dev); 911 sc->ste_dev = dev; 912 913 /* 914 * Only use one PHY since this chip reports multiple 915 * Note on the DFE-550 the PHY is at 1 on the DFE-580 916 * it is at 0 & 1. It is rev 0x12. 917 */ 918 if (pci_get_vendor(dev) == DL_VENDORID && 919 pci_get_device(dev) == DL_DEVICEID_DL10050 && 920 pci_get_revid(dev) == 0x12 ) 921 sc->ste_flags |= STE_FLAG_ONE_PHY; 922 923 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 924 MTX_DEF); 925 /* 926 * Map control/status registers. 927 */ 928 pci_enable_busmaster(dev); 929 930 /* 931 * Prefer memory space register mapping over IO space but use 932 * IO space for a device that is known to have issues on memory 933 * mapping. 934 */ 935 prefer_iomap = 0; 936 if (pci_get_device(dev) == ST_DEVICEID_ST201_1) 937 prefer_iomap = 1; 938 else 939 resource_int_value(device_get_name(sc->ste_dev), 940 device_get_unit(sc->ste_dev), "prefer_iomap", 941 &prefer_iomap); 942 if (prefer_iomap == 0) { 943 sc->ste_res_id = PCIR_BAR(1); 944 sc->ste_res_type = SYS_RES_MEMORY; 945 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 946 &sc->ste_res_id, RF_ACTIVE); 947 } 948 if (prefer_iomap || sc->ste_res == NULL) { 949 sc->ste_res_id = PCIR_BAR(0); 950 sc->ste_res_type = SYS_RES_IOPORT; 951 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 952 &sc->ste_res_id, RF_ACTIVE); 953 } 954 if (sc->ste_res == NULL) { 955 device_printf(dev, "couldn't map ports/memory\n"); 956 error = ENXIO; 957 goto fail; 958 } 959 960 /* Allocate interrupt */ 961 rid = 0; 962 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 963 RF_SHAREABLE | RF_ACTIVE); 964 965 if (sc->ste_irq == NULL) { 966 device_printf(dev, "couldn't map interrupt\n"); 967 error = ENXIO; 968 goto fail; 969 } 970 971 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 972 973 /* Reset the adapter. */ 974 ste_reset(sc); 975 976 /* 977 * Get station address from the EEPROM. 978 */ 979 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) { 980 device_printf(dev, "failed to read station address\n"); 981 error = ENXIO; 982 goto fail; 983 } 984 ste_sysctl_node(sc); 985 986 if ((error = ste_dma_alloc(sc)) != 0) 987 goto fail; 988 989 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 990 if (ifp == NULL) { 991 device_printf(dev, "can not if_alloc()\n"); 992 error = ENOSPC; 993 goto fail; 994 } 995 996 /* Do MII setup. */ 997 phy = MII_PHY_ANY; 998 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0) 999 phy = 0; 1000 error = mii_attach(dev, &sc->ste_miibus, ifp, ste_ifmedia_upd, 1001 ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1002 if (error != 0) { 1003 device_printf(dev, "attaching PHYs failed\n"); 1004 goto fail; 1005 } 1006 1007 if_setsoftc(ifp, sc); 1008 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1009 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1010 if_setioctlfn(ifp, ste_ioctl); 1011 if_setstartfn(ifp, ste_start); 1012 if_setinitfn(ifp, ste_init); 1013 if_setsendqlen(ifp, STE_TX_LIST_CNT - 1); 1014 if_setsendqready(ifp); 1015 1016 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1017 1018 /* 1019 * Call MI attach routine. 1020 */ 1021 ether_ifattach(ifp, (uint8_t *)eaddr); 1022 1023 /* 1024 * Tell the upper layer(s) we support long frames. 1025 */ 1026 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1027 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1028 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 1029 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 1030 if_setcapenable(ifp, if_getcapabilities(ifp)); 1031 #ifdef DEVICE_POLLING 1032 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1033 #endif 1034 1035 /* Hook interrupt last to avoid having to lock softc */ 1036 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1037 NULL, ste_intr, sc, &sc->ste_intrhand); 1038 1039 if (error) { 1040 device_printf(dev, "couldn't set up irq\n"); 1041 ether_ifdetach(ifp); 1042 goto fail; 1043 } 1044 1045 fail: 1046 if (error) 1047 ste_detach(dev); 1048 1049 return (error); 1050 } 1051 1052 /* 1053 * Shutdown hardware and free up resources. This can be called any 1054 * time after the mutex has been initialized. It is called in both 1055 * the error case in attach and the normal detach case so it needs 1056 * to be careful about only freeing resources that have actually been 1057 * allocated. 1058 */ 1059 static int 1060 ste_detach(device_t dev) 1061 { 1062 struct ste_softc *sc; 1063 if_t ifp; 1064 1065 sc = device_get_softc(dev); 1066 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1067 ifp = sc->ste_ifp; 1068 1069 #ifdef DEVICE_POLLING 1070 if (if_getcapenable(ifp) & IFCAP_POLLING) 1071 ether_poll_deregister(ifp); 1072 #endif 1073 1074 /* These should only be active if attach succeeded */ 1075 if (device_is_attached(dev)) { 1076 ether_ifdetach(ifp); 1077 STE_LOCK(sc); 1078 ste_stop(sc); 1079 STE_UNLOCK(sc); 1080 callout_drain(&sc->ste_callout); 1081 } 1082 if (sc->ste_miibus) 1083 device_delete_child(dev, sc->ste_miibus); 1084 bus_generic_detach(dev); 1085 1086 if (sc->ste_intrhand) 1087 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1088 if (sc->ste_irq) 1089 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1090 if (sc->ste_res) 1091 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1092 sc->ste_res); 1093 1094 if (ifp) 1095 if_free(ifp); 1096 1097 ste_dma_free(sc); 1098 mtx_destroy(&sc->ste_mtx); 1099 1100 return (0); 1101 } 1102 1103 struct ste_dmamap_arg { 1104 bus_addr_t ste_busaddr; 1105 }; 1106 1107 static void 1108 ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1109 { 1110 struct ste_dmamap_arg *ctx; 1111 1112 if (error != 0) 1113 return; 1114 1115 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1116 1117 ctx = (struct ste_dmamap_arg *)arg; 1118 ctx->ste_busaddr = segs[0].ds_addr; 1119 } 1120 1121 static int 1122 ste_dma_alloc(struct ste_softc *sc) 1123 { 1124 struct ste_chain *txc; 1125 struct ste_chain_onefrag *rxc; 1126 struct ste_dmamap_arg ctx; 1127 int error, i; 1128 1129 /* Create parent DMA tag. */ 1130 error = bus_dma_tag_create( 1131 bus_get_dma_tag(sc->ste_dev), /* parent */ 1132 1, 0, /* alignment, boundary */ 1133 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1134 BUS_SPACE_MAXADDR, /* highaddr */ 1135 NULL, NULL, /* filter, filterarg */ 1136 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1137 0, /* nsegments */ 1138 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1139 0, /* flags */ 1140 NULL, NULL, /* lockfunc, lockarg */ 1141 &sc->ste_cdata.ste_parent_tag); 1142 if (error != 0) { 1143 device_printf(sc->ste_dev, 1144 "could not create parent DMA tag.\n"); 1145 goto fail; 1146 } 1147 1148 /* Create DMA tag for Tx descriptor list. */ 1149 error = bus_dma_tag_create( 1150 sc->ste_cdata.ste_parent_tag, /* parent */ 1151 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1152 BUS_SPACE_MAXADDR, /* lowaddr */ 1153 BUS_SPACE_MAXADDR, /* highaddr */ 1154 NULL, NULL, /* filter, filterarg */ 1155 STE_TX_LIST_SZ, /* maxsize */ 1156 1, /* nsegments */ 1157 STE_TX_LIST_SZ, /* maxsegsize */ 1158 0, /* flags */ 1159 NULL, NULL, /* lockfunc, lockarg */ 1160 &sc->ste_cdata.ste_tx_list_tag); 1161 if (error != 0) { 1162 device_printf(sc->ste_dev, 1163 "could not create Tx list DMA tag.\n"); 1164 goto fail; 1165 } 1166 1167 /* Create DMA tag for Rx descriptor list. */ 1168 error = bus_dma_tag_create( 1169 sc->ste_cdata.ste_parent_tag, /* parent */ 1170 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1171 BUS_SPACE_MAXADDR, /* lowaddr */ 1172 BUS_SPACE_MAXADDR, /* highaddr */ 1173 NULL, NULL, /* filter, filterarg */ 1174 STE_RX_LIST_SZ, /* maxsize */ 1175 1, /* nsegments */ 1176 STE_RX_LIST_SZ, /* maxsegsize */ 1177 0, /* flags */ 1178 NULL, NULL, /* lockfunc, lockarg */ 1179 &sc->ste_cdata.ste_rx_list_tag); 1180 if (error != 0) { 1181 device_printf(sc->ste_dev, 1182 "could not create Rx list DMA tag.\n"); 1183 goto fail; 1184 } 1185 1186 /* Create DMA tag for Tx buffers. */ 1187 error = bus_dma_tag_create( 1188 sc->ste_cdata.ste_parent_tag, /* parent */ 1189 1, 0, /* alignment, boundary */ 1190 BUS_SPACE_MAXADDR, /* lowaddr */ 1191 BUS_SPACE_MAXADDR, /* highaddr */ 1192 NULL, NULL, /* filter, filterarg */ 1193 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1194 STE_MAXFRAGS, /* nsegments */ 1195 MCLBYTES, /* maxsegsize */ 1196 0, /* flags */ 1197 NULL, NULL, /* lockfunc, lockarg */ 1198 &sc->ste_cdata.ste_tx_tag); 1199 if (error != 0) { 1200 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1201 goto fail; 1202 } 1203 1204 /* Create DMA tag for Rx buffers. */ 1205 error = bus_dma_tag_create( 1206 sc->ste_cdata.ste_parent_tag, /* parent */ 1207 1, 0, /* alignment, boundary */ 1208 BUS_SPACE_MAXADDR, /* lowaddr */ 1209 BUS_SPACE_MAXADDR, /* highaddr */ 1210 NULL, NULL, /* filter, filterarg */ 1211 MCLBYTES, /* maxsize */ 1212 1, /* nsegments */ 1213 MCLBYTES, /* maxsegsize */ 1214 0, /* flags */ 1215 NULL, NULL, /* lockfunc, lockarg */ 1216 &sc->ste_cdata.ste_rx_tag); 1217 if (error != 0) { 1218 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1219 goto fail; 1220 } 1221 1222 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1223 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1224 (void **)&sc->ste_ldata.ste_tx_list, 1225 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1226 &sc->ste_cdata.ste_tx_list_map); 1227 if (error != 0) { 1228 device_printf(sc->ste_dev, 1229 "could not allocate DMA'able memory for Tx list.\n"); 1230 goto fail; 1231 } 1232 ctx.ste_busaddr = 0; 1233 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1234 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1235 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1236 if (error != 0 || ctx.ste_busaddr == 0) { 1237 device_printf(sc->ste_dev, 1238 "could not load DMA'able memory for Tx list.\n"); 1239 goto fail; 1240 } 1241 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1242 1243 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1244 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1245 (void **)&sc->ste_ldata.ste_rx_list, 1246 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1247 &sc->ste_cdata.ste_rx_list_map); 1248 if (error != 0) { 1249 device_printf(sc->ste_dev, 1250 "could not allocate DMA'able memory for Rx list.\n"); 1251 goto fail; 1252 } 1253 ctx.ste_busaddr = 0; 1254 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1255 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1256 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1257 if (error != 0 || ctx.ste_busaddr == 0) { 1258 device_printf(sc->ste_dev, 1259 "could not load DMA'able memory for Rx list.\n"); 1260 goto fail; 1261 } 1262 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1263 1264 /* Create DMA maps for Tx buffers. */ 1265 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1266 txc = &sc->ste_cdata.ste_tx_chain[i]; 1267 txc->ste_ptr = NULL; 1268 txc->ste_mbuf = NULL; 1269 txc->ste_next = NULL; 1270 txc->ste_phys = 0; 1271 txc->ste_map = NULL; 1272 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1273 &txc->ste_map); 1274 if (error != 0) { 1275 device_printf(sc->ste_dev, 1276 "could not create Tx dmamap.\n"); 1277 goto fail; 1278 } 1279 } 1280 /* Create DMA maps for Rx buffers. */ 1281 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1282 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1283 device_printf(sc->ste_dev, 1284 "could not create spare Rx dmamap.\n"); 1285 goto fail; 1286 } 1287 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1288 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1289 rxc->ste_ptr = NULL; 1290 rxc->ste_mbuf = NULL; 1291 rxc->ste_next = NULL; 1292 rxc->ste_map = NULL; 1293 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1294 &rxc->ste_map); 1295 if (error != 0) { 1296 device_printf(sc->ste_dev, 1297 "could not create Rx dmamap.\n"); 1298 goto fail; 1299 } 1300 } 1301 1302 fail: 1303 return (error); 1304 } 1305 1306 static void 1307 ste_dma_free(struct ste_softc *sc) 1308 { 1309 struct ste_chain *txc; 1310 struct ste_chain_onefrag *rxc; 1311 int i; 1312 1313 /* Tx buffers. */ 1314 if (sc->ste_cdata.ste_tx_tag != NULL) { 1315 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1316 txc = &sc->ste_cdata.ste_tx_chain[i]; 1317 if (txc->ste_map != NULL) { 1318 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1319 txc->ste_map); 1320 txc->ste_map = NULL; 1321 } 1322 } 1323 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1324 sc->ste_cdata.ste_tx_tag = NULL; 1325 } 1326 /* Rx buffers. */ 1327 if (sc->ste_cdata.ste_rx_tag != NULL) { 1328 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1329 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1330 if (rxc->ste_map != NULL) { 1331 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1332 rxc->ste_map); 1333 rxc->ste_map = NULL; 1334 } 1335 } 1336 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1337 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1338 sc->ste_cdata.ste_rx_sparemap); 1339 sc->ste_cdata.ste_rx_sparemap = NULL; 1340 } 1341 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1342 sc->ste_cdata.ste_rx_tag = NULL; 1343 } 1344 /* Tx descriptor list. */ 1345 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1346 if (sc->ste_ldata.ste_tx_list_paddr != 0) 1347 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1348 sc->ste_cdata.ste_tx_list_map); 1349 if (sc->ste_ldata.ste_tx_list != NULL) 1350 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1351 sc->ste_ldata.ste_tx_list, 1352 sc->ste_cdata.ste_tx_list_map); 1353 sc->ste_ldata.ste_tx_list = NULL; 1354 sc->ste_ldata.ste_tx_list_paddr = 0; 1355 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1356 sc->ste_cdata.ste_tx_list_tag = NULL; 1357 } 1358 /* Rx descriptor list. */ 1359 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1360 if (sc->ste_ldata.ste_rx_list_paddr != 0) 1361 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1362 sc->ste_cdata.ste_rx_list_map); 1363 if (sc->ste_ldata.ste_rx_list != NULL) 1364 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1365 sc->ste_ldata.ste_rx_list, 1366 sc->ste_cdata.ste_rx_list_map); 1367 sc->ste_ldata.ste_rx_list = NULL; 1368 sc->ste_ldata.ste_rx_list_paddr = 0; 1369 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1370 sc->ste_cdata.ste_rx_list_tag = NULL; 1371 } 1372 if (sc->ste_cdata.ste_parent_tag != NULL) { 1373 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1374 sc->ste_cdata.ste_parent_tag = NULL; 1375 } 1376 } 1377 1378 static int 1379 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1380 { 1381 struct mbuf *m; 1382 bus_dma_segment_t segs[1]; 1383 bus_dmamap_t map; 1384 int error, nsegs; 1385 1386 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1387 if (m == NULL) 1388 return (ENOBUFS); 1389 m->m_len = m->m_pkthdr.len = MCLBYTES; 1390 m_adj(m, ETHER_ALIGN); 1391 1392 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1393 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1394 m_freem(m); 1395 return (error); 1396 } 1397 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1398 1399 if (rxc->ste_mbuf != NULL) { 1400 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1401 BUS_DMASYNC_POSTREAD); 1402 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1403 } 1404 map = rxc->ste_map; 1405 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1406 sc->ste_cdata.ste_rx_sparemap = map; 1407 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1408 BUS_DMASYNC_PREREAD); 1409 rxc->ste_mbuf = m; 1410 rxc->ste_ptr->ste_status = 0; 1411 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1412 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1413 STE_FRAG_LAST); 1414 return (0); 1415 } 1416 1417 static int 1418 ste_init_rx_list(struct ste_softc *sc) 1419 { 1420 struct ste_chain_data *cd; 1421 struct ste_list_data *ld; 1422 int error, i; 1423 1424 sc->ste_int_rx_act = 0; 1425 cd = &sc->ste_cdata; 1426 ld = &sc->ste_ldata; 1427 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1428 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1429 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1430 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1431 if (error != 0) 1432 return (error); 1433 if (i == (STE_RX_LIST_CNT - 1)) { 1434 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1435 ld->ste_rx_list[i].ste_next = 1436 htole32(ld->ste_rx_list_paddr + 1437 (sizeof(struct ste_desc_onefrag) * 0)); 1438 } else { 1439 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1440 ld->ste_rx_list[i].ste_next = 1441 htole32(ld->ste_rx_list_paddr + 1442 (sizeof(struct ste_desc_onefrag) * (i + 1))); 1443 } 1444 } 1445 1446 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1447 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1448 sc->ste_cdata.ste_rx_list_map, 1449 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1450 1451 return (0); 1452 } 1453 1454 static void 1455 ste_init_tx_list(struct ste_softc *sc) 1456 { 1457 struct ste_chain_data *cd; 1458 struct ste_list_data *ld; 1459 int i; 1460 1461 cd = &sc->ste_cdata; 1462 ld = &sc->ste_ldata; 1463 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1464 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1465 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1466 cd->ste_tx_chain[i].ste_mbuf = NULL; 1467 if (i == (STE_TX_LIST_CNT - 1)) { 1468 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1469 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1470 ld->ste_tx_list_paddr + 1471 (sizeof(struct ste_desc) * 0))); 1472 } else { 1473 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1474 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1475 ld->ste_tx_list_paddr + 1476 (sizeof(struct ste_desc) * (i + 1)))); 1477 } 1478 } 1479 1480 cd->ste_last_tx = NULL; 1481 cd->ste_tx_prod = 0; 1482 cd->ste_tx_cons = 0; 1483 cd->ste_tx_cnt = 0; 1484 1485 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1486 sc->ste_cdata.ste_tx_list_map, 1487 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1488 } 1489 1490 static void 1491 ste_init(void *xsc) 1492 { 1493 struct ste_softc *sc; 1494 1495 sc = xsc; 1496 STE_LOCK(sc); 1497 ste_init_locked(sc); 1498 STE_UNLOCK(sc); 1499 } 1500 1501 static void 1502 ste_init_locked(struct ste_softc *sc) 1503 { 1504 if_t ifp; 1505 struct mii_data *mii; 1506 uint8_t val; 1507 int i; 1508 1509 STE_LOCK_ASSERT(sc); 1510 ifp = sc->ste_ifp; 1511 mii = device_get_softc(sc->ste_miibus); 1512 1513 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1514 return; 1515 1516 ste_stop(sc); 1517 /* Reset the chip to a known state. */ 1518 ste_reset(sc); 1519 1520 /* Init our MAC address */ 1521 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1522 CSR_WRITE_2(sc, STE_PAR0 + i, 1523 ((if_getlladdr(sc->ste_ifp)[i] & 0xff) | 1524 if_getlladdr(sc->ste_ifp)[i + 1] << 8)); 1525 } 1526 1527 /* Init RX list */ 1528 if (ste_init_rx_list(sc) != 0) { 1529 device_printf(sc->ste_dev, 1530 "initialization failed: no memory for RX buffers\n"); 1531 ste_stop(sc); 1532 return; 1533 } 1534 1535 /* Set RX polling interval */ 1536 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1537 1538 /* Init TX descriptors */ 1539 ste_init_tx_list(sc); 1540 1541 /* Clear and disable WOL. */ 1542 val = CSR_READ_1(sc, STE_WAKE_EVENT); 1543 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 1544 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 1545 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 1546 1547 /* Set the TX freethresh value */ 1548 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1549 1550 /* Set the TX start threshold for best performance. */ 1551 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1552 1553 /* Set the TX reclaim threshold. */ 1554 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1555 1556 /* Accept VLAN length packets */ 1557 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1558 1559 /* Set up the RX filter. */ 1560 ste_rxfilter(sc); 1561 1562 /* Load the address of the RX list. */ 1563 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1564 ste_wait(sc); 1565 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1566 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1567 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1568 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1569 1570 /* Set TX polling interval(defer until we TX first packet). */ 1571 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1572 1573 /* Load address of the TX list */ 1574 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1575 ste_wait(sc); 1576 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1577 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1578 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1579 ste_wait(sc); 1580 /* Select 3.2us timer. */ 1581 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED | 1582 STE_DMACTL_COUNTDOWN_MODE); 1583 1584 /* Enable receiver and transmitter */ 1585 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1586 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1587 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1588 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1589 1590 /* Enable stats counters. */ 1591 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1592 /* Clear stats counters. */ 1593 ste_stats_clear(sc); 1594 1595 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1596 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1597 #ifdef DEVICE_POLLING 1598 /* Disable interrupts if we are polling. */ 1599 if (if_getcapenable(ifp) & IFCAP_POLLING) 1600 CSR_WRITE_2(sc, STE_IMR, 0); 1601 else 1602 #endif 1603 /* Enable interrupts. */ 1604 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1605 1606 sc->ste_flags &= ~STE_FLAG_LINK; 1607 /* Switch to the current media. */ 1608 mii_mediachg(mii); 1609 1610 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1611 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1612 1613 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1614 } 1615 1616 static void 1617 ste_stop(struct ste_softc *sc) 1618 { 1619 if_t ifp; 1620 struct ste_chain_onefrag *cur_rx; 1621 struct ste_chain *cur_tx; 1622 uint32_t val; 1623 int i; 1624 1625 STE_LOCK_ASSERT(sc); 1626 ifp = sc->ste_ifp; 1627 1628 callout_stop(&sc->ste_callout); 1629 sc->ste_timer = 0; 1630 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)); 1631 1632 CSR_WRITE_2(sc, STE_IMR, 0); 1633 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1634 /* Stop pending DMA. */ 1635 val = CSR_READ_4(sc, STE_DMACTL); 1636 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1637 CSR_WRITE_4(sc, STE_DMACTL, val); 1638 ste_wait(sc); 1639 /* Disable auto-polling. */ 1640 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1641 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1642 /* Nullify DMA address to stop any further DMA. */ 1643 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1644 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1645 /* Stop TX/RX MAC. */ 1646 val = CSR_READ_2(sc, STE_MACCTL1); 1647 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1648 STE_MACCTL1_STATS_DISABLE; 1649 CSR_WRITE_2(sc, STE_MACCTL1, val); 1650 for (i = 0; i < STE_TIMEOUT; i++) { 1651 DELAY(10); 1652 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1653 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1654 break; 1655 } 1656 if (i == STE_TIMEOUT) 1657 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1658 /* Acknowledge any pending interrupts. */ 1659 CSR_READ_2(sc, STE_ISR_ACK); 1660 ste_stats_update(sc); 1661 1662 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1663 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1664 if (cur_rx->ste_mbuf != NULL) { 1665 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1666 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1667 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1668 cur_rx->ste_map); 1669 m_freem(cur_rx->ste_mbuf); 1670 cur_rx->ste_mbuf = NULL; 1671 } 1672 } 1673 1674 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1675 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1676 if (cur_tx->ste_mbuf != NULL) { 1677 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1678 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1679 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1680 cur_tx->ste_map); 1681 m_freem(cur_tx->ste_mbuf); 1682 cur_tx->ste_mbuf = NULL; 1683 } 1684 } 1685 } 1686 1687 static void 1688 ste_reset(struct ste_softc *sc) 1689 { 1690 uint32_t ctl; 1691 int i; 1692 1693 ctl = CSR_READ_4(sc, STE_ASICCTL); 1694 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET | 1695 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET | 1696 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET | 1697 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET | 1698 STE_ASICCTL_EXTRESET_RESET; 1699 CSR_WRITE_4(sc, STE_ASICCTL, ctl); 1700 CSR_READ_4(sc, STE_ASICCTL); 1701 /* 1702 * Due to the need of accessing EEPROM controller can take 1703 * up to 1ms to complete the global reset. 1704 */ 1705 DELAY(1000); 1706 1707 for (i = 0; i < STE_TIMEOUT; i++) { 1708 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1709 break; 1710 DELAY(10); 1711 } 1712 1713 if (i == STE_TIMEOUT) 1714 device_printf(sc->ste_dev, "global reset never completed\n"); 1715 } 1716 1717 static void 1718 ste_restart_tx(struct ste_softc *sc) 1719 { 1720 uint16_t mac; 1721 int i; 1722 1723 for (i = 0; i < STE_TIMEOUT; i++) { 1724 mac = CSR_READ_2(sc, STE_MACCTL1); 1725 mac |= STE_MACCTL1_TX_ENABLE; 1726 CSR_WRITE_2(sc, STE_MACCTL1, mac); 1727 mac = CSR_READ_2(sc, STE_MACCTL1); 1728 if ((mac & STE_MACCTL1_TX_ENABLED) != 0) 1729 break; 1730 DELAY(10); 1731 } 1732 1733 if (i == STE_TIMEOUT) 1734 device_printf(sc->ste_dev, "starting Tx failed"); 1735 } 1736 1737 static int 1738 ste_ioctl(if_t ifp, u_long command, caddr_t data) 1739 { 1740 struct ste_softc *sc; 1741 struct ifreq *ifr; 1742 struct mii_data *mii; 1743 int error = 0, mask; 1744 1745 sc = if_getsoftc(ifp); 1746 ifr = (struct ifreq *)data; 1747 1748 switch (command) { 1749 case SIOCSIFFLAGS: 1750 STE_LOCK(sc); 1751 if ((if_getflags(ifp) & IFF_UP) != 0) { 1752 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1753 ((if_getflags(ifp) ^ sc->ste_if_flags) & 1754 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1755 ste_rxfilter(sc); 1756 else 1757 ste_init_locked(sc); 1758 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1759 ste_stop(sc); 1760 sc->ste_if_flags = if_getflags(ifp); 1761 STE_UNLOCK(sc); 1762 break; 1763 case SIOCADDMULTI: 1764 case SIOCDELMULTI: 1765 STE_LOCK(sc); 1766 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1767 ste_rxfilter(sc); 1768 STE_UNLOCK(sc); 1769 break; 1770 case SIOCGIFMEDIA: 1771 case SIOCSIFMEDIA: 1772 mii = device_get_softc(sc->ste_miibus); 1773 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1774 break; 1775 case SIOCSIFCAP: 1776 STE_LOCK(sc); 1777 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1778 #ifdef DEVICE_POLLING 1779 if ((mask & IFCAP_POLLING) != 0 && 1780 (IFCAP_POLLING & if_getcapabilities(ifp)) != 0) { 1781 if_togglecapenable(ifp, IFCAP_POLLING); 1782 if ((IFCAP_POLLING & if_getcapenable(ifp)) != 0) { 1783 error = ether_poll_register(ste_poll, ifp); 1784 if (error != 0) { 1785 STE_UNLOCK(sc); 1786 break; 1787 } 1788 /* Disable interrupts. */ 1789 CSR_WRITE_2(sc, STE_IMR, 0); 1790 } else { 1791 error = ether_poll_deregister(ifp); 1792 /* Enable interrupts. */ 1793 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1794 } 1795 } 1796 #endif /* DEVICE_POLLING */ 1797 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1798 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1799 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1800 STE_UNLOCK(sc); 1801 break; 1802 default: 1803 error = ether_ioctl(ifp, command, data); 1804 break; 1805 } 1806 1807 return (error); 1808 } 1809 1810 static int 1811 ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1812 { 1813 struct ste_frag *frag; 1814 struct mbuf *m; 1815 struct ste_desc *desc; 1816 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1817 int error, i, nsegs; 1818 1819 STE_LOCK_ASSERT(sc); 1820 M_ASSERTPKTHDR((*m_head)); 1821 1822 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1823 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1824 if (error == EFBIG) { 1825 m = m_collapse(*m_head, M_NOWAIT, STE_MAXFRAGS); 1826 if (m == NULL) { 1827 m_freem(*m_head); 1828 *m_head = NULL; 1829 return (ENOMEM); 1830 } 1831 *m_head = m; 1832 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1833 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1834 if (error != 0) { 1835 m_freem(*m_head); 1836 *m_head = NULL; 1837 return (error); 1838 } 1839 } else if (error != 0) 1840 return (error); 1841 if (nsegs == 0) { 1842 m_freem(*m_head); 1843 *m_head = NULL; 1844 return (EIO); 1845 } 1846 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1847 BUS_DMASYNC_PREWRITE); 1848 1849 desc = txc->ste_ptr; 1850 for (i = 0; i < nsegs; i++) { 1851 frag = &desc->ste_frags[i]; 1852 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1853 frag->ste_len = htole32(txsegs[i].ds_len); 1854 } 1855 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1856 /* 1857 * Because we use Tx polling we can't chain multiple 1858 * Tx descriptors here. Otherwise we race with controller. 1859 */ 1860 desc->ste_next = 0; 1861 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0) 1862 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | 1863 STE_TXCTL_DMAINTR); 1864 else 1865 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS); 1866 txc->ste_mbuf = *m_head; 1867 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1868 sc->ste_cdata.ste_tx_cnt++; 1869 1870 return (0); 1871 } 1872 1873 static void 1874 ste_start(if_t ifp) 1875 { 1876 struct ste_softc *sc; 1877 1878 sc = if_getsoftc(ifp); 1879 STE_LOCK(sc); 1880 ste_start_locked(ifp); 1881 STE_UNLOCK(sc); 1882 } 1883 1884 static void 1885 ste_start_locked(if_t ifp) 1886 { 1887 struct ste_softc *sc; 1888 struct ste_chain *cur_tx; 1889 struct mbuf *m_head = NULL; 1890 int enq; 1891 1892 sc = if_getsoftc(ifp); 1893 STE_LOCK_ASSERT(sc); 1894 1895 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1896 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1897 return; 1898 1899 for (enq = 0; !if_sendq_empty(ifp);) { 1900 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1901 /* 1902 * Controller may have cached copy of the last used 1903 * next ptr so we have to reserve one TFD to avoid 1904 * TFD overruns. 1905 */ 1906 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1907 break; 1908 } 1909 m_head = if_dequeue(ifp); 1910 if (m_head == NULL) 1911 break; 1912 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1913 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1914 if (m_head == NULL) 1915 break; 1916 if_sendq_prepend(ifp, m_head); 1917 break; 1918 } 1919 if (sc->ste_cdata.ste_last_tx == NULL) { 1920 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1921 sc->ste_cdata.ste_tx_list_map, 1922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1923 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1924 ste_wait(sc); 1925 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1926 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1927 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1928 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1929 ste_wait(sc); 1930 } else { 1931 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1932 sc->ste_cdata.ste_last_tx->ste_phys; 1933 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1934 sc->ste_cdata.ste_tx_list_map, 1935 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1936 } 1937 sc->ste_cdata.ste_last_tx = cur_tx; 1938 1939 enq++; 1940 /* 1941 * If there's a BPF listener, bounce a copy of this frame 1942 * to him. 1943 */ 1944 BPF_MTAP(ifp, m_head); 1945 } 1946 1947 if (enq > 0) 1948 sc->ste_timer = STE_TX_TIMEOUT; 1949 } 1950 1951 static void 1952 ste_watchdog(struct ste_softc *sc) 1953 { 1954 if_t ifp; 1955 1956 ifp = sc->ste_ifp; 1957 STE_LOCK_ASSERT(sc); 1958 1959 if (sc->ste_timer == 0 || --sc->ste_timer) 1960 return; 1961 1962 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1963 if_printf(ifp, "watchdog timeout\n"); 1964 1965 ste_txeof(sc); 1966 ste_txeoc(sc); 1967 ste_rxeof(sc, -1); 1968 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1969 ste_init_locked(sc); 1970 1971 if (!if_sendq_empty(ifp)) 1972 ste_start_locked(ifp); 1973 } 1974 1975 static int 1976 ste_shutdown(device_t dev) 1977 { 1978 1979 return (ste_suspend(dev)); 1980 } 1981 1982 static int 1983 ste_suspend(device_t dev) 1984 { 1985 struct ste_softc *sc; 1986 1987 sc = device_get_softc(dev); 1988 1989 STE_LOCK(sc); 1990 ste_stop(sc); 1991 ste_setwol(sc); 1992 STE_UNLOCK(sc); 1993 1994 return (0); 1995 } 1996 1997 static int 1998 ste_resume(device_t dev) 1999 { 2000 struct ste_softc *sc; 2001 if_t ifp; 2002 int pmc; 2003 uint16_t pmstat; 2004 2005 sc = device_get_softc(dev); 2006 STE_LOCK(sc); 2007 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) == 0) { 2008 /* Disable PME and clear PME status. */ 2009 pmstat = pci_read_config(sc->ste_dev, 2010 pmc + PCIR_POWER_STATUS, 2); 2011 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2012 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2013 pci_write_config(sc->ste_dev, 2014 pmc + PCIR_POWER_STATUS, pmstat, 2); 2015 } 2016 } 2017 ifp = sc->ste_ifp; 2018 if ((if_getflags(ifp) & IFF_UP) != 0) { 2019 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2020 ste_init_locked(sc); 2021 } 2022 STE_UNLOCK(sc); 2023 2024 return (0); 2025 } 2026 2027 #define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2028 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2029 #define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2030 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2031 2032 static void 2033 ste_sysctl_node(struct ste_softc *sc) 2034 { 2035 struct sysctl_ctx_list *ctx; 2036 struct sysctl_oid_list *child, *parent; 2037 struct sysctl_oid *tree; 2038 struct ste_hw_stats *stats; 2039 2040 stats = &sc->ste_stats; 2041 ctx = device_get_sysctl_ctx(sc->ste_dev); 2042 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev)); 2043 2044 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod", 2045 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation"); 2046 /* Pull in device tunables. */ 2047 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT; 2048 resource_int_value(device_get_name(sc->ste_dev), 2049 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod); 2050 2051 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 2052 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "STE statistics"); 2053 parent = SYSCTL_CHILDREN(tree); 2054 2055 /* Rx statistics. */ 2056 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2057 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 2058 child = SYSCTL_CHILDREN(tree); 2059 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2060 &stats->rx_bytes, "Good octets"); 2061 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2062 &stats->rx_frames, "Good frames"); 2063 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2064 &stats->rx_bcast_frames, "Good broadcast frames"); 2065 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2066 &stats->rx_mcast_frames, "Good multicast frames"); 2067 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames", 2068 &stats->rx_lost_frames, "Lost frames"); 2069 2070 /* Tx statistics. */ 2071 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2072 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 2073 child = SYSCTL_CHILDREN(tree); 2074 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2075 &stats->tx_bytes, "Good octets"); 2076 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2077 &stats->tx_frames, "Good frames"); 2078 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2079 &stats->tx_bcast_frames, "Good broadcast frames"); 2080 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2081 &stats->tx_mcast_frames, "Good multicast frames"); 2082 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs", 2083 &stats->tx_carrsense_errs, "Carrier sense errors"); 2084 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 2085 &stats->tx_single_colls, "Single collisions"); 2086 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 2087 &stats->tx_multi_colls, "Multiple collisions"); 2088 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2089 &stats->tx_late_colls, "Late collisions"); 2090 STE_SYSCTL_STAT_ADD32(ctx, child, "defers", 2091 &stats->tx_frames_defered, "Frames with deferrals"); 2092 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 2093 &stats->tx_excess_defers, "Frames with excessive derferrals"); 2094 STE_SYSCTL_STAT_ADD32(ctx, child, "abort", 2095 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 2096 } 2097 2098 #undef STE_SYSCTL_STAT_ADD32 2099 #undef STE_SYSCTL_STAT_ADD64 2100 2101 static void 2102 ste_setwol(struct ste_softc *sc) 2103 { 2104 if_t ifp; 2105 uint16_t pmstat; 2106 uint8_t val; 2107 int pmc; 2108 2109 STE_LOCK_ASSERT(sc); 2110 2111 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) != 0) { 2112 /* Disable WOL. */ 2113 CSR_READ_1(sc, STE_WAKE_EVENT); 2114 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0); 2115 return; 2116 } 2117 2118 ifp = sc->ste_ifp; 2119 val = CSR_READ_1(sc, STE_WAKE_EVENT); 2120 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 2121 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 2122 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2123 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB; 2124 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 2125 /* Request PME. */ 2126 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2); 2127 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2128 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2129 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2130 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2131 } 2132