1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 #ifdef HAVE_KERNEL_OPTION_HEADERS 37 #include "opt_device_polling.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/malloc.h> 47 #include <sys/mbuf.h> 48 #include <sys/module.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 54 #include <net/bpf.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_arp.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #include <machine/bus.h> 65 #include <machine/resource.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/mii_bitbang.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ste/if_stereg.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 MODULE_DEPEND(ste, pci, 1, 1, 1); 80 MODULE_DEPEND(ste, ether, 1, 1, 1); 81 MODULE_DEPEND(ste, miibus, 1, 1, 1); 82 83 /* Define to show Tx error status. */ 84 #define STE_SHOW_TXERRORS 85 86 /* 87 * Various supported device vendors/types and their names. 88 */ 89 static const struct ste_type ste_devs[] = { 90 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 91 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 92 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 93 { 0, 0, NULL } 94 }; 95 96 static int ste_attach(device_t); 97 static int ste_detach(device_t); 98 static int ste_probe(device_t); 99 static int ste_resume(device_t); 100 static int ste_shutdown(device_t); 101 static int ste_suspend(device_t); 102 103 static int ste_dma_alloc(struct ste_softc *); 104 static void ste_dma_free(struct ste_softc *); 105 static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 106 static int ste_eeprom_wait(struct ste_softc *); 107 static int ste_encap(struct ste_softc *, struct mbuf **, 108 struct ste_chain *); 109 static int ste_ifmedia_upd(if_t); 110 static void ste_ifmedia_sts(if_t, struct ifmediareq *); 111 static void ste_init(void *); 112 static void ste_init_locked(struct ste_softc *); 113 static int ste_init_rx_list(struct ste_softc *); 114 static void ste_init_tx_list(struct ste_softc *); 115 static void ste_intr(void *); 116 static int ste_ioctl(if_t, u_long, caddr_t); 117 static uint32_t ste_mii_bitbang_read(device_t); 118 static void ste_mii_bitbang_write(device_t, uint32_t); 119 static int ste_miibus_readreg(device_t, int, int); 120 static void ste_miibus_statchg(device_t); 121 static int ste_miibus_writereg(device_t, int, int, int); 122 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 123 static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int); 124 static void ste_reset(struct ste_softc *); 125 static void ste_restart_tx(struct ste_softc *); 126 static int ste_rxeof(struct ste_softc *, int); 127 static void ste_rxfilter(struct ste_softc *); 128 static void ste_setwol(struct ste_softc *); 129 static void ste_start(if_t); 130 static void ste_start_locked(if_t); 131 static void ste_stats_clear(struct ste_softc *); 132 static void ste_stats_update(struct ste_softc *); 133 static void ste_stop(struct ste_softc *); 134 static void ste_sysctl_node(struct ste_softc *); 135 static void ste_tick(void *); 136 static void ste_txeoc(struct ste_softc *); 137 static void ste_txeof(struct ste_softc *); 138 static void ste_wait(struct ste_softc *); 139 static void ste_watchdog(struct ste_softc *); 140 141 /* 142 * MII bit-bang glue 143 */ 144 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 145 ste_mii_bitbang_read, 146 ste_mii_bitbang_write, 147 { 148 STE_PHYCTL_MDATA, /* MII_BIT_MDO */ 149 STE_PHYCTL_MDATA, /* MII_BIT_MDI */ 150 STE_PHYCTL_MCLK, /* MII_BIT_MDC */ 151 STE_PHYCTL_MDIR, /* MII_BIT_DIR_HOST_PHY */ 152 0, /* MII_BIT_DIR_PHY_HOST */ 153 } 154 }; 155 156 static device_method_t ste_methods[] = { 157 /* Device interface */ 158 DEVMETHOD(device_probe, ste_probe), 159 DEVMETHOD(device_attach, ste_attach), 160 DEVMETHOD(device_detach, ste_detach), 161 DEVMETHOD(device_shutdown, ste_shutdown), 162 DEVMETHOD(device_suspend, ste_suspend), 163 DEVMETHOD(device_resume, ste_resume), 164 165 /* MII interface */ 166 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 167 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 168 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 169 170 DEVMETHOD_END 171 }; 172 173 static driver_t ste_driver = { 174 "ste", 175 ste_methods, 176 sizeof(struct ste_softc) 177 }; 178 179 DRIVER_MODULE(ste, pci, ste_driver, 0, 0); 180 DRIVER_MODULE(miibus, ste, miibus_driver, 0, 0); 181 182 #define STE_SETBIT4(sc, reg, x) \ 183 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 184 185 #define STE_CLRBIT4(sc, reg, x) \ 186 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 187 188 #define STE_SETBIT2(sc, reg, x) \ 189 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 190 191 #define STE_CLRBIT2(sc, reg, x) \ 192 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 193 194 #define STE_SETBIT1(sc, reg, x) \ 195 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 196 197 #define STE_CLRBIT1(sc, reg, x) \ 198 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 199 200 /* 201 * Read the MII serial port for the MII bit-bang module. 202 */ 203 static uint32_t 204 ste_mii_bitbang_read(device_t dev) 205 { 206 struct ste_softc *sc; 207 uint32_t val; 208 209 sc = device_get_softc(dev); 210 211 val = CSR_READ_1(sc, STE_PHYCTL); 212 CSR_BARRIER(sc, STE_PHYCTL, 1, 213 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 214 215 return (val); 216 } 217 218 /* 219 * Write the MII serial port for the MII bit-bang module. 220 */ 221 static void 222 ste_mii_bitbang_write(device_t dev, uint32_t val) 223 { 224 struct ste_softc *sc; 225 226 sc = device_get_softc(dev); 227 228 CSR_WRITE_1(sc, STE_PHYCTL, val); 229 CSR_BARRIER(sc, STE_PHYCTL, 1, 230 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 231 } 232 233 static int 234 ste_miibus_readreg(device_t dev, int phy, int reg) 235 { 236 237 return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg)); 238 } 239 240 static int 241 ste_miibus_writereg(device_t dev, int phy, int reg, int data) 242 { 243 244 mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data); 245 246 return (0); 247 } 248 249 static void 250 ste_miibus_statchg(device_t dev) 251 { 252 struct ste_softc *sc; 253 struct mii_data *mii; 254 if_t ifp; 255 uint16_t cfg; 256 257 sc = device_get_softc(dev); 258 259 mii = device_get_softc(sc->ste_miibus); 260 ifp = sc->ste_ifp; 261 if (mii == NULL || ifp == NULL || 262 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 263 return; 264 265 sc->ste_flags &= ~STE_FLAG_LINK; 266 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 267 (IFM_ACTIVE | IFM_AVALID)) { 268 switch (IFM_SUBTYPE(mii->mii_media_active)) { 269 case IFM_10_T: 270 case IFM_100_TX: 271 case IFM_100_FX: 272 case IFM_100_T4: 273 sc->ste_flags |= STE_FLAG_LINK; 274 default: 275 break; 276 } 277 } 278 279 /* Program MACs with resolved speed/duplex/flow-control. */ 280 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 281 cfg = CSR_READ_2(sc, STE_MACCTL0); 282 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 283 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 284 /* 285 * ST201 data sheet says driver should enable receiving 286 * MAC control frames bit of receive mode register to 287 * receive flow-control frames but the register has no 288 * such bits. In addition the controller has no ability 289 * to send pause frames so it should be handled in 290 * driver. Implementing pause timer handling in driver 291 * layer is not trivial, so don't enable flow-control 292 * here. 293 */ 294 cfg |= STE_MACCTL0_FULLDUPLEX; 295 } 296 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 297 } 298 } 299 300 static int 301 ste_ifmedia_upd(if_t ifp) 302 { 303 struct ste_softc *sc; 304 struct mii_data *mii; 305 struct mii_softc *miisc; 306 int error; 307 308 sc = if_getsoftc(ifp); 309 STE_LOCK(sc); 310 mii = device_get_softc(sc->ste_miibus); 311 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 312 PHY_RESET(miisc); 313 error = mii_mediachg(mii); 314 STE_UNLOCK(sc); 315 316 return (error); 317 } 318 319 static void 320 ste_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 321 { 322 struct ste_softc *sc; 323 struct mii_data *mii; 324 325 sc = if_getsoftc(ifp); 326 mii = device_get_softc(sc->ste_miibus); 327 328 STE_LOCK(sc); 329 if ((if_getflags(ifp) & IFF_UP) == 0) { 330 STE_UNLOCK(sc); 331 return; 332 } 333 mii_pollstat(mii); 334 ifmr->ifm_active = mii->mii_media_active; 335 ifmr->ifm_status = mii->mii_media_status; 336 STE_UNLOCK(sc); 337 } 338 339 static void 340 ste_wait(struct ste_softc *sc) 341 { 342 int i; 343 344 for (i = 0; i < STE_TIMEOUT; i++) { 345 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 346 break; 347 DELAY(1); 348 } 349 350 if (i == STE_TIMEOUT) 351 device_printf(sc->ste_dev, "command never completed!\n"); 352 } 353 354 /* 355 * The EEPROM is slow: give it time to come ready after issuing 356 * it a command. 357 */ 358 static int 359 ste_eeprom_wait(struct ste_softc *sc) 360 { 361 int i; 362 363 DELAY(1000); 364 365 for (i = 0; i < 100; i++) { 366 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 367 DELAY(1000); 368 else 369 break; 370 } 371 372 if (i == 100) { 373 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 374 return (1); 375 } 376 377 return (0); 378 } 379 380 /* 381 * Read a sequence of words from the EEPROM. Note that ethernet address 382 * data is stored in the EEPROM in network byte order. 383 */ 384 static int 385 ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt) 386 { 387 int err = 0, i; 388 389 if (ste_eeprom_wait(sc)) 390 return (1); 391 392 for (i = 0; i < cnt; i++) { 393 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 394 err = ste_eeprom_wait(sc); 395 if (err) 396 break; 397 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA)); 398 dest++; 399 } 400 401 return (err ? 1 : 0); 402 } 403 404 static u_int 405 ste_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 406 { 407 uint32_t *hashes = arg; 408 int h; 409 410 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0x3F; 411 if (h < 32) 412 hashes[0] |= (1 << h); 413 else 414 hashes[1] |= (1 << (h - 32)); 415 416 return (1); 417 } 418 419 static void 420 ste_rxfilter(struct ste_softc *sc) 421 { 422 if_t ifp; 423 uint32_t hashes[2] = { 0, 0 }; 424 uint8_t rxcfg; 425 426 STE_LOCK_ASSERT(sc); 427 428 ifp = sc->ste_ifp; 429 rxcfg = CSR_READ_1(sc, STE_RX_MODE); 430 rxcfg |= STE_RXMODE_UNICAST; 431 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH | 432 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC); 433 if (if_getflags(ifp) & IFF_BROADCAST) 434 rxcfg |= STE_RXMODE_BROADCAST; 435 if ((if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 436 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 437 rxcfg |= STE_RXMODE_ALLMULTI; 438 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 439 rxcfg |= STE_RXMODE_PROMISC; 440 goto chipit; 441 } 442 443 rxcfg |= STE_RXMODE_MULTIHASH; 444 /* Now program new ones. */ 445 if_foreach_llmaddr(ifp, ste_hash_maddr, hashes); 446 447 chipit: 448 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 449 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 450 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 451 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 452 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg); 453 CSR_READ_1(sc, STE_RX_MODE); 454 } 455 456 #ifdef DEVICE_POLLING 457 static poll_handler_t ste_poll, ste_poll_locked; 458 459 static int 460 ste_poll(if_t ifp, enum poll_cmd cmd, int count) 461 { 462 struct ste_softc *sc = if_getsoftc(ifp); 463 int rx_npkts = 0; 464 465 STE_LOCK(sc); 466 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 467 rx_npkts = ste_poll_locked(ifp, cmd, count); 468 STE_UNLOCK(sc); 469 return (rx_npkts); 470 } 471 472 static int 473 ste_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 474 { 475 struct ste_softc *sc = if_getsoftc(ifp); 476 int rx_npkts; 477 478 STE_LOCK_ASSERT(sc); 479 480 rx_npkts = ste_rxeof(sc, count); 481 ste_txeof(sc); 482 ste_txeoc(sc); 483 if (!if_sendq_empty(ifp)) 484 ste_start_locked(ifp); 485 486 if (cmd == POLL_AND_CHECK_STATUS) { 487 uint16_t status; 488 489 status = CSR_READ_2(sc, STE_ISR_ACK); 490 491 if (status & STE_ISR_STATS_OFLOW) 492 ste_stats_update(sc); 493 494 if (status & STE_ISR_HOSTERR) { 495 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 496 ste_init_locked(sc); 497 } 498 } 499 return (rx_npkts); 500 } 501 #endif /* DEVICE_POLLING */ 502 503 static void 504 ste_intr(void *xsc) 505 { 506 struct ste_softc *sc; 507 if_t ifp; 508 uint16_t intrs, status; 509 510 sc = xsc; 511 STE_LOCK(sc); 512 ifp = sc->ste_ifp; 513 514 #ifdef DEVICE_POLLING 515 if (if_getcapenable(ifp) & IFCAP_POLLING) { 516 STE_UNLOCK(sc); 517 return; 518 } 519 #endif 520 /* Reading STE_ISR_ACK clears STE_IMR register. */ 521 status = CSR_READ_2(sc, STE_ISR_ACK); 522 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 523 STE_UNLOCK(sc); 524 return; 525 } 526 527 intrs = STE_INTRS; 528 if (status == 0xFFFF || (status & intrs) == 0) 529 goto done; 530 531 if (sc->ste_int_rx_act > 0) { 532 status &= ~STE_ISR_RX_DMADONE; 533 intrs &= ~STE_IMR_RX_DMADONE; 534 } 535 536 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) { 537 ste_rxeof(sc, -1); 538 /* 539 * The controller has no ability to Rx interrupt 540 * moderation feature. Receiving 64 bytes frames 541 * from wire generates too many interrupts which in 542 * turn make system useless to process other useful 543 * things. Fortunately ST201 supports single shot 544 * timer so use the timer to implement Rx interrupt 545 * moderation in driver. This adds more register 546 * access but it greatly reduces number of Rx 547 * interrupts under high network load. 548 */ 549 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 550 (sc->ste_int_rx_mod != 0)) { 551 if ((status & STE_ISR_RX_DMADONE) != 0) { 552 CSR_WRITE_2(sc, STE_COUNTDOWN, 553 STE_TIMER_USECS(sc->ste_int_rx_mod)); 554 intrs &= ~STE_IMR_RX_DMADONE; 555 sc->ste_int_rx_act = 1; 556 } else { 557 intrs |= STE_IMR_RX_DMADONE; 558 sc->ste_int_rx_act = 0; 559 } 560 } 561 } 562 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 563 if ((status & STE_ISR_TX_DMADONE) != 0) 564 ste_txeof(sc); 565 if ((status & STE_ISR_TX_DONE) != 0) 566 ste_txeoc(sc); 567 if ((status & STE_ISR_STATS_OFLOW) != 0) 568 ste_stats_update(sc); 569 if ((status & STE_ISR_HOSTERR) != 0) { 570 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 571 ste_init_locked(sc); 572 STE_UNLOCK(sc); 573 return; 574 } 575 if (!if_sendq_empty(ifp)) 576 ste_start_locked(ifp); 577 done: 578 /* Re-enable interrupts */ 579 CSR_WRITE_2(sc, STE_IMR, intrs); 580 } 581 STE_UNLOCK(sc); 582 } 583 584 /* 585 * A frame has been uploaded: pass the resulting mbuf chain up to 586 * the higher level protocols. 587 */ 588 static int 589 ste_rxeof(struct ste_softc *sc, int count) 590 { 591 struct mbuf *m; 592 if_t ifp; 593 struct ste_chain_onefrag *cur_rx; 594 uint32_t rxstat; 595 int total_len, rx_npkts; 596 597 ifp = sc->ste_ifp; 598 599 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 600 sc->ste_cdata.ste_rx_list_map, 601 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 602 603 cur_rx = sc->ste_cdata.ste_rx_head; 604 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 605 cur_rx = cur_rx->ste_next) { 606 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 607 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 608 break; 609 #ifdef DEVICE_POLLING 610 if (if_getcapenable(ifp) & IFCAP_POLLING) { 611 if (count == 0) 612 break; 613 count--; 614 } 615 #endif 616 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 617 break; 618 /* 619 * If an error occurs, update stats, clear the 620 * status word and leave the mbuf cluster in place: 621 * it should simply get re-used next time this descriptor 622 * comes up in the ring. 623 */ 624 if (rxstat & STE_RXSTAT_FRAME_ERR) { 625 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 626 cur_rx->ste_ptr->ste_status = 0; 627 continue; 628 } 629 630 /* No errors; receive the packet. */ 631 m = cur_rx->ste_mbuf; 632 total_len = STE_RX_BYTES(rxstat); 633 634 /* 635 * Try to conjure up a new mbuf cluster. If that 636 * fails, it means we have an out of memory condition and 637 * should leave the buffer in place and continue. This will 638 * result in a lost packet, but there's little else we 639 * can do in this situation. 640 */ 641 if (ste_newbuf(sc, cur_rx) != 0) { 642 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 643 cur_rx->ste_ptr->ste_status = 0; 644 continue; 645 } 646 647 m->m_pkthdr.rcvif = ifp; 648 m->m_pkthdr.len = m->m_len = total_len; 649 650 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 651 STE_UNLOCK(sc); 652 if_input(ifp, m); 653 STE_LOCK(sc); 654 } 655 656 if (rx_npkts > 0) { 657 sc->ste_cdata.ste_rx_head = cur_rx; 658 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 659 sc->ste_cdata.ste_rx_list_map, 660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 661 } 662 663 return (rx_npkts); 664 } 665 666 static void 667 ste_txeoc(struct ste_softc *sc) 668 { 669 uint16_t txstat; 670 if_t ifp; 671 672 STE_LOCK_ASSERT(sc); 673 674 ifp = sc->ste_ifp; 675 676 /* 677 * STE_TX_STATUS register implements a queue of up to 31 678 * transmit status byte. Writing an arbitrary value to the 679 * register will advance the queue to the next transmit 680 * status byte. This means if driver does not read 681 * STE_TX_STATUS register after completing sending more 682 * than 31 frames the controller would be stalled so driver 683 * should re-wake the Tx MAC. This is the most severe 684 * limitation of ST201 based controller. 685 */ 686 for (;;) { 687 txstat = CSR_READ_2(sc, STE_TX_STATUS); 688 if ((txstat & STE_TXSTATUS_TXDONE) == 0) 689 break; 690 if ((txstat & (STE_TXSTATUS_UNDERRUN | 691 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR | 692 STE_TXSTATUS_STATSOFLOW)) != 0) { 693 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 694 #ifdef STE_SHOW_TXERRORS 695 device_printf(sc->ste_dev, "TX error : 0x%b\n", 696 txstat & 0xFF, STE_ERR_BITS); 697 #endif 698 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 && 699 sc->ste_tx_thresh < STE_PACKET_SIZE) { 700 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 701 if (sc->ste_tx_thresh > STE_PACKET_SIZE) 702 sc->ste_tx_thresh = STE_PACKET_SIZE; 703 device_printf(sc->ste_dev, 704 "TX underrun, increasing TX" 705 " start threshold to %d bytes\n", 706 sc->ste_tx_thresh); 707 /* Make sure to disable active DMA cycles. */ 708 STE_SETBIT4(sc, STE_DMACTL, 709 STE_DMACTL_TXDMA_STALL); 710 ste_wait(sc); 711 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 712 ste_init_locked(sc); 713 break; 714 } 715 /* Restart Tx. */ 716 ste_restart_tx(sc); 717 } 718 /* 719 * Advance to next status and ACK TxComplete 720 * interrupt. ST201 data sheet was wrong here, to 721 * get next Tx status, we have to write both 722 * STE_TX_STATUS and STE_TX_FRAMEID register. 723 * Otherwise controller returns the same status 724 * as well as not acknowledge Tx completion 725 * interrupt. 726 */ 727 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 728 } 729 } 730 731 static void 732 ste_tick(void *arg) 733 { 734 struct ste_softc *sc; 735 struct mii_data *mii; 736 737 sc = (struct ste_softc *)arg; 738 739 STE_LOCK_ASSERT(sc); 740 741 mii = device_get_softc(sc->ste_miibus); 742 mii_tick(mii); 743 /* 744 * ukphy(4) does not seem to generate CB that reports 745 * resolved link state so if we know we lost a link, 746 * explicitly check the link state. 747 */ 748 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 749 ste_miibus_statchg(sc->ste_dev); 750 /* 751 * Because we are not generating Tx completion 752 * interrupt for every frame, reclaim transmitted 753 * buffers here. 754 */ 755 ste_txeof(sc); 756 ste_txeoc(sc); 757 ste_stats_update(sc); 758 ste_watchdog(sc); 759 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 760 } 761 762 static void 763 ste_txeof(struct ste_softc *sc) 764 { 765 if_t ifp; 766 struct ste_chain *cur_tx; 767 uint32_t txstat; 768 int idx; 769 770 STE_LOCK_ASSERT(sc); 771 772 ifp = sc->ste_ifp; 773 idx = sc->ste_cdata.ste_tx_cons; 774 if (idx == sc->ste_cdata.ste_tx_prod) 775 return; 776 777 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 778 sc->ste_cdata.ste_tx_list_map, 779 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 780 781 while (idx != sc->ste_cdata.ste_tx_prod) { 782 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 783 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 784 if ((txstat & STE_TXCTL_DMADONE) == 0) 785 break; 786 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 787 BUS_DMASYNC_POSTWRITE); 788 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 789 KASSERT(cur_tx->ste_mbuf != NULL, 790 ("%s: freeing NULL mbuf!\n", __func__)); 791 m_freem(cur_tx->ste_mbuf); 792 cur_tx->ste_mbuf = NULL; 793 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 794 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 795 sc->ste_cdata.ste_tx_cnt--; 796 STE_INC(idx, STE_TX_LIST_CNT); 797 } 798 799 sc->ste_cdata.ste_tx_cons = idx; 800 if (sc->ste_cdata.ste_tx_cnt == 0) 801 sc->ste_timer = 0; 802 } 803 804 static void 805 ste_stats_clear(struct ste_softc *sc) 806 { 807 808 STE_LOCK_ASSERT(sc); 809 810 /* Rx stats. */ 811 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); 812 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); 813 CSR_READ_2(sc, STE_STAT_RX_FRAMES); 814 CSR_READ_1(sc, STE_STAT_RX_BCAST); 815 CSR_READ_1(sc, STE_STAT_RX_MCAST); 816 CSR_READ_1(sc, STE_STAT_RX_LOST); 817 /* Tx stats. */ 818 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO); 819 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI); 820 CSR_READ_2(sc, STE_STAT_TX_FRAMES); 821 CSR_READ_1(sc, STE_STAT_TX_BCAST); 822 CSR_READ_1(sc, STE_STAT_TX_MCAST); 823 CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 824 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 825 CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 826 CSR_READ_1(sc, STE_STAT_LATE_COLLS); 827 CSR_READ_1(sc, STE_STAT_TX_DEFER); 828 CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 829 CSR_READ_1(sc, STE_STAT_TX_ABORT); 830 } 831 832 static void 833 ste_stats_update(struct ste_softc *sc) 834 { 835 if_t ifp; 836 struct ste_hw_stats *stats; 837 uint32_t val; 838 839 STE_LOCK_ASSERT(sc); 840 841 ifp = sc->ste_ifp; 842 stats = &sc->ste_stats; 843 /* Rx stats. */ 844 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) | 845 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16; 846 val &= 0x000FFFFF; 847 stats->rx_bytes += val; 848 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES); 849 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST); 850 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST); 851 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST); 852 /* Tx stats. */ 853 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) | 854 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16; 855 val &= 0x000FFFFF; 856 stats->tx_bytes += val; 857 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES); 858 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST); 859 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST); 860 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 861 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 862 stats->tx_single_colls += val; 863 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 864 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 865 stats->tx_multi_colls += val; 866 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 867 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS); 868 stats->tx_late_colls += val; 869 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 870 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER); 871 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 872 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT); 873 } 874 875 /* 876 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 877 * IDs against our list and return a device name if we find a match. 878 */ 879 static int 880 ste_probe(device_t dev) 881 { 882 const struct ste_type *t; 883 884 t = ste_devs; 885 886 while (t->ste_name != NULL) { 887 if ((pci_get_vendor(dev) == t->ste_vid) && 888 (pci_get_device(dev) == t->ste_did)) { 889 device_set_desc(dev, t->ste_name); 890 return (BUS_PROBE_DEFAULT); 891 } 892 t++; 893 } 894 895 return (ENXIO); 896 } 897 898 /* 899 * Attach the interface. Allocate softc structures, do ifmedia 900 * setup and ethernet/BPF attach. 901 */ 902 static int 903 ste_attach(device_t dev) 904 { 905 struct ste_softc *sc; 906 if_t ifp; 907 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 908 int error = 0, phy, pmc, prefer_iomap, rid; 909 910 sc = device_get_softc(dev); 911 sc->ste_dev = dev; 912 913 /* 914 * Only use one PHY since this chip reports multiple 915 * Note on the DFE-550 the PHY is at 1 on the DFE-580 916 * it is at 0 & 1. It is rev 0x12. 917 */ 918 if (pci_get_vendor(dev) == DL_VENDORID && 919 pci_get_device(dev) == DL_DEVICEID_DL10050 && 920 pci_get_revid(dev) == 0x12 ) 921 sc->ste_flags |= STE_FLAG_ONE_PHY; 922 923 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 924 MTX_DEF); 925 /* 926 * Map control/status registers. 927 */ 928 pci_enable_busmaster(dev); 929 930 /* 931 * Prefer memory space register mapping over IO space but use 932 * IO space for a device that is known to have issues on memory 933 * mapping. 934 */ 935 prefer_iomap = 0; 936 if (pci_get_device(dev) == ST_DEVICEID_ST201_1) 937 prefer_iomap = 1; 938 else 939 resource_int_value(device_get_name(sc->ste_dev), 940 device_get_unit(sc->ste_dev), "prefer_iomap", 941 &prefer_iomap); 942 if (prefer_iomap == 0) { 943 sc->ste_res_id = PCIR_BAR(1); 944 sc->ste_res_type = SYS_RES_MEMORY; 945 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 946 &sc->ste_res_id, RF_ACTIVE); 947 } 948 if (prefer_iomap || sc->ste_res == NULL) { 949 sc->ste_res_id = PCIR_BAR(0); 950 sc->ste_res_type = SYS_RES_IOPORT; 951 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 952 &sc->ste_res_id, RF_ACTIVE); 953 } 954 if (sc->ste_res == NULL) { 955 device_printf(dev, "couldn't map ports/memory\n"); 956 error = ENXIO; 957 goto fail; 958 } 959 960 /* Allocate interrupt */ 961 rid = 0; 962 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 963 RF_SHAREABLE | RF_ACTIVE); 964 965 if (sc->ste_irq == NULL) { 966 device_printf(dev, "couldn't map interrupt\n"); 967 error = ENXIO; 968 goto fail; 969 } 970 971 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 972 973 /* Reset the adapter. */ 974 ste_reset(sc); 975 976 /* 977 * Get station address from the EEPROM. 978 */ 979 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) { 980 device_printf(dev, "failed to read station address\n"); 981 error = ENXIO; 982 goto fail; 983 } 984 ste_sysctl_node(sc); 985 986 if ((error = ste_dma_alloc(sc)) != 0) 987 goto fail; 988 989 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 990 991 /* Do MII setup. */ 992 phy = MII_PHY_ANY; 993 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0) 994 phy = 0; 995 error = mii_attach(dev, &sc->ste_miibus, ifp, ste_ifmedia_upd, 996 ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 997 if (error != 0) { 998 device_printf(dev, "attaching PHYs failed\n"); 999 goto fail; 1000 } 1001 1002 if_setsoftc(ifp, sc); 1003 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1004 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1005 if_setioctlfn(ifp, ste_ioctl); 1006 if_setstartfn(ifp, ste_start); 1007 if_setinitfn(ifp, ste_init); 1008 if_setsendqlen(ifp, STE_TX_LIST_CNT - 1); 1009 if_setsendqready(ifp); 1010 1011 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1012 1013 /* 1014 * Call MI attach routine. 1015 */ 1016 ether_ifattach(ifp, (uint8_t *)eaddr); 1017 1018 /* 1019 * Tell the upper layer(s) we support long frames. 1020 */ 1021 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1022 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1023 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 1024 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 1025 if_setcapenable(ifp, if_getcapabilities(ifp)); 1026 #ifdef DEVICE_POLLING 1027 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1028 #endif 1029 1030 /* Hook interrupt last to avoid having to lock softc */ 1031 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1032 NULL, ste_intr, sc, &sc->ste_intrhand); 1033 1034 if (error) { 1035 device_printf(dev, "couldn't set up irq\n"); 1036 ether_ifdetach(ifp); 1037 goto fail; 1038 } 1039 1040 fail: 1041 if (error) 1042 ste_detach(dev); 1043 1044 return (error); 1045 } 1046 1047 /* 1048 * Shutdown hardware and free up resources. This can be called any 1049 * time after the mutex has been initialized. It is called in both 1050 * the error case in attach and the normal detach case so it needs 1051 * to be careful about only freeing resources that have actually been 1052 * allocated. 1053 */ 1054 static int 1055 ste_detach(device_t dev) 1056 { 1057 struct ste_softc *sc; 1058 if_t ifp; 1059 1060 sc = device_get_softc(dev); 1061 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1062 ifp = sc->ste_ifp; 1063 1064 #ifdef DEVICE_POLLING 1065 if (if_getcapenable(ifp) & IFCAP_POLLING) 1066 ether_poll_deregister(ifp); 1067 #endif 1068 1069 /* These should only be active if attach succeeded */ 1070 if (device_is_attached(dev)) { 1071 ether_ifdetach(ifp); 1072 STE_LOCK(sc); 1073 ste_stop(sc); 1074 STE_UNLOCK(sc); 1075 callout_drain(&sc->ste_callout); 1076 } 1077 bus_generic_detach(dev); 1078 1079 if (sc->ste_intrhand) 1080 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1081 if (sc->ste_irq) 1082 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1083 if (sc->ste_res) 1084 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1085 sc->ste_res); 1086 1087 if (ifp) 1088 if_free(ifp); 1089 1090 ste_dma_free(sc); 1091 mtx_destroy(&sc->ste_mtx); 1092 1093 return (0); 1094 } 1095 1096 struct ste_dmamap_arg { 1097 bus_addr_t ste_busaddr; 1098 }; 1099 1100 static void 1101 ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1102 { 1103 struct ste_dmamap_arg *ctx; 1104 1105 if (error != 0) 1106 return; 1107 1108 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1109 1110 ctx = (struct ste_dmamap_arg *)arg; 1111 ctx->ste_busaddr = segs[0].ds_addr; 1112 } 1113 1114 static int 1115 ste_dma_alloc(struct ste_softc *sc) 1116 { 1117 struct ste_chain *txc; 1118 struct ste_chain_onefrag *rxc; 1119 struct ste_dmamap_arg ctx; 1120 int error, i; 1121 1122 /* Create parent DMA tag. */ 1123 error = bus_dma_tag_create( 1124 bus_get_dma_tag(sc->ste_dev), /* parent */ 1125 1, 0, /* alignment, boundary */ 1126 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1127 BUS_SPACE_MAXADDR, /* highaddr */ 1128 NULL, NULL, /* filter, filterarg */ 1129 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1130 0, /* nsegments */ 1131 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1132 0, /* flags */ 1133 NULL, NULL, /* lockfunc, lockarg */ 1134 &sc->ste_cdata.ste_parent_tag); 1135 if (error != 0) { 1136 device_printf(sc->ste_dev, 1137 "could not create parent DMA tag.\n"); 1138 goto fail; 1139 } 1140 1141 /* Create DMA tag for Tx descriptor list. */ 1142 error = bus_dma_tag_create( 1143 sc->ste_cdata.ste_parent_tag, /* parent */ 1144 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1145 BUS_SPACE_MAXADDR, /* lowaddr */ 1146 BUS_SPACE_MAXADDR, /* highaddr */ 1147 NULL, NULL, /* filter, filterarg */ 1148 STE_TX_LIST_SZ, /* maxsize */ 1149 1, /* nsegments */ 1150 STE_TX_LIST_SZ, /* maxsegsize */ 1151 0, /* flags */ 1152 NULL, NULL, /* lockfunc, lockarg */ 1153 &sc->ste_cdata.ste_tx_list_tag); 1154 if (error != 0) { 1155 device_printf(sc->ste_dev, 1156 "could not create Tx list DMA tag.\n"); 1157 goto fail; 1158 } 1159 1160 /* Create DMA tag for Rx descriptor list. */ 1161 error = bus_dma_tag_create( 1162 sc->ste_cdata.ste_parent_tag, /* parent */ 1163 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1164 BUS_SPACE_MAXADDR, /* lowaddr */ 1165 BUS_SPACE_MAXADDR, /* highaddr */ 1166 NULL, NULL, /* filter, filterarg */ 1167 STE_RX_LIST_SZ, /* maxsize */ 1168 1, /* nsegments */ 1169 STE_RX_LIST_SZ, /* maxsegsize */ 1170 0, /* flags */ 1171 NULL, NULL, /* lockfunc, lockarg */ 1172 &sc->ste_cdata.ste_rx_list_tag); 1173 if (error != 0) { 1174 device_printf(sc->ste_dev, 1175 "could not create Rx list DMA tag.\n"); 1176 goto fail; 1177 } 1178 1179 /* Create DMA tag for Tx buffers. */ 1180 error = bus_dma_tag_create( 1181 sc->ste_cdata.ste_parent_tag, /* parent */ 1182 1, 0, /* alignment, boundary */ 1183 BUS_SPACE_MAXADDR, /* lowaddr */ 1184 BUS_SPACE_MAXADDR, /* highaddr */ 1185 NULL, NULL, /* filter, filterarg */ 1186 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1187 STE_MAXFRAGS, /* nsegments */ 1188 MCLBYTES, /* maxsegsize */ 1189 0, /* flags */ 1190 NULL, NULL, /* lockfunc, lockarg */ 1191 &sc->ste_cdata.ste_tx_tag); 1192 if (error != 0) { 1193 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1194 goto fail; 1195 } 1196 1197 /* Create DMA tag for Rx buffers. */ 1198 error = bus_dma_tag_create( 1199 sc->ste_cdata.ste_parent_tag, /* parent */ 1200 1, 0, /* alignment, boundary */ 1201 BUS_SPACE_MAXADDR, /* lowaddr */ 1202 BUS_SPACE_MAXADDR, /* highaddr */ 1203 NULL, NULL, /* filter, filterarg */ 1204 MCLBYTES, /* maxsize */ 1205 1, /* nsegments */ 1206 MCLBYTES, /* maxsegsize */ 1207 0, /* flags */ 1208 NULL, NULL, /* lockfunc, lockarg */ 1209 &sc->ste_cdata.ste_rx_tag); 1210 if (error != 0) { 1211 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1212 goto fail; 1213 } 1214 1215 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1216 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1217 (void **)&sc->ste_ldata.ste_tx_list, 1218 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1219 &sc->ste_cdata.ste_tx_list_map); 1220 if (error != 0) { 1221 device_printf(sc->ste_dev, 1222 "could not allocate DMA'able memory for Tx list.\n"); 1223 goto fail; 1224 } 1225 ctx.ste_busaddr = 0; 1226 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1227 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1228 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1229 if (error != 0 || ctx.ste_busaddr == 0) { 1230 device_printf(sc->ste_dev, 1231 "could not load DMA'able memory for Tx list.\n"); 1232 goto fail; 1233 } 1234 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1235 1236 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1237 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1238 (void **)&sc->ste_ldata.ste_rx_list, 1239 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1240 &sc->ste_cdata.ste_rx_list_map); 1241 if (error != 0) { 1242 device_printf(sc->ste_dev, 1243 "could not allocate DMA'able memory for Rx list.\n"); 1244 goto fail; 1245 } 1246 ctx.ste_busaddr = 0; 1247 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1248 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1249 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1250 if (error != 0 || ctx.ste_busaddr == 0) { 1251 device_printf(sc->ste_dev, 1252 "could not load DMA'able memory for Rx list.\n"); 1253 goto fail; 1254 } 1255 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1256 1257 /* Create DMA maps for Tx buffers. */ 1258 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1259 txc = &sc->ste_cdata.ste_tx_chain[i]; 1260 txc->ste_ptr = NULL; 1261 txc->ste_mbuf = NULL; 1262 txc->ste_next = NULL; 1263 txc->ste_phys = 0; 1264 txc->ste_map = NULL; 1265 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1266 &txc->ste_map); 1267 if (error != 0) { 1268 device_printf(sc->ste_dev, 1269 "could not create Tx dmamap.\n"); 1270 goto fail; 1271 } 1272 } 1273 /* Create DMA maps for Rx buffers. */ 1274 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1275 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1276 device_printf(sc->ste_dev, 1277 "could not create spare Rx dmamap.\n"); 1278 goto fail; 1279 } 1280 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1281 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1282 rxc->ste_ptr = NULL; 1283 rxc->ste_mbuf = NULL; 1284 rxc->ste_next = NULL; 1285 rxc->ste_map = NULL; 1286 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1287 &rxc->ste_map); 1288 if (error != 0) { 1289 device_printf(sc->ste_dev, 1290 "could not create Rx dmamap.\n"); 1291 goto fail; 1292 } 1293 } 1294 1295 fail: 1296 return (error); 1297 } 1298 1299 static void 1300 ste_dma_free(struct ste_softc *sc) 1301 { 1302 struct ste_chain *txc; 1303 struct ste_chain_onefrag *rxc; 1304 int i; 1305 1306 /* Tx buffers. */ 1307 if (sc->ste_cdata.ste_tx_tag != NULL) { 1308 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1309 txc = &sc->ste_cdata.ste_tx_chain[i]; 1310 if (txc->ste_map != NULL) { 1311 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1312 txc->ste_map); 1313 txc->ste_map = NULL; 1314 } 1315 } 1316 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1317 sc->ste_cdata.ste_tx_tag = NULL; 1318 } 1319 /* Rx buffers. */ 1320 if (sc->ste_cdata.ste_rx_tag != NULL) { 1321 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1322 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1323 if (rxc->ste_map != NULL) { 1324 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1325 rxc->ste_map); 1326 rxc->ste_map = NULL; 1327 } 1328 } 1329 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1330 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1331 sc->ste_cdata.ste_rx_sparemap); 1332 sc->ste_cdata.ste_rx_sparemap = NULL; 1333 } 1334 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1335 sc->ste_cdata.ste_rx_tag = NULL; 1336 } 1337 /* Tx descriptor list. */ 1338 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1339 if (sc->ste_ldata.ste_tx_list_paddr != 0) 1340 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1341 sc->ste_cdata.ste_tx_list_map); 1342 if (sc->ste_ldata.ste_tx_list != NULL) 1343 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1344 sc->ste_ldata.ste_tx_list, 1345 sc->ste_cdata.ste_tx_list_map); 1346 sc->ste_ldata.ste_tx_list = NULL; 1347 sc->ste_ldata.ste_tx_list_paddr = 0; 1348 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1349 sc->ste_cdata.ste_tx_list_tag = NULL; 1350 } 1351 /* Rx descriptor list. */ 1352 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1353 if (sc->ste_ldata.ste_rx_list_paddr != 0) 1354 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1355 sc->ste_cdata.ste_rx_list_map); 1356 if (sc->ste_ldata.ste_rx_list != NULL) 1357 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1358 sc->ste_ldata.ste_rx_list, 1359 sc->ste_cdata.ste_rx_list_map); 1360 sc->ste_ldata.ste_rx_list = NULL; 1361 sc->ste_ldata.ste_rx_list_paddr = 0; 1362 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1363 sc->ste_cdata.ste_rx_list_tag = NULL; 1364 } 1365 if (sc->ste_cdata.ste_parent_tag != NULL) { 1366 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1367 sc->ste_cdata.ste_parent_tag = NULL; 1368 } 1369 } 1370 1371 static int 1372 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1373 { 1374 struct mbuf *m; 1375 bus_dma_segment_t segs[1]; 1376 bus_dmamap_t map; 1377 int error, nsegs; 1378 1379 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1380 if (m == NULL) 1381 return (ENOBUFS); 1382 m->m_len = m->m_pkthdr.len = MCLBYTES; 1383 m_adj(m, ETHER_ALIGN); 1384 1385 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1386 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1387 m_freem(m); 1388 return (error); 1389 } 1390 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1391 1392 if (rxc->ste_mbuf != NULL) { 1393 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1394 BUS_DMASYNC_POSTREAD); 1395 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1396 } 1397 map = rxc->ste_map; 1398 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1399 sc->ste_cdata.ste_rx_sparemap = map; 1400 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1401 BUS_DMASYNC_PREREAD); 1402 rxc->ste_mbuf = m; 1403 rxc->ste_ptr->ste_status = 0; 1404 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1405 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1406 STE_FRAG_LAST); 1407 return (0); 1408 } 1409 1410 static int 1411 ste_init_rx_list(struct ste_softc *sc) 1412 { 1413 struct ste_chain_data *cd; 1414 struct ste_list_data *ld; 1415 int error, i; 1416 1417 sc->ste_int_rx_act = 0; 1418 cd = &sc->ste_cdata; 1419 ld = &sc->ste_ldata; 1420 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1421 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1422 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1423 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1424 if (error != 0) 1425 return (error); 1426 if (i == (STE_RX_LIST_CNT - 1)) { 1427 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1428 ld->ste_rx_list[i].ste_next = 1429 htole32(ld->ste_rx_list_paddr + 1430 (sizeof(struct ste_desc_onefrag) * 0)); 1431 } else { 1432 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1433 ld->ste_rx_list[i].ste_next = 1434 htole32(ld->ste_rx_list_paddr + 1435 (sizeof(struct ste_desc_onefrag) * (i + 1))); 1436 } 1437 } 1438 1439 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1440 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1441 sc->ste_cdata.ste_rx_list_map, 1442 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1443 1444 return (0); 1445 } 1446 1447 static void 1448 ste_init_tx_list(struct ste_softc *sc) 1449 { 1450 struct ste_chain_data *cd; 1451 struct ste_list_data *ld; 1452 int i; 1453 1454 cd = &sc->ste_cdata; 1455 ld = &sc->ste_ldata; 1456 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1457 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1458 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1459 cd->ste_tx_chain[i].ste_mbuf = NULL; 1460 if (i == (STE_TX_LIST_CNT - 1)) { 1461 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1462 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1463 ld->ste_tx_list_paddr + 1464 (sizeof(struct ste_desc) * 0))); 1465 } else { 1466 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1467 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1468 ld->ste_tx_list_paddr + 1469 (sizeof(struct ste_desc) * (i + 1)))); 1470 } 1471 } 1472 1473 cd->ste_last_tx = NULL; 1474 cd->ste_tx_prod = 0; 1475 cd->ste_tx_cons = 0; 1476 cd->ste_tx_cnt = 0; 1477 1478 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1479 sc->ste_cdata.ste_tx_list_map, 1480 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1481 } 1482 1483 static void 1484 ste_init(void *xsc) 1485 { 1486 struct ste_softc *sc; 1487 1488 sc = xsc; 1489 STE_LOCK(sc); 1490 ste_init_locked(sc); 1491 STE_UNLOCK(sc); 1492 } 1493 1494 static void 1495 ste_init_locked(struct ste_softc *sc) 1496 { 1497 if_t ifp; 1498 struct mii_data *mii; 1499 uint8_t val; 1500 int i; 1501 1502 STE_LOCK_ASSERT(sc); 1503 ifp = sc->ste_ifp; 1504 mii = device_get_softc(sc->ste_miibus); 1505 1506 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1507 return; 1508 1509 ste_stop(sc); 1510 /* Reset the chip to a known state. */ 1511 ste_reset(sc); 1512 1513 /* Init our MAC address */ 1514 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1515 CSR_WRITE_2(sc, STE_PAR0 + i, 1516 ((if_getlladdr(sc->ste_ifp)[i] & 0xff) | 1517 if_getlladdr(sc->ste_ifp)[i + 1] << 8)); 1518 } 1519 1520 /* Init RX list */ 1521 if (ste_init_rx_list(sc) != 0) { 1522 device_printf(sc->ste_dev, 1523 "initialization failed: no memory for RX buffers\n"); 1524 ste_stop(sc); 1525 return; 1526 } 1527 1528 /* Set RX polling interval */ 1529 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1530 1531 /* Init TX descriptors */ 1532 ste_init_tx_list(sc); 1533 1534 /* Clear and disable WOL. */ 1535 val = CSR_READ_1(sc, STE_WAKE_EVENT); 1536 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 1537 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 1538 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 1539 1540 /* Set the TX freethresh value */ 1541 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1542 1543 /* Set the TX start threshold for best performance. */ 1544 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1545 1546 /* Set the TX reclaim threshold. */ 1547 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1548 1549 /* Accept VLAN length packets */ 1550 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1551 1552 /* Set up the RX filter. */ 1553 ste_rxfilter(sc); 1554 1555 /* Load the address of the RX list. */ 1556 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1557 ste_wait(sc); 1558 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1559 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1560 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1561 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1562 1563 /* Set TX polling interval(defer until we TX first packet). */ 1564 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1565 1566 /* Load address of the TX list */ 1567 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1568 ste_wait(sc); 1569 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1570 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1571 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1572 ste_wait(sc); 1573 /* Select 3.2us timer. */ 1574 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED | 1575 STE_DMACTL_COUNTDOWN_MODE); 1576 1577 /* Enable receiver and transmitter */ 1578 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1579 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1580 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1581 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1582 1583 /* Enable stats counters. */ 1584 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1585 /* Clear stats counters. */ 1586 ste_stats_clear(sc); 1587 1588 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1589 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1590 #ifdef DEVICE_POLLING 1591 /* Disable interrupts if we are polling. */ 1592 if (if_getcapenable(ifp) & IFCAP_POLLING) 1593 CSR_WRITE_2(sc, STE_IMR, 0); 1594 else 1595 #endif 1596 /* Enable interrupts. */ 1597 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1598 1599 sc->ste_flags &= ~STE_FLAG_LINK; 1600 /* Switch to the current media. */ 1601 mii_mediachg(mii); 1602 1603 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1604 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1605 1606 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1607 } 1608 1609 static void 1610 ste_stop(struct ste_softc *sc) 1611 { 1612 if_t ifp; 1613 struct ste_chain_onefrag *cur_rx; 1614 struct ste_chain *cur_tx; 1615 uint32_t val; 1616 int i; 1617 1618 STE_LOCK_ASSERT(sc); 1619 ifp = sc->ste_ifp; 1620 1621 callout_stop(&sc->ste_callout); 1622 sc->ste_timer = 0; 1623 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)); 1624 1625 CSR_WRITE_2(sc, STE_IMR, 0); 1626 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1627 /* Stop pending DMA. */ 1628 val = CSR_READ_4(sc, STE_DMACTL); 1629 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1630 CSR_WRITE_4(sc, STE_DMACTL, val); 1631 ste_wait(sc); 1632 /* Disable auto-polling. */ 1633 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1634 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1635 /* Nullify DMA address to stop any further DMA. */ 1636 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1637 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1638 /* Stop TX/RX MAC. */ 1639 val = CSR_READ_2(sc, STE_MACCTL1); 1640 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1641 STE_MACCTL1_STATS_DISABLE; 1642 CSR_WRITE_2(sc, STE_MACCTL1, val); 1643 for (i = 0; i < STE_TIMEOUT; i++) { 1644 DELAY(10); 1645 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1646 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1647 break; 1648 } 1649 if (i == STE_TIMEOUT) 1650 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1651 /* Acknowledge any pending interrupts. */ 1652 CSR_READ_2(sc, STE_ISR_ACK); 1653 ste_stats_update(sc); 1654 1655 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1656 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1657 if (cur_rx->ste_mbuf != NULL) { 1658 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1659 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1660 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1661 cur_rx->ste_map); 1662 m_freem(cur_rx->ste_mbuf); 1663 cur_rx->ste_mbuf = NULL; 1664 } 1665 } 1666 1667 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1668 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1669 if (cur_tx->ste_mbuf != NULL) { 1670 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1671 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1672 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1673 cur_tx->ste_map); 1674 m_freem(cur_tx->ste_mbuf); 1675 cur_tx->ste_mbuf = NULL; 1676 } 1677 } 1678 } 1679 1680 static void 1681 ste_reset(struct ste_softc *sc) 1682 { 1683 uint32_t ctl; 1684 int i; 1685 1686 ctl = CSR_READ_4(sc, STE_ASICCTL); 1687 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET | 1688 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET | 1689 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET | 1690 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET | 1691 STE_ASICCTL_EXTRESET_RESET; 1692 CSR_WRITE_4(sc, STE_ASICCTL, ctl); 1693 CSR_READ_4(sc, STE_ASICCTL); 1694 /* 1695 * Due to the need of accessing EEPROM controller can take 1696 * up to 1ms to complete the global reset. 1697 */ 1698 DELAY(1000); 1699 1700 for (i = 0; i < STE_TIMEOUT; i++) { 1701 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1702 break; 1703 DELAY(10); 1704 } 1705 1706 if (i == STE_TIMEOUT) 1707 device_printf(sc->ste_dev, "global reset never completed\n"); 1708 } 1709 1710 static void 1711 ste_restart_tx(struct ste_softc *sc) 1712 { 1713 uint16_t mac; 1714 int i; 1715 1716 for (i = 0; i < STE_TIMEOUT; i++) { 1717 mac = CSR_READ_2(sc, STE_MACCTL1); 1718 mac |= STE_MACCTL1_TX_ENABLE; 1719 CSR_WRITE_2(sc, STE_MACCTL1, mac); 1720 mac = CSR_READ_2(sc, STE_MACCTL1); 1721 if ((mac & STE_MACCTL1_TX_ENABLED) != 0) 1722 break; 1723 DELAY(10); 1724 } 1725 1726 if (i == STE_TIMEOUT) 1727 device_printf(sc->ste_dev, "starting Tx failed"); 1728 } 1729 1730 static int 1731 ste_ioctl(if_t ifp, u_long command, caddr_t data) 1732 { 1733 struct ste_softc *sc; 1734 struct ifreq *ifr; 1735 struct mii_data *mii; 1736 int error = 0, mask; 1737 1738 sc = if_getsoftc(ifp); 1739 ifr = (struct ifreq *)data; 1740 1741 switch (command) { 1742 case SIOCSIFFLAGS: 1743 STE_LOCK(sc); 1744 if ((if_getflags(ifp) & IFF_UP) != 0) { 1745 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1746 ((if_getflags(ifp) ^ sc->ste_if_flags) & 1747 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1748 ste_rxfilter(sc); 1749 else 1750 ste_init_locked(sc); 1751 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1752 ste_stop(sc); 1753 sc->ste_if_flags = if_getflags(ifp); 1754 STE_UNLOCK(sc); 1755 break; 1756 case SIOCADDMULTI: 1757 case SIOCDELMULTI: 1758 STE_LOCK(sc); 1759 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1760 ste_rxfilter(sc); 1761 STE_UNLOCK(sc); 1762 break; 1763 case SIOCGIFMEDIA: 1764 case SIOCSIFMEDIA: 1765 mii = device_get_softc(sc->ste_miibus); 1766 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1767 break; 1768 case SIOCSIFCAP: 1769 STE_LOCK(sc); 1770 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1771 #ifdef DEVICE_POLLING 1772 if ((mask & IFCAP_POLLING) != 0 && 1773 (IFCAP_POLLING & if_getcapabilities(ifp)) != 0) { 1774 if_togglecapenable(ifp, IFCAP_POLLING); 1775 if ((IFCAP_POLLING & if_getcapenable(ifp)) != 0) { 1776 error = ether_poll_register(ste_poll, ifp); 1777 if (error != 0) { 1778 STE_UNLOCK(sc); 1779 break; 1780 } 1781 /* Disable interrupts. */ 1782 CSR_WRITE_2(sc, STE_IMR, 0); 1783 } else { 1784 error = ether_poll_deregister(ifp); 1785 /* Enable interrupts. */ 1786 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1787 } 1788 } 1789 #endif /* DEVICE_POLLING */ 1790 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1791 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1792 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1793 STE_UNLOCK(sc); 1794 break; 1795 default: 1796 error = ether_ioctl(ifp, command, data); 1797 break; 1798 } 1799 1800 return (error); 1801 } 1802 1803 static int 1804 ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1805 { 1806 struct ste_frag *frag; 1807 struct mbuf *m; 1808 struct ste_desc *desc; 1809 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1810 int error, i, nsegs; 1811 1812 STE_LOCK_ASSERT(sc); 1813 M_ASSERTPKTHDR((*m_head)); 1814 1815 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1816 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1817 if (error == EFBIG) { 1818 m = m_collapse(*m_head, M_NOWAIT, STE_MAXFRAGS); 1819 if (m == NULL) { 1820 m_freem(*m_head); 1821 *m_head = NULL; 1822 return (ENOMEM); 1823 } 1824 *m_head = m; 1825 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1826 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1827 if (error != 0) { 1828 m_freem(*m_head); 1829 *m_head = NULL; 1830 return (error); 1831 } 1832 } else if (error != 0) 1833 return (error); 1834 if (nsegs == 0) { 1835 m_freem(*m_head); 1836 *m_head = NULL; 1837 return (EIO); 1838 } 1839 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1840 BUS_DMASYNC_PREWRITE); 1841 1842 desc = txc->ste_ptr; 1843 for (i = 0; i < nsegs; i++) { 1844 frag = &desc->ste_frags[i]; 1845 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1846 frag->ste_len = htole32(txsegs[i].ds_len); 1847 } 1848 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1849 /* 1850 * Because we use Tx polling we can't chain multiple 1851 * Tx descriptors here. Otherwise we race with controller. 1852 */ 1853 desc->ste_next = 0; 1854 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0) 1855 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | 1856 STE_TXCTL_DMAINTR); 1857 else 1858 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS); 1859 txc->ste_mbuf = *m_head; 1860 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1861 sc->ste_cdata.ste_tx_cnt++; 1862 1863 return (0); 1864 } 1865 1866 static void 1867 ste_start(if_t ifp) 1868 { 1869 struct ste_softc *sc; 1870 1871 sc = if_getsoftc(ifp); 1872 STE_LOCK(sc); 1873 ste_start_locked(ifp); 1874 STE_UNLOCK(sc); 1875 } 1876 1877 static void 1878 ste_start_locked(if_t ifp) 1879 { 1880 struct ste_softc *sc; 1881 struct ste_chain *cur_tx; 1882 struct mbuf *m_head = NULL; 1883 int enq; 1884 1885 sc = if_getsoftc(ifp); 1886 STE_LOCK_ASSERT(sc); 1887 1888 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1889 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1890 return; 1891 1892 for (enq = 0; !if_sendq_empty(ifp);) { 1893 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1894 /* 1895 * Controller may have cached copy of the last used 1896 * next ptr so we have to reserve one TFD to avoid 1897 * TFD overruns. 1898 */ 1899 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1900 break; 1901 } 1902 m_head = if_dequeue(ifp); 1903 if (m_head == NULL) 1904 break; 1905 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1906 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1907 if (m_head == NULL) 1908 break; 1909 if_sendq_prepend(ifp, m_head); 1910 break; 1911 } 1912 if (sc->ste_cdata.ste_last_tx == NULL) { 1913 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1914 sc->ste_cdata.ste_tx_list_map, 1915 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1916 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1917 ste_wait(sc); 1918 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1919 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1920 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1921 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1922 ste_wait(sc); 1923 } else { 1924 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1925 sc->ste_cdata.ste_last_tx->ste_phys; 1926 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1927 sc->ste_cdata.ste_tx_list_map, 1928 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1929 } 1930 sc->ste_cdata.ste_last_tx = cur_tx; 1931 1932 enq++; 1933 /* 1934 * If there's a BPF listener, bounce a copy of this frame 1935 * to him. 1936 */ 1937 BPF_MTAP(ifp, m_head); 1938 } 1939 1940 if (enq > 0) 1941 sc->ste_timer = STE_TX_TIMEOUT; 1942 } 1943 1944 static void 1945 ste_watchdog(struct ste_softc *sc) 1946 { 1947 if_t ifp; 1948 1949 ifp = sc->ste_ifp; 1950 STE_LOCK_ASSERT(sc); 1951 1952 if (sc->ste_timer == 0 || --sc->ste_timer) 1953 return; 1954 1955 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1956 if_printf(ifp, "watchdog timeout\n"); 1957 1958 ste_txeof(sc); 1959 ste_txeoc(sc); 1960 ste_rxeof(sc, -1); 1961 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1962 ste_init_locked(sc); 1963 1964 if (!if_sendq_empty(ifp)) 1965 ste_start_locked(ifp); 1966 } 1967 1968 static int 1969 ste_shutdown(device_t dev) 1970 { 1971 1972 return (ste_suspend(dev)); 1973 } 1974 1975 static int 1976 ste_suspend(device_t dev) 1977 { 1978 struct ste_softc *sc; 1979 1980 sc = device_get_softc(dev); 1981 1982 STE_LOCK(sc); 1983 ste_stop(sc); 1984 ste_setwol(sc); 1985 STE_UNLOCK(sc); 1986 1987 return (0); 1988 } 1989 1990 static int 1991 ste_resume(device_t dev) 1992 { 1993 struct ste_softc *sc; 1994 if_t ifp; 1995 int pmc; 1996 uint16_t pmstat; 1997 1998 sc = device_get_softc(dev); 1999 STE_LOCK(sc); 2000 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) == 0) { 2001 /* Disable PME and clear PME status. */ 2002 pmstat = pci_read_config(sc->ste_dev, 2003 pmc + PCIR_POWER_STATUS, 2); 2004 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2005 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2006 pci_write_config(sc->ste_dev, 2007 pmc + PCIR_POWER_STATUS, pmstat, 2); 2008 } 2009 } 2010 ifp = sc->ste_ifp; 2011 if ((if_getflags(ifp) & IFF_UP) != 0) { 2012 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2013 ste_init_locked(sc); 2014 } 2015 STE_UNLOCK(sc); 2016 2017 return (0); 2018 } 2019 2020 #define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2021 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2022 #define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2023 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2024 2025 static void 2026 ste_sysctl_node(struct ste_softc *sc) 2027 { 2028 struct sysctl_ctx_list *ctx; 2029 struct sysctl_oid_list *child, *parent; 2030 struct sysctl_oid *tree; 2031 struct ste_hw_stats *stats; 2032 2033 stats = &sc->ste_stats; 2034 ctx = device_get_sysctl_ctx(sc->ste_dev); 2035 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev)); 2036 2037 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod", 2038 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation"); 2039 /* Pull in device tunables. */ 2040 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT; 2041 resource_int_value(device_get_name(sc->ste_dev), 2042 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod); 2043 2044 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 2045 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "STE statistics"); 2046 parent = SYSCTL_CHILDREN(tree); 2047 2048 /* Rx statistics. */ 2049 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2050 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 2051 child = SYSCTL_CHILDREN(tree); 2052 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2053 &stats->rx_bytes, "Good octets"); 2054 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2055 &stats->rx_frames, "Good frames"); 2056 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2057 &stats->rx_bcast_frames, "Good broadcast frames"); 2058 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2059 &stats->rx_mcast_frames, "Good multicast frames"); 2060 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames", 2061 &stats->rx_lost_frames, "Lost frames"); 2062 2063 /* Tx statistics. */ 2064 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2065 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 2066 child = SYSCTL_CHILDREN(tree); 2067 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2068 &stats->tx_bytes, "Good octets"); 2069 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2070 &stats->tx_frames, "Good frames"); 2071 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2072 &stats->tx_bcast_frames, "Good broadcast frames"); 2073 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2074 &stats->tx_mcast_frames, "Good multicast frames"); 2075 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs", 2076 &stats->tx_carrsense_errs, "Carrier sense errors"); 2077 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 2078 &stats->tx_single_colls, "Single collisions"); 2079 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 2080 &stats->tx_multi_colls, "Multiple collisions"); 2081 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2082 &stats->tx_late_colls, "Late collisions"); 2083 STE_SYSCTL_STAT_ADD32(ctx, child, "defers", 2084 &stats->tx_frames_defered, "Frames with deferrals"); 2085 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 2086 &stats->tx_excess_defers, "Frames with excessive derferrals"); 2087 STE_SYSCTL_STAT_ADD32(ctx, child, "abort", 2088 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 2089 } 2090 2091 #undef STE_SYSCTL_STAT_ADD32 2092 #undef STE_SYSCTL_STAT_ADD64 2093 2094 static void 2095 ste_setwol(struct ste_softc *sc) 2096 { 2097 if_t ifp; 2098 uint16_t pmstat; 2099 uint8_t val; 2100 int pmc; 2101 2102 STE_LOCK_ASSERT(sc); 2103 2104 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) != 0) { 2105 /* Disable WOL. */ 2106 CSR_READ_1(sc, STE_WAKE_EVENT); 2107 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0); 2108 return; 2109 } 2110 2111 ifp = sc->ste_ifp; 2112 val = CSR_READ_1(sc, STE_WAKE_EVENT); 2113 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 2114 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 2115 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2116 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB; 2117 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 2118 /* Request PME. */ 2119 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2); 2120 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2121 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2122 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2123 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2124 } 2125