1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 #ifdef HAVE_KERNEL_OPTION_HEADERS 37 #include "opt_device_polling.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/malloc.h> 47 #include <sys/mbuf.h> 48 #include <sys/module.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 54 #include <net/bpf.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_arp.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #include <machine/bus.h> 65 #include <machine/resource.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/mii_bitbang.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ste/if_stereg.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 MODULE_DEPEND(ste, pci, 1, 1, 1); 80 MODULE_DEPEND(ste, ether, 1, 1, 1); 81 MODULE_DEPEND(ste, miibus, 1, 1, 1); 82 83 /* Define to show Tx error status. */ 84 #define STE_SHOW_TXERRORS 85 86 /* 87 * Various supported device vendors/types and their names. 88 */ 89 static const struct ste_type ste_devs[] = { 90 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 91 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 92 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 93 { 0, 0, NULL } 94 }; 95 96 static int ste_attach(device_t); 97 static int ste_detach(device_t); 98 static int ste_probe(device_t); 99 static int ste_resume(device_t); 100 static int ste_shutdown(device_t); 101 static int ste_suspend(device_t); 102 103 static int ste_dma_alloc(struct ste_softc *); 104 static void ste_dma_free(struct ste_softc *); 105 static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 106 static int ste_eeprom_wait(struct ste_softc *); 107 static int ste_encap(struct ste_softc *, struct mbuf **, 108 struct ste_chain *); 109 static int ste_ifmedia_upd(if_t); 110 static void ste_ifmedia_sts(if_t, struct ifmediareq *); 111 static void ste_init(void *); 112 static void ste_init_locked(struct ste_softc *); 113 static int ste_init_rx_list(struct ste_softc *); 114 static void ste_init_tx_list(struct ste_softc *); 115 static void ste_intr(void *); 116 static int ste_ioctl(if_t, u_long, caddr_t); 117 static uint32_t ste_mii_bitbang_read(device_t); 118 static void ste_mii_bitbang_write(device_t, uint32_t); 119 static int ste_miibus_readreg(device_t, int, int); 120 static void ste_miibus_statchg(device_t); 121 static int ste_miibus_writereg(device_t, int, int, int); 122 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 123 static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int); 124 static void ste_reset(struct ste_softc *); 125 static void ste_restart_tx(struct ste_softc *); 126 static int ste_rxeof(struct ste_softc *, int); 127 static void ste_rxfilter(struct ste_softc *); 128 static void ste_setwol(struct ste_softc *); 129 static void ste_start(if_t); 130 static void ste_start_locked(if_t); 131 static void ste_stats_clear(struct ste_softc *); 132 static void ste_stats_update(struct ste_softc *); 133 static void ste_stop(struct ste_softc *); 134 static void ste_sysctl_node(struct ste_softc *); 135 static void ste_tick(void *); 136 static void ste_txeoc(struct ste_softc *); 137 static void ste_txeof(struct ste_softc *); 138 static void ste_wait(struct ste_softc *); 139 static void ste_watchdog(struct ste_softc *); 140 141 /* 142 * MII bit-bang glue 143 */ 144 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 145 ste_mii_bitbang_read, 146 ste_mii_bitbang_write, 147 { 148 STE_PHYCTL_MDATA, /* MII_BIT_MDO */ 149 STE_PHYCTL_MDATA, /* MII_BIT_MDI */ 150 STE_PHYCTL_MCLK, /* MII_BIT_MDC */ 151 STE_PHYCTL_MDIR, /* MII_BIT_DIR_HOST_PHY */ 152 0, /* MII_BIT_DIR_PHY_HOST */ 153 } 154 }; 155 156 static device_method_t ste_methods[] = { 157 /* Device interface */ 158 DEVMETHOD(device_probe, ste_probe), 159 DEVMETHOD(device_attach, ste_attach), 160 DEVMETHOD(device_detach, ste_detach), 161 DEVMETHOD(device_shutdown, ste_shutdown), 162 DEVMETHOD(device_suspend, ste_suspend), 163 DEVMETHOD(device_resume, ste_resume), 164 165 /* MII interface */ 166 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 167 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 168 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 169 170 DEVMETHOD_END 171 }; 172 173 static driver_t ste_driver = { 174 "ste", 175 ste_methods, 176 sizeof(struct ste_softc) 177 }; 178 179 DRIVER_MODULE(ste, pci, ste_driver, 0, 0); 180 DRIVER_MODULE(miibus, ste, miibus_driver, 0, 0); 181 182 #define STE_SETBIT4(sc, reg, x) \ 183 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 184 185 #define STE_CLRBIT4(sc, reg, x) \ 186 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 187 188 #define STE_SETBIT2(sc, reg, x) \ 189 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 190 191 #define STE_CLRBIT2(sc, reg, x) \ 192 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 193 194 #define STE_SETBIT1(sc, reg, x) \ 195 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 196 197 #define STE_CLRBIT1(sc, reg, x) \ 198 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 199 200 /* 201 * Read the MII serial port for the MII bit-bang module. 202 */ 203 static uint32_t 204 ste_mii_bitbang_read(device_t dev) 205 { 206 struct ste_softc *sc; 207 uint32_t val; 208 209 sc = device_get_softc(dev); 210 211 val = CSR_READ_1(sc, STE_PHYCTL); 212 CSR_BARRIER(sc, STE_PHYCTL, 1, 213 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 214 215 return (val); 216 } 217 218 /* 219 * Write the MII serial port for the MII bit-bang module. 220 */ 221 static void 222 ste_mii_bitbang_write(device_t dev, uint32_t val) 223 { 224 struct ste_softc *sc; 225 226 sc = device_get_softc(dev); 227 228 CSR_WRITE_1(sc, STE_PHYCTL, val); 229 CSR_BARRIER(sc, STE_PHYCTL, 1, 230 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 231 } 232 233 static int 234 ste_miibus_readreg(device_t dev, int phy, int reg) 235 { 236 237 return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg)); 238 } 239 240 static int 241 ste_miibus_writereg(device_t dev, int phy, int reg, int data) 242 { 243 244 mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data); 245 246 return (0); 247 } 248 249 static void 250 ste_miibus_statchg(device_t dev) 251 { 252 struct ste_softc *sc; 253 struct mii_data *mii; 254 if_t ifp; 255 uint16_t cfg; 256 257 sc = device_get_softc(dev); 258 259 mii = device_get_softc(sc->ste_miibus); 260 ifp = sc->ste_ifp; 261 if (mii == NULL || ifp == NULL || 262 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 263 return; 264 265 sc->ste_flags &= ~STE_FLAG_LINK; 266 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 267 (IFM_ACTIVE | IFM_AVALID)) { 268 switch (IFM_SUBTYPE(mii->mii_media_active)) { 269 case IFM_10_T: 270 case IFM_100_TX: 271 case IFM_100_FX: 272 case IFM_100_T4: 273 sc->ste_flags |= STE_FLAG_LINK; 274 default: 275 break; 276 } 277 } 278 279 /* Program MACs with resolved speed/duplex/flow-control. */ 280 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 281 cfg = CSR_READ_2(sc, STE_MACCTL0); 282 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 283 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 284 /* 285 * ST201 data sheet says driver should enable receiving 286 * MAC control frames bit of receive mode register to 287 * receive flow-control frames but the register has no 288 * such bits. In addition the controller has no ability 289 * to send pause frames so it should be handled in 290 * driver. Implementing pause timer handling in driver 291 * layer is not trivial, so don't enable flow-control 292 * here. 293 */ 294 cfg |= STE_MACCTL0_FULLDUPLEX; 295 } 296 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 297 } 298 } 299 300 static int 301 ste_ifmedia_upd(if_t ifp) 302 { 303 struct ste_softc *sc; 304 struct mii_data *mii; 305 struct mii_softc *miisc; 306 int error; 307 308 sc = if_getsoftc(ifp); 309 STE_LOCK(sc); 310 mii = device_get_softc(sc->ste_miibus); 311 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 312 PHY_RESET(miisc); 313 error = mii_mediachg(mii); 314 STE_UNLOCK(sc); 315 316 return (error); 317 } 318 319 static void 320 ste_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 321 { 322 struct ste_softc *sc; 323 struct mii_data *mii; 324 325 sc = if_getsoftc(ifp); 326 mii = device_get_softc(sc->ste_miibus); 327 328 STE_LOCK(sc); 329 if ((if_getflags(ifp) & IFF_UP) == 0) { 330 STE_UNLOCK(sc); 331 return; 332 } 333 mii_pollstat(mii); 334 ifmr->ifm_active = mii->mii_media_active; 335 ifmr->ifm_status = mii->mii_media_status; 336 STE_UNLOCK(sc); 337 } 338 339 static void 340 ste_wait(struct ste_softc *sc) 341 { 342 int i; 343 344 for (i = 0; i < STE_TIMEOUT; i++) { 345 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 346 break; 347 DELAY(1); 348 } 349 350 if (i == STE_TIMEOUT) 351 device_printf(sc->ste_dev, "command never completed!\n"); 352 } 353 354 /* 355 * The EEPROM is slow: give it time to come ready after issuing 356 * it a command. 357 */ 358 static int 359 ste_eeprom_wait(struct ste_softc *sc) 360 { 361 int i; 362 363 DELAY(1000); 364 365 for (i = 0; i < 100; i++) { 366 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 367 DELAY(1000); 368 else 369 break; 370 } 371 372 if (i == 100) { 373 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 374 return (1); 375 } 376 377 return (0); 378 } 379 380 /* 381 * Read a sequence of words from the EEPROM. Note that ethernet address 382 * data is stored in the EEPROM in network byte order. 383 */ 384 static int 385 ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt) 386 { 387 int err = 0, i; 388 389 if (ste_eeprom_wait(sc)) 390 return (1); 391 392 for (i = 0; i < cnt; i++) { 393 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 394 err = ste_eeprom_wait(sc); 395 if (err) 396 break; 397 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA)); 398 dest++; 399 } 400 401 return (err ? 1 : 0); 402 } 403 404 static u_int 405 ste_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 406 { 407 uint32_t *hashes = arg; 408 int h; 409 410 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0x3F; 411 if (h < 32) 412 hashes[0] |= (1 << h); 413 else 414 hashes[1] |= (1 << (h - 32)); 415 416 return (1); 417 } 418 419 static void 420 ste_rxfilter(struct ste_softc *sc) 421 { 422 if_t ifp; 423 uint32_t hashes[2] = { 0, 0 }; 424 uint8_t rxcfg; 425 426 STE_LOCK_ASSERT(sc); 427 428 ifp = sc->ste_ifp; 429 rxcfg = CSR_READ_1(sc, STE_RX_MODE); 430 rxcfg |= STE_RXMODE_UNICAST; 431 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH | 432 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC); 433 if (if_getflags(ifp) & IFF_BROADCAST) 434 rxcfg |= STE_RXMODE_BROADCAST; 435 if ((if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 436 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 437 rxcfg |= STE_RXMODE_ALLMULTI; 438 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 439 rxcfg |= STE_RXMODE_PROMISC; 440 goto chipit; 441 } 442 443 rxcfg |= STE_RXMODE_MULTIHASH; 444 /* Now program new ones. */ 445 if_foreach_llmaddr(ifp, ste_hash_maddr, hashes); 446 447 chipit: 448 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 449 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 450 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 451 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 452 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg); 453 CSR_READ_1(sc, STE_RX_MODE); 454 } 455 456 #ifdef DEVICE_POLLING 457 static poll_handler_t ste_poll, ste_poll_locked; 458 459 static int 460 ste_poll(if_t ifp, enum poll_cmd cmd, int count) 461 { 462 struct ste_softc *sc = if_getsoftc(ifp); 463 int rx_npkts = 0; 464 465 STE_LOCK(sc); 466 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 467 rx_npkts = ste_poll_locked(ifp, cmd, count); 468 STE_UNLOCK(sc); 469 return (rx_npkts); 470 } 471 472 static int 473 ste_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 474 { 475 struct ste_softc *sc = if_getsoftc(ifp); 476 int rx_npkts; 477 478 STE_LOCK_ASSERT(sc); 479 480 rx_npkts = ste_rxeof(sc, count); 481 ste_txeof(sc); 482 ste_txeoc(sc); 483 if (!if_sendq_empty(ifp)) 484 ste_start_locked(ifp); 485 486 if (cmd == POLL_AND_CHECK_STATUS) { 487 uint16_t status; 488 489 status = CSR_READ_2(sc, STE_ISR_ACK); 490 491 if (status & STE_ISR_STATS_OFLOW) 492 ste_stats_update(sc); 493 494 if (status & STE_ISR_HOSTERR) { 495 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 496 ste_init_locked(sc); 497 } 498 } 499 return (rx_npkts); 500 } 501 #endif /* DEVICE_POLLING */ 502 503 static void 504 ste_intr(void *xsc) 505 { 506 struct ste_softc *sc; 507 if_t ifp; 508 uint16_t intrs, status; 509 510 sc = xsc; 511 STE_LOCK(sc); 512 ifp = sc->ste_ifp; 513 514 #ifdef DEVICE_POLLING 515 if (if_getcapenable(ifp) & IFCAP_POLLING) { 516 STE_UNLOCK(sc); 517 return; 518 } 519 #endif 520 /* Reading STE_ISR_ACK clears STE_IMR register. */ 521 status = CSR_READ_2(sc, STE_ISR_ACK); 522 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 523 STE_UNLOCK(sc); 524 return; 525 } 526 527 intrs = STE_INTRS; 528 if (status == 0xFFFF || (status & intrs) == 0) 529 goto done; 530 531 if (sc->ste_int_rx_act > 0) { 532 status &= ~STE_ISR_RX_DMADONE; 533 intrs &= ~STE_IMR_RX_DMADONE; 534 } 535 536 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) { 537 ste_rxeof(sc, -1); 538 /* 539 * The controller has no ability to Rx interrupt 540 * moderation feature. Receiving 64 bytes frames 541 * from wire generates too many interrupts which in 542 * turn make system useless to process other useful 543 * things. Fortunately ST201 supports single shot 544 * timer so use the timer to implement Rx interrupt 545 * moderation in driver. This adds more register 546 * access but it greatly reduces number of Rx 547 * interrupts under high network load. 548 */ 549 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 550 (sc->ste_int_rx_mod != 0)) { 551 if ((status & STE_ISR_RX_DMADONE) != 0) { 552 CSR_WRITE_2(sc, STE_COUNTDOWN, 553 STE_TIMER_USECS(sc->ste_int_rx_mod)); 554 intrs &= ~STE_IMR_RX_DMADONE; 555 sc->ste_int_rx_act = 1; 556 } else { 557 intrs |= STE_IMR_RX_DMADONE; 558 sc->ste_int_rx_act = 0; 559 } 560 } 561 } 562 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 563 if ((status & STE_ISR_TX_DMADONE) != 0) 564 ste_txeof(sc); 565 if ((status & STE_ISR_TX_DONE) != 0) 566 ste_txeoc(sc); 567 if ((status & STE_ISR_STATS_OFLOW) != 0) 568 ste_stats_update(sc); 569 if ((status & STE_ISR_HOSTERR) != 0) { 570 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 571 ste_init_locked(sc); 572 STE_UNLOCK(sc); 573 return; 574 } 575 if (!if_sendq_empty(ifp)) 576 ste_start_locked(ifp); 577 done: 578 /* Re-enable interrupts */ 579 CSR_WRITE_2(sc, STE_IMR, intrs); 580 } 581 STE_UNLOCK(sc); 582 } 583 584 /* 585 * A frame has been uploaded: pass the resulting mbuf chain up to 586 * the higher level protocols. 587 */ 588 static int 589 ste_rxeof(struct ste_softc *sc, int count) 590 { 591 struct mbuf *m; 592 if_t ifp; 593 struct ste_chain_onefrag *cur_rx; 594 uint32_t rxstat; 595 int total_len, rx_npkts; 596 597 ifp = sc->ste_ifp; 598 599 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 600 sc->ste_cdata.ste_rx_list_map, 601 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 602 603 cur_rx = sc->ste_cdata.ste_rx_head; 604 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 605 cur_rx = cur_rx->ste_next) { 606 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 607 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 608 break; 609 #ifdef DEVICE_POLLING 610 if (if_getcapenable(ifp) & IFCAP_POLLING) { 611 if (count == 0) 612 break; 613 count--; 614 } 615 #endif 616 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 617 break; 618 /* 619 * If an error occurs, update stats, clear the 620 * status word and leave the mbuf cluster in place: 621 * it should simply get re-used next time this descriptor 622 * comes up in the ring. 623 */ 624 if (rxstat & STE_RXSTAT_FRAME_ERR) { 625 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 626 cur_rx->ste_ptr->ste_status = 0; 627 continue; 628 } 629 630 /* No errors; receive the packet. */ 631 m = cur_rx->ste_mbuf; 632 total_len = STE_RX_BYTES(rxstat); 633 634 /* 635 * Try to conjure up a new mbuf cluster. If that 636 * fails, it means we have an out of memory condition and 637 * should leave the buffer in place and continue. This will 638 * result in a lost packet, but there's little else we 639 * can do in this situation. 640 */ 641 if (ste_newbuf(sc, cur_rx) != 0) { 642 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 643 cur_rx->ste_ptr->ste_status = 0; 644 continue; 645 } 646 647 m->m_pkthdr.rcvif = ifp; 648 m->m_pkthdr.len = m->m_len = total_len; 649 650 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 651 STE_UNLOCK(sc); 652 if_input(ifp, m); 653 STE_LOCK(sc); 654 } 655 656 if (rx_npkts > 0) { 657 sc->ste_cdata.ste_rx_head = cur_rx; 658 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 659 sc->ste_cdata.ste_rx_list_map, 660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 661 } 662 663 return (rx_npkts); 664 } 665 666 static void 667 ste_txeoc(struct ste_softc *sc) 668 { 669 uint16_t txstat; 670 if_t ifp; 671 672 STE_LOCK_ASSERT(sc); 673 674 ifp = sc->ste_ifp; 675 676 /* 677 * STE_TX_STATUS register implements a queue of up to 31 678 * transmit status byte. Writing an arbitrary value to the 679 * register will advance the queue to the next transmit 680 * status byte. This means if driver does not read 681 * STE_TX_STATUS register after completing sending more 682 * than 31 frames the controller would be stalled so driver 683 * should re-wake the Tx MAC. This is the most severe 684 * limitation of ST201 based controller. 685 */ 686 for (;;) { 687 txstat = CSR_READ_2(sc, STE_TX_STATUS); 688 if ((txstat & STE_TXSTATUS_TXDONE) == 0) 689 break; 690 if ((txstat & (STE_TXSTATUS_UNDERRUN | 691 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR | 692 STE_TXSTATUS_STATSOFLOW)) != 0) { 693 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 694 #ifdef STE_SHOW_TXERRORS 695 device_printf(sc->ste_dev, "TX error : 0x%b\n", 696 txstat & 0xFF, STE_ERR_BITS); 697 #endif 698 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 && 699 sc->ste_tx_thresh < STE_PACKET_SIZE) { 700 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 701 if (sc->ste_tx_thresh > STE_PACKET_SIZE) 702 sc->ste_tx_thresh = STE_PACKET_SIZE; 703 device_printf(sc->ste_dev, 704 "TX underrun, increasing TX" 705 " start threshold to %d bytes\n", 706 sc->ste_tx_thresh); 707 /* Make sure to disable active DMA cycles. */ 708 STE_SETBIT4(sc, STE_DMACTL, 709 STE_DMACTL_TXDMA_STALL); 710 ste_wait(sc); 711 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 712 ste_init_locked(sc); 713 break; 714 } 715 /* Restart Tx. */ 716 ste_restart_tx(sc); 717 } 718 /* 719 * Advance to next status and ACK TxComplete 720 * interrupt. ST201 data sheet was wrong here, to 721 * get next Tx status, we have to write both 722 * STE_TX_STATUS and STE_TX_FRAMEID register. 723 * Otherwise controller returns the same status 724 * as well as not acknowledge Tx completion 725 * interrupt. 726 */ 727 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 728 } 729 } 730 731 static void 732 ste_tick(void *arg) 733 { 734 struct ste_softc *sc; 735 struct mii_data *mii; 736 737 sc = (struct ste_softc *)arg; 738 739 STE_LOCK_ASSERT(sc); 740 741 mii = device_get_softc(sc->ste_miibus); 742 mii_tick(mii); 743 /* 744 * ukphy(4) does not seem to generate CB that reports 745 * resolved link state so if we know we lost a link, 746 * explicitly check the link state. 747 */ 748 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 749 ste_miibus_statchg(sc->ste_dev); 750 /* 751 * Because we are not generating Tx completion 752 * interrupt for every frame, reclaim transmitted 753 * buffers here. 754 */ 755 ste_txeof(sc); 756 ste_txeoc(sc); 757 ste_stats_update(sc); 758 ste_watchdog(sc); 759 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 760 } 761 762 static void 763 ste_txeof(struct ste_softc *sc) 764 { 765 if_t ifp; 766 struct ste_chain *cur_tx; 767 uint32_t txstat; 768 int idx; 769 770 STE_LOCK_ASSERT(sc); 771 772 ifp = sc->ste_ifp; 773 idx = sc->ste_cdata.ste_tx_cons; 774 if (idx == sc->ste_cdata.ste_tx_prod) 775 return; 776 777 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 778 sc->ste_cdata.ste_tx_list_map, 779 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 780 781 while (idx != sc->ste_cdata.ste_tx_prod) { 782 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 783 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 784 if ((txstat & STE_TXCTL_DMADONE) == 0) 785 break; 786 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 787 BUS_DMASYNC_POSTWRITE); 788 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 789 KASSERT(cur_tx->ste_mbuf != NULL, 790 ("%s: freeing NULL mbuf!\n", __func__)); 791 m_freem(cur_tx->ste_mbuf); 792 cur_tx->ste_mbuf = NULL; 793 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 794 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 795 sc->ste_cdata.ste_tx_cnt--; 796 STE_INC(idx, STE_TX_LIST_CNT); 797 } 798 799 sc->ste_cdata.ste_tx_cons = idx; 800 if (sc->ste_cdata.ste_tx_cnt == 0) 801 sc->ste_timer = 0; 802 } 803 804 static void 805 ste_stats_clear(struct ste_softc *sc) 806 { 807 808 STE_LOCK_ASSERT(sc); 809 810 /* Rx stats. */ 811 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); 812 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); 813 CSR_READ_2(sc, STE_STAT_RX_FRAMES); 814 CSR_READ_1(sc, STE_STAT_RX_BCAST); 815 CSR_READ_1(sc, STE_STAT_RX_MCAST); 816 CSR_READ_1(sc, STE_STAT_RX_LOST); 817 /* Tx stats. */ 818 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO); 819 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI); 820 CSR_READ_2(sc, STE_STAT_TX_FRAMES); 821 CSR_READ_1(sc, STE_STAT_TX_BCAST); 822 CSR_READ_1(sc, STE_STAT_TX_MCAST); 823 CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 824 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 825 CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 826 CSR_READ_1(sc, STE_STAT_LATE_COLLS); 827 CSR_READ_1(sc, STE_STAT_TX_DEFER); 828 CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 829 CSR_READ_1(sc, STE_STAT_TX_ABORT); 830 } 831 832 static void 833 ste_stats_update(struct ste_softc *sc) 834 { 835 if_t ifp; 836 struct ste_hw_stats *stats; 837 uint32_t val; 838 839 STE_LOCK_ASSERT(sc); 840 841 ifp = sc->ste_ifp; 842 stats = &sc->ste_stats; 843 /* Rx stats. */ 844 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) | 845 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16; 846 val &= 0x000FFFFF; 847 stats->rx_bytes += val; 848 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES); 849 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST); 850 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST); 851 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST); 852 /* Tx stats. */ 853 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) | 854 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16; 855 val &= 0x000FFFFF; 856 stats->tx_bytes += val; 857 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES); 858 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST); 859 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST); 860 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 861 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 862 stats->tx_single_colls += val; 863 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 864 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 865 stats->tx_multi_colls += val; 866 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 867 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS); 868 stats->tx_late_colls += val; 869 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 870 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER); 871 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 872 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT); 873 } 874 875 /* 876 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 877 * IDs against our list and return a device name if we find a match. 878 */ 879 static int 880 ste_probe(device_t dev) 881 { 882 const struct ste_type *t; 883 884 t = ste_devs; 885 886 while (t->ste_name != NULL) { 887 if ((pci_get_vendor(dev) == t->ste_vid) && 888 (pci_get_device(dev) == t->ste_did)) { 889 device_set_desc(dev, t->ste_name); 890 return (BUS_PROBE_DEFAULT); 891 } 892 t++; 893 } 894 895 return (ENXIO); 896 } 897 898 /* 899 * Attach the interface. Allocate softc structures, do ifmedia 900 * setup and ethernet/BPF attach. 901 */ 902 static int 903 ste_attach(device_t dev) 904 { 905 struct ste_softc *sc; 906 if_t ifp; 907 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 908 int error = 0, phy, pmc, prefer_iomap, rid; 909 910 sc = device_get_softc(dev); 911 sc->ste_dev = dev; 912 913 /* 914 * Only use one PHY since this chip reports multiple 915 * Note on the DFE-550 the PHY is at 1 on the DFE-580 916 * it is at 0 & 1. It is rev 0x12. 917 */ 918 if (pci_get_vendor(dev) == DL_VENDORID && 919 pci_get_device(dev) == DL_DEVICEID_DL10050 && 920 pci_get_revid(dev) == 0x12 ) 921 sc->ste_flags |= STE_FLAG_ONE_PHY; 922 923 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 924 MTX_DEF); 925 /* 926 * Map control/status registers. 927 */ 928 pci_enable_busmaster(dev); 929 930 /* 931 * Prefer memory space register mapping over IO space but use 932 * IO space for a device that is known to have issues on memory 933 * mapping. 934 */ 935 prefer_iomap = 0; 936 if (pci_get_device(dev) == ST_DEVICEID_ST201_1) 937 prefer_iomap = 1; 938 else 939 resource_int_value(device_get_name(sc->ste_dev), 940 device_get_unit(sc->ste_dev), "prefer_iomap", 941 &prefer_iomap); 942 if (prefer_iomap == 0) { 943 sc->ste_res_id = PCIR_BAR(1); 944 sc->ste_res_type = SYS_RES_MEMORY; 945 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 946 &sc->ste_res_id, RF_ACTIVE); 947 } 948 if (prefer_iomap || sc->ste_res == NULL) { 949 sc->ste_res_id = PCIR_BAR(0); 950 sc->ste_res_type = SYS_RES_IOPORT; 951 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 952 &sc->ste_res_id, RF_ACTIVE); 953 } 954 if (sc->ste_res == NULL) { 955 device_printf(dev, "couldn't map ports/memory\n"); 956 error = ENXIO; 957 goto fail; 958 } 959 960 /* Allocate interrupt */ 961 rid = 0; 962 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 963 RF_SHAREABLE | RF_ACTIVE); 964 965 if (sc->ste_irq == NULL) { 966 device_printf(dev, "couldn't map interrupt\n"); 967 error = ENXIO; 968 goto fail; 969 } 970 971 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 972 973 /* Reset the adapter. */ 974 ste_reset(sc); 975 976 /* 977 * Get station address from the EEPROM. 978 */ 979 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) { 980 device_printf(dev, "failed to read station address\n"); 981 error = ENXIO; 982 goto fail; 983 } 984 ste_sysctl_node(sc); 985 986 if ((error = ste_dma_alloc(sc)) != 0) 987 goto fail; 988 989 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 990 991 /* Do MII setup. */ 992 phy = MII_PHY_ANY; 993 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0) 994 phy = 0; 995 error = mii_attach(dev, &sc->ste_miibus, ifp, ste_ifmedia_upd, 996 ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 997 if (error != 0) { 998 device_printf(dev, "attaching PHYs failed\n"); 999 goto fail; 1000 } 1001 1002 if_setsoftc(ifp, sc); 1003 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1004 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1005 if_setioctlfn(ifp, ste_ioctl); 1006 if_setstartfn(ifp, ste_start); 1007 if_setinitfn(ifp, ste_init); 1008 if_setsendqlen(ifp, STE_TX_LIST_CNT - 1); 1009 if_setsendqready(ifp); 1010 1011 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1012 1013 /* 1014 * Call MI attach routine. 1015 */ 1016 ether_ifattach(ifp, (uint8_t *)eaddr); 1017 1018 /* 1019 * Tell the upper layer(s) we support long frames. 1020 */ 1021 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1022 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1023 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 1024 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 1025 if_setcapenable(ifp, if_getcapabilities(ifp)); 1026 #ifdef DEVICE_POLLING 1027 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1028 #endif 1029 1030 /* Hook interrupt last to avoid having to lock softc */ 1031 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1032 NULL, ste_intr, sc, &sc->ste_intrhand); 1033 1034 if (error) { 1035 device_printf(dev, "couldn't set up irq\n"); 1036 ether_ifdetach(ifp); 1037 goto fail; 1038 } 1039 1040 fail: 1041 if (error) 1042 ste_detach(dev); 1043 1044 return (error); 1045 } 1046 1047 /* 1048 * Shutdown hardware and free up resources. This can be called any 1049 * time after the mutex has been initialized. It is called in both 1050 * the error case in attach and the normal detach case so it needs 1051 * to be careful about only freeing resources that have actually been 1052 * allocated. 1053 */ 1054 static int 1055 ste_detach(device_t dev) 1056 { 1057 struct ste_softc *sc; 1058 if_t ifp; 1059 1060 sc = device_get_softc(dev); 1061 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1062 ifp = sc->ste_ifp; 1063 1064 #ifdef DEVICE_POLLING 1065 if (if_getcapenable(ifp) & IFCAP_POLLING) 1066 ether_poll_deregister(ifp); 1067 #endif 1068 1069 /* These should only be active if attach succeeded */ 1070 if (device_is_attached(dev)) { 1071 ether_ifdetach(ifp); 1072 STE_LOCK(sc); 1073 ste_stop(sc); 1074 STE_UNLOCK(sc); 1075 callout_drain(&sc->ste_callout); 1076 } 1077 if (sc->ste_miibus) 1078 device_delete_child(dev, sc->ste_miibus); 1079 bus_generic_detach(dev); 1080 1081 if (sc->ste_intrhand) 1082 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1083 if (sc->ste_irq) 1084 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1085 if (sc->ste_res) 1086 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1087 sc->ste_res); 1088 1089 if (ifp) 1090 if_free(ifp); 1091 1092 ste_dma_free(sc); 1093 mtx_destroy(&sc->ste_mtx); 1094 1095 return (0); 1096 } 1097 1098 struct ste_dmamap_arg { 1099 bus_addr_t ste_busaddr; 1100 }; 1101 1102 static void 1103 ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1104 { 1105 struct ste_dmamap_arg *ctx; 1106 1107 if (error != 0) 1108 return; 1109 1110 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1111 1112 ctx = (struct ste_dmamap_arg *)arg; 1113 ctx->ste_busaddr = segs[0].ds_addr; 1114 } 1115 1116 static int 1117 ste_dma_alloc(struct ste_softc *sc) 1118 { 1119 struct ste_chain *txc; 1120 struct ste_chain_onefrag *rxc; 1121 struct ste_dmamap_arg ctx; 1122 int error, i; 1123 1124 /* Create parent DMA tag. */ 1125 error = bus_dma_tag_create( 1126 bus_get_dma_tag(sc->ste_dev), /* parent */ 1127 1, 0, /* alignment, boundary */ 1128 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1129 BUS_SPACE_MAXADDR, /* highaddr */ 1130 NULL, NULL, /* filter, filterarg */ 1131 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1132 0, /* nsegments */ 1133 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1134 0, /* flags */ 1135 NULL, NULL, /* lockfunc, lockarg */ 1136 &sc->ste_cdata.ste_parent_tag); 1137 if (error != 0) { 1138 device_printf(sc->ste_dev, 1139 "could not create parent DMA tag.\n"); 1140 goto fail; 1141 } 1142 1143 /* Create DMA tag for Tx descriptor list. */ 1144 error = bus_dma_tag_create( 1145 sc->ste_cdata.ste_parent_tag, /* parent */ 1146 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1147 BUS_SPACE_MAXADDR, /* lowaddr */ 1148 BUS_SPACE_MAXADDR, /* highaddr */ 1149 NULL, NULL, /* filter, filterarg */ 1150 STE_TX_LIST_SZ, /* maxsize */ 1151 1, /* nsegments */ 1152 STE_TX_LIST_SZ, /* maxsegsize */ 1153 0, /* flags */ 1154 NULL, NULL, /* lockfunc, lockarg */ 1155 &sc->ste_cdata.ste_tx_list_tag); 1156 if (error != 0) { 1157 device_printf(sc->ste_dev, 1158 "could not create Tx list DMA tag.\n"); 1159 goto fail; 1160 } 1161 1162 /* Create DMA tag for Rx descriptor list. */ 1163 error = bus_dma_tag_create( 1164 sc->ste_cdata.ste_parent_tag, /* parent */ 1165 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1166 BUS_SPACE_MAXADDR, /* lowaddr */ 1167 BUS_SPACE_MAXADDR, /* highaddr */ 1168 NULL, NULL, /* filter, filterarg */ 1169 STE_RX_LIST_SZ, /* maxsize */ 1170 1, /* nsegments */ 1171 STE_RX_LIST_SZ, /* maxsegsize */ 1172 0, /* flags */ 1173 NULL, NULL, /* lockfunc, lockarg */ 1174 &sc->ste_cdata.ste_rx_list_tag); 1175 if (error != 0) { 1176 device_printf(sc->ste_dev, 1177 "could not create Rx list DMA tag.\n"); 1178 goto fail; 1179 } 1180 1181 /* Create DMA tag for Tx buffers. */ 1182 error = bus_dma_tag_create( 1183 sc->ste_cdata.ste_parent_tag, /* parent */ 1184 1, 0, /* alignment, boundary */ 1185 BUS_SPACE_MAXADDR, /* lowaddr */ 1186 BUS_SPACE_MAXADDR, /* highaddr */ 1187 NULL, NULL, /* filter, filterarg */ 1188 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1189 STE_MAXFRAGS, /* nsegments */ 1190 MCLBYTES, /* maxsegsize */ 1191 0, /* flags */ 1192 NULL, NULL, /* lockfunc, lockarg */ 1193 &sc->ste_cdata.ste_tx_tag); 1194 if (error != 0) { 1195 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1196 goto fail; 1197 } 1198 1199 /* Create DMA tag for Rx buffers. */ 1200 error = bus_dma_tag_create( 1201 sc->ste_cdata.ste_parent_tag, /* parent */ 1202 1, 0, /* alignment, boundary */ 1203 BUS_SPACE_MAXADDR, /* lowaddr */ 1204 BUS_SPACE_MAXADDR, /* highaddr */ 1205 NULL, NULL, /* filter, filterarg */ 1206 MCLBYTES, /* maxsize */ 1207 1, /* nsegments */ 1208 MCLBYTES, /* maxsegsize */ 1209 0, /* flags */ 1210 NULL, NULL, /* lockfunc, lockarg */ 1211 &sc->ste_cdata.ste_rx_tag); 1212 if (error != 0) { 1213 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1214 goto fail; 1215 } 1216 1217 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1218 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1219 (void **)&sc->ste_ldata.ste_tx_list, 1220 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1221 &sc->ste_cdata.ste_tx_list_map); 1222 if (error != 0) { 1223 device_printf(sc->ste_dev, 1224 "could not allocate DMA'able memory for Tx list.\n"); 1225 goto fail; 1226 } 1227 ctx.ste_busaddr = 0; 1228 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1229 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1230 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1231 if (error != 0 || ctx.ste_busaddr == 0) { 1232 device_printf(sc->ste_dev, 1233 "could not load DMA'able memory for Tx list.\n"); 1234 goto fail; 1235 } 1236 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1237 1238 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1239 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1240 (void **)&sc->ste_ldata.ste_rx_list, 1241 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1242 &sc->ste_cdata.ste_rx_list_map); 1243 if (error != 0) { 1244 device_printf(sc->ste_dev, 1245 "could not allocate DMA'able memory for Rx list.\n"); 1246 goto fail; 1247 } 1248 ctx.ste_busaddr = 0; 1249 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1250 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1251 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1252 if (error != 0 || ctx.ste_busaddr == 0) { 1253 device_printf(sc->ste_dev, 1254 "could not load DMA'able memory for Rx list.\n"); 1255 goto fail; 1256 } 1257 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1258 1259 /* Create DMA maps for Tx buffers. */ 1260 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1261 txc = &sc->ste_cdata.ste_tx_chain[i]; 1262 txc->ste_ptr = NULL; 1263 txc->ste_mbuf = NULL; 1264 txc->ste_next = NULL; 1265 txc->ste_phys = 0; 1266 txc->ste_map = NULL; 1267 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1268 &txc->ste_map); 1269 if (error != 0) { 1270 device_printf(sc->ste_dev, 1271 "could not create Tx dmamap.\n"); 1272 goto fail; 1273 } 1274 } 1275 /* Create DMA maps for Rx buffers. */ 1276 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1277 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1278 device_printf(sc->ste_dev, 1279 "could not create spare Rx dmamap.\n"); 1280 goto fail; 1281 } 1282 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1283 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1284 rxc->ste_ptr = NULL; 1285 rxc->ste_mbuf = NULL; 1286 rxc->ste_next = NULL; 1287 rxc->ste_map = NULL; 1288 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1289 &rxc->ste_map); 1290 if (error != 0) { 1291 device_printf(sc->ste_dev, 1292 "could not create Rx dmamap.\n"); 1293 goto fail; 1294 } 1295 } 1296 1297 fail: 1298 return (error); 1299 } 1300 1301 static void 1302 ste_dma_free(struct ste_softc *sc) 1303 { 1304 struct ste_chain *txc; 1305 struct ste_chain_onefrag *rxc; 1306 int i; 1307 1308 /* Tx buffers. */ 1309 if (sc->ste_cdata.ste_tx_tag != NULL) { 1310 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1311 txc = &sc->ste_cdata.ste_tx_chain[i]; 1312 if (txc->ste_map != NULL) { 1313 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1314 txc->ste_map); 1315 txc->ste_map = NULL; 1316 } 1317 } 1318 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1319 sc->ste_cdata.ste_tx_tag = NULL; 1320 } 1321 /* Rx buffers. */ 1322 if (sc->ste_cdata.ste_rx_tag != NULL) { 1323 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1324 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1325 if (rxc->ste_map != NULL) { 1326 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1327 rxc->ste_map); 1328 rxc->ste_map = NULL; 1329 } 1330 } 1331 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1332 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1333 sc->ste_cdata.ste_rx_sparemap); 1334 sc->ste_cdata.ste_rx_sparemap = NULL; 1335 } 1336 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1337 sc->ste_cdata.ste_rx_tag = NULL; 1338 } 1339 /* Tx descriptor list. */ 1340 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1341 if (sc->ste_ldata.ste_tx_list_paddr != 0) 1342 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1343 sc->ste_cdata.ste_tx_list_map); 1344 if (sc->ste_ldata.ste_tx_list != NULL) 1345 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1346 sc->ste_ldata.ste_tx_list, 1347 sc->ste_cdata.ste_tx_list_map); 1348 sc->ste_ldata.ste_tx_list = NULL; 1349 sc->ste_ldata.ste_tx_list_paddr = 0; 1350 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1351 sc->ste_cdata.ste_tx_list_tag = NULL; 1352 } 1353 /* Rx descriptor list. */ 1354 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1355 if (sc->ste_ldata.ste_rx_list_paddr != 0) 1356 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1357 sc->ste_cdata.ste_rx_list_map); 1358 if (sc->ste_ldata.ste_rx_list != NULL) 1359 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1360 sc->ste_ldata.ste_rx_list, 1361 sc->ste_cdata.ste_rx_list_map); 1362 sc->ste_ldata.ste_rx_list = NULL; 1363 sc->ste_ldata.ste_rx_list_paddr = 0; 1364 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1365 sc->ste_cdata.ste_rx_list_tag = NULL; 1366 } 1367 if (sc->ste_cdata.ste_parent_tag != NULL) { 1368 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1369 sc->ste_cdata.ste_parent_tag = NULL; 1370 } 1371 } 1372 1373 static int 1374 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1375 { 1376 struct mbuf *m; 1377 bus_dma_segment_t segs[1]; 1378 bus_dmamap_t map; 1379 int error, nsegs; 1380 1381 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1382 if (m == NULL) 1383 return (ENOBUFS); 1384 m->m_len = m->m_pkthdr.len = MCLBYTES; 1385 m_adj(m, ETHER_ALIGN); 1386 1387 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1388 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1389 m_freem(m); 1390 return (error); 1391 } 1392 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1393 1394 if (rxc->ste_mbuf != NULL) { 1395 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1396 BUS_DMASYNC_POSTREAD); 1397 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1398 } 1399 map = rxc->ste_map; 1400 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1401 sc->ste_cdata.ste_rx_sparemap = map; 1402 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1403 BUS_DMASYNC_PREREAD); 1404 rxc->ste_mbuf = m; 1405 rxc->ste_ptr->ste_status = 0; 1406 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1407 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1408 STE_FRAG_LAST); 1409 return (0); 1410 } 1411 1412 static int 1413 ste_init_rx_list(struct ste_softc *sc) 1414 { 1415 struct ste_chain_data *cd; 1416 struct ste_list_data *ld; 1417 int error, i; 1418 1419 sc->ste_int_rx_act = 0; 1420 cd = &sc->ste_cdata; 1421 ld = &sc->ste_ldata; 1422 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1423 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1424 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1425 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1426 if (error != 0) 1427 return (error); 1428 if (i == (STE_RX_LIST_CNT - 1)) { 1429 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1430 ld->ste_rx_list[i].ste_next = 1431 htole32(ld->ste_rx_list_paddr + 1432 (sizeof(struct ste_desc_onefrag) * 0)); 1433 } else { 1434 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1435 ld->ste_rx_list[i].ste_next = 1436 htole32(ld->ste_rx_list_paddr + 1437 (sizeof(struct ste_desc_onefrag) * (i + 1))); 1438 } 1439 } 1440 1441 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1442 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1443 sc->ste_cdata.ste_rx_list_map, 1444 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1445 1446 return (0); 1447 } 1448 1449 static void 1450 ste_init_tx_list(struct ste_softc *sc) 1451 { 1452 struct ste_chain_data *cd; 1453 struct ste_list_data *ld; 1454 int i; 1455 1456 cd = &sc->ste_cdata; 1457 ld = &sc->ste_ldata; 1458 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1459 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1460 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1461 cd->ste_tx_chain[i].ste_mbuf = NULL; 1462 if (i == (STE_TX_LIST_CNT - 1)) { 1463 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1464 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1465 ld->ste_tx_list_paddr + 1466 (sizeof(struct ste_desc) * 0))); 1467 } else { 1468 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1469 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1470 ld->ste_tx_list_paddr + 1471 (sizeof(struct ste_desc) * (i + 1)))); 1472 } 1473 } 1474 1475 cd->ste_last_tx = NULL; 1476 cd->ste_tx_prod = 0; 1477 cd->ste_tx_cons = 0; 1478 cd->ste_tx_cnt = 0; 1479 1480 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1481 sc->ste_cdata.ste_tx_list_map, 1482 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1483 } 1484 1485 static void 1486 ste_init(void *xsc) 1487 { 1488 struct ste_softc *sc; 1489 1490 sc = xsc; 1491 STE_LOCK(sc); 1492 ste_init_locked(sc); 1493 STE_UNLOCK(sc); 1494 } 1495 1496 static void 1497 ste_init_locked(struct ste_softc *sc) 1498 { 1499 if_t ifp; 1500 struct mii_data *mii; 1501 uint8_t val; 1502 int i; 1503 1504 STE_LOCK_ASSERT(sc); 1505 ifp = sc->ste_ifp; 1506 mii = device_get_softc(sc->ste_miibus); 1507 1508 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1509 return; 1510 1511 ste_stop(sc); 1512 /* Reset the chip to a known state. */ 1513 ste_reset(sc); 1514 1515 /* Init our MAC address */ 1516 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1517 CSR_WRITE_2(sc, STE_PAR0 + i, 1518 ((if_getlladdr(sc->ste_ifp)[i] & 0xff) | 1519 if_getlladdr(sc->ste_ifp)[i + 1] << 8)); 1520 } 1521 1522 /* Init RX list */ 1523 if (ste_init_rx_list(sc) != 0) { 1524 device_printf(sc->ste_dev, 1525 "initialization failed: no memory for RX buffers\n"); 1526 ste_stop(sc); 1527 return; 1528 } 1529 1530 /* Set RX polling interval */ 1531 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1532 1533 /* Init TX descriptors */ 1534 ste_init_tx_list(sc); 1535 1536 /* Clear and disable WOL. */ 1537 val = CSR_READ_1(sc, STE_WAKE_EVENT); 1538 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 1539 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 1540 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 1541 1542 /* Set the TX freethresh value */ 1543 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1544 1545 /* Set the TX start threshold for best performance. */ 1546 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1547 1548 /* Set the TX reclaim threshold. */ 1549 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1550 1551 /* Accept VLAN length packets */ 1552 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1553 1554 /* Set up the RX filter. */ 1555 ste_rxfilter(sc); 1556 1557 /* Load the address of the RX list. */ 1558 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1559 ste_wait(sc); 1560 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1561 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1562 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1563 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1564 1565 /* Set TX polling interval(defer until we TX first packet). */ 1566 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1567 1568 /* Load address of the TX list */ 1569 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1570 ste_wait(sc); 1571 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1572 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1573 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1574 ste_wait(sc); 1575 /* Select 3.2us timer. */ 1576 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED | 1577 STE_DMACTL_COUNTDOWN_MODE); 1578 1579 /* Enable receiver and transmitter */ 1580 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1581 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1582 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1583 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1584 1585 /* Enable stats counters. */ 1586 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1587 /* Clear stats counters. */ 1588 ste_stats_clear(sc); 1589 1590 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1591 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1592 #ifdef DEVICE_POLLING 1593 /* Disable interrupts if we are polling. */ 1594 if (if_getcapenable(ifp) & IFCAP_POLLING) 1595 CSR_WRITE_2(sc, STE_IMR, 0); 1596 else 1597 #endif 1598 /* Enable interrupts. */ 1599 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1600 1601 sc->ste_flags &= ~STE_FLAG_LINK; 1602 /* Switch to the current media. */ 1603 mii_mediachg(mii); 1604 1605 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1606 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1607 1608 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1609 } 1610 1611 static void 1612 ste_stop(struct ste_softc *sc) 1613 { 1614 if_t ifp; 1615 struct ste_chain_onefrag *cur_rx; 1616 struct ste_chain *cur_tx; 1617 uint32_t val; 1618 int i; 1619 1620 STE_LOCK_ASSERT(sc); 1621 ifp = sc->ste_ifp; 1622 1623 callout_stop(&sc->ste_callout); 1624 sc->ste_timer = 0; 1625 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)); 1626 1627 CSR_WRITE_2(sc, STE_IMR, 0); 1628 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1629 /* Stop pending DMA. */ 1630 val = CSR_READ_4(sc, STE_DMACTL); 1631 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1632 CSR_WRITE_4(sc, STE_DMACTL, val); 1633 ste_wait(sc); 1634 /* Disable auto-polling. */ 1635 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1636 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1637 /* Nullify DMA address to stop any further DMA. */ 1638 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1639 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1640 /* Stop TX/RX MAC. */ 1641 val = CSR_READ_2(sc, STE_MACCTL1); 1642 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1643 STE_MACCTL1_STATS_DISABLE; 1644 CSR_WRITE_2(sc, STE_MACCTL1, val); 1645 for (i = 0; i < STE_TIMEOUT; i++) { 1646 DELAY(10); 1647 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1648 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1649 break; 1650 } 1651 if (i == STE_TIMEOUT) 1652 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1653 /* Acknowledge any pending interrupts. */ 1654 CSR_READ_2(sc, STE_ISR_ACK); 1655 ste_stats_update(sc); 1656 1657 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1658 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1659 if (cur_rx->ste_mbuf != NULL) { 1660 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1661 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1662 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1663 cur_rx->ste_map); 1664 m_freem(cur_rx->ste_mbuf); 1665 cur_rx->ste_mbuf = NULL; 1666 } 1667 } 1668 1669 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1670 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1671 if (cur_tx->ste_mbuf != NULL) { 1672 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1673 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1674 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1675 cur_tx->ste_map); 1676 m_freem(cur_tx->ste_mbuf); 1677 cur_tx->ste_mbuf = NULL; 1678 } 1679 } 1680 } 1681 1682 static void 1683 ste_reset(struct ste_softc *sc) 1684 { 1685 uint32_t ctl; 1686 int i; 1687 1688 ctl = CSR_READ_4(sc, STE_ASICCTL); 1689 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET | 1690 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET | 1691 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET | 1692 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET | 1693 STE_ASICCTL_EXTRESET_RESET; 1694 CSR_WRITE_4(sc, STE_ASICCTL, ctl); 1695 CSR_READ_4(sc, STE_ASICCTL); 1696 /* 1697 * Due to the need of accessing EEPROM controller can take 1698 * up to 1ms to complete the global reset. 1699 */ 1700 DELAY(1000); 1701 1702 for (i = 0; i < STE_TIMEOUT; i++) { 1703 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1704 break; 1705 DELAY(10); 1706 } 1707 1708 if (i == STE_TIMEOUT) 1709 device_printf(sc->ste_dev, "global reset never completed\n"); 1710 } 1711 1712 static void 1713 ste_restart_tx(struct ste_softc *sc) 1714 { 1715 uint16_t mac; 1716 int i; 1717 1718 for (i = 0; i < STE_TIMEOUT; i++) { 1719 mac = CSR_READ_2(sc, STE_MACCTL1); 1720 mac |= STE_MACCTL1_TX_ENABLE; 1721 CSR_WRITE_2(sc, STE_MACCTL1, mac); 1722 mac = CSR_READ_2(sc, STE_MACCTL1); 1723 if ((mac & STE_MACCTL1_TX_ENABLED) != 0) 1724 break; 1725 DELAY(10); 1726 } 1727 1728 if (i == STE_TIMEOUT) 1729 device_printf(sc->ste_dev, "starting Tx failed"); 1730 } 1731 1732 static int 1733 ste_ioctl(if_t ifp, u_long command, caddr_t data) 1734 { 1735 struct ste_softc *sc; 1736 struct ifreq *ifr; 1737 struct mii_data *mii; 1738 int error = 0, mask; 1739 1740 sc = if_getsoftc(ifp); 1741 ifr = (struct ifreq *)data; 1742 1743 switch (command) { 1744 case SIOCSIFFLAGS: 1745 STE_LOCK(sc); 1746 if ((if_getflags(ifp) & IFF_UP) != 0) { 1747 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1748 ((if_getflags(ifp) ^ sc->ste_if_flags) & 1749 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1750 ste_rxfilter(sc); 1751 else 1752 ste_init_locked(sc); 1753 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1754 ste_stop(sc); 1755 sc->ste_if_flags = if_getflags(ifp); 1756 STE_UNLOCK(sc); 1757 break; 1758 case SIOCADDMULTI: 1759 case SIOCDELMULTI: 1760 STE_LOCK(sc); 1761 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1762 ste_rxfilter(sc); 1763 STE_UNLOCK(sc); 1764 break; 1765 case SIOCGIFMEDIA: 1766 case SIOCSIFMEDIA: 1767 mii = device_get_softc(sc->ste_miibus); 1768 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1769 break; 1770 case SIOCSIFCAP: 1771 STE_LOCK(sc); 1772 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1773 #ifdef DEVICE_POLLING 1774 if ((mask & IFCAP_POLLING) != 0 && 1775 (IFCAP_POLLING & if_getcapabilities(ifp)) != 0) { 1776 if_togglecapenable(ifp, IFCAP_POLLING); 1777 if ((IFCAP_POLLING & if_getcapenable(ifp)) != 0) { 1778 error = ether_poll_register(ste_poll, ifp); 1779 if (error != 0) { 1780 STE_UNLOCK(sc); 1781 break; 1782 } 1783 /* Disable interrupts. */ 1784 CSR_WRITE_2(sc, STE_IMR, 0); 1785 } else { 1786 error = ether_poll_deregister(ifp); 1787 /* Enable interrupts. */ 1788 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1789 } 1790 } 1791 #endif /* DEVICE_POLLING */ 1792 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1793 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1794 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1795 STE_UNLOCK(sc); 1796 break; 1797 default: 1798 error = ether_ioctl(ifp, command, data); 1799 break; 1800 } 1801 1802 return (error); 1803 } 1804 1805 static int 1806 ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1807 { 1808 struct ste_frag *frag; 1809 struct mbuf *m; 1810 struct ste_desc *desc; 1811 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1812 int error, i, nsegs; 1813 1814 STE_LOCK_ASSERT(sc); 1815 M_ASSERTPKTHDR((*m_head)); 1816 1817 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1818 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1819 if (error == EFBIG) { 1820 m = m_collapse(*m_head, M_NOWAIT, STE_MAXFRAGS); 1821 if (m == NULL) { 1822 m_freem(*m_head); 1823 *m_head = NULL; 1824 return (ENOMEM); 1825 } 1826 *m_head = m; 1827 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1828 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1829 if (error != 0) { 1830 m_freem(*m_head); 1831 *m_head = NULL; 1832 return (error); 1833 } 1834 } else if (error != 0) 1835 return (error); 1836 if (nsegs == 0) { 1837 m_freem(*m_head); 1838 *m_head = NULL; 1839 return (EIO); 1840 } 1841 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1842 BUS_DMASYNC_PREWRITE); 1843 1844 desc = txc->ste_ptr; 1845 for (i = 0; i < nsegs; i++) { 1846 frag = &desc->ste_frags[i]; 1847 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1848 frag->ste_len = htole32(txsegs[i].ds_len); 1849 } 1850 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1851 /* 1852 * Because we use Tx polling we can't chain multiple 1853 * Tx descriptors here. Otherwise we race with controller. 1854 */ 1855 desc->ste_next = 0; 1856 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0) 1857 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | 1858 STE_TXCTL_DMAINTR); 1859 else 1860 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS); 1861 txc->ste_mbuf = *m_head; 1862 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1863 sc->ste_cdata.ste_tx_cnt++; 1864 1865 return (0); 1866 } 1867 1868 static void 1869 ste_start(if_t ifp) 1870 { 1871 struct ste_softc *sc; 1872 1873 sc = if_getsoftc(ifp); 1874 STE_LOCK(sc); 1875 ste_start_locked(ifp); 1876 STE_UNLOCK(sc); 1877 } 1878 1879 static void 1880 ste_start_locked(if_t ifp) 1881 { 1882 struct ste_softc *sc; 1883 struct ste_chain *cur_tx; 1884 struct mbuf *m_head = NULL; 1885 int enq; 1886 1887 sc = if_getsoftc(ifp); 1888 STE_LOCK_ASSERT(sc); 1889 1890 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1891 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1892 return; 1893 1894 for (enq = 0; !if_sendq_empty(ifp);) { 1895 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1896 /* 1897 * Controller may have cached copy of the last used 1898 * next ptr so we have to reserve one TFD to avoid 1899 * TFD overruns. 1900 */ 1901 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1902 break; 1903 } 1904 m_head = if_dequeue(ifp); 1905 if (m_head == NULL) 1906 break; 1907 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1908 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1909 if (m_head == NULL) 1910 break; 1911 if_sendq_prepend(ifp, m_head); 1912 break; 1913 } 1914 if (sc->ste_cdata.ste_last_tx == NULL) { 1915 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1916 sc->ste_cdata.ste_tx_list_map, 1917 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1918 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1919 ste_wait(sc); 1920 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1921 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1922 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1923 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1924 ste_wait(sc); 1925 } else { 1926 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1927 sc->ste_cdata.ste_last_tx->ste_phys; 1928 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1929 sc->ste_cdata.ste_tx_list_map, 1930 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1931 } 1932 sc->ste_cdata.ste_last_tx = cur_tx; 1933 1934 enq++; 1935 /* 1936 * If there's a BPF listener, bounce a copy of this frame 1937 * to him. 1938 */ 1939 BPF_MTAP(ifp, m_head); 1940 } 1941 1942 if (enq > 0) 1943 sc->ste_timer = STE_TX_TIMEOUT; 1944 } 1945 1946 static void 1947 ste_watchdog(struct ste_softc *sc) 1948 { 1949 if_t ifp; 1950 1951 ifp = sc->ste_ifp; 1952 STE_LOCK_ASSERT(sc); 1953 1954 if (sc->ste_timer == 0 || --sc->ste_timer) 1955 return; 1956 1957 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1958 if_printf(ifp, "watchdog timeout\n"); 1959 1960 ste_txeof(sc); 1961 ste_txeoc(sc); 1962 ste_rxeof(sc, -1); 1963 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1964 ste_init_locked(sc); 1965 1966 if (!if_sendq_empty(ifp)) 1967 ste_start_locked(ifp); 1968 } 1969 1970 static int 1971 ste_shutdown(device_t dev) 1972 { 1973 1974 return (ste_suspend(dev)); 1975 } 1976 1977 static int 1978 ste_suspend(device_t dev) 1979 { 1980 struct ste_softc *sc; 1981 1982 sc = device_get_softc(dev); 1983 1984 STE_LOCK(sc); 1985 ste_stop(sc); 1986 ste_setwol(sc); 1987 STE_UNLOCK(sc); 1988 1989 return (0); 1990 } 1991 1992 static int 1993 ste_resume(device_t dev) 1994 { 1995 struct ste_softc *sc; 1996 if_t ifp; 1997 int pmc; 1998 uint16_t pmstat; 1999 2000 sc = device_get_softc(dev); 2001 STE_LOCK(sc); 2002 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) == 0) { 2003 /* Disable PME and clear PME status. */ 2004 pmstat = pci_read_config(sc->ste_dev, 2005 pmc + PCIR_POWER_STATUS, 2); 2006 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2007 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2008 pci_write_config(sc->ste_dev, 2009 pmc + PCIR_POWER_STATUS, pmstat, 2); 2010 } 2011 } 2012 ifp = sc->ste_ifp; 2013 if ((if_getflags(ifp) & IFF_UP) != 0) { 2014 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2015 ste_init_locked(sc); 2016 } 2017 STE_UNLOCK(sc); 2018 2019 return (0); 2020 } 2021 2022 #define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2023 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2024 #define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2025 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2026 2027 static void 2028 ste_sysctl_node(struct ste_softc *sc) 2029 { 2030 struct sysctl_ctx_list *ctx; 2031 struct sysctl_oid_list *child, *parent; 2032 struct sysctl_oid *tree; 2033 struct ste_hw_stats *stats; 2034 2035 stats = &sc->ste_stats; 2036 ctx = device_get_sysctl_ctx(sc->ste_dev); 2037 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev)); 2038 2039 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod", 2040 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation"); 2041 /* Pull in device tunables. */ 2042 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT; 2043 resource_int_value(device_get_name(sc->ste_dev), 2044 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod); 2045 2046 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 2047 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "STE statistics"); 2048 parent = SYSCTL_CHILDREN(tree); 2049 2050 /* Rx statistics. */ 2051 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2052 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 2053 child = SYSCTL_CHILDREN(tree); 2054 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2055 &stats->rx_bytes, "Good octets"); 2056 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2057 &stats->rx_frames, "Good frames"); 2058 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2059 &stats->rx_bcast_frames, "Good broadcast frames"); 2060 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2061 &stats->rx_mcast_frames, "Good multicast frames"); 2062 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames", 2063 &stats->rx_lost_frames, "Lost frames"); 2064 2065 /* Tx statistics. */ 2066 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2067 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 2068 child = SYSCTL_CHILDREN(tree); 2069 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2070 &stats->tx_bytes, "Good octets"); 2071 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2072 &stats->tx_frames, "Good frames"); 2073 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2074 &stats->tx_bcast_frames, "Good broadcast frames"); 2075 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2076 &stats->tx_mcast_frames, "Good multicast frames"); 2077 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs", 2078 &stats->tx_carrsense_errs, "Carrier sense errors"); 2079 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 2080 &stats->tx_single_colls, "Single collisions"); 2081 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 2082 &stats->tx_multi_colls, "Multiple collisions"); 2083 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2084 &stats->tx_late_colls, "Late collisions"); 2085 STE_SYSCTL_STAT_ADD32(ctx, child, "defers", 2086 &stats->tx_frames_defered, "Frames with deferrals"); 2087 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 2088 &stats->tx_excess_defers, "Frames with excessive derferrals"); 2089 STE_SYSCTL_STAT_ADD32(ctx, child, "abort", 2090 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 2091 } 2092 2093 #undef STE_SYSCTL_STAT_ADD32 2094 #undef STE_SYSCTL_STAT_ADD64 2095 2096 static void 2097 ste_setwol(struct ste_softc *sc) 2098 { 2099 if_t ifp; 2100 uint16_t pmstat; 2101 uint8_t val; 2102 int pmc; 2103 2104 STE_LOCK_ASSERT(sc); 2105 2106 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) != 0) { 2107 /* Disable WOL. */ 2108 CSR_READ_1(sc, STE_WAKE_EVENT); 2109 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0); 2110 return; 2111 } 2112 2113 ifp = sc->ste_ifp; 2114 val = CSR_READ_1(sc, STE_WAKE_EVENT); 2115 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 2116 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 2117 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2118 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB; 2119 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 2120 /* Request PME. */ 2121 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2); 2122 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2123 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2124 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2125 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2126 } 2127