1 /*- 2 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/bus.h> 29 #include <sys/kernel.h> 30 #include <sys/lock.h> 31 #include <sys/module.h> 32 #include <sys/mutex.h> 33 #include <sys/rman.h> 34 #include <sys/resource.h> 35 #include <machine/bus.h> 36 37 #include <dev/ofw/ofw_bus.h> 38 #include <dev/ofw/ofw_bus_subr.h> 39 40 #include <dev/spibus/spi.h> 41 #include <dev/spibus/spibusvar.h> 42 43 #include <dev/clk/clk.h> 44 #include <dev/hwreset/hwreset.h> 45 46 #include "spibus_if.h" 47 48 #define AW_SPI_GCR 0x04 /* Global Control Register */ 49 #define AW_SPI_GCR_EN (1 << 0) /* ENable */ 50 #define AW_SPI_GCR_MODE_MASTER (1 << 1) /* 1 = Master, 0 = Slave */ 51 #define AW_SPI_GCR_TP_EN (1 << 7) /* 1 = Stop transmit when FIFO is full */ 52 #define AW_SPI_GCR_SRST (1 << 31) /* Soft Reset */ 53 54 #define AW_SPI_TCR 0x08 /* Transfer Control register */ 55 #define AW_SPI_TCR_XCH (1 << 31) /* Initiate transfer */ 56 #define AW_SPI_TCR_SDDM (1 << 14) /* Sending Delay Data Mode */ 57 #define AW_SPI_TCR_SDM (1 << 13) /* Master Sample Data Mode */ 58 #define AW_SPI_TCR_FBS (1 << 12) /* First Transmit Bit Select (1 == LSB) */ 59 #define AW_SPI_TCR_SDC (1 << 11) /* Master Sample Data Control */ 60 #define AW_SPI_TCR_RPSM (1 << 10) /* Rapid Mode Select */ 61 #define AW_SPI_TCR_DDB (1 << 9) /* Dummy Burst Type */ 62 #define AW_SPI_TCR_SSSEL_MASK 0x30 /* Chip select */ 63 #define AW_SPI_TCR_SSSEL_SHIFT 4 64 #define AW_SPI_TCR_SS_LEVEL (1 << 7) /* 1 == CS High */ 65 #define AW_SPI_TCR_SS_OWNER (1 << 6) /* 1 == Software controlled */ 66 #define AW_SPI_TCR_SPOL (1 << 2) /* 1 == Active low */ 67 #define AW_SPI_TCR_CPOL (1 << 1) /* 1 == Active low */ 68 #define AW_SPI_TCR_CPHA (1 << 0) /* 1 == Phase 1 */ 69 70 #define AW_SPI_IER 0x10 /* Interrupt Control Register */ 71 #define AW_SPI_IER_SS (1 << 13) /* Chip select went from valid to invalid */ 72 #define AW_SPI_IER_TC (1 << 12) /* Transfer complete */ 73 #define AW_SPI_IER_TF_UDR (1 << 11) /* TXFIFO underrun */ 74 #define AW_SPI_IER_TF_OVF (1 << 10) /* TXFIFO overrun */ 75 #define AW_SPI_IER_RF_UDR (1 << 9) /* RXFIFO underrun */ 76 #define AW_SPI_IER_RF_OVF (1 << 8) /* RXFIFO overrun */ 77 #define AW_SPI_IER_TF_FULL (1 << 6) /* TXFIFO Full */ 78 #define AW_SPI_IER_TF_EMP (1 << 5) /* TXFIFO Empty */ 79 #define AW_SPI_IER_TF_ERQ (1 << 4) /* TXFIFO Empty Request */ 80 #define AW_SPI_IER_RF_FULL (1 << 2) /* RXFIFO Full */ 81 #define AW_SPI_IER_RF_EMP (1 << 1) /* RXFIFO Empty */ 82 #define AW_SPI_IER_RF_RDY (1 << 0) /* RXFIFO Ready Request */ 83 84 #define AW_SPI_ISR 0x14 /* Interrupt Status Register */ 85 86 #define AW_SPI_FCR 0x18 /* FIFO Control Register */ 87 #define AW_SPI_FCR_TX_RST (1 << 31) /* Reset TX FIFO */ 88 #define AW_SPI_FCR_TX_TRIG_MASK 0xFF0000 /* TX FIFO Trigger level */ 89 #define AW_SPI_FCR_TX_TRIG_SHIFT 16 90 #define AW_SPI_FCR_RX_RST (1 << 15) /* Reset RX FIFO */ 91 #define AW_SPI_FCR_RX_TRIG_MASK 0xFF /* RX FIFO Trigger level */ 92 #define AW_SPI_FCR_RX_TRIG_SHIFT 0 93 94 #define AW_SPI_FSR 0x1C /* FIFO Status Register */ 95 #define AW_SPI_FSR_TB_WR (1 << 31) 96 #define AW_SPI_FSR_TB_CNT_MASK 0x70000000 97 #define AW_SPI_FSR_TB_CNT_SHIFT 28 98 #define AW_SPI_FSR_TF_CNT_MASK 0xFF0000 99 #define AW_SPI_FSR_TF_CNT_SHIFT 16 100 #define AW_SPI_FSR_RB_WR (1 << 15) 101 #define AW_SPI_FSR_RB_CNT_MASK 0x7000 102 #define AW_SPI_FSR_RB_CNT_SHIFT 12 103 #define AW_SPI_FSR_RF_CNT_MASK 0xFF 104 #define AW_SPI_FSR_RF_CNT_SHIFT 0 105 106 #define AW_SPI_WCR 0x20 /* Wait Clock Counter Register */ 107 108 #define AW_SPI_CCR 0x24 /* Clock Rate Control Register */ 109 #define AW_SPI_CCR_DRS (1 << 12) /* Clock divider select */ 110 #define AW_SPI_CCR_CDR1_MASK 0xF00 111 #define AW_SPI_CCR_CDR1_SHIFT 8 112 #define AW_SPI_CCR_CDR2_MASK 0xFF 113 #define AW_SPI_CCR_CDR2_SHIFT 0 114 115 #define AW_SPI_MBC 0x30 /* Burst Counter Register */ 116 #define AW_SPI_MTC 0x34 /* Transmit Counter Register */ 117 #define AW_SPI_BCC 0x38 /* Burst Control Register */ 118 #define AW_SPI_MDMA_CTL 0x88 /* Normal DMA Control Register */ 119 #define AW_SPI_TXD 0x200 /* TX Data Register */ 120 #define AW_SPI_RDX 0x300 /* RX Data Register */ 121 122 #define AW_SPI_MAX_CS 4 123 #define AW_SPI_FIFO_SIZE 64 124 125 static struct ofw_compat_data compat_data[] = { 126 { "allwinner,sun8i-h3-spi", 1 }, 127 { NULL, 0 } 128 }; 129 130 static struct resource_spec aw_spi_spec[] = { 131 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 132 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 133 { -1, 0 } 134 }; 135 136 struct aw_spi_softc { 137 device_t dev; 138 device_t spibus; 139 struct resource *res[2]; 140 struct mtx mtx; 141 clk_t clk_ahb; 142 clk_t clk_mod; 143 uint64_t mod_freq; 144 hwreset_t rst_ahb; 145 void * intrhand; 146 int transfer; 147 148 uint8_t *rxbuf; 149 uint32_t rxcnt; 150 uint8_t *txbuf; 151 uint32_t txcnt; 152 uint32_t txlen; 153 uint32_t rxlen; 154 }; 155 156 #define AW_SPI_LOCK(sc) mtx_lock(&(sc)->mtx) 157 #define AW_SPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 158 #define AW_SPI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 159 #define AW_SPI_READ_1(sc, reg) bus_read_1((sc)->res[0], (reg)) 160 #define AW_SPI_WRITE_1(sc, reg, val) bus_write_1((sc)->res[0], (reg), (val)) 161 #define AW_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) 162 #define AW_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 163 164 static int aw_spi_probe(device_t dev); 165 static int aw_spi_attach(device_t dev); 166 static int aw_spi_detach(device_t dev); 167 static int aw_spi_intr(void *arg); 168 169 static int 170 aw_spi_probe(device_t dev) 171 { 172 if (!ofw_bus_status_okay(dev)) 173 return (ENXIO); 174 175 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 176 return (ENXIO); 177 178 device_set_desc(dev, "Allwinner SPI"); 179 return (BUS_PROBE_DEFAULT); 180 } 181 182 static int 183 aw_spi_attach(device_t dev) 184 { 185 struct aw_spi_softc *sc; 186 int error; 187 188 sc = device_get_softc(dev); 189 sc->dev = dev; 190 191 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 192 193 if (bus_alloc_resources(dev, aw_spi_spec, sc->res) != 0) { 194 device_printf(dev, "cannot allocate resources for device\n"); 195 error = ENXIO; 196 goto fail; 197 } 198 199 if (bus_setup_intr(dev, sc->res[1], 200 INTR_TYPE_MISC | INTR_MPSAFE, aw_spi_intr, NULL, sc, 201 &sc->intrhand)) { 202 bus_release_resources(dev, aw_spi_spec, sc->res); 203 device_printf(dev, "cannot setup interrupt handler\n"); 204 return (ENXIO); 205 } 206 207 /* De-assert reset */ 208 if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst_ahb) == 0) { 209 error = hwreset_deassert(sc->rst_ahb); 210 if (error != 0) { 211 device_printf(dev, "cannot de-assert reset\n"); 212 goto fail; 213 } 214 } 215 216 /* Activate the module clock. */ 217 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->clk_ahb); 218 if (error != 0) { 219 device_printf(dev, "cannot get ahb clock\n"); 220 goto fail; 221 } 222 error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_mod); 223 if (error != 0) { 224 device_printf(dev, "cannot get mod clock\n"); 225 goto fail; 226 } 227 error = clk_enable(sc->clk_ahb); 228 if (error != 0) { 229 device_printf(dev, "cannot enable ahb clock\n"); 230 goto fail; 231 } 232 error = clk_enable(sc->clk_mod); 233 if (error != 0) { 234 device_printf(dev, "cannot enable mod clock\n"); 235 goto fail; 236 } 237 238 sc->spibus = device_add_child(dev, "spibus", DEVICE_UNIT_ANY); 239 240 bus_attach_children(dev); 241 return (0); 242 243 fail: 244 aw_spi_detach(dev); 245 return (error); 246 } 247 248 static int 249 aw_spi_detach(device_t dev) 250 { 251 struct aw_spi_softc *sc; 252 253 sc = device_get_softc(dev); 254 255 bus_generic_detach(sc->dev); 256 if (sc->spibus != NULL) 257 device_delete_child(dev, sc->spibus); 258 259 if (sc->clk_mod != NULL) 260 clk_release(sc->clk_mod); 261 if (sc->clk_ahb) 262 clk_release(sc->clk_ahb); 263 if (sc->rst_ahb) 264 hwreset_assert(sc->rst_ahb); 265 266 if (sc->intrhand != NULL) 267 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand); 268 269 bus_release_resources(dev, aw_spi_spec, sc->res); 270 mtx_destroy(&sc->mtx); 271 272 return (0); 273 } 274 275 static phandle_t 276 aw_spi_get_node(device_t bus, device_t dev) 277 { 278 279 return ofw_bus_get_node(bus); 280 } 281 282 static void 283 aw_spi_setup_mode(struct aw_spi_softc *sc, uint32_t mode) 284 { 285 uint32_t reg; 286 287 /* We only support master mode */ 288 reg = AW_SPI_READ_4(sc, AW_SPI_GCR); 289 reg |= AW_SPI_GCR_MODE_MASTER; 290 AW_SPI_WRITE_4(sc, AW_SPI_GCR, reg); 291 292 /* Setup the modes */ 293 reg = AW_SPI_READ_4(sc, AW_SPI_TCR); 294 if (mode & SPIBUS_MODE_CPHA) 295 reg |= AW_SPI_TCR_CPHA; 296 if (mode & SPIBUS_MODE_CPOL) 297 reg |= AW_SPI_TCR_CPOL; 298 299 AW_SPI_WRITE_4(sc, AW_SPI_TCR, reg); 300 } 301 302 static void 303 aw_spi_setup_cs(struct aw_spi_softc *sc, uint32_t cs, bool low) 304 { 305 uint32_t reg; 306 307 /* Setup CS */ 308 reg = AW_SPI_READ_4(sc, AW_SPI_TCR); 309 reg &= ~(AW_SPI_TCR_SSSEL_MASK); 310 reg |= cs << AW_SPI_TCR_SSSEL_SHIFT; 311 reg |= AW_SPI_TCR_SS_OWNER; 312 if (low) 313 reg &= ~(AW_SPI_TCR_SS_LEVEL); 314 else 315 reg |= AW_SPI_TCR_SS_LEVEL; 316 317 AW_SPI_WRITE_4(sc, AW_SPI_TCR, reg); 318 } 319 320 static uint64_t 321 aw_spi_clock_test_cdr1(struct aw_spi_softc *sc, uint64_t clock, uint32_t *ccr) 322 { 323 uint64_t cur, best = 0; 324 int i, max, best_div; 325 326 max = AW_SPI_CCR_CDR1_MASK >> AW_SPI_CCR_CDR1_SHIFT; 327 for (i = 0; i < max; i++) { 328 cur = sc->mod_freq / (1 << i); 329 if ((clock - cur) < (clock - best)) { 330 best = cur; 331 best_div = i; 332 } 333 } 334 335 *ccr = (best_div << AW_SPI_CCR_CDR1_SHIFT); 336 return (best); 337 } 338 339 static uint64_t 340 aw_spi_clock_test_cdr2(struct aw_spi_softc *sc, uint64_t clock, uint32_t *ccr) 341 { 342 uint64_t cur, best = 0; 343 int i, max, best_div; 344 345 max = ((AW_SPI_CCR_CDR2_MASK) >> AW_SPI_CCR_CDR2_SHIFT); 346 for (i = 0; i < max; i++) { 347 cur = sc->mod_freq / (2 * i + 1); 348 if ((clock - cur) < (clock - best)) { 349 best = cur; 350 best_div = i; 351 } 352 } 353 354 *ccr = AW_SPI_CCR_DRS | (best_div << AW_SPI_CCR_CDR2_SHIFT); 355 return (best); 356 } 357 358 static void 359 aw_spi_setup_clock(struct aw_spi_softc *sc, uint64_t clock) 360 { 361 uint64_t best_ccr1, best_ccr2; 362 uint32_t ccr, ccr1, ccr2; 363 364 best_ccr1 = aw_spi_clock_test_cdr1(sc, clock, &ccr1); 365 best_ccr2 = aw_spi_clock_test_cdr2(sc, clock, &ccr2); 366 367 if (best_ccr1 == clock) { 368 ccr = ccr1; 369 } else if (best_ccr2 == clock) { 370 ccr = ccr2; 371 } else { 372 if ((clock - best_ccr1) < (clock - best_ccr2)) 373 ccr = ccr1; 374 else 375 ccr = ccr2; 376 } 377 378 AW_SPI_WRITE_4(sc, AW_SPI_CCR, ccr); 379 } 380 381 static inline void 382 aw_spi_fill_txfifo(struct aw_spi_softc *sc) 383 { 384 uint32_t reg, txcnt; 385 int i; 386 387 if (sc->txcnt == sc->txlen) 388 return; 389 390 reg = AW_SPI_READ_4(sc, AW_SPI_FSR); 391 reg &= AW_SPI_FSR_TF_CNT_MASK; 392 txcnt = reg >> AW_SPI_FSR_TF_CNT_SHIFT; 393 394 for (i = 0; i < (AW_SPI_FIFO_SIZE - txcnt); i++) { 395 AW_SPI_WRITE_1(sc, AW_SPI_TXD, sc->txbuf[sc->txcnt++]); 396 if (sc->txcnt == sc->txlen) 397 break; 398 } 399 400 return; 401 } 402 403 static inline void 404 aw_spi_read_rxfifo(struct aw_spi_softc *sc) 405 { 406 uint32_t reg; 407 uint8_t val; 408 int i; 409 410 if (sc->rxcnt == sc->rxlen) 411 return; 412 413 reg = AW_SPI_READ_4(sc, AW_SPI_FSR); 414 reg = (reg & AW_SPI_FSR_RF_CNT_MASK) >> AW_SPI_FSR_RF_CNT_SHIFT; 415 416 for (i = 0; i < reg; i++) { 417 val = AW_SPI_READ_1(sc, AW_SPI_RDX); 418 if (sc->rxcnt < sc->rxlen) 419 sc->rxbuf[sc->rxcnt++] = val; 420 } 421 } 422 423 static int 424 aw_spi_intr(void *arg) 425 { 426 struct aw_spi_softc *sc; 427 uint32_t intr; 428 429 sc = (struct aw_spi_softc *)arg; 430 431 intr = AW_SPI_READ_4(sc, AW_SPI_ISR); 432 433 if (intr & AW_SPI_IER_RF_RDY) 434 aw_spi_read_rxfifo(sc); 435 436 if (intr & AW_SPI_IER_TF_ERQ) { 437 aw_spi_fill_txfifo(sc); 438 439 /* 440 * If we don't have anything else to write 441 * disable TXFifo interrupts 442 */ 443 if (sc->txcnt == sc->txlen) 444 AW_SPI_WRITE_4(sc, AW_SPI_IER, AW_SPI_IER_TC | 445 AW_SPI_IER_RF_RDY); 446 } 447 448 if (intr & AW_SPI_IER_TC) { 449 /* read the rest of the data from the fifo */ 450 aw_spi_read_rxfifo(sc); 451 452 /* Disable the interrupts */ 453 AW_SPI_WRITE_4(sc, AW_SPI_IER, 0); 454 sc->transfer = 0; 455 wakeup(sc); 456 } 457 458 /* Clear Interrupts */ 459 AW_SPI_WRITE_4(sc, AW_SPI_ISR, intr); 460 return (intr != 0 ? FILTER_HANDLED : FILTER_STRAY); 461 } 462 463 static int 464 aw_spi_xfer(struct aw_spi_softc *sc, void *rxbuf, void *txbuf, uint32_t txlen, uint32_t rxlen) 465 { 466 uint32_t reg; 467 int error = 0, timeout; 468 469 sc->rxbuf = rxbuf; 470 sc->rxcnt = 0; 471 sc->txbuf = txbuf; 472 sc->txcnt = 0; 473 sc->txlen = txlen; 474 sc->rxlen = rxlen; 475 476 /* Reset the FIFOs */ 477 AW_SPI_WRITE_4(sc, AW_SPI_FCR, AW_SPI_FCR_TX_RST | AW_SPI_FCR_RX_RST); 478 479 for (timeout = 1000; timeout > 0; timeout--) { 480 reg = AW_SPI_READ_4(sc, AW_SPI_FCR); 481 if (reg == 0) 482 break; 483 } 484 if (timeout == 0) { 485 device_printf(sc->dev, "Cannot reset the FIFOs\n"); 486 return (EIO); 487 } 488 489 /* 490 * Set the TX FIFO threshold to 3/4-th the size and 491 * the RX FIFO one to 1/4-th. 492 */ 493 AW_SPI_WRITE_4(sc, AW_SPI_FCR, 494 ((3 * AW_SPI_FIFO_SIZE / 4) << AW_SPI_FCR_TX_TRIG_SHIFT) | 495 ((AW_SPI_FIFO_SIZE / 4) << AW_SPI_FCR_RX_TRIG_SHIFT)); 496 497 /* Write the counters */ 498 AW_SPI_WRITE_4(sc, AW_SPI_MBC, txlen); 499 AW_SPI_WRITE_4(sc, AW_SPI_MTC, txlen); 500 AW_SPI_WRITE_4(sc, AW_SPI_BCC, txlen); 501 502 /* First fill */ 503 aw_spi_fill_txfifo(sc); 504 505 /* Start transmit */ 506 reg = AW_SPI_READ_4(sc, AW_SPI_TCR); 507 reg |= AW_SPI_TCR_XCH; 508 AW_SPI_WRITE_4(sc, AW_SPI_TCR, reg); 509 510 /* 511 * Enable interrupts for : 512 * Transmit complete 513 * TX Fifo is below its trigger threshold 514 * RX Fifo is above its trigger threshold 515 */ 516 AW_SPI_WRITE_4(sc, AW_SPI_IER, AW_SPI_IER_TC | 517 AW_SPI_IER_TF_ERQ | AW_SPI_IER_RF_RDY); 518 519 sc->transfer = 1; 520 521 while (error == 0 && sc->transfer != 0) 522 error = msleep(sc, &sc->mtx, 0, "aw_spi", 10 * hz); 523 524 return (0); 525 } 526 527 static int 528 aw_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 529 { 530 struct aw_spi_softc *sc; 531 uint32_t cs, mode, clock, reg; 532 int err = 0; 533 534 sc = device_get_softc(dev); 535 536 spibus_get_cs(child, &cs); 537 spibus_get_clock(child, &clock); 538 spibus_get_mode(child, &mode); 539 540 /* The minimum divider is 2 so set the clock at twice the needed speed */ 541 clk_set_freq(sc->clk_mod, 2 * clock, CLK_SET_ROUND_DOWN); 542 clk_get_freq(sc->clk_mod, &sc->mod_freq); 543 if (cs >= AW_SPI_MAX_CS) { 544 device_printf(dev, "Invalid cs %d\n", cs); 545 return (EINVAL); 546 } 547 548 mtx_lock(&sc->mtx); 549 550 /* Enable and reset the module */ 551 reg = AW_SPI_READ_4(sc, AW_SPI_GCR); 552 reg |= AW_SPI_GCR_EN | AW_SPI_GCR_SRST; 553 AW_SPI_WRITE_4(sc, AW_SPI_GCR, reg); 554 555 /* Setup clock, CS and mode */ 556 aw_spi_setup_clock(sc, clock); 557 aw_spi_setup_mode(sc, mode); 558 if (cs & SPIBUS_CS_HIGH) 559 aw_spi_setup_cs(sc, cs, false); 560 else 561 aw_spi_setup_cs(sc, cs, true); 562 563 /* xfer */ 564 err = 0; 565 if (cmd->tx_cmd_sz > 0) 566 err = aw_spi_xfer(sc, cmd->rx_cmd, cmd->tx_cmd, 567 cmd->tx_cmd_sz, cmd->rx_cmd_sz); 568 if (cmd->tx_data_sz > 0 && err == 0) 569 err = aw_spi_xfer(sc, cmd->rx_data, cmd->tx_data, 570 cmd->tx_data_sz, cmd->rx_data_sz); 571 572 if (cs & SPIBUS_CS_HIGH) 573 aw_spi_setup_cs(sc, cs, true); 574 else 575 aw_spi_setup_cs(sc, cs, false); 576 577 /* Disable the module */ 578 reg = AW_SPI_READ_4(sc, AW_SPI_GCR); 579 reg &= ~AW_SPI_GCR_EN; 580 AW_SPI_WRITE_4(sc, AW_SPI_GCR, reg); 581 582 mtx_unlock(&sc->mtx); 583 584 return (err); 585 } 586 587 static device_method_t aw_spi_methods[] = { 588 /* Device interface */ 589 DEVMETHOD(device_probe, aw_spi_probe), 590 DEVMETHOD(device_attach, aw_spi_attach), 591 DEVMETHOD(device_detach, aw_spi_detach), 592 593 /* spibus_if */ 594 DEVMETHOD(spibus_transfer, aw_spi_transfer), 595 596 /* ofw_bus_if */ 597 DEVMETHOD(ofw_bus_get_node, aw_spi_get_node), 598 599 DEVMETHOD_END 600 }; 601 602 static driver_t aw_spi_driver = { 603 "aw_spi", 604 aw_spi_methods, 605 sizeof(struct aw_spi_softc), 606 }; 607 608 DRIVER_MODULE(aw_spi, simplebus, aw_spi_driver, 0, 0); 609 DRIVER_MODULE(ofw_spibus, aw_spi, ofw_spibus_driver, 0, 0); 610 MODULE_DEPEND(aw_spi, ofw_spibus, 1, 1, 1); 611 SIMPLEBUS_PNP_INFO(compat_data); 612