1 /*- 2 * Copyright (c) 2001 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* ------------------------------------------------------------------------- */ 30 /* PCI Configuration Register Offsets */ 31 32 #define SV_PCI_COMPAT 0x10 33 #define SV_PCI_ENHANCED 0x14 34 #define SV_PCI_FMSYNTH 0x18 35 #define SV_PCI_MIDI 0x1c 36 #define SV_PCI_GAMES 0x20 37 #define SV_PCI_DMAA 0x40 38 #define SV_PCI_DMAC 0x48 39 40 #define SV_PCI_DMAA_SIZE 0x10 41 #define SV_PCI_DMAA_ALIGN 0x10 42 #define SV_PCI_DMAC_SIZE 0x10 43 #define SV_PCI_DMAC_ALIGN 0x10 44 45 #define SV_PCI_ENHANCED_SIZE 0x08 46 47 #define SV_PCI_DMA_ENABLE 0x00000001 48 #define SV_PCI_DMA_EXTENDED 0x00000008 49 50 /* ------------------------------------------------------------------------- */ 51 /* DMA Configuration Registers */ 52 53 #define SV_DMA_ADDR 0x00 54 #define SV_DMA_COUNT 0x04 55 56 #define SV_DMA_MODE 0x0B 57 #define SV_DMA_MODE_AUTO 0x10 58 #define SV_DMA_MODE_RD 0x04 59 #define SV_DMA_MODE_WR 0x08 60 61 /* ------------------------------------------------------------------------- */ 62 /* Enhanced Mode Configuration Registers */ 63 64 #define SV_CM_CONTROL 0x00 65 #define SV_CM_CONTROL_ENHANCED 0x01 66 #define SV_CM_CONTROL_TEST 0x02 67 #define SV_CM_CONTROL_REVERB 0x04 68 #define SV_CM_CONTROL_PWS 0x08 69 #define SV_CM_CONTROL_INTA 0x20 70 #define SV_CM_CONTROL_RESET 0x80 71 72 #define SV_CM_IMR 0x01 73 #define SV_CM_IMR_AMSK 0x01 74 #define SV_CM_IMR_CMSK 0x04 75 #define SV_CM_IMR_SMSK 0x08 76 #define SV_CM_IMR_UDM 0x40 77 #define SV_CM_IMR_MIDM 0x80 78 79 #define SV_CM_STATUS 0x02 80 #define SV_CM_STATUS_AINT 0x01 81 #define SV_CM_STATUS_CINT 0x04 82 #define SV_CM_STATUS_SINT 0x08 83 #define SV_CM_STATUS_UDI 0x40 84 #define SV_CM_STATUS_MI 0x80 85 86 #define SV_CM_INDEX 0x04 87 #define SV_CM_INDEX_MASK 0x3f 88 #define SV_CM_INDEX_MCE 0x40 89 #define SV_CM_INDEX_TRD 0x80 90 91 #define SV_CM_DATA 0x05 92 93 /* ------------------------------------------------------------------------- */ 94 /* Indexed Codec/Mixer Registers (left channels were applicable) */ 95 96 #define SV_REG_ADC_INPUT 0x00 97 #define SV_INPUT_GAIN_MASK 0x0f 98 #define SV_INPUT_MICGAIN 0x10 99 #define SV_INPUT_CD 0x20 100 #define SV_INPUT_DAC 0x40 101 #define SV_INPUT_AUX2 0x60 102 #define SV_INPUT_LINE 0x80 103 #define SV_INPUT_AUX1 0xa0 104 #define SV_INPUT_MIC 0xc0 105 #define SV_INPUT_MIXOUT 0xe0 106 107 #define SV_REG_AUX1 0x02 108 #define SV_REG_CD 0x04 109 #define SV_REG_LINE 0x06 110 #define SV_REG_MIC 0x08 111 #define SV_REG_SYNTH 0x0a 112 #define SV_REG_AUX2 0x0c 113 #define SV_REG_MIX 0x0e 114 #define SV_REG_PCM 0x10 115 #define SV_DEFAULT_MAX 0x1f 116 #define SV_ADC_MAX 0x0f 117 #define SV_MIC_MAX 0x0f 118 #define SV_PCM_MAX 0x3f 119 #define SV_MUTE 0x80 120 121 #define SV_REG_FORMAT 0x12 122 #define SV_AFMT_MONO 0x00 123 #define SV_AFMT_STEREO 0x01 124 #define SV_AFMT_S16 0x02 125 #define SV_AFMT_U8 0x00 126 #define SV_AFMT_DMAA(x) (x) 127 #define SV_AFMT_DMAA_MSK 0x03 128 #define SV_AFMT_DMAC(x) ((x) << 4) 129 #define SV_AFMT_DMAC_MSK 0x30 130 131 #define SV_REG_ENABLE 0x13 132 #define SV_PLAY_ENABLE 0x01 133 #define SV_RECORD_ENABLE 0x02 134 #define SV_PLAYBACK_PAUSE 0x04 135 136 #define SV_REG_REVISION 0x15 137 138 #define SV_REG_LOOPBACK 0x16 139 #define SV_LOOPBACK_ENABLE 0x01 140 #define SV_LOOPBACK_MAX 0x3f 141 #define SV_LOOPBACK_LEVEL(x) ((x) << 2) 142 143 #define SV_REG_DMAA_COUNT_HI 0x18 144 #define SV_REG_DMAA_COUNT_LO 0x19 145 #define SV_REG_DMAC_COUNT_HI 0x1c 146 #define SV_REG_DMAC_COUNT_LO 0x1d 147 148 #define SV_REG_PCM_SAMPLING_LO 0x1e 149 #define SV_REG_PCM_SAMPLING_HI 0x1f 150 151 #define SV_REG_SYN_SAMPLING_LO 0x20 152 #define SV_REG_SYN_SAMPLING_HI 0x21 153 154 #define SV_REG_CLOCK_SOURCE 0x22 155 #define SV_CLOCK_ALTERNATE 0x10 156 #define SV_REG_ALT_RATE 0x23 157 158 #define SV_REG_ADC_PLLM 0x24 159 #define SV_REG_ADC_PLLN 0x25 160 #define SV_ADC_PLLN(x) ((x) & 0x1f) 161 #define SV_ADC_PLLR(x) ((x) << 5) 162 163 #define SV_REG_SYNTH_PLLM 0x26 164 #define SV_REG_SYNTH_PLLN 0x27 165 #define SV_SYNTH_PLLN(x) ((x) & 0x1f) 166 #define SV_SYNTH_PLLR(x) ((x) << 5) 167 168 #define SV_REG_SRS_SPACE 0x2c 169 #define SV_SRS_SPACE_100 0x00 170 #define SV_SRS_SPACE_75 0x01 171 #define SV_SRS_SPACE_50 0x02 172 #define SV_SRS_SPACE_25 0x03 173 #define SV_SRS_SPACE_0 0x04 174 #define SV_SRS_DISABLED 0x80 175 176 #define SV_REG_SRS_CENTER 0x2d 177 #define SV_SRS_CENTER_100 0x00 178 #define SV_SRS_CENTER_75 0x01 179 #define SV_SRS_CENTER_50 0x02 180 #define SV_SRS_CENTER_25 0x03 181 #define SV_SRS_CENTER_0 0x04 182 183 #define SV_REG_ANALOG_PWR 0x30 184 #define SV_ANALOG_OFF_DAC 0x01 185 #define SV_ANALOG_OFF_ADC 0x08 186 #define SV_ANALOG_OFF_MIX 0x10 187 #define SV_ANALOG_OFF_SRS 0x20 188 #define SV_ANALOG_OFF_SPLL 0x40 189 #define SV_ANALOG_OFF_APLL 0x80 190 #define SV_ANALOG_OFF 0xf9 191 192 #define SV_REG_DIGITAL_PWR 0x31 193 #define SV_DIGITAL_OFF_SYN 0x01 194 #define SV_DIGITAL_OFF_MU 0x02 195 #define SV_DIGITAL_OFF_GP 0x04 196 #define SV_DIGITAL_OFF_BI 0x08 197 #define SV_DIGITAL_OFF 0x0f 198 199 /* ------------------------------------------------------------------------- */ 200 /* ADC PLL constants */ 201 202 #define SV_F_SCALE 512 203 #define SV_F_REF 24576000 204