1 /*- 2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org> 3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Maestro-3/Allegro FreeBSD pcm sound driver 30 * 31 * executive status summary: 32 * (+) /dev/dsp multiple concurrent play channels. 33 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit). 34 * (+) /dev/mixer sets left/right volumes. 35 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel 36 * (+) apm suspend/resume works, and works properly!. 37 * (-) hardware volme controls don't work =-( 38 * (-) setblocksize() does nothing. 39 * 40 * The real credit goes to: 41 * 42 * Zach Brown for his Linux driver core and helpful technical comments. 43 * <zab@zabbo.net>, http://www.zabbo.net/maestro3 44 * 45 * Cameron Grant created the pcm framework used here nearly verbatim. 46 * <cg@freebsd.org>, http://people.freebsd.org/~cg/template.c 47 * 48 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference. 49 * <taku@cent.saitama-u.ac.jp> 50 * 51 * ESS docs explained a few magic registers and numbers. 52 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz 53 */ 54 55 #include <dev/sound/pcm/sound.h> 56 #include <dev/sound/pcm/ac97.h> 57 58 #include <pci/pcireg.h> 59 #include <pci/pcivar.h> 60 61 #include <gnu/dev/sound/pci/maestro3_reg.h> 62 #include <gnu/dev/sound/pci/maestro3_dsp.h> 63 64 SND_DECLARE_FILE("$FreeBSD$"); 65 66 /* -------------------------------------------------------------------- */ 67 68 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1}; 69 #ifndef M3_DEBUG_LEVEL 70 #define M3_DEBUG_LEVEL NONE 71 #endif 72 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}} 73 74 /* -------------------------------------------------------------------- */ 75 enum { 76 ESS_ALLEGRO_1, 77 ESS_MAESTRO3 78 }; 79 80 static struct m3_card_type { 81 u_int32_t pci_id; int which; int delay1; int delay2; char *name; 82 } m3_card_types[] = { 83 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" }, 84 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, 85 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, 86 { 0, 0, 0, 0, NULL } 87 }; 88 89 #define M3_BUFSIZE_DEFAULT 4096 90 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */ 91 #define M3_RCHANS 1 92 #define M3_MAXADDR ((1 << 27) - 1) 93 94 struct sc_info; 95 96 struct sc_pchinfo { 97 u_int32_t spd; 98 u_int32_t fmt; 99 struct snd_dbuf *buffer; 100 struct pcm_channel *channel; 101 struct sc_info *parent; 102 u_int32_t bufsize; 103 u_int32_t dac_data; 104 u_int32_t dac_idx; 105 u_int32_t active; 106 }; 107 108 struct sc_rchinfo { 109 u_int32_t spd; 110 u_int32_t fmt; 111 struct snd_dbuf *buffer; 112 struct pcm_channel *channel; 113 struct sc_info *parent; 114 u_int32_t bufsize; 115 u_int32_t adc_data; 116 u_int32_t adc_idx; 117 u_int32_t active; 118 }; 119 120 struct sc_info { 121 device_t dev; 122 u_int32_t type; 123 int which; 124 int delay1; 125 int delay2; 126 127 bus_space_tag_t st; 128 bus_space_handle_t sh; 129 bus_dma_tag_t parent_dmat; 130 131 struct resource *reg; 132 struct resource *irq; 133 int regtype; 134 int regid; 135 int irqid; 136 void *ih; 137 138 struct sc_pchinfo pch[M3_PCHANS]; 139 struct sc_rchinfo rch[M3_RCHANS]; 140 int pch_cnt; 141 int rch_cnt; 142 int pch_active_cnt; 143 unsigned int bufsz; 144 u_int16_t *savemem; 145 }; 146 147 /* -------------------------------------------------------------------- */ 148 149 /* play channel interface */ 150 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int); 151 static int m3_pchan_free(kobj_t, void *); 152 static int m3_pchan_setformat(kobj_t, void *, u_int32_t); 153 static int m3_pchan_setspeed(kobj_t, void *, u_int32_t); 154 static int m3_pchan_setblocksize(kobj_t, void *, u_int32_t); 155 static int m3_pchan_trigger(kobj_t, void *, int); 156 static int m3_pchan_getptr(kobj_t, void *); 157 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *); 158 159 /* record channel interface */ 160 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int); 161 static int m3_rchan_free(kobj_t, void *); 162 static int m3_rchan_setformat(kobj_t, void *, u_int32_t); 163 static int m3_rchan_setspeed(kobj_t, void *, u_int32_t); 164 static int m3_rchan_setblocksize(kobj_t, void *, u_int32_t); 165 static int m3_rchan_trigger(kobj_t, void *, int); 166 static int m3_rchan_getptr(kobj_t, void *); 167 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *); 168 169 /* talk to the codec - called from ac97.c */ 170 static int m3_initcd(kobj_t, void *); 171 static int m3_rdcd(kobj_t, void *, int); 172 static int m3_wrcd(kobj_t, void *, int, u_int32_t); 173 174 /* stuff */ 175 static void m3_intr(void *); 176 static int m3_power(struct sc_info *, int); 177 static int m3_init(struct sc_info *); 178 static int m3_uninit(struct sc_info *); 179 static u_int8_t m3_assp_halt(struct sc_info *); 180 static void m3_config(struct sc_info *); 181 static void m3_amp_enable(struct sc_info *); 182 static void m3_enable_ints(struct sc_info *); 183 static void m3_codec_reset(struct sc_info *); 184 185 /* -------------------------------------------------------------------- */ 186 /* Codec descriptor */ 187 static kobj_method_t m3_codec_methods[] = { 188 KOBJMETHOD(ac97_init, m3_initcd), 189 KOBJMETHOD(ac97_read, m3_rdcd), 190 KOBJMETHOD(ac97_write, m3_wrcd), 191 { 0, 0 } 192 }; 193 AC97_DECLARE(m3_codec); 194 195 /* -------------------------------------------------------------------- */ 196 /* channel descriptors */ 197 198 static u_int32_t m3_playfmt[] = { 199 AFMT_U8, 200 AFMT_STEREO | AFMT_U8, 201 AFMT_S16_LE, 202 AFMT_STEREO | AFMT_S16_LE, 203 0 204 }; 205 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0}; 206 207 static kobj_method_t m3_pch_methods[] = { 208 KOBJMETHOD(channel_init, m3_pchan_init), 209 KOBJMETHOD(channel_setformat, m3_pchan_setformat), 210 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed), 211 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize), 212 KOBJMETHOD(channel_trigger, m3_pchan_trigger), 213 KOBJMETHOD(channel_getptr, m3_pchan_getptr), 214 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps), 215 KOBJMETHOD(channel_free, m3_pchan_free), 216 { 0, 0 } 217 }; 218 CHANNEL_DECLARE(m3_pch); 219 220 static u_int32_t m3_recfmt[] = { 221 AFMT_U8, 222 AFMT_STEREO | AFMT_U8, 223 AFMT_S16_LE, 224 AFMT_STEREO | AFMT_S16_LE, 225 0 226 }; 227 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0}; 228 229 static kobj_method_t m3_rch_methods[] = { 230 KOBJMETHOD(channel_init, m3_rchan_init), 231 KOBJMETHOD(channel_setformat, m3_rchan_setformat), 232 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed), 233 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize), 234 KOBJMETHOD(channel_trigger, m3_rchan_trigger), 235 KOBJMETHOD(channel_getptr, m3_rchan_getptr), 236 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps), 237 KOBJMETHOD(channel_free, m3_rchan_free), 238 { 0, 0 } 239 }; 240 CHANNEL_DECLARE(m3_rch); 241 242 /* -------------------------------------------------------------------- */ 243 /* some i/o convenience functions */ 244 245 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno) 246 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno) 247 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno) 248 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data) 249 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data) 250 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data) 251 #define m3_rd_assp_code(sc, index) \ 252 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index) 253 #define m3_wr_assp_code(sc, index, data) \ 254 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data) 255 #define m3_rd_assp_data(sc, index) \ 256 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index) 257 #define m3_wr_assp_data(sc, index, data) \ 258 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data) 259 260 static __inline u_int16_t 261 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index) 262 { 263 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); 264 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); 265 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA); 266 } 267 268 static __inline void 269 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index, 270 u_int16_t data) 271 { 272 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); 273 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); 274 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data); 275 } 276 277 static __inline int 278 m3_wait(struct sc_info *sc) 279 { 280 int i; 281 282 for (i=0 ; i<20 ; i++) { 283 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) { 284 return 0; 285 } 286 DELAY(2); 287 } 288 return -1; 289 } 290 291 /* -------------------------------------------------------------------- */ 292 /* ac97 codec */ 293 294 static int 295 m3_initcd(kobj_t kobj, void *devinfo) 296 { 297 struct sc_info *sc = (struct sc_info *)devinfo; 298 u_int32_t data; 299 300 M3_DEBUG(CALL, ("m3_initcd\n")); 301 302 /* init ac-link */ 303 304 data = m3_rd_1(sc, CODEC_COMMAND); 305 return ((data & 0x1) ? 0 : 1); 306 } 307 308 static int 309 m3_rdcd(kobj_t kobj, void *devinfo, int regno) 310 { 311 struct sc_info *sc = (struct sc_info *)devinfo; 312 u_int32_t data; 313 314 if (m3_wait(sc)) { 315 device_printf(sc->dev, "m3_rdcd timed out.\n"); 316 return -1; 317 } 318 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80); 319 DELAY(50); /* ac97 cycle = 20.8 usec */ 320 if (m3_wait(sc)) { 321 device_printf(sc->dev, "m3_rdcd timed out.\n"); 322 return -1; 323 } 324 data = m3_rd_2(sc, CODEC_DATA); 325 return data; 326 } 327 328 static int 329 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data) 330 { 331 struct sc_info *sc = (struct sc_info *)devinfo; 332 if (m3_wait(sc)) { 333 device_printf(sc->dev, "m3_wrcd timed out.\n"); 334 return -1;; 335 } 336 m3_wr_2(sc, CODEC_DATA, data); 337 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f); 338 DELAY(50); /* ac97 cycle = 20.8 usec */ 339 return 0; 340 } 341 342 /* -------------------------------------------------------------------- */ 343 /* play channel interface */ 344 345 #define LO(x) (((x) & 0x0000ffff) ) 346 #define HI(x) (((x) & 0xffff0000) >> 16) 347 348 static void * 349 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 350 { 351 struct sc_info *sc = devinfo; 352 struct sc_pchinfo *ch; 353 u_int32_t bus_addr, i; 354 355 int idx = sc->pch_cnt; /* dac instance number, no active reuse! */ 356 int data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + 357 (MINISRC_IN_BUFFER_SIZE & ~1) + 358 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; 359 int dac_data = 0x1100 + (data_bytes * idx); 360 361 int dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); 362 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); 363 int dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2); 364 int dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1; 365 366 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx)); 367 368 if (dir != PCMDIR_PLAY) { 369 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n"); 370 return NULL; 371 } 372 ch = &sc->pch[idx]; 373 374 ch->dac_idx = idx; 375 ch->dac_data = dac_data; 376 if (ch->dac_data + data_bytes/2 >= 0x1c00) { 377 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n"); 378 return NULL; 379 } 380 381 ch->buffer = b; 382 ch->parent = sc; 383 ch->channel = c; 384 ch->fmt = AFMT_U8; 385 ch->spd = DSP_DEFAULT_SPEED; 386 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1) { 387 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n"); 388 return NULL; 389 } 390 ch->bufsize = sndbuf_getsize(ch->buffer); 391 392 /* host dma buffer pointers */ 393 bus_addr = vtophys(sndbuf_getbuf(ch->buffer)); 394 if (bus_addr & 3) { 395 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n"); 396 bus_addr = (bus_addr + 4) & ~3; 397 } 398 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); 399 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); 400 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L, 401 LO(bus_addr + ch->bufsize)); 402 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H, 403 HI(bus_addr + ch->bufsize)); 404 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL, 405 LO(bus_addr)); 406 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH, 407 HI(bus_addr)); 408 409 /* dsp buffers */ 410 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); 411 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1, 412 dsp_in_buf + dsp_in_size/2); 413 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf); 414 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf); 415 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); 416 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1, 417 dsp_out_buf + dsp_out_size/2); 418 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); 419 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); 420 421 /* some per client initializers */ 422 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12, 423 ch->dac_data + 40 + 8); 424 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19, 425 0x400 + MINISRC_COEF_LOC); 426 /* enable or disable low pass filter? (0xff if rate> 45000) */ 427 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0); 428 /* tell it which way dma is going? */ 429 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL, 430 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + 431 DMAC_BLOCKF_SELECTOR); 432 433 /* set an armload of static initializers */ 434 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) { 435 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val); 436 } 437 438 /* put us in the packed task lists */ 439 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 440 (sc->pch_cnt + sc->rch_cnt), 441 ch->dac_data >> DP_SHIFT_COUNT); 442 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), 443 ch->dac_data >> DP_SHIFT_COUNT); 444 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt, 445 ch->dac_data >> DP_SHIFT_COUNT); 446 447 m3_pchan_trigger(NULL, ch, PCMTRIG_START); /* gotta start before stop */ 448 m3_pchan_trigger(NULL, ch, PCMTRIG_STOP); /* silence noise on load */ 449 450 sc->pch_cnt++; 451 return ch; 452 } 453 454 static int 455 m3_pchan_free(kobj_t kobj, void *chdata) 456 { 457 struct sc_pchinfo *ch = chdata; 458 struct sc_info *sc = ch->parent; 459 460 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx)); 461 462 /* 463 * should remove this exact instance from the packed lists, but all 464 * are released at once (and in a stopped state) so this is ok. 465 */ 466 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 467 (sc->pch_cnt - 1) + sc->rch_cnt, 0); 468 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + 469 (sc->pch_cnt - 1) + sc->rch_cnt, 0); 470 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0); 471 472 sc->pch_cnt--; 473 return 0; 474 } 475 476 static int 477 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) 478 { 479 struct sc_pchinfo *ch = chdata; 480 struct sc_info *sc = ch->parent; 481 u_int32_t data; 482 483 M3_DEBUG(CHANGE, 484 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n", 485 ch->dac_idx, format, 486 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", 487 format & AFMT_STEREO ? "STEREO":"MONO")); 488 489 /* mono word */ 490 data = (format & AFMT_STEREO) ? 0 : 1; 491 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data); 492 493 /* 8bit word */ 494 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; 495 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data); 496 497 ch->fmt = format; 498 return 0; 499 } 500 501 static int 502 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) 503 { 504 struct sc_pchinfo *ch = chdata; 505 struct sc_info *sc = ch->parent; 506 u_int32_t freq; 507 508 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n", 509 ch->dac_idx, speed)); 510 511 if ((freq = ((speed << 15) + 24000) / 48000) != 0) { 512 freq--; 513 } 514 515 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq); 516 517 ch->spd = speed; 518 return speed; /* return closest possible speed */ 519 } 520 521 static int 522 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) 523 { 524 struct sc_pchinfo *ch = chdata; 525 526 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n", 527 ch->dac_idx, blocksize)); 528 529 return blocksize; 530 } 531 532 static int 533 m3_pchan_trigger(kobj_t kobj, void *chdata, int go) 534 { 535 struct sc_pchinfo *ch = chdata; 536 struct sc_info *sc = ch->parent; 537 u_int32_t data; 538 539 M3_DEBUG(go == PCMTRIG_START ? CHANGE : 540 go == PCMTRIG_STOP ? CHANGE : 541 go == PCMTRIG_ABORT ? CHANGE : 542 CALL, 543 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go, 544 go == PCMTRIG_START ? "PCMTRIG_START" : 545 go == PCMTRIG_STOP ? "PCMTRIG_STOP" : 546 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); 547 548 switch(go) { 549 case PCMTRIG_START: 550 if (ch->active) { 551 return 0; 552 } 553 ch->active = 1; 554 sc->pch_active_cnt++; 555 556 /*[[inc_timer_users]]*/ 557 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); 558 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); 559 data = m3_rd_2(sc, HOST_INT_CTRL); 560 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); 561 562 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1); 563 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 564 sc->pch_active_cnt); 565 break; 566 567 case PCMTRIG_STOP: 568 case PCMTRIG_ABORT: 569 if (ch->active == 0) { 570 return 0; 571 } 572 ch->active = 0; 573 sc->pch_active_cnt--; 574 575 /* XXX should the channel be drained? */ 576 /*[[dec_timer_users]]*/ 577 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); 578 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); 579 data = m3_rd_2(sc, HOST_INT_CTRL); 580 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); 581 582 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0); 583 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 584 sc->pch_active_cnt); 585 break; 586 587 case PCMTRIG_EMLDMAWR: 588 /* got play irq, transfer next buffer - ignore if using dma */ 589 case PCMTRIG_EMLDMARD: 590 /* got rec irq, transfer next buffer - ignore if using dma */ 591 default: 592 break; 593 } 594 return 0; 595 } 596 597 static int 598 m3_pchan_getptr(kobj_t kobj, void *chdata) 599 { 600 struct sc_pchinfo *ch = chdata; 601 struct sc_info *sc = ch->parent; 602 u_int32_t hi, lo, bus_crnt; 603 u_int32_t bus_base = vtophys(sndbuf_getbuf(ch->buffer)); 604 605 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH); 606 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL); 607 bus_crnt = lo | (hi << 16); 608 609 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n", 610 ch->dac_idx, bus_crnt - bus_base)); 611 612 return (bus_crnt - bus_base); /* current byte offset of channel */ 613 } 614 615 static struct pcmchan_caps * 616 m3_pchan_getcaps(kobj_t kobj, void *chdata) 617 { 618 struct sc_pchinfo *ch = chdata; 619 620 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx)); 621 622 return &m3_playcaps; 623 } 624 625 /* -------------------------------------------------------------------- */ 626 /* rec channel interface */ 627 628 static void * 629 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 630 { 631 struct sc_info *sc = devinfo; 632 struct sc_rchinfo *ch; 633 u_int32_t bus_addr, i; 634 635 int idx = sc->rch_cnt; /* adc instance number, no active reuse! */ 636 int data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + 637 (MINISRC_IN_BUFFER_SIZE & ~1) + 638 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; 639 int adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2; 640 641 int dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2); 642 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); 643 int dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2); 644 int dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1; 645 646 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx)); 647 648 if (dir != PCMDIR_REC) { 649 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n"); 650 return NULL; 651 } 652 ch = &sc->rch[idx]; 653 654 ch->adc_idx = idx; 655 ch->adc_data = adc_data; 656 if (ch->adc_data + data_bytes/2 >= 0x1c00) { 657 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n"); 658 return NULL; 659 } 660 661 ch->buffer = b; 662 ch->parent = sc; 663 ch->channel = c; 664 ch->fmt = AFMT_U8; 665 ch->spd = DSP_DEFAULT_SPEED; 666 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1) { 667 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n"); 668 return NULL; 669 } 670 ch->bufsize = sndbuf_getsize(ch->buffer); 671 672 /* host dma buffer pointers */ 673 bus_addr = vtophys(sndbuf_getbuf(ch->buffer)); 674 if (bus_addr & 3) { 675 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n"); 676 bus_addr = (bus_addr + 4) & ~3; 677 } 678 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); 679 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); 680 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L, 681 LO(bus_addr + ch->bufsize)); 682 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H, 683 HI(bus_addr + ch->bufsize)); 684 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL, 685 LO(bus_addr)); 686 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH, 687 HI(bus_addr)); 688 689 /* dsp buffers */ 690 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); 691 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1, 692 dsp_in_buf + dsp_in_size/2); 693 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf); 694 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf); 695 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); 696 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1, 697 dsp_out_buf + dsp_out_size/2); 698 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); 699 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); 700 701 /* some per client initializers */ 702 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12, 703 ch->adc_data + 40 + 8); 704 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL, 705 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + 706 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 707 708 /* set an armload of static initializers */ 709 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) { 710 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val); 711 } 712 713 /* put us in the packed task lists */ 714 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 715 (sc->pch_cnt + sc->rch_cnt), 716 ch->adc_data >> DP_SHIFT_COUNT); 717 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), 718 ch->adc_data >> DP_SHIFT_COUNT); 719 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt, 720 ch->adc_data >> DP_SHIFT_COUNT); 721 722 m3_rchan_trigger(NULL, ch, PCMTRIG_START); /* gotta start before stop */ 723 m3_rchan_trigger(NULL, ch, PCMTRIG_STOP); /* stop on init */ 724 725 sc->rch_cnt++; 726 return ch; 727 } 728 729 static int 730 m3_rchan_free(kobj_t kobj, void *chdata) 731 { 732 struct sc_rchinfo *ch = chdata; 733 struct sc_info *sc = ch->parent; 734 735 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx)); 736 737 /* 738 * should remove this exact instance from the packed lists, but all 739 * are released at once (and in a stopped state) so this is ok. 740 */ 741 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 742 (sc->rch_cnt - 1) + sc->pch_cnt, 0); 743 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + 744 (sc->rch_cnt - 1) + sc->pch_cnt, 0); 745 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0); 746 747 sc->rch_cnt--; 748 return 0; 749 } 750 751 static int 752 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) 753 { 754 struct sc_rchinfo *ch = chdata; 755 struct sc_info *sc = ch->parent; 756 u_int32_t data; 757 758 M3_DEBUG(CHANGE, 759 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n", 760 ch->adc_idx, format, 761 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", 762 format & AFMT_STEREO ? "STEREO":"MONO")); 763 764 /* mono word */ 765 data = (format & AFMT_STEREO) ? 0 : 1; 766 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data); 767 768 /* 8bit word */ 769 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; 770 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data); 771 772 ch->fmt = format; 773 return 0; 774 } 775 776 static int 777 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) 778 { 779 struct sc_rchinfo *ch = chdata; 780 struct sc_info *sc = ch->parent; 781 u_int32_t freq; 782 783 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n", 784 ch->adc_idx, speed)); 785 786 if ((freq = ((speed << 15) + 24000) / 48000) != 0) { 787 freq--; 788 } 789 790 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq); 791 792 ch->spd = speed; 793 return speed; /* return closest possible speed */ 794 } 795 796 static int 797 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) 798 { 799 struct sc_rchinfo *ch = chdata; 800 801 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n", 802 ch->adc_idx, blocksize)); 803 804 return blocksize; 805 } 806 807 static int 808 m3_rchan_trigger(kobj_t kobj, void *chdata, int go) 809 { 810 struct sc_rchinfo *ch = chdata; 811 struct sc_info *sc = ch->parent; 812 u_int32_t data; 813 814 M3_DEBUG(go == PCMTRIG_START ? CHANGE : 815 go == PCMTRIG_STOP ? CHANGE : 816 go == PCMTRIG_ABORT ? CHANGE : 817 CALL, 818 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go, 819 go == PCMTRIG_START ? "PCMTRIG_START" : 820 go == PCMTRIG_STOP ? "PCMTRIG_STOP" : 821 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); 822 823 switch(go) { 824 case PCMTRIG_START: 825 if (ch->active) { 826 return 0; 827 } 828 ch->active = 1; 829 830 /*[[inc_timer_users]]*/ 831 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); 832 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); 833 data = m3_rd_2(sc, HOST_INT_CTRL); 834 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); 835 836 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1); 837 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1); 838 break; 839 840 case PCMTRIG_STOP: 841 case PCMTRIG_ABORT: 842 if (ch->active == 0) { 843 return 0; 844 } 845 ch->active = 0; 846 847 /*[[dec_timer_users]]*/ 848 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); 849 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); 850 data = m3_rd_2(sc, HOST_INT_CTRL); 851 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); 852 853 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0); 854 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0); 855 break; 856 857 case PCMTRIG_EMLDMAWR: 858 /* got play irq, transfer next buffer - ignore if using dma */ 859 case PCMTRIG_EMLDMARD: 860 /* got rec irq, transfer next buffer - ignore if using dma */ 861 default: 862 break; 863 } 864 return 0; 865 } 866 867 static int 868 m3_rchan_getptr(kobj_t kobj, void *chdata) 869 { 870 struct sc_rchinfo *ch = chdata; 871 struct sc_info *sc = ch->parent; 872 u_int32_t hi, lo, bus_crnt; 873 u_int32_t bus_base = vtophys(sndbuf_getbuf(ch->buffer)); 874 875 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH); 876 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL); 877 bus_crnt = lo | (hi << 16); 878 879 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n", 880 ch->adc_idx, bus_crnt - bus_base)); 881 882 return (bus_crnt - bus_base); /* current byte offset of channel */ 883 } 884 885 static struct pcmchan_caps * 886 m3_rchan_getcaps(kobj_t kobj, void *chdata) 887 { 888 struct sc_rchinfo *ch = chdata; 889 890 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx)); 891 892 return &m3_reccaps; 893 } 894 895 /* -------------------------------------------------------------------- */ 896 /* The interrupt handler */ 897 898 static void 899 m3_intr(void *p) 900 { 901 struct sc_info *sc = (struct sc_info *)p; 902 u_int32_t status, ctl, i; 903 904 M3_DEBUG(INTR, ("m3_intr\n")); 905 906 status = m3_rd_1(sc, HOST_INT_STATUS); 907 if (!status) 908 return; 909 910 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */ 911 912 if (status & HV_INT_PENDING) { 913 u_int8_t event; 914 915 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER); 916 switch (event) { 917 case 0x99: 918 mixer_hwvol_mute(sc->dev); 919 break; 920 case 0xaa: 921 mixer_hwvol_step(sc->dev, 1, 1); 922 break; 923 case 0x66: 924 mixer_hwvol_step(sc->dev, -1, -1); 925 break; 926 case 0x88: 927 break; 928 default: 929 device_printf(sc->dev, "Unknown HWVOL event\n"); 930 } 931 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88); 932 933 } 934 935 if (status & ASSP_INT_PENDING) { 936 ctl = m3_rd_1(sc, ASSP_CONTROL_B); 937 if (!(ctl & STOP_ASSP_CLOCK)) { 938 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS); 939 if (ctl & DSP2HOST_REQ_TIMER) { 940 m3_wr_1(sc, ASSP_HOST_INT_STATUS, 941 DSP2HOST_REQ_TIMER); 942 /*[[ess_update_ptr]]*/ 943 } 944 } 945 } 946 947 for (i=0 ; i<sc->pch_cnt ; i++) { 948 if (sc->pch[i].active) { 949 chn_intr(sc->pch[i].channel); 950 } 951 } 952 for (i=0 ; i<sc->rch_cnt ; i++) { 953 if (sc->rch[i].active) { 954 chn_intr(sc->rch[i].channel); 955 } 956 } 957 } 958 959 /* -------------------------------------------------------------------- */ 960 /* stuff */ 961 962 static int 963 m3_power(struct sc_info *sc, int state) 964 { 965 u_int32_t data; 966 967 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state)); 968 969 data = pci_read_config(sc->dev, 0x34, 1); 970 if (pci_read_config(sc->dev, data, 1) == 1) { 971 pci_write_config(sc->dev, data + 4, state, 1); 972 } 973 974 return 0; 975 } 976 977 static int 978 m3_init(struct sc_info *sc) 979 { 980 u_int32_t data, i, size; 981 u_int8_t reset_state; 982 983 M3_DEBUG(CHANGE, ("m3_init\n")); 984 985 /* diable legacy emulations. */ 986 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2); 987 data |= DISABLE_LEGACY; 988 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2); 989 990 m3_config(sc); 991 992 reset_state = m3_assp_halt(sc); 993 994 m3_codec_reset(sc); 995 996 /* [m3_assp_init] */ 997 /* zero kernel data */ 998 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; 999 for(i = 0 ; i < size / 2 ; i++) { 1000 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0); 1001 } 1002 /* zero mixer data? */ 1003 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; 1004 for(i = 0 ; i < size / 2 ; i++) { 1005 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0); 1006 } 1007 /* init dma pointer */ 1008 m3_wr_assp_data(sc, KDATA_CURRENT_DMA, 1009 KDATA_DMA_XFER0); 1010 /* write kernel into code memory */ 1011 size = sizeof(assp_kernel_image); 1012 for(i = 0 ; i < size / 2; i++) { 1013 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i, 1014 assp_kernel_image[i]); 1015 } 1016 /* 1017 * We only have this one client and we know that 0x400 is free in 1018 * our kernel's mem map, so lets just drop it there. It seems that 1019 * the minisrc doesn't need vectors, so we won't bother with them.. 1020 */ 1021 size = sizeof(assp_minisrc_image); 1022 for(i = 0 ; i < size / 2; i++) { 1023 m3_wr_assp_code(sc, 0x400 + i, assp_minisrc_image[i]); 1024 } 1025 /* write the coefficients for the low pass filter? */ 1026 size = sizeof(minisrc_lpf_image); 1027 for(i = 0; i < size / 2 ; i++) { 1028 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i, 1029 minisrc_lpf_image[i]); 1030 } 1031 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000); 1032 /* the minisrc is the only thing on our task list */ 1033 m3_wr_assp_data(sc, KDATA_TASK0, 0x400); 1034 /* init the mixer number */ 1035 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0); 1036 /* extreme kernel master volume */ 1037 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); 1038 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); 1039 1040 m3_amp_enable(sc); 1041 1042 /* [m3_assp_client_init] (only one client at index 0) */ 1043 for (i=0x1100 ; i<0x1c00 ; i++) { 1044 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */ 1045 } 1046 1047 /* [m3_assp_continue] */ 1048 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); 1049 1050 return 0; 1051 } 1052 1053 static int 1054 m3_uninit(struct sc_info *sc) 1055 { 1056 M3_DEBUG(CHANGE, ("m3_uninit\n")); 1057 return 0; 1058 } 1059 1060 /* -------------------------------------------------------------------- */ 1061 /* Probe and attach the card */ 1062 1063 static int 1064 m3_pci_probe(device_t dev) 1065 { 1066 struct m3_card_type *card; 1067 1068 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev))); 1069 1070 for (card = m3_card_types ; card->pci_id ; card++) { 1071 if (pci_get_devid(dev) == card->pci_id) { 1072 device_set_desc(dev, card->name); 1073 return 0; 1074 } 1075 } 1076 return ENXIO; 1077 } 1078 1079 static int 1080 m3_pci_attach(device_t dev) 1081 { 1082 struct sc_info *sc; 1083 struct ac97_info *codec = NULL; 1084 u_int32_t data, i; 1085 char status[SND_STATUSLEN]; 1086 struct m3_card_type *card; 1087 int len; 1088 1089 M3_DEBUG(CALL, ("m3_pci_attach\n")); 1090 1091 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 1092 device_printf(dev, "cannot allocate softc\n"); 1093 return ENXIO; 1094 } 1095 1096 sc->dev = dev; 1097 sc->type = pci_get_devid(dev); 1098 1099 for (card = m3_card_types ; card->pci_id ; card++) { 1100 if (sc->type == card->pci_id) { 1101 sc->which = card->which; 1102 sc->delay1 = card->delay1; 1103 sc->delay2 = card->delay2; 1104 break; 1105 } 1106 } 1107 1108 data = pci_read_config(dev, PCIR_COMMAND, 2); 1109 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1110 pci_write_config(dev, PCIR_COMMAND, data, 2); 1111 1112 sc->regid = PCIR_MAPS; 1113 sc->regtype = SYS_RES_MEMORY; 1114 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 1115 0, ~0, 1, RF_ACTIVE); 1116 if (!sc->reg) { 1117 sc->regtype = SYS_RES_IOPORT; 1118 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 1119 0, ~0, 1, RF_ACTIVE); 1120 } 1121 if (!sc->reg) { 1122 device_printf(dev, "unable to allocate register space\n"); 1123 goto bad; 1124 } 1125 sc->st = rman_get_bustag(sc->reg); 1126 sc->sh = rman_get_bushandle(sc->reg); 1127 1128 sc->irqid = 0; 1129 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 1130 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 1131 if (!sc->irq) { 1132 device_printf(dev, "unable to allocate interrupt\n"); 1133 goto bad; 1134 } 1135 1136 if (snd_setup_intr(dev, sc->irq, 0, m3_intr, sc, &sc->ih)) { 1137 device_printf(dev, "unable to setup interrupt\n"); 1138 goto bad; 1139 } 1140 1141 sc->bufsz = pcm_getbuffersize(dev, 1024, M3_BUFSIZE_DEFAULT, 65536); 1142 1143 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 1144 /*lowaddr*/M3_MAXADDR, 1145 /*highaddr*/BUS_SPACE_MAXADDR, 1146 /*filter*/NULL, /*filterarg*/NULL, 1147 /*maxsize*/sc->bufsz, /*nsegments*/1, 1148 /*maxsegz*/0x3ffff, 1149 /*flags*/0, &sc->parent_dmat) != 0) { 1150 device_printf(dev, "unable to create dma tag\n"); 1151 goto bad; 1152 } 1153 1154 m3_power(sc, 0); /* power up */ 1155 1156 /* init chip */ 1157 if (m3_init(sc) == -1) { 1158 device_printf(dev, "unable to initialize the card\n"); 1159 goto bad; 1160 } 1161 1162 /* create/init mixer */ 1163 codec = AC97_CREATE(dev, sc, m3_codec); 1164 if (codec == NULL) { 1165 device_printf(dev, "ac97_create error\n"); 1166 goto bad; 1167 } 1168 if (mixer_init(dev, ac97_getmixerclass(), codec)) { 1169 device_printf(dev, "mixer_init error\n"); 1170 goto bad; 1171 } 1172 1173 m3_enable_ints(sc); 1174 1175 if (pcm_register(dev, sc, M3_PCHANS, M3_RCHANS)) { 1176 device_printf(dev, "pcm_register error\n"); 1177 goto bad; 1178 } 1179 for (i=0 ; i<M3_PCHANS ; i++) { 1180 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) { 1181 device_printf(dev, "pcm_addchan (play) error\n"); 1182 goto bad; 1183 } 1184 } 1185 for (i=0 ; i<M3_RCHANS ; i++) { 1186 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) { 1187 device_printf(dev, "pcm_addchan (rec) error\n"); 1188 goto bad; 1189 } 1190 } 1191 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld", 1192 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 1193 rman_get_start(sc->reg), rman_get_start(sc->irq)); 1194 if (pcm_setstatus(dev, status)) { 1195 device_printf(dev, "attach: pcm_setstatus error\n"); 1196 goto bad; 1197 } 1198 1199 mixer_hwvol_init(dev); 1200 1201 /* Create the buffer for saving the card state during suspend */ 1202 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH + 1203 REV_B_DATA_MEMORY_LENGTH); 1204 sc->savemem = (u_int16_t*)malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 1205 if (sc->savemem == NULL) { 1206 device_printf(dev, "Failed to create suspend buffer\n"); 1207 goto bad; 1208 } 1209 1210 return 0; 1211 1212 bad: 1213 if (codec) { 1214 ac97_destroy(codec); 1215 } 1216 if (sc->reg) { 1217 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1218 } 1219 if (sc->ih) { 1220 bus_teardown_intr(dev, sc->irq, sc->ih); 1221 } 1222 if (sc->irq) { 1223 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1224 } 1225 if (sc->parent_dmat) { 1226 bus_dma_tag_destroy(sc->parent_dmat); 1227 } 1228 free(sc, M_DEVBUF); 1229 return ENXIO; 1230 } 1231 1232 static int 1233 m3_pci_detach(device_t dev) 1234 { 1235 struct sc_info *sc = pcm_getdevinfo(dev); 1236 int r; 1237 1238 M3_DEBUG(CALL, ("m3_pci_detach\n")); 1239 1240 if ((r = pcm_unregister(dev)) != 0) { 1241 return r; 1242 } 1243 m3_uninit(sc); /* shutdown chip */ 1244 m3_power(sc, 3); /* power off */ 1245 1246 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1247 bus_teardown_intr(dev, sc->irq, sc->ih); 1248 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1249 bus_dma_tag_destroy(sc->parent_dmat); 1250 1251 free(sc->savemem, M_DEVBUF); 1252 free(sc, M_DEVBUF); 1253 return 0; 1254 } 1255 1256 static int 1257 m3_pci_suspend(device_t dev) 1258 { 1259 struct sc_info *sc = pcm_getdevinfo(dev); 1260 int i, index = 0; 1261 1262 M3_DEBUG(CHANGE, ("m3_pci_suspend\n")); 1263 1264 for (i=0 ; i<sc->pch_cnt ; i++) { 1265 if (sc->pch[i].active) { 1266 m3_pchan_trigger(NULL, &sc->pch[i], PCMTRIG_STOP); 1267 } 1268 } 1269 for (i=0 ; i<sc->rch_cnt ; i++) { 1270 if (sc->rch[i].active) { 1271 m3_rchan_trigger(NULL, &sc->rch[i], PCMTRIG_STOP); 1272 } 1273 } 1274 DELAY(10 * 1000); /* give things a chance to stop */ 1275 1276 /* Disable interrupts */ 1277 m3_wr_2(sc, HOST_INT_CTRL, 0); 1278 m3_wr_1(sc, ASSP_CONTROL_C, 0); 1279 1280 m3_assp_halt(sc); 1281 1282 /* Save the state of the ASSP */ 1283 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 1284 sc->savemem[index++] = m3_rd_assp_code(sc, i); 1285 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) 1286 sc->savemem[index++] = m3_rd_assp_data(sc, i); 1287 1288 /* Power down the card to D3 state */ 1289 m3_power(sc, 3); 1290 1291 return 0; 1292 } 1293 1294 static int 1295 m3_pci_resume(device_t dev) 1296 { 1297 struct sc_info *sc = pcm_getdevinfo(dev); 1298 int i, index = 0; 1299 u_int8_t reset_state; 1300 1301 M3_DEBUG(CHANGE, ("m3_pci_resume\n")); 1302 1303 /* Power the card back to D0 */ 1304 m3_power(sc, 0); 1305 1306 m3_config(sc); 1307 1308 reset_state = m3_assp_halt(sc); 1309 1310 m3_codec_reset(sc); 1311 1312 /* Restore the ASSP state */ 1313 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 1314 m3_wr_assp_code(sc, i, sc->savemem[index++]); 1315 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) 1316 m3_wr_assp_data(sc, i, sc->savemem[index++]); 1317 1318 /* Restart the DMA engine */ 1319 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0); 1320 1321 /* [m3_assp_continue] */ 1322 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); 1323 1324 m3_amp_enable(sc); 1325 1326 m3_enable_ints(sc); 1327 1328 if (mixer_reinit(dev) == -1) { 1329 device_printf(dev, "unable to reinitialize the mixer\n"); 1330 return ENXIO; 1331 } 1332 1333 /* Turn the channels back on */ 1334 for (i=0 ; i<sc->pch_cnt ; i++) { 1335 if (sc->pch[i].active) { 1336 m3_pchan_trigger(NULL, &sc->pch[i], PCMTRIG_START); 1337 } 1338 } 1339 for (i=0 ; i<sc->rch_cnt ; i++) { 1340 if (sc->rch[i].active) { 1341 m3_rchan_trigger(NULL, &sc->rch[i], PCMTRIG_START); 1342 } 1343 } 1344 1345 return 0; 1346 } 1347 1348 static int 1349 m3_pci_shutdown(device_t dev) 1350 { 1351 struct sc_info *sc = pcm_getdevinfo(dev); 1352 1353 M3_DEBUG(CALL, ("m3_pci_shutdown\n")); 1354 1355 m3_power(sc, 3); /* power off */ 1356 return 0; 1357 } 1358 1359 static u_int8_t 1360 m3_assp_halt(struct sc_info *sc) 1361 { 1362 u_int8_t data, reset_state; 1363 1364 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B); 1365 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */ 1366 DELAY(10 * 1000); 1367 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET); 1368 DELAY(10 * 1000); /* necessary? */ 1369 1370 return reset_state; 1371 } 1372 1373 static void 1374 m3_config(struct sc_info *sc) 1375 { 1376 u_int32_t data, hv_cfg; 1377 int hint; 1378 1379 /* 1380 * The volume buttons can be wired up via two different sets of pins. 1381 * This presents a problem since we can't tell which way it's 1382 * configured. Allow the user to set a hint in order to twiddle 1383 * the proper bits. 1384 */ 1385 if (resource_int_value(device_get_name(sc->dev), 1386 device_get_unit(sc->dev), 1387 "hwvol_config", &hint) == 0) 1388 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0; 1389 else 1390 hv_cfg = HV_BUTTON_FROM_GD; 1391 1392 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); 1393 data &= ~HV_BUTTON_FROM_GD; 1394 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg; 1395 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; 1396 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); 1397 1398 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP); 1399 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); 1400 data &= ~INT_CLK_SELECT; 1401 if (sc->which == ESS_MAESTRO3) { 1402 data &= ~INT_CLK_MULT_ENABLE; 1403 data |= INT_CLK_SRC_NOT_PCI; 1404 } 1405 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2); 1406 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); 1407 1408 if (sc->which == ESS_ALLEGRO_1) { 1409 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4); 1410 data |= IN_CLK_12MHZ_SELECT; 1411 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4); 1412 } 1413 1414 data = m3_rd_1(sc, ASSP_CONTROL_A); 1415 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); 1416 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/ 1417 data |= ASSP_0_WS_ENABLE; 1418 m3_wr_1(sc, ASSP_CONTROL_A, data); 1419 1420 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP); 1421 } 1422 1423 static void 1424 m3_enable_ints(struct sc_info *sc) 1425 { 1426 u_int8_t data; 1427 1428 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE); 1429 data = m3_rd_1(sc, ASSP_CONTROL_C); 1430 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE); 1431 } 1432 1433 static void 1434 m3_amp_enable(struct sc_info *sc) 1435 { 1436 u_int32_t gpo, polarity_port, polarity; 1437 u_int16_t data; 1438 1439 switch (sc->which) { 1440 case ESS_ALLEGRO_1: 1441 polarity_port = 0x1800; 1442 break; 1443 case ESS_MAESTRO3: 1444 polarity_port = 0x1100; 1445 break; 1446 default: 1447 panic("bad sc->which"); 1448 } 1449 gpo = (polarity_port >> 8) & 0x0f; 1450 polarity = polarity_port >> 12; 1451 polarity = !polarity; /* enable */ 1452 polarity = polarity << gpo; 1453 gpo = 1 << gpo; 1454 m3_wr_2(sc, GPIO_MASK, ~gpo); 1455 data = m3_rd_2(sc, GPIO_DIRECTION); 1456 m3_wr_2(sc, GPIO_DIRECTION, data | gpo); 1457 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity; 1458 m3_wr_2(sc, GPIO_DATA, data); 1459 m3_wr_2(sc, GPIO_MASK, ~0); 1460 } 1461 1462 static void 1463 m3_codec_reset(struct sc_info *sc) 1464 { 1465 u_int16_t data, dir; 1466 int retry = 0; 1467 1468 do { 1469 data = m3_rd_2(sc, GPIO_DIRECTION); 1470 dir = data | 0x10; /* assuming pci bus master? */ 1471 1472 /* [[remote_codec_config]] */ 1473 data = m3_rd_2(sc, RING_BUS_CTRL_B); 1474 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK); 1475 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL); 1476 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT); 1477 data = m3_rd_2(sc, SDO_IN_DEST_CTRL); 1478 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN); 1479 1480 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE); 1481 DELAY(20); 1482 1483 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97); 1484 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97); 1485 m3_wr_2(sc, GPIO_DATA, 0); 1486 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97); 1487 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/ 1488 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97); 1489 DELAY(5); 1490 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE | 1491 SERIAL_AC_LINK_ENABLE); 1492 m3_wr_2(sc, GPIO_MASK, ~0); 1493 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/ 1494 1495 /* [[try read vendor]] */ 1496 data = m3_rdcd(NULL, sc, 0x7c); 1497 if ((data == 0) || (data == 0xffff)) { 1498 retry++; 1499 if (retry > 3) { 1500 device_printf(sc->dev, "Codec reset failed\n"); 1501 break; 1502 } 1503 device_printf(sc->dev, "Codec reset retry\n"); 1504 } else retry = 0; 1505 } while (retry); 1506 } 1507 1508 static device_method_t m3_methods[] = { 1509 DEVMETHOD(device_probe, m3_pci_probe), 1510 DEVMETHOD(device_attach, m3_pci_attach), 1511 DEVMETHOD(device_detach, m3_pci_detach), 1512 DEVMETHOD(device_suspend, m3_pci_suspend), 1513 DEVMETHOD(device_resume, m3_pci_resume), 1514 DEVMETHOD(device_shutdown, m3_pci_shutdown), 1515 { 0, 0 } 1516 }; 1517 1518 static driver_t m3_driver = { 1519 "pcm", 1520 m3_methods, 1521 PCM_SOFTC_SIZE, 1522 }; 1523 1524 DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, 0, 0); 1525 MODULE_DEPEND(snd_maestro3, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1526 MODULE_VERSION(snd_maestro3, 1); 1527