1 /*- 2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org> 3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Maestro-3/Allegro FreeBSD pcm sound driver 30 * 31 * executive status summary: 32 * (+) /dev/dsp multiple concurrent play channels. 33 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit). 34 * (+) /dev/mixer sets left/right volumes. 35 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel 36 * (+) apm suspend/resume works, and works properly!. 37 * (-) hardware volme controls don't work =-( 38 * (-) setblocksize() does nothing. 39 * 40 * The real credit goes to: 41 * 42 * Zach Brown for his Linux driver core and helpful technical comments. 43 * <zab@zabbo.net>, http://www.zabbo.net/maestro3 44 * 45 * Cameron Grant created the pcm framework used here nearly verbatim. 46 * <cg@freebsd.org>, http://people.freebsd.org/~cg/template.c 47 * 48 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference. 49 * <taku@cent.saitama-u.ac.jp> 50 * 51 * ESS docs explained a few magic registers and numbers. 52 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz 53 */ 54 55 #include <dev/sound/pcm/sound.h> 56 #include <dev/sound/pcm/ac97.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 61 #include <gnu/dev/sound/pci/maestro3_reg.h> 62 #include <gnu/dev/sound/pci/maestro3_dsp.h> 63 64 SND_DECLARE_FILE("$FreeBSD$"); 65 66 /* -------------------------------------------------------------------- */ 67 68 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1}; 69 #ifndef M3_DEBUG_LEVEL 70 #define M3_DEBUG_LEVEL NONE 71 #endif 72 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}} 73 74 /* -------------------------------------------------------------------- */ 75 enum { 76 ESS_ALLEGRO_1, 77 ESS_MAESTRO3 78 }; 79 80 static struct m3_card_type { 81 u_int32_t pci_id; int which; int delay1; int delay2; char *name; 82 } m3_card_types[] = { 83 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" }, 84 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, 85 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, 86 { 0, 0, 0, 0, NULL } 87 }; 88 89 #define M3_BUFSIZE_MIN 4096 90 #define M3_BUFSIZE_MAX 65536 91 #define M3_BUFSIZE_DEFAULT 4096 92 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */ 93 #define M3_RCHANS 1 94 #define M3_MAXADDR ((1 << 27) - 1) 95 96 struct sc_info; 97 98 struct sc_pchinfo { 99 u_int32_t spd; 100 u_int32_t fmt; 101 struct snd_dbuf *buffer; 102 struct pcm_channel *channel; 103 struct sc_info *parent; 104 u_int32_t bufsize; 105 u_int32_t dac_data; 106 u_int32_t dac_idx; 107 u_int32_t active; 108 u_int32_t ptr; 109 u_int32_t prevptr; 110 }; 111 112 struct sc_rchinfo { 113 u_int32_t spd; 114 u_int32_t fmt; 115 struct snd_dbuf *buffer; 116 struct pcm_channel *channel; 117 struct sc_info *parent; 118 u_int32_t bufsize; 119 u_int32_t adc_data; 120 u_int32_t adc_idx; 121 u_int32_t active; 122 u_int32_t ptr; 123 u_int32_t prevptr; 124 }; 125 126 struct sc_info { 127 device_t dev; 128 u_int32_t type; 129 int which; 130 int delay1; 131 int delay2; 132 133 bus_space_tag_t st; 134 bus_space_handle_t sh; 135 bus_dma_tag_t parent_dmat; 136 137 struct resource *reg; 138 struct resource *irq; 139 int regtype; 140 int regid; 141 int irqid; 142 void *ih; 143 144 struct sc_pchinfo pch[M3_PCHANS]; 145 struct sc_rchinfo rch[M3_RCHANS]; 146 int pch_cnt; 147 int rch_cnt; 148 int pch_active_cnt; 149 unsigned int bufsz; 150 u_int16_t *savemem; 151 152 struct mtx *sc_lock; 153 }; 154 155 #define M3_LOCK(_sc) snd_mtxlock((_sc)->sc_lock) 156 #define M3_UNLOCK(_sc) snd_mtxunlock((_sc)->sc_lock) 157 #define M3_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->sc_lock) 158 159 /* -------------------------------------------------------------------- */ 160 161 /* play channel interface */ 162 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int); 163 static int m3_pchan_free(kobj_t, void *); 164 static int m3_pchan_setformat(kobj_t, void *, u_int32_t); 165 static int m3_pchan_setspeed(kobj_t, void *, u_int32_t); 166 static int m3_pchan_setblocksize(kobj_t, void *, u_int32_t); 167 static int m3_pchan_trigger(kobj_t, void *, int); 168 static int m3_pchan_trigger_locked(kobj_t, void *, int); 169 static u_int32_t m3_pchan_getptr_internal(struct sc_pchinfo *); 170 static u_int32_t m3_pchan_getptr(kobj_t, void *); 171 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *); 172 173 /* record channel interface */ 174 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int); 175 static int m3_rchan_free(kobj_t, void *); 176 static int m3_rchan_setformat(kobj_t, void *, u_int32_t); 177 static int m3_rchan_setspeed(kobj_t, void *, u_int32_t); 178 static int m3_rchan_setblocksize(kobj_t, void *, u_int32_t); 179 static int m3_rchan_trigger(kobj_t, void *, int); 180 static int m3_rchan_trigger_locked(kobj_t, void *, int); 181 static u_int32_t m3_rchan_getptr_internal(struct sc_rchinfo *); 182 static u_int32_t m3_rchan_getptr(kobj_t, void *); 183 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *); 184 185 static int m3_chan_active(struct sc_info *); 186 187 /* talk to the codec - called from ac97.c */ 188 static int m3_initcd(kobj_t, void *); 189 static int m3_rdcd(kobj_t, void *, int); 190 static int m3_wrcd(kobj_t, void *, int, u_int32_t); 191 192 /* stuff */ 193 static void m3_intr(void *); 194 static int m3_power(struct sc_info *, int); 195 static int m3_init(struct sc_info *); 196 static int m3_uninit(struct sc_info *); 197 static u_int8_t m3_assp_halt(struct sc_info *); 198 static void m3_config(struct sc_info *); 199 static void m3_amp_enable(struct sc_info *); 200 static void m3_enable_ints(struct sc_info *); 201 static void m3_codec_reset(struct sc_info *); 202 203 /* -------------------------------------------------------------------- */ 204 /* Codec descriptor */ 205 static kobj_method_t m3_codec_methods[] = { 206 KOBJMETHOD(ac97_init, m3_initcd), 207 KOBJMETHOD(ac97_read, m3_rdcd), 208 KOBJMETHOD(ac97_write, m3_wrcd), 209 { 0, 0 } 210 }; 211 AC97_DECLARE(m3_codec); 212 213 /* -------------------------------------------------------------------- */ 214 /* channel descriptors */ 215 216 static u_int32_t m3_playfmt[] = { 217 AFMT_U8, 218 AFMT_STEREO | AFMT_U8, 219 AFMT_S16_LE, 220 AFMT_STEREO | AFMT_S16_LE, 221 0 222 }; 223 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0}; 224 225 static kobj_method_t m3_pch_methods[] = { 226 KOBJMETHOD(channel_init, m3_pchan_init), 227 KOBJMETHOD(channel_setformat, m3_pchan_setformat), 228 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed), 229 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize), 230 KOBJMETHOD(channel_trigger, m3_pchan_trigger), 231 KOBJMETHOD(channel_getptr, m3_pchan_getptr), 232 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps), 233 KOBJMETHOD(channel_free, m3_pchan_free), 234 { 0, 0 } 235 }; 236 CHANNEL_DECLARE(m3_pch); 237 238 static u_int32_t m3_recfmt[] = { 239 AFMT_U8, 240 AFMT_STEREO | AFMT_U8, 241 AFMT_S16_LE, 242 AFMT_STEREO | AFMT_S16_LE, 243 0 244 }; 245 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0}; 246 247 static kobj_method_t m3_rch_methods[] = { 248 KOBJMETHOD(channel_init, m3_rchan_init), 249 KOBJMETHOD(channel_setformat, m3_rchan_setformat), 250 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed), 251 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize), 252 KOBJMETHOD(channel_trigger, m3_rchan_trigger), 253 KOBJMETHOD(channel_getptr, m3_rchan_getptr), 254 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps), 255 KOBJMETHOD(channel_free, m3_rchan_free), 256 { 0, 0 } 257 }; 258 CHANNEL_DECLARE(m3_rch); 259 260 /* -------------------------------------------------------------------- */ 261 /* some i/o convenience functions */ 262 263 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno) 264 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno) 265 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno) 266 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data) 267 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data) 268 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data) 269 #define m3_rd_assp_code(sc, index) \ 270 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index) 271 #define m3_wr_assp_code(sc, index, data) \ 272 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data) 273 #define m3_rd_assp_data(sc, index) \ 274 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index) 275 #define m3_wr_assp_data(sc, index, data) \ 276 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data) 277 278 static __inline u_int16_t 279 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index) 280 { 281 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); 282 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); 283 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA); 284 } 285 286 static __inline void 287 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index, 288 u_int16_t data) 289 { 290 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); 291 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); 292 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data); 293 } 294 295 static __inline int 296 m3_wait(struct sc_info *sc) 297 { 298 int i; 299 300 for (i=0 ; i<20 ; i++) { 301 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) { 302 return 0; 303 } 304 DELAY(2); 305 } 306 return -1; 307 } 308 309 /* -------------------------------------------------------------------- */ 310 /* ac97 codec */ 311 312 static int 313 m3_initcd(kobj_t kobj, void *devinfo) 314 { 315 struct sc_info *sc = (struct sc_info *)devinfo; 316 u_int32_t data; 317 318 M3_DEBUG(CALL, ("m3_initcd\n")); 319 320 /* init ac-link */ 321 322 data = m3_rd_1(sc, CODEC_COMMAND); 323 return ((data & 0x1) ? 0 : 1); 324 } 325 326 static int 327 m3_rdcd(kobj_t kobj, void *devinfo, int regno) 328 { 329 struct sc_info *sc = (struct sc_info *)devinfo; 330 u_int32_t data; 331 332 if (m3_wait(sc)) { 333 device_printf(sc->dev, "m3_rdcd timed out.\n"); 334 return -1; 335 } 336 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80); 337 DELAY(50); /* ac97 cycle = 20.8 usec */ 338 if (m3_wait(sc)) { 339 device_printf(sc->dev, "m3_rdcd timed out.\n"); 340 return -1; 341 } 342 data = m3_rd_2(sc, CODEC_DATA); 343 return data; 344 } 345 346 static int 347 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data) 348 { 349 struct sc_info *sc = (struct sc_info *)devinfo; 350 if (m3_wait(sc)) { 351 device_printf(sc->dev, "m3_wrcd timed out.\n"); 352 return -1;; 353 } 354 m3_wr_2(sc, CODEC_DATA, data); 355 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f); 356 DELAY(50); /* ac97 cycle = 20.8 usec */ 357 return 0; 358 } 359 360 /* -------------------------------------------------------------------- */ 361 /* play channel interface */ 362 363 #define LO(x) (((x) & 0x0000ffff) ) 364 #define HI(x) (((x) & 0xffff0000) >> 16) 365 366 static void * 367 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 368 { 369 struct sc_info *sc = devinfo; 370 struct sc_pchinfo *ch; 371 u_int32_t bus_addr, i; 372 int idx, data_bytes, dac_data; 373 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf; 374 375 M3_LOCK(sc); 376 idx = sc->pch_cnt; /* dac instance number, no active reuse! */ 377 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx)); 378 379 if (dir != PCMDIR_PLAY) { 380 M3_UNLOCK(sc); 381 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n"); 382 return (NULL); 383 } 384 385 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + 386 (MINISRC_IN_BUFFER_SIZE & ~1) + 387 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; 388 dac_data = 0x1100 + (data_bytes * idx); 389 390 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); 391 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); 392 dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2); 393 dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1; 394 395 ch = &sc->pch[idx]; 396 ch->dac_idx = idx; 397 ch->dac_data = dac_data; 398 if (ch->dac_data + data_bytes/2 >= 0x1c00) { 399 M3_UNLOCK(sc); 400 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n"); 401 return (NULL); 402 } 403 404 ch->buffer = b; 405 ch->parent = sc; 406 ch->channel = c; 407 ch->fmt = AFMT_U8; 408 ch->spd = DSP_DEFAULT_SPEED; 409 M3_UNLOCK(sc); /* XXX */ 410 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 411 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n"); 412 return (NULL); 413 } 414 M3_LOCK(sc); 415 ch->bufsize = sndbuf_getsize(ch->buffer); 416 417 /* host dma buffer pointers */ 418 bus_addr = sndbuf_getbufaddr(ch->buffer); 419 if (bus_addr & 3) { 420 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n"); 421 bus_addr = (bus_addr + 4) & ~3; 422 } 423 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); 424 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); 425 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L, 426 LO(bus_addr + ch->bufsize)); 427 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H, 428 HI(bus_addr + ch->bufsize)); 429 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL, 430 LO(bus_addr)); 431 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH, 432 HI(bus_addr)); 433 434 /* dsp buffers */ 435 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); 436 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1, 437 dsp_in_buf + dsp_in_size/2); 438 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf); 439 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf); 440 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); 441 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1, 442 dsp_out_buf + dsp_out_size/2); 443 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); 444 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); 445 446 /* some per client initializers */ 447 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12, 448 ch->dac_data + 40 + 8); 449 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19, 450 0x400 + MINISRC_COEF_LOC); 451 /* enable or disable low pass filter? (0xff if rate> 45000) */ 452 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0); 453 /* tell it which way dma is going? */ 454 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL, 455 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + 456 DMAC_BLOCKF_SELECTOR); 457 458 /* set an armload of static initializers */ 459 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) { 460 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val); 461 } 462 463 /* put us in the packed task lists */ 464 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 465 (sc->pch_cnt + sc->rch_cnt), 466 ch->dac_data >> DP_SHIFT_COUNT); 467 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), 468 ch->dac_data >> DP_SHIFT_COUNT); 469 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt, 470 ch->dac_data >> DP_SHIFT_COUNT); 471 472 /* gotta start before stop */ 473 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_START); 474 /* silence noise on load */ 475 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_STOP); 476 477 sc->pch_cnt++; 478 M3_UNLOCK(sc); 479 480 return (ch); 481 } 482 483 static int 484 m3_pchan_free(kobj_t kobj, void *chdata) 485 { 486 struct sc_pchinfo *ch = chdata; 487 struct sc_info *sc = ch->parent; 488 489 M3_LOCK(sc); 490 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx)); 491 492 /* 493 * should remove this exact instance from the packed lists, but all 494 * are released at once (and in a stopped state) so this is ok. 495 */ 496 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 497 (sc->pch_cnt - 1) + sc->rch_cnt, 0); 498 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + 499 (sc->pch_cnt - 1) + sc->rch_cnt, 0); 500 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0); 501 sc->pch_cnt--; 502 M3_UNLOCK(sc); 503 504 return (0); 505 } 506 507 static int 508 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) 509 { 510 struct sc_pchinfo *ch = chdata; 511 struct sc_info *sc = ch->parent; 512 u_int32_t data; 513 514 M3_LOCK(sc); 515 M3_DEBUG(CHANGE, 516 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n", 517 ch->dac_idx, format, 518 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", 519 format & AFMT_STEREO ? "STEREO":"MONO")); 520 521 /* mono word */ 522 data = (format & AFMT_STEREO) ? 0 : 1; 523 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data); 524 525 /* 8bit word */ 526 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; 527 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data); 528 529 ch->fmt = format; 530 M3_UNLOCK(sc); 531 532 return (0); 533 } 534 535 static int 536 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) 537 { 538 struct sc_pchinfo *ch = chdata; 539 struct sc_info *sc = ch->parent; 540 u_int32_t freq; 541 542 M3_LOCK(sc); 543 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n", 544 ch->dac_idx, speed)); 545 546 if ((freq = ((speed << 15) + 24000) / 48000) != 0) { 547 freq--; 548 } 549 550 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq); 551 ch->spd = speed; 552 M3_UNLOCK(sc); 553 554 /* return closest possible speed */ 555 return (speed); 556 } 557 558 static int 559 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) 560 { 561 struct sc_pchinfo *ch = chdata; 562 563 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n", 564 ch->dac_idx, blocksize)); 565 566 return (sndbuf_getblksz(ch->buffer)); 567 } 568 569 static int 570 m3_pchan_trigger(kobj_t kobj, void *chdata, int go) 571 { 572 struct sc_pchinfo *ch = chdata; 573 struct sc_info *sc = ch->parent; 574 int ret; 575 576 if (!PCMTRIG_COMMON(go)) 577 return (0); 578 579 M3_LOCK(sc); 580 ret = m3_pchan_trigger_locked(kobj, chdata, go); 581 M3_UNLOCK(sc); 582 583 return (ret); 584 } 585 586 static int 587 m3_chan_active(struct sc_info *sc) 588 { 589 int i, ret; 590 591 ret = 0; 592 593 for (i = 0; i < sc->pch_cnt; i++) 594 ret += sc->pch[i].active; 595 596 for (i = 0; i < sc->rch_cnt; i++) 597 ret += sc->rch[i].active; 598 599 return (ret); 600 } 601 602 static int 603 m3_pchan_trigger_locked(kobj_t kobj, void *chdata, int go) 604 { 605 struct sc_pchinfo *ch = chdata; 606 struct sc_info *sc = ch->parent; 607 u_int32_t data; 608 609 M3_LOCK_ASSERT(sc); 610 M3_DEBUG(go == PCMTRIG_START ? CHANGE : 611 go == PCMTRIG_STOP ? CHANGE : 612 go == PCMTRIG_ABORT ? CHANGE : 613 CALL, 614 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go, 615 go == PCMTRIG_START ? "PCMTRIG_START" : 616 go == PCMTRIG_STOP ? "PCMTRIG_STOP" : 617 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); 618 619 switch(go) { 620 case PCMTRIG_START: 621 if (ch->active) { 622 return 0; 623 } 624 ch->active = 1; 625 ch->ptr = 0; 626 ch->prevptr = 0; 627 sc->pch_active_cnt++; 628 629 /*[[inc_timer_users]]*/ 630 if (m3_chan_active(sc) == 1) { 631 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); 632 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); 633 data = m3_rd_2(sc, HOST_INT_CTRL); 634 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); 635 } 636 637 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1); 638 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 639 sc->pch_active_cnt); 640 break; 641 642 case PCMTRIG_STOP: 643 case PCMTRIG_ABORT: 644 if (ch->active == 0) { 645 return 0; 646 } 647 ch->active = 0; 648 sc->pch_active_cnt--; 649 650 /* XXX should the channel be drained? */ 651 /*[[dec_timer_users]]*/ 652 if (m3_chan_active(sc) == 0) { 653 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); 654 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); 655 data = m3_rd_2(sc, HOST_INT_CTRL); 656 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); 657 } 658 659 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0); 660 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 661 sc->pch_active_cnt); 662 break; 663 664 case PCMTRIG_EMLDMAWR: 665 /* got play irq, transfer next buffer - ignore if using dma */ 666 case PCMTRIG_EMLDMARD: 667 /* got rec irq, transfer next buffer - ignore if using dma */ 668 default: 669 break; 670 } 671 return 0; 672 } 673 674 static u_int32_t 675 m3_pchan_getptr_internal(struct sc_pchinfo *ch) 676 { 677 struct sc_info *sc = ch->parent; 678 u_int32_t hi, lo, bus_base, bus_crnt; 679 680 bus_base = sndbuf_getbufaddr(ch->buffer); 681 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH); 682 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL); 683 bus_crnt = lo | (hi << 16); 684 685 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n", 686 ch->dac_idx, bus_crnt - bus_base)); 687 688 return (bus_crnt - bus_base); /* current byte offset of channel */ 689 } 690 691 static u_int32_t 692 m3_pchan_getptr(kobj_t kobj, void *chdata) 693 { 694 struct sc_pchinfo *ch = chdata; 695 struct sc_info *sc = ch->parent; 696 u_int32_t ptr; 697 698 M3_LOCK(sc); 699 ptr = ch->ptr; 700 M3_UNLOCK(sc); 701 702 return (ptr); 703 } 704 705 static struct pcmchan_caps * 706 m3_pchan_getcaps(kobj_t kobj, void *chdata) 707 { 708 struct sc_pchinfo *ch = chdata; 709 710 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx)); 711 712 return &m3_playcaps; 713 } 714 715 /* -------------------------------------------------------------------- */ 716 /* rec channel interface */ 717 718 static void * 719 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 720 { 721 struct sc_info *sc = devinfo; 722 struct sc_rchinfo *ch; 723 u_int32_t bus_addr, i; 724 725 int idx, data_bytes, adc_data; 726 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf; 727 728 M3_LOCK(sc); 729 idx = sc->rch_cnt; /* adc instance number, no active reuse! */ 730 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx)); 731 732 if (dir != PCMDIR_REC) { 733 M3_UNLOCK(sc); 734 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n"); 735 return (NULL); 736 } 737 738 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + 739 (MINISRC_IN_BUFFER_SIZE & ~1) + 740 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; 741 adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2; 742 dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2); 743 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); 744 dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2); 745 dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1; 746 747 ch = &sc->rch[idx]; 748 ch->adc_idx = idx; 749 ch->adc_data = adc_data; 750 if (ch->adc_data + data_bytes/2 >= 0x1c00) { 751 M3_UNLOCK(sc); 752 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n"); 753 return (NULL); 754 } 755 756 ch->buffer = b; 757 ch->parent = sc; 758 ch->channel = c; 759 ch->fmt = AFMT_U8; 760 ch->spd = DSP_DEFAULT_SPEED; 761 M3_UNLOCK(sc); /* XXX */ 762 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 763 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n"); 764 return (NULL); 765 } 766 M3_LOCK(sc); 767 ch->bufsize = sndbuf_getsize(ch->buffer); 768 769 /* host dma buffer pointers */ 770 bus_addr = sndbuf_getbufaddr(ch->buffer); 771 if (bus_addr & 3) { 772 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n"); 773 bus_addr = (bus_addr + 4) & ~3; 774 } 775 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); 776 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); 777 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L, 778 LO(bus_addr + ch->bufsize)); 779 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H, 780 HI(bus_addr + ch->bufsize)); 781 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL, 782 LO(bus_addr)); 783 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH, 784 HI(bus_addr)); 785 786 /* dsp buffers */ 787 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); 788 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1, 789 dsp_in_buf + dsp_in_size/2); 790 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf); 791 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf); 792 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); 793 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1, 794 dsp_out_buf + dsp_out_size/2); 795 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); 796 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); 797 798 /* some per client initializers */ 799 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12, 800 ch->adc_data + 40 + 8); 801 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL, 802 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + 803 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 804 805 /* set an armload of static initializers */ 806 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) { 807 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val); 808 } 809 810 /* put us in the packed task lists */ 811 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 812 (sc->pch_cnt + sc->rch_cnt), 813 ch->adc_data >> DP_SHIFT_COUNT); 814 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), 815 ch->adc_data >> DP_SHIFT_COUNT); 816 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt, 817 ch->adc_data >> DP_SHIFT_COUNT); 818 819 /* gotta start before stop */ 820 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_START); 821 /* stop on init */ 822 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_STOP); 823 824 sc->rch_cnt++; 825 M3_UNLOCK(sc); 826 827 return (ch); 828 } 829 830 static int 831 m3_rchan_free(kobj_t kobj, void *chdata) 832 { 833 struct sc_rchinfo *ch = chdata; 834 struct sc_info *sc = ch->parent; 835 836 M3_LOCK(sc); 837 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx)); 838 839 /* 840 * should remove this exact instance from the packed lists, but all 841 * are released at once (and in a stopped state) so this is ok. 842 */ 843 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 844 (sc->rch_cnt - 1) + sc->pch_cnt, 0); 845 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + 846 (sc->rch_cnt - 1) + sc->pch_cnt, 0); 847 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0); 848 sc->rch_cnt--; 849 M3_UNLOCK(sc); 850 851 return (0); 852 } 853 854 static int 855 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) 856 { 857 struct sc_rchinfo *ch = chdata; 858 struct sc_info *sc = ch->parent; 859 u_int32_t data; 860 861 M3_LOCK(sc); 862 M3_DEBUG(CHANGE, 863 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n", 864 ch->adc_idx, format, 865 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", 866 format & AFMT_STEREO ? "STEREO":"MONO")); 867 868 /* mono word */ 869 data = (format & AFMT_STEREO) ? 0 : 1; 870 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data); 871 872 /* 8bit word */ 873 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; 874 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data); 875 ch->fmt = format; 876 M3_UNLOCK(sc); 877 878 return (0); 879 } 880 881 static int 882 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) 883 { 884 struct sc_rchinfo *ch = chdata; 885 struct sc_info *sc = ch->parent; 886 u_int32_t freq; 887 888 M3_LOCK(sc); 889 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n", 890 ch->adc_idx, speed)); 891 892 if ((freq = ((speed << 15) + 24000) / 48000) != 0) { 893 freq--; 894 } 895 896 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq); 897 ch->spd = speed; 898 M3_UNLOCK(sc); 899 900 /* return closest possible speed */ 901 return (speed); 902 } 903 904 static int 905 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) 906 { 907 struct sc_rchinfo *ch = chdata; 908 909 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n", 910 ch->adc_idx, blocksize)); 911 912 return (sndbuf_getblksz(ch->buffer)); 913 } 914 915 static int 916 m3_rchan_trigger(kobj_t kobj, void *chdata, int go) 917 { 918 struct sc_rchinfo *ch = chdata; 919 struct sc_info *sc = ch->parent; 920 int ret; 921 922 if (!PCMTRIG_COMMON(go)) 923 return (0); 924 925 M3_LOCK(sc); 926 ret = m3_rchan_trigger_locked(kobj, chdata, go); 927 M3_UNLOCK(sc); 928 929 return (ret); 930 } 931 932 static int 933 m3_rchan_trigger_locked(kobj_t kobj, void *chdata, int go) 934 { 935 struct sc_rchinfo *ch = chdata; 936 struct sc_info *sc = ch->parent; 937 u_int32_t data; 938 939 M3_LOCK_ASSERT(sc); 940 M3_DEBUG(go == PCMTRIG_START ? CHANGE : 941 go == PCMTRIG_STOP ? CHANGE : 942 go == PCMTRIG_ABORT ? CHANGE : 943 CALL, 944 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go, 945 go == PCMTRIG_START ? "PCMTRIG_START" : 946 go == PCMTRIG_STOP ? "PCMTRIG_STOP" : 947 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); 948 949 switch(go) { 950 case PCMTRIG_START: 951 if (ch->active) { 952 return 0; 953 } 954 ch->active = 1; 955 ch->ptr = 0; 956 ch->prevptr = 0; 957 958 /*[[inc_timer_users]]*/ 959 if (m3_chan_active(sc) == 1) { 960 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); 961 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); 962 data = m3_rd_2(sc, HOST_INT_CTRL); 963 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); 964 } 965 966 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1); 967 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1); 968 break; 969 970 case PCMTRIG_STOP: 971 case PCMTRIG_ABORT: 972 if (ch->active == 0) { 973 return 0; 974 } 975 ch->active = 0; 976 977 /*[[dec_timer_users]]*/ 978 if (m3_chan_active(sc) == 0) { 979 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); 980 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); 981 data = m3_rd_2(sc, HOST_INT_CTRL); 982 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); 983 } 984 985 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0); 986 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0); 987 break; 988 989 case PCMTRIG_EMLDMAWR: 990 /* got play irq, transfer next buffer - ignore if using dma */ 991 case PCMTRIG_EMLDMARD: 992 /* got rec irq, transfer next buffer - ignore if using dma */ 993 default: 994 break; 995 } 996 return 0; 997 } 998 999 static u_int32_t 1000 m3_rchan_getptr_internal(struct sc_rchinfo *ch) 1001 { 1002 struct sc_info *sc = ch->parent; 1003 u_int32_t hi, lo, bus_base, bus_crnt; 1004 1005 bus_base = sndbuf_getbufaddr(ch->buffer); 1006 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH); 1007 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL); 1008 bus_crnt = lo | (hi << 16); 1009 1010 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n", 1011 ch->adc_idx, bus_crnt - bus_base)); 1012 1013 return (bus_crnt - bus_base); /* current byte offset of channel */ 1014 } 1015 1016 static u_int32_t 1017 m3_rchan_getptr(kobj_t kobj, void *chdata) 1018 { 1019 struct sc_rchinfo *ch = chdata; 1020 struct sc_info *sc = ch->parent; 1021 u_int32_t ptr; 1022 1023 M3_LOCK(sc); 1024 ptr = ch->ptr; 1025 M3_UNLOCK(sc); 1026 1027 return (ptr); 1028 } 1029 1030 static struct pcmchan_caps * 1031 m3_rchan_getcaps(kobj_t kobj, void *chdata) 1032 { 1033 struct sc_rchinfo *ch = chdata; 1034 1035 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx)); 1036 1037 return &m3_reccaps; 1038 } 1039 1040 /* -------------------------------------------------------------------- */ 1041 /* The interrupt handler */ 1042 1043 static void 1044 m3_intr(void *p) 1045 { 1046 struct sc_info *sc = (struct sc_info *)p; 1047 struct sc_pchinfo *pch; 1048 struct sc_rchinfo *rch; 1049 u_int32_t status, ctl, i, delta; 1050 1051 M3_DEBUG(INTR, ("m3_intr\n")); 1052 1053 M3_LOCK(sc); 1054 status = m3_rd_1(sc, HOST_INT_STATUS); 1055 if (!status) { 1056 M3_UNLOCK(sc); 1057 return; 1058 } 1059 1060 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */ 1061 1062 if (status & HV_INT_PENDING) { 1063 u_int8_t event; 1064 1065 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER); 1066 switch (event) { 1067 case 0x99: 1068 mixer_hwvol_mute(sc->dev); 1069 break; 1070 case 0xaa: 1071 mixer_hwvol_step(sc->dev, 1, 1); 1072 break; 1073 case 0x66: 1074 mixer_hwvol_step(sc->dev, -1, -1); 1075 break; 1076 case 0x88: 1077 break; 1078 default: 1079 device_printf(sc->dev, "Unknown HWVOL event\n"); 1080 } 1081 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88); 1082 1083 } 1084 1085 if (status & ASSP_INT_PENDING) { 1086 ctl = m3_rd_1(sc, ASSP_CONTROL_B); 1087 if (!(ctl & STOP_ASSP_CLOCK)) { 1088 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS); 1089 if (ctl & DSP2HOST_REQ_TIMER) { 1090 m3_wr_1(sc, ASSP_HOST_INT_STATUS, 1091 DSP2HOST_REQ_TIMER); 1092 /*[[ess_update_ptr]]*/ 1093 goto m3_handle_channel_intr; 1094 } 1095 } 1096 } 1097 1098 goto m3_handle_channel_intr_out; 1099 1100 m3_handle_channel_intr: 1101 for (i=0 ; i<sc->pch_cnt ; i++) { 1102 pch = &sc->pch[i]; 1103 if (pch->active) { 1104 pch->ptr = m3_pchan_getptr_internal(pch); 1105 delta = pch->bufsize + pch->ptr - pch->prevptr; 1106 delta %= pch->bufsize; 1107 if (delta < sndbuf_getblksz(pch->buffer)) 1108 continue; 1109 pch->prevptr = pch->ptr; 1110 M3_UNLOCK(sc); 1111 chn_intr(pch->channel); 1112 M3_LOCK(sc); 1113 } 1114 } 1115 for (i=0 ; i<sc->rch_cnt ; i++) { 1116 rch = &sc->rch[i]; 1117 if (rch->active) { 1118 rch->ptr = m3_rchan_getptr_internal(rch); 1119 delta = rch->bufsize + rch->ptr - rch->prevptr; 1120 delta %= rch->bufsize; 1121 if (delta < sndbuf_getblksz(rch->buffer)) 1122 continue; 1123 rch->prevptr = rch->ptr; 1124 M3_UNLOCK(sc); 1125 chn_intr(rch->channel); 1126 M3_LOCK(sc); 1127 } 1128 } 1129 1130 m3_handle_channel_intr_out: 1131 M3_UNLOCK(sc); 1132 } 1133 1134 /* -------------------------------------------------------------------- */ 1135 /* stuff */ 1136 1137 static int 1138 m3_power(struct sc_info *sc, int state) 1139 { 1140 u_int32_t data; 1141 1142 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state)); 1143 M3_LOCK_ASSERT(sc); 1144 1145 data = pci_read_config(sc->dev, 0x34, 1); 1146 if (pci_read_config(sc->dev, data, 1) == 1) { 1147 pci_write_config(sc->dev, data + 4, state, 1); 1148 } 1149 1150 return 0; 1151 } 1152 1153 static int 1154 m3_init(struct sc_info *sc) 1155 { 1156 u_int32_t data, i, size; 1157 u_int8_t reset_state; 1158 1159 M3_LOCK_ASSERT(sc); 1160 M3_DEBUG(CHANGE, ("m3_init\n")); 1161 1162 /* diable legacy emulations. */ 1163 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2); 1164 data |= DISABLE_LEGACY; 1165 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2); 1166 1167 m3_config(sc); 1168 1169 reset_state = m3_assp_halt(sc); 1170 1171 m3_codec_reset(sc); 1172 1173 /* [m3_assp_init] */ 1174 /* zero kernel data */ 1175 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; 1176 for(i = 0 ; i < size / 2 ; i++) { 1177 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0); 1178 } 1179 /* zero mixer data? */ 1180 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; 1181 for(i = 0 ; i < size / 2 ; i++) { 1182 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0); 1183 } 1184 /* init dma pointer */ 1185 m3_wr_assp_data(sc, KDATA_CURRENT_DMA, 1186 KDATA_DMA_XFER0); 1187 /* write kernel into code memory */ 1188 size = sizeof(assp_kernel_image); 1189 for(i = 0 ; i < size / 2; i++) { 1190 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i, 1191 assp_kernel_image[i]); 1192 } 1193 /* 1194 * We only have this one client and we know that 0x400 is free in 1195 * our kernel's mem map, so lets just drop it there. It seems that 1196 * the minisrc doesn't need vectors, so we won't bother with them.. 1197 */ 1198 size = sizeof(assp_minisrc_image); 1199 for(i = 0 ; i < size / 2; i++) { 1200 m3_wr_assp_code(sc, 0x400 + i, assp_minisrc_image[i]); 1201 } 1202 /* write the coefficients for the low pass filter? */ 1203 size = sizeof(minisrc_lpf_image); 1204 for(i = 0; i < size / 2 ; i++) { 1205 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i, 1206 minisrc_lpf_image[i]); 1207 } 1208 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000); 1209 /* the minisrc is the only thing on our task list */ 1210 m3_wr_assp_data(sc, KDATA_TASK0, 0x400); 1211 /* init the mixer number */ 1212 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0); 1213 /* extreme kernel master volume */ 1214 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); 1215 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); 1216 1217 m3_amp_enable(sc); 1218 1219 /* [m3_assp_client_init] (only one client at index 0) */ 1220 for (i=0x1100 ; i<0x1c00 ; i++) { 1221 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */ 1222 } 1223 1224 /* [m3_assp_continue] */ 1225 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); 1226 1227 return 0; 1228 } 1229 1230 static int 1231 m3_uninit(struct sc_info *sc) 1232 { 1233 M3_DEBUG(CHANGE, ("m3_uninit\n")); 1234 return 0; 1235 } 1236 1237 /* -------------------------------------------------------------------- */ 1238 /* Probe and attach the card */ 1239 1240 static int 1241 m3_pci_probe(device_t dev) 1242 { 1243 struct m3_card_type *card; 1244 1245 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev))); 1246 1247 for (card = m3_card_types ; card->pci_id ; card++) { 1248 if (pci_get_devid(dev) == card->pci_id) { 1249 device_set_desc(dev, card->name); 1250 return BUS_PROBE_DEFAULT; 1251 } 1252 } 1253 return ENXIO; 1254 } 1255 1256 static int 1257 m3_pci_attach(device_t dev) 1258 { 1259 struct sc_info *sc; 1260 struct ac97_info *codec = NULL; 1261 u_int32_t data; 1262 char status[SND_STATUSLEN]; 1263 struct m3_card_type *card; 1264 int i, len, dacn, adcn; 1265 1266 M3_DEBUG(CALL, ("m3_pci_attach\n")); 1267 1268 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 1269 sc->dev = dev; 1270 sc->type = pci_get_devid(dev); 1271 sc->sc_lock = snd_mtxcreate(device_get_nameunit(dev), 1272 "snd_maestro3 softc"); 1273 for (card = m3_card_types ; card->pci_id ; card++) { 1274 if (sc->type == card->pci_id) { 1275 sc->which = card->which; 1276 sc->delay1 = card->delay1; 1277 sc->delay2 = card->delay2; 1278 break; 1279 } 1280 } 1281 1282 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 1283 "dac", &i) == 0) { 1284 if (i < 1) 1285 dacn = 1; 1286 else if (i > M3_PCHANS) 1287 dacn = M3_PCHANS; 1288 else 1289 dacn = i; 1290 } else 1291 dacn = M3_PCHANS; 1292 1293 adcn = M3_RCHANS; 1294 1295 data = pci_read_config(dev, PCIR_COMMAND, 2); 1296 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1297 pci_write_config(dev, PCIR_COMMAND, data, 2); 1298 1299 sc->regid = PCIR_BAR(0); 1300 sc->regtype = SYS_RES_MEMORY; 1301 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 1302 RF_ACTIVE); 1303 if (!sc->reg) { 1304 sc->regtype = SYS_RES_IOPORT; 1305 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 1306 RF_ACTIVE); 1307 } 1308 if (!sc->reg) { 1309 device_printf(dev, "unable to allocate register space\n"); 1310 goto bad; 1311 } 1312 sc->st = rman_get_bustag(sc->reg); 1313 sc->sh = rman_get_bushandle(sc->reg); 1314 1315 sc->irqid = 0; 1316 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 1317 RF_ACTIVE | RF_SHAREABLE); 1318 if (!sc->irq) { 1319 device_printf(dev, "unable to allocate interrupt\n"); 1320 goto bad; 1321 } 1322 1323 if (snd_setup_intr(dev, sc->irq, INTR_MPSAFE, m3_intr, sc, &sc->ih)) { 1324 device_printf(dev, "unable to setup interrupt\n"); 1325 goto bad; 1326 } 1327 1328 sc->bufsz = pcm_getbuffersize(dev, M3_BUFSIZE_MIN, M3_BUFSIZE_DEFAULT, 1329 M3_BUFSIZE_MAX); 1330 1331 if (bus_dma_tag_create( 1332 bus_get_dma_tag(dev), /* parent */ 1333 2, 0, /* alignment, boundary */ 1334 M3_MAXADDR, /* lowaddr */ 1335 BUS_SPACE_MAXADDR, /* highaddr */ 1336 NULL, NULL, /* filtfunc, filtfuncarg */ 1337 sc->bufsz, /* maxsize */ 1338 1, /* nsegments */ 1339 0x3ffff, /* maxsegz */ 1340 0, /* flags */ 1341 NULL, /* lockfunc */ 1342 NULL, /* lockfuncarg */ 1343 &sc->parent_dmat) != 0) { 1344 device_printf(dev, "unable to create dma tag\n"); 1345 goto bad; 1346 } 1347 1348 M3_LOCK(sc); 1349 m3_power(sc, 0); /* power up */ 1350 /* init chip */ 1351 i = m3_init(sc); 1352 M3_UNLOCK(sc); 1353 if (i == -1) { 1354 device_printf(dev, "unable to initialize the card\n"); 1355 goto bad; 1356 } 1357 1358 /* create/init mixer */ 1359 codec = AC97_CREATE(dev, sc, m3_codec); 1360 if (codec == NULL) { 1361 device_printf(dev, "ac97_create error\n"); 1362 goto bad; 1363 } 1364 if (mixer_init(dev, ac97_getmixerclass(), codec)) { 1365 device_printf(dev, "mixer_init error\n"); 1366 goto bad; 1367 } 1368 1369 m3_enable_ints(sc); 1370 1371 if (pcm_register(dev, sc, dacn, adcn)) { 1372 device_printf(dev, "pcm_register error\n"); 1373 goto bad; 1374 } 1375 for (i=0 ; i<dacn ; i++) { 1376 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) { 1377 device_printf(dev, "pcm_addchan (play) error\n"); 1378 goto bad; 1379 } 1380 } 1381 for (i=0 ; i<adcn ; i++) { 1382 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) { 1383 device_printf(dev, "pcm_addchan (rec) error\n"); 1384 goto bad; 1385 } 1386 } 1387 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s", 1388 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 1389 rman_get_start(sc->reg), rman_get_start(sc->irq), 1390 PCM_KLDSTRING(snd_maestro3)); 1391 if (pcm_setstatus(dev, status)) { 1392 device_printf(dev, "attach: pcm_setstatus error\n"); 1393 goto bad; 1394 } 1395 1396 mixer_hwvol_init(dev); 1397 1398 /* Create the buffer for saving the card state during suspend */ 1399 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH + 1400 REV_B_DATA_MEMORY_LENGTH); 1401 sc->savemem = (u_int16_t*)malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1402 1403 return 0; 1404 1405 bad: 1406 if (codec) 1407 ac97_destroy(codec); 1408 if (sc->ih) 1409 bus_teardown_intr(dev, sc->irq, sc->ih); 1410 if (sc->irq) 1411 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1412 if (sc->reg) 1413 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1414 if (sc->parent_dmat) 1415 bus_dma_tag_destroy(sc->parent_dmat); 1416 if (sc->sc_lock) 1417 snd_mtxfree(sc->sc_lock); 1418 free(sc, M_DEVBUF); 1419 return ENXIO; 1420 } 1421 1422 static int 1423 m3_pci_detach(device_t dev) 1424 { 1425 struct sc_info *sc = pcm_getdevinfo(dev); 1426 int r; 1427 1428 M3_DEBUG(CALL, ("m3_pci_detach\n")); 1429 1430 if ((r = pcm_unregister(dev)) != 0) { 1431 return r; 1432 } 1433 1434 M3_LOCK(sc); 1435 m3_uninit(sc); /* shutdown chip */ 1436 m3_power(sc, 3); /* power off */ 1437 M3_UNLOCK(sc); 1438 1439 bus_teardown_intr(dev, sc->irq, sc->ih); 1440 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1441 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1442 bus_dma_tag_destroy(sc->parent_dmat); 1443 1444 free(sc->savemem, M_DEVBUF); 1445 snd_mtxfree(sc->sc_lock); 1446 free(sc, M_DEVBUF); 1447 return 0; 1448 } 1449 1450 static int 1451 m3_pci_suspend(device_t dev) 1452 { 1453 struct sc_info *sc = pcm_getdevinfo(dev); 1454 int i, index = 0; 1455 1456 M3_DEBUG(CHANGE, ("m3_pci_suspend\n")); 1457 1458 M3_LOCK(sc); 1459 for (i=0 ; i<sc->pch_cnt ; i++) { 1460 if (sc->pch[i].active) { 1461 m3_pchan_trigger_locked(NULL, &sc->pch[i], 1462 PCMTRIG_STOP); 1463 } 1464 } 1465 for (i=0 ; i<sc->rch_cnt ; i++) { 1466 if (sc->rch[i].active) { 1467 m3_rchan_trigger_locked(NULL, &sc->rch[i], 1468 PCMTRIG_STOP); 1469 } 1470 } 1471 DELAY(10 * 1000); /* give things a chance to stop */ 1472 1473 /* Disable interrupts */ 1474 m3_wr_2(sc, HOST_INT_CTRL, 0); 1475 m3_wr_1(sc, ASSP_CONTROL_C, 0); 1476 1477 m3_assp_halt(sc); 1478 1479 /* Save the state of the ASSP */ 1480 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 1481 sc->savemem[index++] = m3_rd_assp_code(sc, i); 1482 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) 1483 sc->savemem[index++] = m3_rd_assp_data(sc, i); 1484 1485 /* Power down the card to D3 state */ 1486 m3_power(sc, 3); 1487 M3_UNLOCK(sc); 1488 1489 return 0; 1490 } 1491 1492 static int 1493 m3_pci_resume(device_t dev) 1494 { 1495 struct sc_info *sc = pcm_getdevinfo(dev); 1496 int i, index = 0; 1497 u_int8_t reset_state; 1498 1499 M3_DEBUG(CHANGE, ("m3_pci_resume\n")); 1500 1501 M3_LOCK(sc); 1502 /* Power the card back to D0 */ 1503 m3_power(sc, 0); 1504 1505 m3_config(sc); 1506 1507 reset_state = m3_assp_halt(sc); 1508 1509 m3_codec_reset(sc); 1510 1511 /* Restore the ASSP state */ 1512 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 1513 m3_wr_assp_code(sc, i, sc->savemem[index++]); 1514 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) 1515 m3_wr_assp_data(sc, i, sc->savemem[index++]); 1516 1517 /* Restart the DMA engine */ 1518 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0); 1519 1520 /* [m3_assp_continue] */ 1521 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); 1522 1523 m3_amp_enable(sc); 1524 1525 m3_enable_ints(sc); 1526 1527 M3_UNLOCK(sc); /* XXX */ 1528 if (mixer_reinit(dev) == -1) { 1529 device_printf(dev, "unable to reinitialize the mixer\n"); 1530 return (ENXIO); 1531 } 1532 M3_LOCK(sc); 1533 1534 /* Turn the channels back on */ 1535 for (i=0 ; i<sc->pch_cnt ; i++) { 1536 if (sc->pch[i].active) { 1537 m3_pchan_trigger_locked(NULL, &sc->pch[i], 1538 PCMTRIG_START); 1539 } 1540 } 1541 for (i=0 ; i<sc->rch_cnt ; i++) { 1542 if (sc->rch[i].active) { 1543 m3_rchan_trigger_locked(NULL, &sc->rch[i], 1544 PCMTRIG_START); 1545 } 1546 } 1547 1548 M3_UNLOCK(sc); 1549 return 0; 1550 } 1551 1552 static int 1553 m3_pci_shutdown(device_t dev) 1554 { 1555 struct sc_info *sc = pcm_getdevinfo(dev); 1556 1557 M3_DEBUG(CALL, ("m3_pci_shutdown\n")); 1558 1559 M3_LOCK(sc); 1560 m3_power(sc, 3); /* power off */ 1561 M3_UNLOCK(sc); 1562 1563 return 0; 1564 } 1565 1566 static u_int8_t 1567 m3_assp_halt(struct sc_info *sc) 1568 { 1569 u_int8_t data, reset_state; 1570 1571 M3_LOCK_ASSERT(sc); 1572 1573 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B); 1574 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */ 1575 DELAY(10 * 1000); 1576 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET); 1577 DELAY(10 * 1000); /* necessary? */ 1578 1579 return reset_state; 1580 } 1581 1582 static void 1583 m3_config(struct sc_info *sc) 1584 { 1585 u_int32_t data, hv_cfg; 1586 int hint; 1587 1588 M3_LOCK_ASSERT(sc); 1589 1590 M3_UNLOCK(sc); 1591 /* 1592 * The volume buttons can be wired up via two different sets of pins. 1593 * This presents a problem since we can't tell which way it's 1594 * configured. Allow the user to set a hint in order to twiddle 1595 * the proper bits. 1596 */ 1597 if (resource_int_value(device_get_name(sc->dev), 1598 device_get_unit(sc->dev), 1599 "hwvol_config", &hint) == 0) 1600 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0; 1601 else 1602 hv_cfg = HV_BUTTON_FROM_GD; 1603 M3_LOCK(sc); 1604 1605 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); 1606 data &= ~HV_BUTTON_FROM_GD; 1607 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg; 1608 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; 1609 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); 1610 1611 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP); 1612 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); 1613 data &= ~INT_CLK_SELECT; 1614 if (sc->which == ESS_MAESTRO3) { 1615 data &= ~INT_CLK_MULT_ENABLE; 1616 data |= INT_CLK_SRC_NOT_PCI; 1617 } 1618 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2); 1619 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); 1620 1621 if (sc->which == ESS_ALLEGRO_1) { 1622 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4); 1623 data |= IN_CLK_12MHZ_SELECT; 1624 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4); 1625 } 1626 1627 data = m3_rd_1(sc, ASSP_CONTROL_A); 1628 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); 1629 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/ 1630 data |= ASSP_0_WS_ENABLE; 1631 m3_wr_1(sc, ASSP_CONTROL_A, data); 1632 1633 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP); 1634 } 1635 1636 static void 1637 m3_enable_ints(struct sc_info *sc) 1638 { 1639 u_int8_t data; 1640 1641 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE); 1642 data = m3_rd_1(sc, ASSP_CONTROL_C); 1643 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE); 1644 } 1645 1646 static void 1647 m3_amp_enable(struct sc_info *sc) 1648 { 1649 u_int32_t gpo, polarity_port, polarity; 1650 u_int16_t data; 1651 1652 M3_LOCK_ASSERT(sc); 1653 1654 switch (sc->which) { 1655 case ESS_ALLEGRO_1: 1656 polarity_port = 0x1800; 1657 break; 1658 case ESS_MAESTRO3: 1659 polarity_port = 0x1100; 1660 break; 1661 default: 1662 panic("bad sc->which"); 1663 } 1664 gpo = (polarity_port >> 8) & 0x0f; 1665 polarity = polarity_port >> 12; 1666 polarity = !polarity; /* enable */ 1667 polarity = polarity << gpo; 1668 gpo = 1 << gpo; 1669 m3_wr_2(sc, GPIO_MASK, ~gpo); 1670 data = m3_rd_2(sc, GPIO_DIRECTION); 1671 m3_wr_2(sc, GPIO_DIRECTION, data | gpo); 1672 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity; 1673 m3_wr_2(sc, GPIO_DATA, data); 1674 m3_wr_2(sc, GPIO_MASK, ~0); 1675 } 1676 1677 static void 1678 m3_codec_reset(struct sc_info *sc) 1679 { 1680 u_int16_t data, dir; 1681 int retry = 0; 1682 1683 M3_LOCK_ASSERT(sc); 1684 do { 1685 data = m3_rd_2(sc, GPIO_DIRECTION); 1686 dir = data | 0x10; /* assuming pci bus master? */ 1687 1688 /* [[remote_codec_config]] */ 1689 data = m3_rd_2(sc, RING_BUS_CTRL_B); 1690 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK); 1691 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL); 1692 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT); 1693 data = m3_rd_2(sc, SDO_IN_DEST_CTRL); 1694 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN); 1695 1696 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE); 1697 DELAY(20); 1698 1699 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97); 1700 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97); 1701 m3_wr_2(sc, GPIO_DATA, 0); 1702 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97); 1703 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/ 1704 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97); 1705 DELAY(5); 1706 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE | 1707 SERIAL_AC_LINK_ENABLE); 1708 m3_wr_2(sc, GPIO_MASK, ~0); 1709 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/ 1710 1711 /* [[try read vendor]] */ 1712 data = m3_rdcd(NULL, sc, 0x7c); 1713 if ((data == 0) || (data == 0xffff)) { 1714 retry++; 1715 if (retry > 3) { 1716 device_printf(sc->dev, "Codec reset failed\n"); 1717 break; 1718 } 1719 device_printf(sc->dev, "Codec reset retry\n"); 1720 } else retry = 0; 1721 } while (retry); 1722 } 1723 1724 static device_method_t m3_methods[] = { 1725 DEVMETHOD(device_probe, m3_pci_probe), 1726 DEVMETHOD(device_attach, m3_pci_attach), 1727 DEVMETHOD(device_detach, m3_pci_detach), 1728 DEVMETHOD(device_suspend, m3_pci_suspend), 1729 DEVMETHOD(device_resume, m3_pci_resume), 1730 DEVMETHOD(device_shutdown, m3_pci_shutdown), 1731 { 0, 0 } 1732 }; 1733 1734 static driver_t m3_driver = { 1735 "pcm", 1736 m3_methods, 1737 PCM_SOFTC_SIZE, 1738 }; 1739 1740 DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, 0, 0); 1741 MODULE_DEPEND(snd_maestro3, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1742 MODULE_VERSION(snd_maestro3, 1); 1743