1 /*- 2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org> 3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* 31 * Maestro-3/Allegro FreeBSD pcm sound driver 32 * 33 * executive status summary: 34 * (+) /dev/dsp multiple concurrent play channels. 35 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit). 36 * (+) /dev/mixer sets left/right volumes. 37 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel 38 * (+) apm suspend/resume works, and works properly!. 39 * (-) hardware volme controls don't work =-( 40 * (-) setblocksize() does nothing. 41 * 42 * The real credit goes to: 43 * 44 * Zach Brown for his Linux driver core and helpful technical comments. 45 * <zab@zabbo.net>, http://www.zabbo.net/maestro3 46 * 47 * Cameron Grant created the pcm framework used here nearly verbatim. 48 * <cg@freebsd.org>, http://people.freebsd.org/~cg/template.c 49 * 50 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference. 51 * <taku@cent.saitama-u.ac.jp> 52 * 53 * ESS docs explained a few magic registers and numbers. 54 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz 55 */ 56 57 #include <dev/sound/pcm/sound.h> 58 #include <dev/sound/pcm/ac97.h> 59 60 #include <pci/pcireg.h> 61 #include <pci/pcivar.h> 62 63 #include <gnu/dev/sound/pci/maestro3_reg.h> 64 #include <gnu/dev/sound/pci/maestro3_dsp.h> 65 66 /* -------------------------------------------------------------------- */ 67 68 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1}; 69 #ifndef M3_DEBUG_LEVEL 70 #define M3_DEBUG_LEVEL NONE 71 #endif 72 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}} 73 74 /* -------------------------------------------------------------------- */ 75 enum { 76 ESS_ALLEGRO_1, 77 ESS_MAESTRO3 78 }; 79 80 static struct m3_card_type { 81 u_int32_t pci_id; int which; int delay1; int delay2; char *name; 82 } m3_card_types[] = { 83 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" }, 84 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, 85 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, 86 { 0, 0, 0, 0, NULL } 87 }; 88 89 #define M3_BUFSIZE 4096 90 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */ 91 #define M3_RCHANS 1 92 93 struct sc_info; 94 95 struct sc_pchinfo { 96 u_int32_t spd; 97 u_int32_t fmt; 98 struct snd_dbuf *buffer; 99 struct pcm_channel *channel; 100 struct sc_info *parent; 101 u_int32_t bufsize; 102 u_int32_t dac_data; 103 u_int32_t dac_idx; 104 u_int32_t active; 105 }; 106 107 struct sc_rchinfo { 108 u_int32_t spd; 109 u_int32_t fmt; 110 struct snd_dbuf *buffer; 111 struct pcm_channel *channel; 112 struct sc_info *parent; 113 u_int32_t bufsize; 114 u_int32_t adc_data; 115 u_int32_t adc_idx; 116 u_int32_t active; 117 }; 118 119 struct sc_info { 120 device_t dev; 121 u_int32_t type; 122 int which; 123 int delay1; 124 int delay2; 125 126 bus_space_tag_t st; 127 bus_space_handle_t sh; 128 bus_dma_tag_t parent_dmat; 129 130 struct resource *reg; 131 struct resource *irq; 132 int regtype; 133 int regid; 134 int irqid; 135 void *ih; 136 137 struct sc_pchinfo pch[M3_PCHANS]; 138 struct sc_rchinfo rch[M3_RCHANS]; 139 int pch_cnt; 140 int rch_cnt; 141 int pch_active_cnt; 142 u_int16_t *savemem; 143 }; 144 145 /* -------------------------------------------------------------------- */ 146 147 /* play channel interface */ 148 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int); 149 static int m3_pchan_free(kobj_t, void *); 150 static int m3_pchan_setformat(kobj_t, void *, u_int32_t); 151 static int m3_pchan_setspeed(kobj_t, void *, u_int32_t); 152 static int m3_pchan_setblocksize(kobj_t, void *, u_int32_t); 153 static int m3_pchan_trigger(kobj_t, void *, int); 154 static int m3_pchan_getptr(kobj_t, void *); 155 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *); 156 157 /* record channel interface */ 158 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int); 159 static int m3_rchan_free(kobj_t, void *); 160 static int m3_rchan_setformat(kobj_t, void *, u_int32_t); 161 static int m3_rchan_setspeed(kobj_t, void *, u_int32_t); 162 static int m3_rchan_setblocksize(kobj_t, void *, u_int32_t); 163 static int m3_rchan_trigger(kobj_t, void *, int); 164 static int m3_rchan_getptr(kobj_t, void *); 165 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *); 166 167 /* talk to the codec - called from ac97.c */ 168 static int m3_initcd(kobj_t, void *); 169 static int m3_rdcd(kobj_t, void *, int); 170 static int m3_wrcd(kobj_t, void *, int, u_int32_t); 171 172 /* stuff */ 173 static void m3_intr(void *); 174 static int m3_power(struct sc_info *, int); 175 static int m3_init(struct sc_info *); 176 static int m3_uninit(struct sc_info *); 177 static u_int8_t m3_assp_halt(struct sc_info *); 178 static void m3_config(struct sc_info *); 179 static void m3_amp_enable(struct sc_info *); 180 static void m3_enable_ints(struct sc_info *); 181 static void m3_codec_reset(struct sc_info *); 182 183 /* -------------------------------------------------------------------- */ 184 /* Codec descriptor */ 185 static kobj_method_t m3_codec_methods[] = { 186 KOBJMETHOD(ac97_init, m3_initcd), 187 KOBJMETHOD(ac97_read, m3_rdcd), 188 KOBJMETHOD(ac97_write, m3_wrcd), 189 { 0, 0 } 190 }; 191 AC97_DECLARE(m3_codec); 192 193 /* -------------------------------------------------------------------- */ 194 /* channel descriptors */ 195 196 static u_int32_t m3_playfmt[] = { 197 AFMT_U8, 198 AFMT_STEREO | AFMT_U8, 199 AFMT_S16_LE, 200 AFMT_STEREO | AFMT_S16_LE, 201 0 202 }; 203 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0}; 204 205 static kobj_method_t m3_pch_methods[] = { 206 KOBJMETHOD(channel_init, m3_pchan_init), 207 KOBJMETHOD(channel_setformat, m3_pchan_setformat), 208 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed), 209 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize), 210 KOBJMETHOD(channel_trigger, m3_pchan_trigger), 211 KOBJMETHOD(channel_getptr, m3_pchan_getptr), 212 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps), 213 KOBJMETHOD(channel_free, m3_pchan_free), 214 { 0, 0 } 215 }; 216 CHANNEL_DECLARE(m3_pch); 217 218 static u_int32_t m3_recfmt[] = { 219 AFMT_U8, 220 AFMT_STEREO | AFMT_U8, 221 AFMT_S16_LE, 222 AFMT_STEREO | AFMT_S16_LE, 223 0 224 }; 225 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0}; 226 227 static kobj_method_t m3_rch_methods[] = { 228 KOBJMETHOD(channel_init, m3_rchan_init), 229 KOBJMETHOD(channel_setformat, m3_rchan_setformat), 230 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed), 231 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize), 232 KOBJMETHOD(channel_trigger, m3_rchan_trigger), 233 KOBJMETHOD(channel_getptr, m3_rchan_getptr), 234 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps), 235 KOBJMETHOD(channel_free, m3_rchan_free), 236 { 0, 0 } 237 }; 238 CHANNEL_DECLARE(m3_rch); 239 240 /* -------------------------------------------------------------------- */ 241 /* some i/o convenience functions */ 242 243 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno) 244 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno) 245 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno) 246 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data) 247 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data) 248 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data) 249 #define m3_rd_assp_code(sc, index) \ 250 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index) 251 #define m3_wr_assp_code(sc, index, data) \ 252 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data) 253 #define m3_rd_assp_data(sc, index) \ 254 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index) 255 #define m3_wr_assp_data(sc, index, data) \ 256 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data) 257 258 static __inline u_int16_t 259 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index) 260 { 261 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); 262 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); 263 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA); 264 } 265 266 static __inline void 267 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index, 268 u_int16_t data) 269 { 270 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); 271 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); 272 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data); 273 } 274 275 static __inline int 276 m3_wait(struct sc_info *sc) 277 { 278 int i; 279 280 for (i=0 ; i<20 ; i++) { 281 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) { 282 return 0; 283 } 284 DELAY(2); 285 } 286 return -1; 287 } 288 289 /* -------------------------------------------------------------------- */ 290 /* ac97 codec */ 291 292 static int 293 m3_initcd(kobj_t kobj, void *devinfo) 294 { 295 struct sc_info *sc = (struct sc_info *)devinfo; 296 u_int32_t data; 297 298 M3_DEBUG(CALL, ("m3_initcd\n")); 299 300 /* init ac-link */ 301 302 data = m3_rd_1(sc, CODEC_COMMAND); 303 return ((data & 0x1) ? 0 : 1); 304 } 305 306 static int 307 m3_rdcd(kobj_t kobj, void *devinfo, int regno) 308 { 309 struct sc_info *sc = (struct sc_info *)devinfo; 310 u_int32_t data; 311 312 if (m3_wait(sc)) { 313 device_printf(sc->dev, "m3_rdcd timed out.\n"); 314 return -1; 315 } 316 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80); 317 DELAY(50); /* ac97 cycle = 20.8 usec */ 318 if (m3_wait(sc)) { 319 device_printf(sc->dev, "m3_rdcd timed out.\n"); 320 return -1; 321 } 322 data = m3_rd_2(sc, CODEC_DATA); 323 return data; 324 } 325 326 static int 327 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data) 328 { 329 struct sc_info *sc = (struct sc_info *)devinfo; 330 if (m3_wait(sc)) { 331 device_printf(sc->dev, "m3_wrcd timed out.\n"); 332 return -1;; 333 } 334 m3_wr_2(sc, CODEC_DATA, data); 335 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f); 336 DELAY(50); /* ac97 cycle = 20.8 usec */ 337 return 0; 338 } 339 340 /* -------------------------------------------------------------------- */ 341 /* play channel interface */ 342 343 #define LO(x) (((x) & 0x0000ffff) ) 344 #define HI(x) (((x) & 0xffff0000) >> 16) 345 346 static void * 347 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 348 { 349 struct sc_info *sc = devinfo; 350 struct sc_pchinfo *ch; 351 u_int32_t bus_addr, i; 352 353 int idx = sc->pch_cnt; /* dac instance number, no active reuse! */ 354 int data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + 355 (MINISRC_IN_BUFFER_SIZE & ~1) + 356 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; 357 int dac_data = 0x1100 + (data_bytes * idx); 358 359 int dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); 360 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); 361 int dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2); 362 int dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1; 363 364 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx)); 365 366 if (dir != PCMDIR_PLAY) { 367 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n"); 368 return NULL; 369 } 370 ch = &sc->pch[idx]; 371 372 ch->dac_idx = idx; 373 ch->dac_data = dac_data; 374 if (ch->dac_data + data_bytes/2 >= 0x1c00) { 375 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n"); 376 return NULL; 377 } 378 379 ch->buffer = b; 380 ch->parent = sc; 381 ch->channel = c; 382 ch->fmt = AFMT_U8; 383 ch->spd = DSP_DEFAULT_SPEED; 384 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, M3_BUFSIZE) == -1) { 385 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n"); 386 return NULL; 387 } 388 ch->bufsize = sndbuf_getsize(ch->buffer); 389 390 /* host dma buffer pointers */ 391 bus_addr = vtophys(sndbuf_getbuf(ch->buffer)); 392 if (bus_addr & 3) { 393 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n"); 394 bus_addr = (bus_addr + 4) & ~3; 395 } 396 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); 397 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); 398 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L, 399 LO(bus_addr + ch->bufsize)); 400 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H, 401 HI(bus_addr + ch->bufsize)); 402 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL, 403 LO(bus_addr)); 404 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH, 405 HI(bus_addr)); 406 407 /* dsp buffers */ 408 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); 409 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1, 410 dsp_in_buf + dsp_in_size/2); 411 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf); 412 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf); 413 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); 414 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1, 415 dsp_out_buf + dsp_out_size/2); 416 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); 417 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); 418 419 /* some per client initializers */ 420 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12, 421 ch->dac_data + 40 + 8); 422 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19, 423 0x400 + MINISRC_COEF_LOC); 424 /* enable or disable low pass filter? (0xff if rate> 45000) */ 425 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0); 426 /* tell it which way dma is going? */ 427 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL, 428 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + 429 DMAC_BLOCKF_SELECTOR); 430 431 /* set an armload of static initializers */ 432 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) { 433 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val); 434 } 435 436 /* put us in the packed task lists */ 437 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 438 (sc->pch_cnt + sc->rch_cnt), 439 ch->dac_data >> DP_SHIFT_COUNT); 440 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), 441 ch->dac_data >> DP_SHIFT_COUNT); 442 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt, 443 ch->dac_data >> DP_SHIFT_COUNT); 444 445 m3_pchan_trigger(NULL, ch, PCMTRIG_START); /* gotta start before stop */ 446 m3_pchan_trigger(NULL, ch, PCMTRIG_STOP); /* silence noise on load */ 447 448 sc->pch_cnt++; 449 return ch; 450 } 451 452 static int 453 m3_pchan_free(kobj_t kobj, void *chdata) 454 { 455 struct sc_pchinfo *ch = chdata; 456 struct sc_info *sc = ch->parent; 457 458 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx)); 459 460 /* 461 * should remove this exact instance from the packed lists, but all 462 * are released at once (and in a stopped state) so this is ok. 463 */ 464 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 465 (sc->pch_cnt - 1) + sc->rch_cnt, 0); 466 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + 467 (sc->pch_cnt - 1) + sc->rch_cnt, 0); 468 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0); 469 470 sc->pch_cnt--; 471 return 0; 472 } 473 474 static int 475 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) 476 { 477 struct sc_pchinfo *ch = chdata; 478 struct sc_info *sc = ch->parent; 479 u_int32_t data; 480 481 M3_DEBUG(CHANGE, 482 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n", 483 ch->dac_idx, format, 484 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", 485 format & AFMT_STEREO ? "STEREO":"MONO")); 486 487 /* mono word */ 488 data = (format & AFMT_STEREO) ? 0 : 1; 489 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data); 490 491 /* 8bit word */ 492 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; 493 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data); 494 495 ch->fmt = format; 496 return format; 497 } 498 499 static int 500 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) 501 { 502 struct sc_pchinfo *ch = chdata; 503 struct sc_info *sc = ch->parent; 504 u_int32_t freq; 505 506 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n", 507 ch->dac_idx, speed)); 508 509 if ((freq = ((speed << 15) + 24000) / 48000) != 0) { 510 freq--; 511 } 512 513 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq); 514 515 ch->spd = speed; 516 return speed; /* return closest possible speed */ 517 } 518 519 static int 520 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) 521 { 522 struct sc_pchinfo *ch = chdata; 523 524 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n", 525 ch->dac_idx, blocksize)); 526 527 return blocksize; 528 } 529 530 static int 531 m3_pchan_trigger(kobj_t kobj, void *chdata, int go) 532 { 533 struct sc_pchinfo *ch = chdata; 534 struct sc_info *sc = ch->parent; 535 u_int32_t data; 536 537 M3_DEBUG(go == PCMTRIG_START ? CHANGE : 538 go == PCMTRIG_STOP ? CHANGE : 539 go == PCMTRIG_ABORT ? CHANGE : 540 CALL, 541 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go, 542 go == PCMTRIG_START ? "PCMTRIG_START" : 543 go == PCMTRIG_STOP ? "PCMTRIG_STOP" : 544 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); 545 546 switch(go) { 547 case PCMTRIG_START: 548 if (ch->active) { 549 return 0; 550 } 551 ch->active = 1; 552 sc->pch_active_cnt++; 553 554 /*[[inc_timer_users]]*/ 555 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); 556 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); 557 data = m3_rd_2(sc, HOST_INT_CTRL); 558 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); 559 560 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1); 561 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 562 sc->pch_active_cnt); 563 break; 564 565 case PCMTRIG_STOP: 566 case PCMTRIG_ABORT: 567 if (ch->active == 0) { 568 return 0; 569 } 570 ch->active = 0; 571 sc->pch_active_cnt--; 572 573 /* XXX should the channel be drained? */ 574 /*[[dec_timer_users]]*/ 575 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); 576 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); 577 data = m3_rd_2(sc, HOST_INT_CTRL); 578 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); 579 580 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0); 581 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 582 sc->pch_active_cnt); 583 break; 584 585 case PCMTRIG_EMLDMAWR: 586 /* got play irq, transfer next buffer - ignore if using dma */ 587 case PCMTRIG_EMLDMARD: 588 /* got rec irq, transfer next buffer - ignore if using dma */ 589 default: 590 break; 591 } 592 return 0; 593 } 594 595 static int 596 m3_pchan_getptr(kobj_t kobj, void *chdata) 597 { 598 struct sc_pchinfo *ch = chdata; 599 struct sc_info *sc = ch->parent; 600 u_int32_t hi, lo, bus_crnt; 601 u_int32_t bus_base = vtophys(sndbuf_getbuf(ch->buffer)); 602 603 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH); 604 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL); 605 bus_crnt = lo | (hi << 16); 606 607 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n", 608 ch->dac_idx, bus_crnt - bus_base)); 609 610 return (bus_crnt - bus_base); /* current byte offset of channel */ 611 } 612 613 static struct pcmchan_caps * 614 m3_pchan_getcaps(kobj_t kobj, void *chdata) 615 { 616 struct sc_pchinfo *ch = chdata; 617 618 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx)); 619 620 return &m3_playcaps; 621 } 622 623 /* -------------------------------------------------------------------- */ 624 /* rec channel interface */ 625 626 static void * 627 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 628 { 629 struct sc_info *sc = devinfo; 630 struct sc_rchinfo *ch; 631 u_int32_t bus_addr, i; 632 633 int idx = sc->rch_cnt; /* adc instance number, no active reuse! */ 634 int data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + 635 (MINISRC_IN_BUFFER_SIZE & ~1) + 636 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; 637 int adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2; 638 639 int dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2); 640 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); 641 int dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2); 642 int dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1; 643 644 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx)); 645 646 if (dir != PCMDIR_REC) { 647 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n"); 648 return NULL; 649 } 650 ch = &sc->rch[idx]; 651 652 ch->adc_idx = idx; 653 ch->adc_data = adc_data; 654 if (ch->adc_data + data_bytes/2 >= 0x1c00) { 655 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n"); 656 return NULL; 657 } 658 659 ch->buffer = b; 660 ch->parent = sc; 661 ch->channel = c; 662 ch->fmt = AFMT_U8; 663 ch->spd = DSP_DEFAULT_SPEED; 664 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, M3_BUFSIZE) == -1) { 665 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n"); 666 return NULL; 667 } 668 ch->bufsize = sndbuf_getsize(ch->buffer); 669 670 /* host dma buffer pointers */ 671 bus_addr = vtophys(sndbuf_getbuf(ch->buffer)); 672 if (bus_addr & 3) { 673 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n"); 674 bus_addr = (bus_addr + 4) & ~3; 675 } 676 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); 677 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); 678 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L, 679 LO(bus_addr + ch->bufsize)); 680 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H, 681 HI(bus_addr + ch->bufsize)); 682 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL, 683 LO(bus_addr)); 684 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH, 685 HI(bus_addr)); 686 687 /* dsp buffers */ 688 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); 689 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1, 690 dsp_in_buf + dsp_in_size/2); 691 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf); 692 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf); 693 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); 694 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1, 695 dsp_out_buf + dsp_out_size/2); 696 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); 697 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); 698 699 /* some per client initializers */ 700 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12, 701 ch->adc_data + 40 + 8); 702 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL, 703 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + 704 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 705 706 /* set an armload of static initializers */ 707 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) { 708 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val); 709 } 710 711 /* put us in the packed task lists */ 712 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 713 (sc->pch_cnt + sc->rch_cnt), 714 ch->adc_data >> DP_SHIFT_COUNT); 715 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), 716 ch->adc_data >> DP_SHIFT_COUNT); 717 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt, 718 ch->adc_data >> DP_SHIFT_COUNT); 719 720 m3_rchan_trigger(NULL, ch, PCMTRIG_START); /* gotta start before stop */ 721 m3_rchan_trigger(NULL, ch, PCMTRIG_STOP); /* stop on init */ 722 723 sc->rch_cnt++; 724 return ch; 725 } 726 727 static int 728 m3_rchan_free(kobj_t kobj, void *chdata) 729 { 730 struct sc_rchinfo *ch = chdata; 731 struct sc_info *sc = ch->parent; 732 733 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx)); 734 735 /* 736 * should remove this exact instance from the packed lists, but all 737 * are released at once (and in a stopped state) so this is ok. 738 */ 739 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 740 (sc->rch_cnt - 1) + sc->pch_cnt, 0); 741 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + 742 (sc->rch_cnt - 1) + sc->pch_cnt, 0); 743 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0); 744 745 sc->rch_cnt--; 746 return 0; 747 } 748 749 static int 750 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) 751 { 752 struct sc_rchinfo *ch = chdata; 753 struct sc_info *sc = ch->parent; 754 u_int32_t data; 755 756 M3_DEBUG(CHANGE, 757 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n", 758 ch->adc_idx, format, 759 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", 760 format & AFMT_STEREO ? "STEREO":"MONO")); 761 762 /* mono word */ 763 data = (format & AFMT_STEREO) ? 0 : 1; 764 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data); 765 766 /* 8bit word */ 767 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; 768 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data); 769 770 ch->fmt = format; 771 return format; 772 } 773 774 static int 775 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) 776 { 777 struct sc_rchinfo *ch = chdata; 778 struct sc_info *sc = ch->parent; 779 u_int32_t freq; 780 781 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n", 782 ch->adc_idx, speed)); 783 784 if ((freq = ((speed << 15) + 24000) / 48000) != 0) { 785 freq--; 786 } 787 788 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq); 789 790 ch->spd = speed; 791 return speed; /* return closest possible speed */ 792 } 793 794 static int 795 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) 796 { 797 struct sc_rchinfo *ch = chdata; 798 799 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n", 800 ch->adc_idx, blocksize)); 801 802 return blocksize; 803 } 804 805 static int 806 m3_rchan_trigger(kobj_t kobj, void *chdata, int go) 807 { 808 struct sc_rchinfo *ch = chdata; 809 struct sc_info *sc = ch->parent; 810 u_int32_t data; 811 812 M3_DEBUG(go == PCMTRIG_START ? CHANGE : 813 go == PCMTRIG_STOP ? CHANGE : 814 go == PCMTRIG_ABORT ? CHANGE : 815 CALL, 816 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go, 817 go == PCMTRIG_START ? "PCMTRIG_START" : 818 go == PCMTRIG_STOP ? "PCMTRIG_STOP" : 819 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); 820 821 switch(go) { 822 case PCMTRIG_START: 823 if (ch->active) { 824 return 0; 825 } 826 ch->active = 1; 827 828 /*[[inc_timer_users]]*/ 829 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); 830 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); 831 data = m3_rd_2(sc, HOST_INT_CTRL); 832 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); 833 834 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1); 835 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1); 836 break; 837 838 case PCMTRIG_STOP: 839 case PCMTRIG_ABORT: 840 if (ch->active == 0) { 841 return 0; 842 } 843 ch->active = 0; 844 845 /*[[dec_timer_users]]*/ 846 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); 847 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); 848 data = m3_rd_2(sc, HOST_INT_CTRL); 849 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); 850 851 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0); 852 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0); 853 break; 854 855 case PCMTRIG_EMLDMAWR: 856 /* got play irq, transfer next buffer - ignore if using dma */ 857 case PCMTRIG_EMLDMARD: 858 /* got rec irq, transfer next buffer - ignore if using dma */ 859 default: 860 break; 861 } 862 return 0; 863 } 864 865 static int 866 m3_rchan_getptr(kobj_t kobj, void *chdata) 867 { 868 struct sc_rchinfo *ch = chdata; 869 struct sc_info *sc = ch->parent; 870 u_int32_t hi, lo, bus_crnt; 871 u_int32_t bus_base = vtophys(sndbuf_getbuf(ch->buffer)); 872 873 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH); 874 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL); 875 bus_crnt = lo | (hi << 16); 876 877 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n", 878 ch->adc_idx, bus_crnt - bus_base)); 879 880 return (bus_crnt - bus_base); /* current byte offset of channel */ 881 } 882 883 static struct pcmchan_caps * 884 m3_rchan_getcaps(kobj_t kobj, void *chdata) 885 { 886 struct sc_rchinfo *ch = chdata; 887 888 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx)); 889 890 return &m3_reccaps; 891 } 892 893 /* -------------------------------------------------------------------- */ 894 /* The interrupt handler */ 895 896 static void 897 m3_intr(void *p) 898 { 899 struct sc_info *sc = (struct sc_info *)p; 900 u_int32_t status, ctl, i; 901 902 M3_DEBUG(INTR, ("m3_intr\n")); 903 904 status = m3_rd_1(sc, HOST_INT_STATUS); 905 if (!status) 906 return; 907 908 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */ 909 910 if (status & HV_INT_PENDING) { 911 u_int8_t event; 912 913 device_printf(sc->dev, "Hardware Volume Interrupt\n"); 914 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER); 915 switch (event) { 916 case 0x99: 917 mixer_hwvol_mute(sc->dev); 918 break; 919 case 0xaa: 920 mixer_hwvol_step(sc->dev, 1, 1); 921 break; 922 case 0x66: 923 mixer_hwvol_step(sc->dev, -1, -1); 924 break; 925 case 0x88: 926 break; 927 default: 928 device_printf(sc->dev, "Unknown HWVOL event\n"); 929 } 930 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88); 931 932 } 933 934 if (status & ASSP_INT_PENDING) { 935 ctl = m3_rd_1(sc, ASSP_CONTROL_B); 936 if (!(ctl & STOP_ASSP_CLOCK)) { 937 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS); 938 if (ctl & DSP2HOST_REQ_TIMER) { 939 m3_wr_1(sc, ASSP_HOST_INT_STATUS, 940 DSP2HOST_REQ_TIMER); 941 /*[[ess_update_ptr]]*/ 942 } 943 } 944 } 945 946 for (i=0 ; i<sc->pch_cnt ; i++) { 947 if (sc->pch[i].active) { 948 chn_intr(sc->pch[i].channel); 949 } 950 } 951 for (i=0 ; i<sc->rch_cnt ; i++) { 952 if (sc->rch[i].active) { 953 chn_intr(sc->rch[i].channel); 954 } 955 } 956 } 957 958 /* -------------------------------------------------------------------- */ 959 /* stuff */ 960 961 static int 962 m3_power(struct sc_info *sc, int state) 963 { 964 u_int32_t data; 965 966 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state)); 967 968 data = pci_read_config(sc->dev, 0x34, 1); 969 if (pci_read_config(sc->dev, data, 1) == 1) { 970 pci_write_config(sc->dev, data + 4, state, 1); 971 } 972 973 return 0; 974 } 975 976 static int 977 m3_init(struct sc_info *sc) 978 { 979 u_int32_t data, i, size; 980 u_int8_t reset_state; 981 982 M3_DEBUG(CHANGE, ("m3_init\n")); 983 984 /* diable legacy emulations. */ 985 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2); 986 data |= DISABLE_LEGACY; 987 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2); 988 989 m3_config(sc); 990 991 reset_state = m3_assp_halt(sc); 992 993 m3_codec_reset(sc); 994 995 /* [m3_assp_init] */ 996 /* zero kernel data */ 997 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; 998 for(i = 0 ; i < size / 2 ; i++) { 999 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0); 1000 } 1001 /* zero mixer data? */ 1002 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; 1003 for(i = 0 ; i < size / 2 ; i++) { 1004 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0); 1005 } 1006 /* init dma pointer */ 1007 m3_wr_assp_data(sc, KDATA_CURRENT_DMA, 1008 KDATA_DMA_XFER0); 1009 /* write kernel into code memory */ 1010 size = sizeof(assp_kernel_image); 1011 for(i = 0 ; i < size / 2; i++) { 1012 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i, 1013 assp_kernel_image[i]); 1014 } 1015 /* 1016 * We only have this one client and we know that 0x400 is free in 1017 * our kernel's mem map, so lets just drop it there. It seems that 1018 * the minisrc doesn't need vectors, so we won't bother with them.. 1019 */ 1020 size = sizeof(assp_minisrc_image); 1021 for(i = 0 ; i < size / 2; i++) { 1022 m3_wr_assp_code(sc, 0x400 + i, assp_minisrc_image[i]); 1023 } 1024 /* write the coefficients for the low pass filter? */ 1025 size = sizeof(minisrc_lpf_image); 1026 for(i = 0; i < size / 2 ; i++) { 1027 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i, 1028 minisrc_lpf_image[i]); 1029 } 1030 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000); 1031 /* the minisrc is the only thing on our task list */ 1032 m3_wr_assp_data(sc, KDATA_TASK0, 0x400); 1033 /* init the mixer number */ 1034 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0); 1035 /* extreme kernel master volume */ 1036 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); 1037 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); 1038 1039 m3_amp_enable(sc); 1040 1041 /* [m3_assp_client_init] (only one client at index 0) */ 1042 for (i=0x1100 ; i<0x1c00 ; i++) { 1043 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */ 1044 } 1045 1046 m3_enable_ints(sc); 1047 1048 /* [m3_assp_continue] */ 1049 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); 1050 1051 return 0; 1052 } 1053 1054 static int 1055 m3_uninit(struct sc_info *sc) 1056 { 1057 M3_DEBUG(CHANGE, ("m3_uninit\n")); 1058 return 0; 1059 } 1060 1061 /* -------------------------------------------------------------------- */ 1062 /* Probe and attach the card */ 1063 1064 static int 1065 m3_pci_probe(device_t dev) 1066 { 1067 struct m3_card_type *card; 1068 1069 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev))); 1070 1071 for (card = m3_card_types ; card->pci_id ; card++) { 1072 if (pci_get_devid(dev) == card->pci_id) { 1073 device_set_desc(dev, card->name); 1074 return 0; 1075 } 1076 } 1077 return ENXIO; 1078 } 1079 1080 static int 1081 m3_pci_attach(device_t dev) 1082 { 1083 struct sc_info *sc; 1084 struct ac97_info *codec = NULL; 1085 u_int32_t data, i; 1086 char status[SND_STATUSLEN]; 1087 struct m3_card_type *card; 1088 int len; 1089 1090 M3_DEBUG(CALL, ("m3_pci_attach\n")); 1091 1092 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 1093 device_printf(dev, "cannot allocate softc\n"); 1094 return ENXIO; 1095 } 1096 1097 sc->dev = dev; 1098 sc->type = pci_get_devid(dev); 1099 1100 for (card = m3_card_types ; card->pci_id ; card++) { 1101 if (sc->type == card->pci_id) { 1102 sc->which = card->which; 1103 sc->delay1 = card->delay1; 1104 sc->delay2 = card->delay2; 1105 break; 1106 } 1107 } 1108 1109 data = pci_read_config(dev, PCIR_COMMAND, 2); 1110 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1111 pci_write_config(dev, PCIR_COMMAND, data, 2); 1112 1113 sc->regid = PCIR_MAPS; 1114 sc->regtype = SYS_RES_MEMORY; 1115 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 1116 0, ~0, 1, RF_ACTIVE); 1117 if (!sc->reg) { 1118 sc->regtype = SYS_RES_IOPORT; 1119 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 1120 0, ~0, 1, RF_ACTIVE); 1121 } 1122 if (!sc->reg) { 1123 device_printf(dev, "unable to allocate register space\n"); 1124 goto bad; 1125 } 1126 sc->st = rman_get_bustag(sc->reg); 1127 sc->sh = rman_get_bushandle(sc->reg); 1128 1129 sc->irqid = 0; 1130 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 1131 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 1132 if (!sc->irq) { 1133 device_printf(dev, "unable to allocate interrupt\n"); 1134 goto bad; 1135 } 1136 1137 if (snd_setup_intr(dev, sc->irq, 0, m3_intr, sc, &sc->ih)) { 1138 device_printf(dev, "unable to setup interrupt\n"); 1139 goto bad; 1140 } 1141 1142 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 1143 /*lowaddr*/0x08000000, 1144 /*highaddr*/BUS_SPACE_MAXADDR, 1145 /*filter*/NULL, /*filterarg*/NULL, 1146 /*maxsize*/M3_BUFSIZE, /*nsegments*/1, 1147 /*maxsegz*/0x3ffff, 1148 /*flags*/0, &sc->parent_dmat) != 0) { 1149 device_printf(dev, "unable to create dma tag\n"); 1150 goto bad; 1151 } 1152 1153 m3_power(sc, 0); /* power up */ 1154 1155 /* init chip */ 1156 if (m3_init(sc) == -1) { 1157 device_printf(dev, "unable to initialize the card\n"); 1158 goto bad; 1159 } 1160 1161 /* create/init mixer */ 1162 codec = AC97_CREATE(dev, sc, m3_codec); 1163 if (codec == NULL) { 1164 device_printf(dev, "ac97_create error\n"); 1165 goto bad; 1166 } 1167 if (mixer_init(dev, ac97_getmixerclass(), codec)) { 1168 device_printf(dev, "mixer_init error\n"); 1169 goto bad; 1170 } 1171 1172 if (pcm_register(dev, sc, M3_PCHANS, M3_RCHANS)) { 1173 device_printf(dev, "pcm_register error\n"); 1174 goto bad; 1175 } 1176 for (i=0 ; i<M3_PCHANS ; i++) { 1177 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) { 1178 device_printf(dev, "pcm_addchan (play) error\n"); 1179 goto bad; 1180 } 1181 } 1182 for (i=0 ; i<M3_RCHANS ; i++) { 1183 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) { 1184 device_printf(dev, "pcm_addchan (rec) error\n"); 1185 goto bad; 1186 } 1187 } 1188 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld", 1189 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 1190 rman_get_start(sc->reg), rman_get_start(sc->irq)); 1191 if (pcm_setstatus(dev, status)) { 1192 device_printf(dev, "attach: pcm_setstatus error\n"); 1193 goto bad; 1194 } 1195 mixer_hwvol_init(dev); 1196 1197 /* Create the buffer for saving the card state during suspend */ 1198 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH + 1199 REV_B_DATA_MEMORY_LENGTH); 1200 sc->savemem = (u_int16_t*)malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 1201 if (sc->savemem == NULL) { 1202 device_printf(dev, "Failed to create suspend buffer\n"); 1203 goto bad; 1204 } 1205 1206 return 0; 1207 1208 bad: 1209 if (codec) { 1210 ac97_destroy(codec); 1211 } 1212 if (sc->reg) { 1213 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1214 } 1215 if (sc->ih) { 1216 bus_teardown_intr(dev, sc->irq, sc->ih); 1217 } 1218 if (sc->irq) { 1219 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1220 } 1221 if (sc->parent_dmat) { 1222 bus_dma_tag_destroy(sc->parent_dmat); 1223 } 1224 free(sc, M_DEVBUF); 1225 return ENXIO; 1226 } 1227 1228 static int 1229 m3_pci_detach(device_t dev) 1230 { 1231 struct sc_info *sc = pcm_getdevinfo(dev); 1232 int r; 1233 1234 M3_DEBUG(CALL, ("m3_pci_detach\n")); 1235 1236 if ((r = pcm_unregister(dev)) != 0) { 1237 return r; 1238 } 1239 m3_uninit(sc); /* shutdown chip */ 1240 m3_power(sc, 3); /* power off */ 1241 1242 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1243 bus_teardown_intr(dev, sc->irq, sc->ih); 1244 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1245 bus_dma_tag_destroy(sc->parent_dmat); 1246 1247 free(sc->savemem, M_DEVBUF); 1248 free(sc, M_DEVBUF); 1249 return 0; 1250 } 1251 1252 static int 1253 m3_pci_suspend(device_t dev) 1254 { 1255 struct sc_info *sc = pcm_getdevinfo(dev); 1256 int i, index = 0; 1257 1258 M3_DEBUG(CHANGE, ("m3_pci_suspend\n")); 1259 1260 for (i=0 ; i<sc->pch_cnt ; i++) { 1261 if (sc->pch[i].active) { 1262 m3_pchan_trigger(NULL, &sc->pch[i], PCMTRIG_STOP); 1263 } 1264 } 1265 for (i=0 ; i<sc->rch_cnt ; i++) { 1266 if (sc->rch[i].active) { 1267 m3_rchan_trigger(NULL, &sc->rch[i], PCMTRIG_STOP); 1268 } 1269 } 1270 DELAY(10 * 1000); /* give things a chance to stop */ 1271 1272 /* Disable interrupts */ 1273 m3_wr_2(sc, HOST_INT_CTRL, 0); 1274 m3_wr_1(sc, ASSP_CONTROL_C, 0); 1275 1276 m3_assp_halt(sc); 1277 1278 /* Save the state of the ASSP */ 1279 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 1280 sc->savemem[index++] = m3_rd_assp_code(sc, i); 1281 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) 1282 sc->savemem[index++] = m3_rd_assp_data(sc, i); 1283 1284 /* Power down the card to D3 state */ 1285 m3_power(sc, 3); 1286 1287 return 0; 1288 } 1289 1290 static int 1291 m3_pci_resume(device_t dev) 1292 { 1293 struct sc_info *sc = pcm_getdevinfo(dev); 1294 int i, index = 0; 1295 u_int8_t reset_state; 1296 1297 M3_DEBUG(CHANGE, ("m3_pci_resume\n")); 1298 1299 /* Power the card back to D0 */ 1300 m3_power(sc, 0); 1301 1302 m3_config(sc); 1303 1304 reset_state = m3_assp_halt(sc); 1305 1306 /* Restore the ASSP state */ 1307 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 1308 m3_wr_assp_code(sc, i, sc->savemem[index++]); 1309 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) 1310 m3_wr_assp_data(sc, i, sc->savemem[index++]); 1311 1312 /* Restart the DMA engine */ 1313 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0); 1314 1315 /* [m3_assp_continue] */ 1316 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); 1317 1318 m3_enable_ints(sc); 1319 1320 m3_amp_enable(sc); 1321 1322 /* Turn the channels back on */ 1323 for (i=0 ; i<sc->pch_cnt ; i++) { 1324 if (sc->pch[i].active) { 1325 m3_pchan_trigger(NULL, &sc->pch[i], PCMTRIG_START); 1326 } 1327 } 1328 for (i=0 ; i<sc->rch_cnt ; i++) { 1329 if (sc->rch[i].active) { 1330 m3_rchan_trigger(NULL, &sc->rch[i], PCMTRIG_START); 1331 } 1332 } 1333 1334 return 0; 1335 } 1336 1337 static int 1338 m3_pci_shutdown(device_t dev) 1339 { 1340 struct sc_info *sc = pcm_getdevinfo(dev); 1341 1342 M3_DEBUG(CALL, ("m3_pci_shutdown\n")); 1343 1344 m3_power(sc, 3); /* power off */ 1345 return 0; 1346 } 1347 1348 static u_int8_t 1349 m3_assp_halt(struct sc_info *sc) 1350 { 1351 u_int8_t data, reset_state; 1352 1353 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B); 1354 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */ 1355 DELAY(10 * 1000); 1356 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET); 1357 DELAY(10 * 1000); /* necessary? */ 1358 1359 return reset_state; 1360 } 1361 1362 static void 1363 m3_config(struct sc_info *sc) 1364 { 1365 u_int32_t data; 1366 1367 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); 1368 data &= REDUCED_DEBOUNCE; 1369 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; 1370 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); 1371 1372 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP); 1373 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); 1374 data &= ~INT_CLK_SELECT; 1375 if (sc->which == ESS_MAESTRO3) { 1376 data &= ~INT_CLK_MULT_ENABLE; 1377 data |= INT_CLK_SRC_NOT_PCI; 1378 } 1379 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2); 1380 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); 1381 1382 if (sc->which == ESS_ALLEGRO_1) { 1383 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4); 1384 data |= IN_CLK_12MHZ_SELECT; 1385 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4); 1386 } 1387 1388 data = m3_rd_1(sc, ASSP_CONTROL_A); 1389 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); 1390 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/ 1391 data |= ASSP_0_WS_ENABLE; 1392 m3_wr_1(sc, ASSP_CONTROL_A, data); 1393 1394 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP); 1395 } 1396 1397 static void 1398 m3_enable_ints(struct sc_info *sc) 1399 { 1400 u_int8_t data; 1401 1402 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE); 1403 data = m3_rd_1(sc, ASSP_CONTROL_C); 1404 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE); 1405 } 1406 1407 static void 1408 m3_amp_enable(struct sc_info *sc) 1409 { 1410 u_int32_t gpo, polarity_port, polarity; 1411 u_int16_t data; 1412 1413 switch (sc->which) { 1414 case ESS_ALLEGRO_1: 1415 polarity_port = 0x1800; 1416 break; 1417 case ESS_MAESTRO3: 1418 polarity_port = 0x1100; 1419 break; 1420 default: 1421 panic("bad sc->which"); 1422 } 1423 gpo = (polarity_port >> 8) & 0x0f; 1424 polarity = polarity_port >> 12; 1425 polarity = !polarity; /* enable */ 1426 polarity = polarity << gpo; 1427 gpo = 1 << gpo; 1428 m3_wr_2(sc, GPIO_MASK, ~gpo); 1429 data = m3_rd_2(sc, GPIO_DIRECTION); 1430 m3_wr_2(sc, GPIO_DIRECTION, data | gpo); 1431 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity; 1432 m3_wr_2(sc, GPIO_DATA, data); 1433 m3_wr_2(sc, GPIO_MASK, ~0); 1434 } 1435 1436 static void 1437 m3_codec_reset(struct sc_info *sc) 1438 { 1439 u_int16_t data, dir; 1440 int retry = 0; 1441 1442 do { 1443 data = m3_rd_2(sc, GPIO_DIRECTION); 1444 dir = data | 0x10; /* assuming pci bus master? */ 1445 1446 /* [[remote_codec_config]] */ 1447 data = m3_rd_2(sc, RING_BUS_CTRL_B); 1448 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK); 1449 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL); 1450 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT); 1451 data = m3_rd_2(sc, SDO_IN_DEST_CTRL); 1452 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN); 1453 1454 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE); 1455 DELAY(20); 1456 1457 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97); 1458 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97); 1459 m3_wr_2(sc, GPIO_DATA, 0); 1460 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97); 1461 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/ 1462 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97); 1463 DELAY(5); 1464 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE | 1465 SERIAL_AC_LINK_ENABLE); 1466 m3_wr_2(sc, GPIO_MASK, ~0); 1467 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/ 1468 1469 /* [[try read vendor]] */ 1470 data = m3_rdcd(NULL, sc, 0x7c); 1471 if ((data == 0) || (data == 0xffff)) { 1472 retry++; 1473 if (retry > 3) { 1474 device_printf(sc->dev, "Codec reset failed\n"); 1475 break; 1476 } 1477 device_printf(sc->dev, "Codec reset retry\n"); 1478 } else retry = 0; 1479 } while (retry); 1480 } 1481 1482 static device_method_t m3_methods[] = { 1483 DEVMETHOD(device_probe, m3_pci_probe), 1484 DEVMETHOD(device_attach, m3_pci_attach), 1485 DEVMETHOD(device_detach, m3_pci_detach), 1486 DEVMETHOD(device_suspend, m3_pci_suspend), 1487 DEVMETHOD(device_resume, m3_pci_resume), 1488 DEVMETHOD(device_shutdown, m3_pci_shutdown), 1489 { 0, 0 } 1490 }; 1491 1492 static driver_t m3_driver = { 1493 "pcm", 1494 m3_methods, 1495 sizeof(struct snddev_info), 1496 }; 1497 1498 DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, 0, 0); 1499 MODULE_DEPEND(snd_maestro3, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1500 MODULE_VERSION(snd_maestro3, 1); 1501