1 /*- 2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org> 3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Maestro-3/Allegro FreeBSD pcm sound driver 30 * 31 * executive status summary: 32 * (+) /dev/dsp multiple concurrent play channels. 33 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit). 34 * (+) /dev/mixer sets left/right volumes. 35 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel 36 * (+) apm suspend/resume works, and works properly!. 37 * (-) hardware volme controls don't work =-( 38 * (-) setblocksize() does nothing. 39 * 40 * The real credit goes to: 41 * 42 * Zach Brown for his Linux driver core and helpful technical comments. 43 * <zab@zabbo.net>, http://www.zabbo.net/maestro3 44 * 45 * Cameron Grant created the pcm framework used here nearly verbatim. 46 * <cg@freebsd.org>, http://people.freebsd.org/~cg/template.c 47 * 48 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference. 49 * <taku@cent.saitama-u.ac.jp> 50 * 51 * ESS docs explained a few magic registers and numbers. 52 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz 53 */ 54 55 #ifdef HAVE_KERNEL_OPTION_HEADERS 56 #include "opt_snd.h" 57 #endif 58 59 #include <dev/sound/pcm/sound.h> 60 #include <dev/sound/pcm/ac97.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 65 #include <gnu/dev/sound/pci/maestro3_reg.h> 66 #include <gnu/dev/sound/pci/maestro3_dsp.h> 67 68 SND_DECLARE_FILE("$FreeBSD$"); 69 70 /* -------------------------------------------------------------------- */ 71 72 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1}; 73 #ifndef M3_DEBUG_LEVEL 74 #define M3_DEBUG_LEVEL NONE 75 #endif 76 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}} 77 78 /* -------------------------------------------------------------------- */ 79 enum { 80 ESS_ALLEGRO_1, 81 ESS_MAESTRO3 82 }; 83 84 static struct m3_card_type { 85 u_int32_t pci_id; int which; int delay1; int delay2; char *name; 86 } m3_card_types[] = { 87 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" }, 88 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, 89 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, 90 { 0, 0, 0, 0, NULL } 91 }; 92 93 #define M3_BUFSIZE_MIN 4096 94 #define M3_BUFSIZE_MAX 65536 95 #define M3_BUFSIZE_DEFAULT 4096 96 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */ 97 #define M3_RCHANS 1 98 #define M3_MAXADDR ((1 << 27) - 1) 99 100 struct sc_info; 101 102 struct sc_pchinfo { 103 u_int32_t spd; 104 u_int32_t fmt; 105 struct snd_dbuf *buffer; 106 struct pcm_channel *channel; 107 struct sc_info *parent; 108 u_int32_t bufsize; 109 u_int32_t dac_data; 110 u_int32_t dac_idx; 111 u_int32_t active; 112 u_int32_t ptr; 113 u_int32_t prevptr; 114 }; 115 116 struct sc_rchinfo { 117 u_int32_t spd; 118 u_int32_t fmt; 119 struct snd_dbuf *buffer; 120 struct pcm_channel *channel; 121 struct sc_info *parent; 122 u_int32_t bufsize; 123 u_int32_t adc_data; 124 u_int32_t adc_idx; 125 u_int32_t active; 126 u_int32_t ptr; 127 u_int32_t prevptr; 128 }; 129 130 struct sc_info { 131 device_t dev; 132 u_int32_t type; 133 int which; 134 int delay1; 135 int delay2; 136 137 bus_space_tag_t st; 138 bus_space_handle_t sh; 139 bus_dma_tag_t parent_dmat; 140 141 struct resource *reg; 142 struct resource *irq; 143 int regtype; 144 int regid; 145 int irqid; 146 void *ih; 147 148 struct sc_pchinfo pch[M3_PCHANS]; 149 struct sc_rchinfo rch[M3_RCHANS]; 150 int pch_cnt; 151 int rch_cnt; 152 int pch_active_cnt; 153 unsigned int bufsz; 154 u_int16_t *savemem; 155 156 struct mtx *sc_lock; 157 }; 158 159 #define M3_LOCK(_sc) snd_mtxlock((_sc)->sc_lock) 160 #define M3_UNLOCK(_sc) snd_mtxunlock((_sc)->sc_lock) 161 #define M3_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->sc_lock) 162 163 /* -------------------------------------------------------------------- */ 164 165 /* play channel interface */ 166 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int); 167 static int m3_pchan_free(kobj_t, void *); 168 static int m3_pchan_setformat(kobj_t, void *, u_int32_t); 169 static u_int32_t m3_pchan_setspeed(kobj_t, void *, u_int32_t); 170 static u_int32_t m3_pchan_setblocksize(kobj_t, void *, u_int32_t); 171 static int m3_pchan_trigger(kobj_t, void *, int); 172 static int m3_pchan_trigger_locked(kobj_t, void *, int); 173 static u_int32_t m3_pchan_getptr_internal(struct sc_pchinfo *); 174 static u_int32_t m3_pchan_getptr(kobj_t, void *); 175 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *); 176 177 /* record channel interface */ 178 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int); 179 static int m3_rchan_free(kobj_t, void *); 180 static int m3_rchan_setformat(kobj_t, void *, u_int32_t); 181 static u_int32_t m3_rchan_setspeed(kobj_t, void *, u_int32_t); 182 static u_int32_t m3_rchan_setblocksize(kobj_t, void *, u_int32_t); 183 static int m3_rchan_trigger(kobj_t, void *, int); 184 static int m3_rchan_trigger_locked(kobj_t, void *, int); 185 static u_int32_t m3_rchan_getptr_internal(struct sc_rchinfo *); 186 static u_int32_t m3_rchan_getptr(kobj_t, void *); 187 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *); 188 189 static int m3_chan_active(struct sc_info *); 190 191 /* talk to the codec - called from ac97.c */ 192 static u_int32_t m3_initcd(kobj_t, void *); 193 static int m3_rdcd(kobj_t, void *, int); 194 static int m3_wrcd(kobj_t, void *, int, u_int32_t); 195 196 /* stuff */ 197 static void m3_intr(void *); 198 static int m3_power(struct sc_info *, int); 199 static int m3_init(struct sc_info *); 200 static int m3_uninit(struct sc_info *); 201 static u_int8_t m3_assp_halt(struct sc_info *); 202 static void m3_config(struct sc_info *); 203 static void m3_amp_enable(struct sc_info *); 204 static void m3_enable_ints(struct sc_info *); 205 static void m3_codec_reset(struct sc_info *); 206 207 /* -------------------------------------------------------------------- */ 208 /* Codec descriptor */ 209 static kobj_method_t m3_codec_methods[] = { 210 KOBJMETHOD(ac97_init, m3_initcd), 211 KOBJMETHOD(ac97_read, m3_rdcd), 212 KOBJMETHOD(ac97_write, m3_wrcd), 213 KOBJMETHOD_END 214 }; 215 AC97_DECLARE(m3_codec); 216 217 /* -------------------------------------------------------------------- */ 218 /* channel descriptors */ 219 220 static u_int32_t m3_playfmt[] = { 221 SND_FORMAT(AFMT_U8, 1, 0), 222 SND_FORMAT(AFMT_U8, 2, 0), 223 SND_FORMAT(AFMT_S16_LE, 1, 0), 224 SND_FORMAT(AFMT_S16_LE, 2, 0), 225 0 226 }; 227 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0}; 228 229 static kobj_method_t m3_pch_methods[] = { 230 KOBJMETHOD(channel_init, m3_pchan_init), 231 KOBJMETHOD(channel_setformat, m3_pchan_setformat), 232 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed), 233 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize), 234 KOBJMETHOD(channel_trigger, m3_pchan_trigger), 235 KOBJMETHOD(channel_getptr, m3_pchan_getptr), 236 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps), 237 KOBJMETHOD(channel_free, m3_pchan_free), 238 KOBJMETHOD_END 239 }; 240 CHANNEL_DECLARE(m3_pch); 241 242 static u_int32_t m3_recfmt[] = { 243 SND_FORMAT(AFMT_U8, 1, 0), 244 SND_FORMAT(AFMT_U8, 2, 0), 245 SND_FORMAT(AFMT_S16_LE, 1, 0), 246 SND_FORMAT(AFMT_S16_LE, 2, 0), 247 0 248 }; 249 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0}; 250 251 static kobj_method_t m3_rch_methods[] = { 252 KOBJMETHOD(channel_init, m3_rchan_init), 253 KOBJMETHOD(channel_setformat, m3_rchan_setformat), 254 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed), 255 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize), 256 KOBJMETHOD(channel_trigger, m3_rchan_trigger), 257 KOBJMETHOD(channel_getptr, m3_rchan_getptr), 258 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps), 259 KOBJMETHOD(channel_free, m3_rchan_free), 260 KOBJMETHOD_END 261 }; 262 CHANNEL_DECLARE(m3_rch); 263 264 /* -------------------------------------------------------------------- */ 265 /* some i/o convenience functions */ 266 267 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno) 268 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno) 269 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno) 270 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data) 271 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data) 272 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data) 273 #define m3_rd_assp_code(sc, index) \ 274 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index) 275 #define m3_wr_assp_code(sc, index, data) \ 276 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data) 277 #define m3_rd_assp_data(sc, index) \ 278 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index) 279 #define m3_wr_assp_data(sc, index, data) \ 280 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data) 281 282 static __inline u_int16_t 283 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index) 284 { 285 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); 286 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); 287 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA); 288 } 289 290 static __inline void 291 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index, 292 u_int16_t data) 293 { 294 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); 295 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); 296 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data); 297 } 298 299 static __inline int 300 m3_wait(struct sc_info *sc) 301 { 302 int i; 303 304 for (i=0 ; i<20 ; i++) { 305 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) { 306 return 0; 307 } 308 DELAY(2); 309 } 310 return -1; 311 } 312 313 /* -------------------------------------------------------------------- */ 314 /* ac97 codec */ 315 316 static u_int32_t 317 m3_initcd(kobj_t kobj, void *devinfo) 318 { 319 struct sc_info *sc = (struct sc_info *)devinfo; 320 u_int32_t data; 321 322 M3_DEBUG(CALL, ("m3_initcd\n")); 323 324 /* init ac-link */ 325 326 data = m3_rd_1(sc, CODEC_COMMAND); 327 return ((data & 0x1) ? 0 : 1); 328 } 329 330 static int 331 m3_rdcd(kobj_t kobj, void *devinfo, int regno) 332 { 333 struct sc_info *sc = (struct sc_info *)devinfo; 334 u_int32_t data; 335 336 if (m3_wait(sc)) { 337 device_printf(sc->dev, "m3_rdcd timed out.\n"); 338 return -1; 339 } 340 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80); 341 DELAY(50); /* ac97 cycle = 20.8 usec */ 342 if (m3_wait(sc)) { 343 device_printf(sc->dev, "m3_rdcd timed out.\n"); 344 return -1; 345 } 346 data = m3_rd_2(sc, CODEC_DATA); 347 return data; 348 } 349 350 static int 351 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data) 352 { 353 struct sc_info *sc = (struct sc_info *)devinfo; 354 if (m3_wait(sc)) { 355 device_printf(sc->dev, "m3_wrcd timed out.\n"); 356 return -1; 357 } 358 m3_wr_2(sc, CODEC_DATA, data); 359 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f); 360 DELAY(50); /* ac97 cycle = 20.8 usec */ 361 return 0; 362 } 363 364 /* -------------------------------------------------------------------- */ 365 /* play channel interface */ 366 367 #define LO(x) (((x) & 0x0000ffff) ) 368 #define HI(x) (((x) & 0xffff0000) >> 16) 369 370 static void * 371 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 372 { 373 struct sc_info *sc = devinfo; 374 struct sc_pchinfo *ch; 375 u_int32_t bus_addr, i; 376 int idx, data_bytes, dac_data; 377 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf; 378 379 M3_LOCK(sc); 380 idx = sc->pch_cnt; /* dac instance number, no active reuse! */ 381 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx)); 382 383 if (dir != PCMDIR_PLAY) { 384 M3_UNLOCK(sc); 385 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n"); 386 return (NULL); 387 } 388 389 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + 390 (MINISRC_IN_BUFFER_SIZE & ~1) + 391 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; 392 dac_data = 0x1100 + (data_bytes * idx); 393 394 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); 395 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); 396 dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2); 397 dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1; 398 399 ch = &sc->pch[idx]; 400 ch->dac_idx = idx; 401 ch->dac_data = dac_data; 402 if (ch->dac_data + data_bytes/2 >= 0x1c00) { 403 M3_UNLOCK(sc); 404 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n"); 405 return (NULL); 406 } 407 408 ch->buffer = b; 409 ch->parent = sc; 410 ch->channel = c; 411 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 412 ch->spd = DSP_DEFAULT_SPEED; 413 M3_UNLOCK(sc); /* XXX */ 414 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 415 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n"); 416 return (NULL); 417 } 418 M3_LOCK(sc); 419 ch->bufsize = sndbuf_getsize(ch->buffer); 420 421 /* host dma buffer pointers */ 422 bus_addr = sndbuf_getbufaddr(ch->buffer); 423 if (bus_addr & 3) { 424 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n"); 425 bus_addr = (bus_addr + 4) & ~3; 426 } 427 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); 428 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); 429 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L, 430 LO(bus_addr + ch->bufsize)); 431 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H, 432 HI(bus_addr + ch->bufsize)); 433 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL, 434 LO(bus_addr)); 435 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH, 436 HI(bus_addr)); 437 438 /* dsp buffers */ 439 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); 440 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1, 441 dsp_in_buf + dsp_in_size/2); 442 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf); 443 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf); 444 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); 445 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1, 446 dsp_out_buf + dsp_out_size/2); 447 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); 448 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); 449 450 /* some per client initializers */ 451 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12, 452 ch->dac_data + 40 + 8); 453 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19, 454 0x400 + MINISRC_COEF_LOC); 455 /* enable or disable low pass filter? (0xff if rate> 45000) */ 456 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0); 457 /* tell it which way dma is going? */ 458 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL, 459 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + 460 DMAC_BLOCKF_SELECTOR); 461 462 /* set an armload of static initializers */ 463 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) { 464 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val); 465 } 466 467 /* put us in the packed task lists */ 468 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 469 (sc->pch_cnt + sc->rch_cnt), 470 ch->dac_data >> DP_SHIFT_COUNT); 471 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), 472 ch->dac_data >> DP_SHIFT_COUNT); 473 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt, 474 ch->dac_data >> DP_SHIFT_COUNT); 475 476 /* gotta start before stop */ 477 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_START); 478 /* silence noise on load */ 479 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_STOP); 480 481 sc->pch_cnt++; 482 M3_UNLOCK(sc); 483 484 return (ch); 485 } 486 487 static int 488 m3_pchan_free(kobj_t kobj, void *chdata) 489 { 490 struct sc_pchinfo *ch = chdata; 491 struct sc_info *sc = ch->parent; 492 493 M3_LOCK(sc); 494 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx)); 495 496 /* 497 * should remove this exact instance from the packed lists, but all 498 * are released at once (and in a stopped state) so this is ok. 499 */ 500 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 501 (sc->pch_cnt - 1) + sc->rch_cnt, 0); 502 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + 503 (sc->pch_cnt - 1) + sc->rch_cnt, 0); 504 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0); 505 sc->pch_cnt--; 506 M3_UNLOCK(sc); 507 508 return (0); 509 } 510 511 static int 512 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) 513 { 514 struct sc_pchinfo *ch = chdata; 515 struct sc_info *sc = ch->parent; 516 u_int32_t data; 517 518 M3_LOCK(sc); 519 M3_DEBUG(CHANGE, 520 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n", 521 ch->dac_idx, format, 522 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", 523 (AFMT_CHANNEL(format) > 1) ? "STEREO":"MONO")); 524 525 /* mono word */ 526 data = (AFMT_CHANNEL(format) > 1)? 0 : 1; 527 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data); 528 529 /* 8bit word */ 530 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; 531 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data); 532 533 ch->fmt = format; 534 M3_UNLOCK(sc); 535 536 return (0); 537 } 538 539 static u_int32_t 540 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) 541 { 542 struct sc_pchinfo *ch = chdata; 543 struct sc_info *sc = ch->parent; 544 u_int32_t freq; 545 546 M3_LOCK(sc); 547 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n", 548 ch->dac_idx, speed)); 549 550 if ((freq = ((speed << 15) + 24000) / 48000) != 0) { 551 freq--; 552 } 553 554 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq); 555 ch->spd = speed; 556 M3_UNLOCK(sc); 557 558 /* return closest possible speed */ 559 return (speed); 560 } 561 562 static u_int32_t 563 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) 564 { 565 struct sc_pchinfo *ch = chdata; 566 567 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n", 568 ch->dac_idx, blocksize)); 569 570 return (sndbuf_getblksz(ch->buffer)); 571 } 572 573 static int 574 m3_pchan_trigger(kobj_t kobj, void *chdata, int go) 575 { 576 struct sc_pchinfo *ch = chdata; 577 struct sc_info *sc = ch->parent; 578 int ret; 579 580 if (!PCMTRIG_COMMON(go)) 581 return (0); 582 583 M3_LOCK(sc); 584 ret = m3_pchan_trigger_locked(kobj, chdata, go); 585 M3_UNLOCK(sc); 586 587 return (ret); 588 } 589 590 static int 591 m3_chan_active(struct sc_info *sc) 592 { 593 int i, ret; 594 595 ret = 0; 596 597 for (i = 0; i < sc->pch_cnt; i++) 598 ret += sc->pch[i].active; 599 600 for (i = 0; i < sc->rch_cnt; i++) 601 ret += sc->rch[i].active; 602 603 return (ret); 604 } 605 606 static int 607 m3_pchan_trigger_locked(kobj_t kobj, void *chdata, int go) 608 { 609 struct sc_pchinfo *ch = chdata; 610 struct sc_info *sc = ch->parent; 611 u_int32_t data; 612 613 M3_LOCK_ASSERT(sc); 614 M3_DEBUG(go == PCMTRIG_START ? CHANGE : 615 go == PCMTRIG_STOP ? CHANGE : 616 go == PCMTRIG_ABORT ? CHANGE : 617 CALL, 618 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go, 619 go == PCMTRIG_START ? "PCMTRIG_START" : 620 go == PCMTRIG_STOP ? "PCMTRIG_STOP" : 621 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); 622 623 switch(go) { 624 case PCMTRIG_START: 625 if (ch->active) { 626 return 0; 627 } 628 ch->active = 1; 629 ch->ptr = 0; 630 ch->prevptr = 0; 631 sc->pch_active_cnt++; 632 633 /*[[inc_timer_users]]*/ 634 if (m3_chan_active(sc) == 1) { 635 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); 636 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); 637 data = m3_rd_2(sc, HOST_INT_CTRL); 638 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); 639 } 640 641 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1); 642 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 643 sc->pch_active_cnt); 644 break; 645 646 case PCMTRIG_STOP: 647 case PCMTRIG_ABORT: 648 if (ch->active == 0) { 649 return 0; 650 } 651 ch->active = 0; 652 sc->pch_active_cnt--; 653 654 /* XXX should the channel be drained? */ 655 /*[[dec_timer_users]]*/ 656 if (m3_chan_active(sc) == 0) { 657 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); 658 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); 659 data = m3_rd_2(sc, HOST_INT_CTRL); 660 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); 661 } 662 663 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0); 664 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 665 sc->pch_active_cnt); 666 break; 667 668 case PCMTRIG_EMLDMAWR: 669 /* got play irq, transfer next buffer - ignore if using dma */ 670 case PCMTRIG_EMLDMARD: 671 /* got rec irq, transfer next buffer - ignore if using dma */ 672 default: 673 break; 674 } 675 return 0; 676 } 677 678 static u_int32_t 679 m3_pchan_getptr_internal(struct sc_pchinfo *ch) 680 { 681 struct sc_info *sc = ch->parent; 682 u_int32_t hi, lo, bus_base, bus_crnt; 683 684 bus_base = sndbuf_getbufaddr(ch->buffer); 685 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH); 686 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL); 687 bus_crnt = lo | (hi << 16); 688 689 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n", 690 ch->dac_idx, bus_crnt - bus_base)); 691 692 return (bus_crnt - bus_base); /* current byte offset of channel */ 693 } 694 695 static u_int32_t 696 m3_pchan_getptr(kobj_t kobj, void *chdata) 697 { 698 struct sc_pchinfo *ch = chdata; 699 struct sc_info *sc = ch->parent; 700 u_int32_t ptr; 701 702 M3_LOCK(sc); 703 ptr = ch->ptr; 704 M3_UNLOCK(sc); 705 706 return (ptr); 707 } 708 709 static struct pcmchan_caps * 710 m3_pchan_getcaps(kobj_t kobj, void *chdata) 711 { 712 struct sc_pchinfo *ch = chdata; 713 714 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx)); 715 716 return &m3_playcaps; 717 } 718 719 /* -------------------------------------------------------------------- */ 720 /* rec channel interface */ 721 722 static void * 723 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 724 { 725 struct sc_info *sc = devinfo; 726 struct sc_rchinfo *ch; 727 u_int32_t bus_addr, i; 728 729 int idx, data_bytes, adc_data; 730 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf; 731 732 M3_LOCK(sc); 733 idx = sc->rch_cnt; /* adc instance number, no active reuse! */ 734 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx)); 735 736 if (dir != PCMDIR_REC) { 737 M3_UNLOCK(sc); 738 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n"); 739 return (NULL); 740 } 741 742 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + 743 (MINISRC_IN_BUFFER_SIZE & ~1) + 744 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; 745 adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2; 746 dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2); 747 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); 748 dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2); 749 dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1; 750 751 ch = &sc->rch[idx]; 752 ch->adc_idx = idx; 753 ch->adc_data = adc_data; 754 if (ch->adc_data + data_bytes/2 >= 0x1c00) { 755 M3_UNLOCK(sc); 756 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n"); 757 return (NULL); 758 } 759 760 ch->buffer = b; 761 ch->parent = sc; 762 ch->channel = c; 763 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 764 ch->spd = DSP_DEFAULT_SPEED; 765 M3_UNLOCK(sc); /* XXX */ 766 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 767 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n"); 768 return (NULL); 769 } 770 M3_LOCK(sc); 771 ch->bufsize = sndbuf_getsize(ch->buffer); 772 773 /* host dma buffer pointers */ 774 bus_addr = sndbuf_getbufaddr(ch->buffer); 775 if (bus_addr & 3) { 776 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n"); 777 bus_addr = (bus_addr + 4) & ~3; 778 } 779 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); 780 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); 781 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L, 782 LO(bus_addr + ch->bufsize)); 783 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H, 784 HI(bus_addr + ch->bufsize)); 785 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL, 786 LO(bus_addr)); 787 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH, 788 HI(bus_addr)); 789 790 /* dsp buffers */ 791 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); 792 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1, 793 dsp_in_buf + dsp_in_size/2); 794 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf); 795 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf); 796 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); 797 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1, 798 dsp_out_buf + dsp_out_size/2); 799 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); 800 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); 801 802 /* some per client initializers */ 803 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12, 804 ch->adc_data + 40 + 8); 805 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL, 806 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + 807 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 808 809 /* set an armload of static initializers */ 810 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) { 811 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val); 812 } 813 814 /* put us in the packed task lists */ 815 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 816 (sc->pch_cnt + sc->rch_cnt), 817 ch->adc_data >> DP_SHIFT_COUNT); 818 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), 819 ch->adc_data >> DP_SHIFT_COUNT); 820 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt, 821 ch->adc_data >> DP_SHIFT_COUNT); 822 823 /* gotta start before stop */ 824 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_START); 825 /* stop on init */ 826 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_STOP); 827 828 sc->rch_cnt++; 829 M3_UNLOCK(sc); 830 831 return (ch); 832 } 833 834 static int 835 m3_rchan_free(kobj_t kobj, void *chdata) 836 { 837 struct sc_rchinfo *ch = chdata; 838 struct sc_info *sc = ch->parent; 839 840 M3_LOCK(sc); 841 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx)); 842 843 /* 844 * should remove this exact instance from the packed lists, but all 845 * are released at once (and in a stopped state) so this is ok. 846 */ 847 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 848 (sc->rch_cnt - 1) + sc->pch_cnt, 0); 849 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + 850 (sc->rch_cnt - 1) + sc->pch_cnt, 0); 851 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0); 852 sc->rch_cnt--; 853 M3_UNLOCK(sc); 854 855 return (0); 856 } 857 858 static int 859 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) 860 { 861 struct sc_rchinfo *ch = chdata; 862 struct sc_info *sc = ch->parent; 863 u_int32_t data; 864 865 M3_LOCK(sc); 866 M3_DEBUG(CHANGE, 867 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n", 868 ch->adc_idx, format, 869 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", 870 (AFMT_CHANNEL(format) > 1) ? "STEREO":"MONO")); 871 872 /* mono word */ 873 data = (AFMT_CHANNEL(format) > 1) ? 0 : 1; 874 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data); 875 876 /* 8bit word */ 877 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; 878 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data); 879 ch->fmt = format; 880 M3_UNLOCK(sc); 881 882 return (0); 883 } 884 885 static u_int32_t 886 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) 887 { 888 struct sc_rchinfo *ch = chdata; 889 struct sc_info *sc = ch->parent; 890 u_int32_t freq; 891 892 M3_LOCK(sc); 893 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n", 894 ch->adc_idx, speed)); 895 896 if ((freq = ((speed << 15) + 24000) / 48000) != 0) { 897 freq--; 898 } 899 900 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq); 901 ch->spd = speed; 902 M3_UNLOCK(sc); 903 904 /* return closest possible speed */ 905 return (speed); 906 } 907 908 static u_int32_t 909 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) 910 { 911 struct sc_rchinfo *ch = chdata; 912 913 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n", 914 ch->adc_idx, blocksize)); 915 916 return (sndbuf_getblksz(ch->buffer)); 917 } 918 919 static int 920 m3_rchan_trigger(kobj_t kobj, void *chdata, int go) 921 { 922 struct sc_rchinfo *ch = chdata; 923 struct sc_info *sc = ch->parent; 924 int ret; 925 926 if (!PCMTRIG_COMMON(go)) 927 return (0); 928 929 M3_LOCK(sc); 930 ret = m3_rchan_trigger_locked(kobj, chdata, go); 931 M3_UNLOCK(sc); 932 933 return (ret); 934 } 935 936 static int 937 m3_rchan_trigger_locked(kobj_t kobj, void *chdata, int go) 938 { 939 struct sc_rchinfo *ch = chdata; 940 struct sc_info *sc = ch->parent; 941 u_int32_t data; 942 943 M3_LOCK_ASSERT(sc); 944 M3_DEBUG(go == PCMTRIG_START ? CHANGE : 945 go == PCMTRIG_STOP ? CHANGE : 946 go == PCMTRIG_ABORT ? CHANGE : 947 CALL, 948 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go, 949 go == PCMTRIG_START ? "PCMTRIG_START" : 950 go == PCMTRIG_STOP ? "PCMTRIG_STOP" : 951 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); 952 953 switch(go) { 954 case PCMTRIG_START: 955 if (ch->active) { 956 return 0; 957 } 958 ch->active = 1; 959 ch->ptr = 0; 960 ch->prevptr = 0; 961 962 /*[[inc_timer_users]]*/ 963 if (m3_chan_active(sc) == 1) { 964 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); 965 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); 966 data = m3_rd_2(sc, HOST_INT_CTRL); 967 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); 968 } 969 970 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1); 971 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1); 972 break; 973 974 case PCMTRIG_STOP: 975 case PCMTRIG_ABORT: 976 if (ch->active == 0) { 977 return 0; 978 } 979 ch->active = 0; 980 981 /*[[dec_timer_users]]*/ 982 if (m3_chan_active(sc) == 0) { 983 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); 984 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); 985 data = m3_rd_2(sc, HOST_INT_CTRL); 986 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); 987 } 988 989 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0); 990 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0); 991 break; 992 993 case PCMTRIG_EMLDMAWR: 994 /* got play irq, transfer next buffer - ignore if using dma */ 995 case PCMTRIG_EMLDMARD: 996 /* got rec irq, transfer next buffer - ignore if using dma */ 997 default: 998 break; 999 } 1000 return 0; 1001 } 1002 1003 static u_int32_t 1004 m3_rchan_getptr_internal(struct sc_rchinfo *ch) 1005 { 1006 struct sc_info *sc = ch->parent; 1007 u_int32_t hi, lo, bus_base, bus_crnt; 1008 1009 bus_base = sndbuf_getbufaddr(ch->buffer); 1010 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH); 1011 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL); 1012 bus_crnt = lo | (hi << 16); 1013 1014 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n", 1015 ch->adc_idx, bus_crnt - bus_base)); 1016 1017 return (bus_crnt - bus_base); /* current byte offset of channel */ 1018 } 1019 1020 static u_int32_t 1021 m3_rchan_getptr(kobj_t kobj, void *chdata) 1022 { 1023 struct sc_rchinfo *ch = chdata; 1024 struct sc_info *sc = ch->parent; 1025 u_int32_t ptr; 1026 1027 M3_LOCK(sc); 1028 ptr = ch->ptr; 1029 M3_UNLOCK(sc); 1030 1031 return (ptr); 1032 } 1033 1034 static struct pcmchan_caps * 1035 m3_rchan_getcaps(kobj_t kobj, void *chdata) 1036 { 1037 struct sc_rchinfo *ch = chdata; 1038 1039 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx)); 1040 1041 return &m3_reccaps; 1042 } 1043 1044 /* -------------------------------------------------------------------- */ 1045 /* The interrupt handler */ 1046 1047 static void 1048 m3_intr(void *p) 1049 { 1050 struct sc_info *sc = (struct sc_info *)p; 1051 struct sc_pchinfo *pch; 1052 struct sc_rchinfo *rch; 1053 u_int32_t status, ctl, i, delta; 1054 1055 M3_DEBUG(INTR, ("m3_intr\n")); 1056 1057 M3_LOCK(sc); 1058 status = m3_rd_1(sc, HOST_INT_STATUS); 1059 if (!status) { 1060 M3_UNLOCK(sc); 1061 return; 1062 } 1063 1064 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */ 1065 1066 if (status & HV_INT_PENDING) { 1067 u_int8_t event; 1068 1069 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER); 1070 switch (event) { 1071 case 0x99: 1072 mixer_hwvol_mute(sc->dev); 1073 break; 1074 case 0xaa: 1075 mixer_hwvol_step(sc->dev, 1, 1); 1076 break; 1077 case 0x66: 1078 mixer_hwvol_step(sc->dev, -1, -1); 1079 break; 1080 case 0x88: 1081 break; 1082 default: 1083 device_printf(sc->dev, "Unknown HWVOL event\n"); 1084 } 1085 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88); 1086 1087 } 1088 1089 if (status & ASSP_INT_PENDING) { 1090 ctl = m3_rd_1(sc, ASSP_CONTROL_B); 1091 if (!(ctl & STOP_ASSP_CLOCK)) { 1092 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS); 1093 if (ctl & DSP2HOST_REQ_TIMER) { 1094 m3_wr_1(sc, ASSP_HOST_INT_STATUS, 1095 DSP2HOST_REQ_TIMER); 1096 /*[[ess_update_ptr]]*/ 1097 goto m3_handle_channel_intr; 1098 } 1099 } 1100 } 1101 1102 goto m3_handle_channel_intr_out; 1103 1104 m3_handle_channel_intr: 1105 for (i=0 ; i<sc->pch_cnt ; i++) { 1106 pch = &sc->pch[i]; 1107 if (pch->active) { 1108 pch->ptr = m3_pchan_getptr_internal(pch); 1109 delta = pch->bufsize + pch->ptr - pch->prevptr; 1110 delta %= pch->bufsize; 1111 if (delta < sndbuf_getblksz(pch->buffer)) 1112 continue; 1113 pch->prevptr = pch->ptr; 1114 M3_UNLOCK(sc); 1115 chn_intr(pch->channel); 1116 M3_LOCK(sc); 1117 } 1118 } 1119 for (i=0 ; i<sc->rch_cnt ; i++) { 1120 rch = &sc->rch[i]; 1121 if (rch->active) { 1122 rch->ptr = m3_rchan_getptr_internal(rch); 1123 delta = rch->bufsize + rch->ptr - rch->prevptr; 1124 delta %= rch->bufsize; 1125 if (delta < sndbuf_getblksz(rch->buffer)) 1126 continue; 1127 rch->prevptr = rch->ptr; 1128 M3_UNLOCK(sc); 1129 chn_intr(rch->channel); 1130 M3_LOCK(sc); 1131 } 1132 } 1133 1134 m3_handle_channel_intr_out: 1135 M3_UNLOCK(sc); 1136 } 1137 1138 /* -------------------------------------------------------------------- */ 1139 /* stuff */ 1140 1141 static int 1142 m3_power(struct sc_info *sc, int state) 1143 { 1144 u_int32_t data; 1145 1146 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state)); 1147 M3_LOCK_ASSERT(sc); 1148 1149 data = pci_read_config(sc->dev, 0x34, 1); 1150 if (pci_read_config(sc->dev, data, 1) == 1) { 1151 pci_write_config(sc->dev, data + 4, state, 1); 1152 } 1153 1154 return 0; 1155 } 1156 1157 static int 1158 m3_init(struct sc_info *sc) 1159 { 1160 u_int32_t data, i, size; 1161 u_int8_t reset_state; 1162 1163 M3_LOCK_ASSERT(sc); 1164 M3_DEBUG(CHANGE, ("m3_init\n")); 1165 1166 /* diable legacy emulations. */ 1167 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2); 1168 data |= DISABLE_LEGACY; 1169 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2); 1170 1171 m3_config(sc); 1172 1173 reset_state = m3_assp_halt(sc); 1174 1175 m3_codec_reset(sc); 1176 1177 /* [m3_assp_init] */ 1178 /* zero kernel data */ 1179 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; 1180 for(i = 0 ; i < size / 2 ; i++) { 1181 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0); 1182 } 1183 /* zero mixer data? */ 1184 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; 1185 for(i = 0 ; i < size / 2 ; i++) { 1186 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0); 1187 } 1188 /* init dma pointer */ 1189 m3_wr_assp_data(sc, KDATA_CURRENT_DMA, 1190 KDATA_DMA_XFER0); 1191 /* write kernel into code memory */ 1192 size = sizeof(assp_kernel_image); 1193 for(i = 0 ; i < size / 2; i++) { 1194 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i, 1195 assp_kernel_image[i]); 1196 } 1197 /* 1198 * We only have this one client and we know that 0x400 is free in 1199 * our kernel's mem map, so lets just drop it there. It seems that 1200 * the minisrc doesn't need vectors, so we won't bother with them.. 1201 */ 1202 size = sizeof(assp_minisrc_image); 1203 for(i = 0 ; i < size / 2; i++) { 1204 m3_wr_assp_code(sc, 0x400 + i, assp_minisrc_image[i]); 1205 } 1206 /* write the coefficients for the low pass filter? */ 1207 size = sizeof(minisrc_lpf_image); 1208 for(i = 0; i < size / 2 ; i++) { 1209 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i, 1210 minisrc_lpf_image[i]); 1211 } 1212 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000); 1213 /* the minisrc is the only thing on our task list */ 1214 m3_wr_assp_data(sc, KDATA_TASK0, 0x400); 1215 /* init the mixer number */ 1216 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0); 1217 /* extreme kernel master volume */ 1218 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); 1219 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); 1220 1221 m3_amp_enable(sc); 1222 1223 /* [m3_assp_client_init] (only one client at index 0) */ 1224 for (i=0x1100 ; i<0x1c00 ; i++) { 1225 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */ 1226 } 1227 1228 /* [m3_assp_continue] */ 1229 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); 1230 1231 return 0; 1232 } 1233 1234 static int 1235 m3_uninit(struct sc_info *sc) 1236 { 1237 M3_DEBUG(CHANGE, ("m3_uninit\n")); 1238 return 0; 1239 } 1240 1241 /* -------------------------------------------------------------------- */ 1242 /* Probe and attach the card */ 1243 1244 static int 1245 m3_pci_probe(device_t dev) 1246 { 1247 struct m3_card_type *card; 1248 1249 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev))); 1250 1251 for (card = m3_card_types ; card->pci_id ; card++) { 1252 if (pci_get_devid(dev) == card->pci_id) { 1253 device_set_desc(dev, card->name); 1254 return BUS_PROBE_DEFAULT; 1255 } 1256 } 1257 return ENXIO; 1258 } 1259 1260 static int 1261 m3_pci_attach(device_t dev) 1262 { 1263 struct sc_info *sc; 1264 struct ac97_info *codec = NULL; 1265 u_int32_t data; 1266 char status[SND_STATUSLEN]; 1267 struct m3_card_type *card; 1268 int i, len, dacn, adcn; 1269 1270 M3_DEBUG(CALL, ("m3_pci_attach\n")); 1271 1272 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 1273 sc->dev = dev; 1274 sc->type = pci_get_devid(dev); 1275 sc->sc_lock = snd_mtxcreate(device_get_nameunit(dev), 1276 "snd_maestro3 softc"); 1277 for (card = m3_card_types ; card->pci_id ; card++) { 1278 if (sc->type == card->pci_id) { 1279 sc->which = card->which; 1280 sc->delay1 = card->delay1; 1281 sc->delay2 = card->delay2; 1282 break; 1283 } 1284 } 1285 1286 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 1287 "dac", &i) == 0) { 1288 if (i < 1) 1289 dacn = 1; 1290 else if (i > M3_PCHANS) 1291 dacn = M3_PCHANS; 1292 else 1293 dacn = i; 1294 } else 1295 dacn = M3_PCHANS; 1296 1297 adcn = M3_RCHANS; 1298 1299 data = pci_read_config(dev, PCIR_COMMAND, 2); 1300 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1301 pci_write_config(dev, PCIR_COMMAND, data, 2); 1302 1303 sc->regid = PCIR_BAR(0); 1304 sc->regtype = SYS_RES_MEMORY; 1305 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 1306 RF_ACTIVE); 1307 if (!sc->reg) { 1308 sc->regtype = SYS_RES_IOPORT; 1309 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 1310 RF_ACTIVE); 1311 } 1312 if (!sc->reg) { 1313 device_printf(dev, "unable to allocate register space\n"); 1314 goto bad; 1315 } 1316 sc->st = rman_get_bustag(sc->reg); 1317 sc->sh = rman_get_bushandle(sc->reg); 1318 1319 sc->irqid = 0; 1320 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 1321 RF_ACTIVE | RF_SHAREABLE); 1322 if (!sc->irq) { 1323 device_printf(dev, "unable to allocate interrupt\n"); 1324 goto bad; 1325 } 1326 1327 if (snd_setup_intr(dev, sc->irq, INTR_MPSAFE, m3_intr, sc, &sc->ih)) { 1328 device_printf(dev, "unable to setup interrupt\n"); 1329 goto bad; 1330 } 1331 1332 sc->bufsz = pcm_getbuffersize(dev, M3_BUFSIZE_MIN, M3_BUFSIZE_DEFAULT, 1333 M3_BUFSIZE_MAX); 1334 1335 if (bus_dma_tag_create( 1336 bus_get_dma_tag(dev), /* parent */ 1337 2, 0, /* alignment, boundary */ 1338 M3_MAXADDR, /* lowaddr */ 1339 BUS_SPACE_MAXADDR, /* highaddr */ 1340 NULL, NULL, /* filtfunc, filtfuncarg */ 1341 sc->bufsz, /* maxsize */ 1342 1, /* nsegments */ 1343 0x3ffff, /* maxsegz */ 1344 0, /* flags */ 1345 NULL, /* lockfunc */ 1346 NULL, /* lockfuncarg */ 1347 &sc->parent_dmat) != 0) { 1348 device_printf(dev, "unable to create dma tag\n"); 1349 goto bad; 1350 } 1351 1352 M3_LOCK(sc); 1353 m3_power(sc, 0); /* power up */ 1354 /* init chip */ 1355 i = m3_init(sc); 1356 M3_UNLOCK(sc); 1357 if (i == -1) { 1358 device_printf(dev, "unable to initialize the card\n"); 1359 goto bad; 1360 } 1361 1362 /* create/init mixer */ 1363 codec = AC97_CREATE(dev, sc, m3_codec); 1364 if (codec == NULL) { 1365 device_printf(dev, "ac97_create error\n"); 1366 goto bad; 1367 } 1368 if (mixer_init(dev, ac97_getmixerclass(), codec)) { 1369 device_printf(dev, "mixer_init error\n"); 1370 goto bad; 1371 } 1372 1373 m3_enable_ints(sc); 1374 1375 if (pcm_register(dev, sc, dacn, adcn)) { 1376 device_printf(dev, "pcm_register error\n"); 1377 goto bad; 1378 } 1379 for (i=0 ; i<dacn ; i++) { 1380 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) { 1381 device_printf(dev, "pcm_addchan (play) error\n"); 1382 goto bad; 1383 } 1384 } 1385 for (i=0 ; i<adcn ; i++) { 1386 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) { 1387 device_printf(dev, "pcm_addchan (rec) error\n"); 1388 goto bad; 1389 } 1390 } 1391 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s", 1392 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 1393 rman_get_start(sc->reg), rman_get_start(sc->irq), 1394 PCM_KLDSTRING(snd_maestro3)); 1395 if (pcm_setstatus(dev, status)) { 1396 device_printf(dev, "attach: pcm_setstatus error\n"); 1397 goto bad; 1398 } 1399 1400 mixer_hwvol_init(dev); 1401 1402 /* Create the buffer for saving the card state during suspend */ 1403 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH + 1404 REV_B_DATA_MEMORY_LENGTH); 1405 sc->savemem = (u_int16_t*)malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1406 1407 return 0; 1408 1409 bad: 1410 if (codec) 1411 ac97_destroy(codec); 1412 if (sc->ih) 1413 bus_teardown_intr(dev, sc->irq, sc->ih); 1414 if (sc->irq) 1415 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1416 if (sc->reg) 1417 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1418 if (sc->parent_dmat) 1419 bus_dma_tag_destroy(sc->parent_dmat); 1420 if (sc->sc_lock) 1421 snd_mtxfree(sc->sc_lock); 1422 free(sc, M_DEVBUF); 1423 return ENXIO; 1424 } 1425 1426 static int 1427 m3_pci_detach(device_t dev) 1428 { 1429 struct sc_info *sc = pcm_getdevinfo(dev); 1430 int r; 1431 1432 M3_DEBUG(CALL, ("m3_pci_detach\n")); 1433 1434 if ((r = pcm_unregister(dev)) != 0) { 1435 return r; 1436 } 1437 1438 M3_LOCK(sc); 1439 m3_uninit(sc); /* shutdown chip */ 1440 m3_power(sc, 3); /* power off */ 1441 M3_UNLOCK(sc); 1442 1443 bus_teardown_intr(dev, sc->irq, sc->ih); 1444 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1445 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1446 bus_dma_tag_destroy(sc->parent_dmat); 1447 1448 free(sc->savemem, M_DEVBUF); 1449 snd_mtxfree(sc->sc_lock); 1450 free(sc, M_DEVBUF); 1451 return 0; 1452 } 1453 1454 static int 1455 m3_pci_suspend(device_t dev) 1456 { 1457 struct sc_info *sc = pcm_getdevinfo(dev); 1458 int i, index = 0; 1459 1460 M3_DEBUG(CHANGE, ("m3_pci_suspend\n")); 1461 1462 M3_LOCK(sc); 1463 for (i=0 ; i<sc->pch_cnt ; i++) { 1464 if (sc->pch[i].active) { 1465 m3_pchan_trigger_locked(NULL, &sc->pch[i], 1466 PCMTRIG_STOP); 1467 } 1468 } 1469 for (i=0 ; i<sc->rch_cnt ; i++) { 1470 if (sc->rch[i].active) { 1471 m3_rchan_trigger_locked(NULL, &sc->rch[i], 1472 PCMTRIG_STOP); 1473 } 1474 } 1475 DELAY(10 * 1000); /* give things a chance to stop */ 1476 1477 /* Disable interrupts */ 1478 m3_wr_2(sc, HOST_INT_CTRL, 0); 1479 m3_wr_1(sc, ASSP_CONTROL_C, 0); 1480 1481 m3_assp_halt(sc); 1482 1483 /* Save the state of the ASSP */ 1484 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 1485 sc->savemem[index++] = m3_rd_assp_code(sc, i); 1486 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) 1487 sc->savemem[index++] = m3_rd_assp_data(sc, i); 1488 1489 /* Power down the card to D3 state */ 1490 m3_power(sc, 3); 1491 M3_UNLOCK(sc); 1492 1493 return 0; 1494 } 1495 1496 static int 1497 m3_pci_resume(device_t dev) 1498 { 1499 struct sc_info *sc = pcm_getdevinfo(dev); 1500 int i, index = 0; 1501 u_int8_t reset_state; 1502 1503 M3_DEBUG(CHANGE, ("m3_pci_resume\n")); 1504 1505 M3_LOCK(sc); 1506 /* Power the card back to D0 */ 1507 m3_power(sc, 0); 1508 1509 m3_config(sc); 1510 1511 reset_state = m3_assp_halt(sc); 1512 1513 m3_codec_reset(sc); 1514 1515 /* Restore the ASSP state */ 1516 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 1517 m3_wr_assp_code(sc, i, sc->savemem[index++]); 1518 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) 1519 m3_wr_assp_data(sc, i, sc->savemem[index++]); 1520 1521 /* Restart the DMA engine */ 1522 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0); 1523 1524 /* [m3_assp_continue] */ 1525 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); 1526 1527 m3_amp_enable(sc); 1528 1529 m3_enable_ints(sc); 1530 1531 M3_UNLOCK(sc); /* XXX */ 1532 if (mixer_reinit(dev) == -1) { 1533 device_printf(dev, "unable to reinitialize the mixer\n"); 1534 return (ENXIO); 1535 } 1536 M3_LOCK(sc); 1537 1538 /* Turn the channels back on */ 1539 for (i=0 ; i<sc->pch_cnt ; i++) { 1540 if (sc->pch[i].active) { 1541 m3_pchan_trigger_locked(NULL, &sc->pch[i], 1542 PCMTRIG_START); 1543 } 1544 } 1545 for (i=0 ; i<sc->rch_cnt ; i++) { 1546 if (sc->rch[i].active) { 1547 m3_rchan_trigger_locked(NULL, &sc->rch[i], 1548 PCMTRIG_START); 1549 } 1550 } 1551 1552 M3_UNLOCK(sc); 1553 return 0; 1554 } 1555 1556 static int 1557 m3_pci_shutdown(device_t dev) 1558 { 1559 struct sc_info *sc = pcm_getdevinfo(dev); 1560 1561 M3_DEBUG(CALL, ("m3_pci_shutdown\n")); 1562 1563 M3_LOCK(sc); 1564 m3_power(sc, 3); /* power off */ 1565 M3_UNLOCK(sc); 1566 1567 return 0; 1568 } 1569 1570 static u_int8_t 1571 m3_assp_halt(struct sc_info *sc) 1572 { 1573 u_int8_t data, reset_state; 1574 1575 M3_LOCK_ASSERT(sc); 1576 1577 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B); 1578 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */ 1579 DELAY(10 * 1000); 1580 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET); 1581 DELAY(10 * 1000); /* necessary? */ 1582 1583 return reset_state; 1584 } 1585 1586 static void 1587 m3_config(struct sc_info *sc) 1588 { 1589 u_int32_t data, hv_cfg; 1590 int hint; 1591 1592 M3_LOCK_ASSERT(sc); 1593 1594 M3_UNLOCK(sc); 1595 /* 1596 * The volume buttons can be wired up via two different sets of pins. 1597 * This presents a problem since we can't tell which way it's 1598 * configured. Allow the user to set a hint in order to twiddle 1599 * the proper bits. 1600 */ 1601 if (resource_int_value(device_get_name(sc->dev), 1602 device_get_unit(sc->dev), 1603 "hwvol_config", &hint) == 0) 1604 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0; 1605 else 1606 hv_cfg = HV_BUTTON_FROM_GD; 1607 M3_LOCK(sc); 1608 1609 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); 1610 data &= ~HV_BUTTON_FROM_GD; 1611 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg; 1612 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; 1613 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); 1614 1615 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP); 1616 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); 1617 data &= ~INT_CLK_SELECT; 1618 if (sc->which == ESS_MAESTRO3) { 1619 data &= ~INT_CLK_MULT_ENABLE; 1620 data |= INT_CLK_SRC_NOT_PCI; 1621 } 1622 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2); 1623 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); 1624 1625 if (sc->which == ESS_ALLEGRO_1) { 1626 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4); 1627 data |= IN_CLK_12MHZ_SELECT; 1628 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4); 1629 } 1630 1631 data = m3_rd_1(sc, ASSP_CONTROL_A); 1632 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); 1633 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/ 1634 data |= ASSP_0_WS_ENABLE; 1635 m3_wr_1(sc, ASSP_CONTROL_A, data); 1636 1637 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP); 1638 } 1639 1640 static void 1641 m3_enable_ints(struct sc_info *sc) 1642 { 1643 u_int8_t data; 1644 1645 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE); 1646 data = m3_rd_1(sc, ASSP_CONTROL_C); 1647 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE); 1648 } 1649 1650 static void 1651 m3_amp_enable(struct sc_info *sc) 1652 { 1653 u_int32_t gpo, polarity_port, polarity; 1654 u_int16_t data; 1655 1656 M3_LOCK_ASSERT(sc); 1657 1658 switch (sc->which) { 1659 case ESS_ALLEGRO_1: 1660 polarity_port = 0x1800; 1661 break; 1662 case ESS_MAESTRO3: 1663 polarity_port = 0x1100; 1664 break; 1665 default: 1666 panic("bad sc->which"); 1667 } 1668 gpo = (polarity_port >> 8) & 0x0f; 1669 polarity = polarity_port >> 12; 1670 polarity = !polarity; /* enable */ 1671 polarity = polarity << gpo; 1672 gpo = 1 << gpo; 1673 m3_wr_2(sc, GPIO_MASK, ~gpo); 1674 data = m3_rd_2(sc, GPIO_DIRECTION); 1675 m3_wr_2(sc, GPIO_DIRECTION, data | gpo); 1676 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity; 1677 m3_wr_2(sc, GPIO_DATA, data); 1678 m3_wr_2(sc, GPIO_MASK, ~0); 1679 } 1680 1681 static void 1682 m3_codec_reset(struct sc_info *sc) 1683 { 1684 u_int16_t data, dir; 1685 int retry = 0; 1686 1687 M3_LOCK_ASSERT(sc); 1688 do { 1689 data = m3_rd_2(sc, GPIO_DIRECTION); 1690 dir = data | 0x10; /* assuming pci bus master? */ 1691 1692 /* [[remote_codec_config]] */ 1693 data = m3_rd_2(sc, RING_BUS_CTRL_B); 1694 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK); 1695 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL); 1696 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT); 1697 data = m3_rd_2(sc, SDO_IN_DEST_CTRL); 1698 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN); 1699 1700 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE); 1701 DELAY(20); 1702 1703 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97); 1704 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97); 1705 m3_wr_2(sc, GPIO_DATA, 0); 1706 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97); 1707 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/ 1708 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97); 1709 DELAY(5); 1710 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE | 1711 SERIAL_AC_LINK_ENABLE); 1712 m3_wr_2(sc, GPIO_MASK, ~0); 1713 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/ 1714 1715 /* [[try read vendor]] */ 1716 data = m3_rdcd(NULL, sc, 0x7c); 1717 if ((data == 0) || (data == 0xffff)) { 1718 retry++; 1719 if (retry > 3) { 1720 device_printf(sc->dev, "Codec reset failed\n"); 1721 break; 1722 } 1723 device_printf(sc->dev, "Codec reset retry\n"); 1724 } else retry = 0; 1725 } while (retry); 1726 } 1727 1728 static device_method_t m3_methods[] = { 1729 DEVMETHOD(device_probe, m3_pci_probe), 1730 DEVMETHOD(device_attach, m3_pci_attach), 1731 DEVMETHOD(device_detach, m3_pci_detach), 1732 DEVMETHOD(device_suspend, m3_pci_suspend), 1733 DEVMETHOD(device_resume, m3_pci_resume), 1734 DEVMETHOD(device_shutdown, m3_pci_shutdown), 1735 { 0, 0 } 1736 }; 1737 1738 static driver_t m3_driver = { 1739 "pcm", 1740 m3_methods, 1741 PCM_SOFTC_SIZE, 1742 }; 1743 1744 DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, 0, 0); 1745 MODULE_DEPEND(snd_maestro3, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1746 MODULE_VERSION(snd_maestro3, 1); 1747