1 /* 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <dev/sound/pcm/sound.h> 29 #include <dev/sound/pcm/ac97.h> 30 #include <dev/sound/pci/ich.h> 31 32 #include <pci/pcireg.h> 33 #include <pci/pcivar.h> 34 35 SND_DECLARE_FILE("$FreeBSD$"); 36 37 /* -------------------------------------------------------------------- */ 38 39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40 #define ICH_DTBL_LENGTH 32 41 #define ICH_DEFAULT_BUFSZ 16384 42 #define ICH_MAX_BUFSZ 65536 43 44 #define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45 46 /* buffer descriptor */ 47 struct ich_desc { 48 volatile u_int32_t buffer; 49 volatile u_int32_t length; 50 }; 51 52 struct sc_info; 53 54 /* channel registers */ 55 struct sc_chinfo { 56 u_int32_t num:8, run:1, run_save:1; 57 u_int32_t blksz, blkcnt, spd; 58 u_int32_t regbase, spdreg; 59 u_int32_t imask; 60 u_int32_t civ; 61 62 struct snd_dbuf *buffer; 63 struct pcm_channel *channel; 64 struct sc_info *parent; 65 66 struct ich_desc *dtbl; 67 }; 68 69 /* device private data */ 70 struct sc_info { 71 device_t dev; 72 int hasvra, hasvrm, hasmic; 73 unsigned int chnum, bufsz; 74 int sample_size, swap_reg; 75 76 struct resource *nambar, *nabmbar, *irq; 77 int nambarid, nabmbarid, irqid; 78 bus_space_tag_t nambart, nabmbart; 79 bus_space_handle_t nambarh, nabmbarh; 80 bus_dma_tag_t dmat; 81 bus_dmamap_t dtmap; 82 void *ih; 83 84 struct ac97_info *codec; 85 struct sc_chinfo ch[3]; 86 int ac97rate; 87 struct ich_desc *dtbl; 88 }; 89 90 /* -------------------------------------------------------------------- */ 91 92 static u_int32_t ich_fmt[] = { 93 AFMT_STEREO | AFMT_S16_LE, 94 0 95 }; 96 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 97 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 98 99 /* -------------------------------------------------------------------- */ 100 /* Hardware */ 101 static u_int32_t 102 ich_rd(struct sc_info *sc, int regno, int size) 103 { 104 switch (size) { 105 case 1: 106 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 107 case 2: 108 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 109 case 4: 110 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 111 default: 112 return 0xffffffff; 113 } 114 } 115 116 static void 117 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 118 { 119 switch (size) { 120 case 1: 121 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 122 break; 123 case 2: 124 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 125 break; 126 case 4: 127 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 128 break; 129 } 130 } 131 132 /* ac97 codec */ 133 static int 134 ich_waitcd(void *devinfo) 135 { 136 int i; 137 u_int32_t data; 138 struct sc_info *sc = (struct sc_info *)devinfo; 139 140 for (i = 0; i < ICH_TIMEOUT; i++) { 141 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 142 if ((data & 0x01) == 0) 143 return 0; 144 } 145 device_printf(sc->dev, "CODEC semaphore timeout\n"); 146 return ETIMEDOUT; 147 } 148 149 static int 150 ich_rdcd(kobj_t obj, void *devinfo, int regno) 151 { 152 struct sc_info *sc = (struct sc_info *)devinfo; 153 154 regno &= 0xff; 155 ich_waitcd(sc); 156 157 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 158 } 159 160 static int 161 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 162 { 163 struct sc_info *sc = (struct sc_info *)devinfo; 164 165 regno &= 0xff; 166 ich_waitcd(sc); 167 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 168 169 return 0; 170 } 171 172 static kobj_method_t ich_ac97_methods[] = { 173 KOBJMETHOD(ac97_read, ich_rdcd), 174 KOBJMETHOD(ac97_write, ich_wrcd), 175 { 0, 0 } 176 }; 177 AC97_DECLARE(ich_ac97); 178 179 /* -------------------------------------------------------------------- */ 180 /* common routines */ 181 182 static void 183 ich_filldtbl(struct sc_chinfo *ch) 184 { 185 u_int32_t base; 186 int i; 187 188 base = vtophys(sndbuf_getbuf(ch->buffer)); 189 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 190 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 191 ch->blkcnt = 2; 192 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 193 } 194 195 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 196 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 197 ch->dtbl[i].length = ICH_BDC_IOC 198 | (ch->blksz / ch->parent->sample_size); 199 } 200 } 201 202 static int 203 ich_resetchan(struct sc_info *sc, int num) 204 { 205 int i, cr, regbase; 206 207 if (num == 0) 208 regbase = ICH_REG_PO_BASE; 209 else if (num == 1) 210 regbase = ICH_REG_PI_BASE; 211 else if (num == 2) 212 regbase = ICH_REG_MC_BASE; 213 else 214 return ENXIO; 215 216 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 217 DELAY(100); 218 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 219 for (i = 0; i < ICH_TIMEOUT; i++) { 220 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 221 if (cr == 0) 222 return 0; 223 } 224 225 device_printf(sc->dev, "cannot reset channel %d\n", num); 226 return ENXIO; 227 } 228 229 /* -------------------------------------------------------------------- */ 230 /* channel interface */ 231 232 static void * 233 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 234 { 235 struct sc_info *sc = devinfo; 236 struct sc_chinfo *ch; 237 unsigned int num; 238 239 num = sc->chnum++; 240 ch = &sc->ch[num]; 241 ch->num = num; 242 ch->buffer = b; 243 ch->channel = c; 244 ch->parent = sc; 245 ch->run = 0; 246 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 247 ch->blkcnt = 2; 248 ch->blksz = sc->bufsz / ch->blkcnt; 249 250 switch(ch->num) { 251 case 0: /* play */ 252 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 253 ch->regbase = ICH_REG_PO_BASE; 254 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 255 ch->imask = ICH_GLOB_STA_POINT; 256 break; 257 258 case 1: /* record */ 259 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 260 ch->regbase = ICH_REG_PI_BASE; 261 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 262 ch->imask = ICH_GLOB_STA_PIINT; 263 break; 264 265 case 2: /* mic */ 266 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 267 ch->regbase = ICH_REG_MC_BASE; 268 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 269 ch->imask = ICH_GLOB_STA_MINT; 270 break; 271 272 default: 273 return NULL; 274 } 275 276 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 277 return NULL; 278 279 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 280 281 return ch; 282 } 283 284 static int 285 ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 286 { 287 return 0; 288 } 289 290 static int 291 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 292 { 293 struct sc_chinfo *ch = data; 294 struct sc_info *sc = ch->parent; 295 296 if (ch->spdreg) { 297 int r; 298 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 299 sc->ac97rate = 48000; 300 r = (speed * 48000) / sc->ac97rate; 301 /* 302 * Cast the return value of ac97_setrate() to u_int so that 303 * the math don't overflow into the negative range. 304 */ 305 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 306 sc->ac97rate) / 48000; 307 } else { 308 ch->spd = 48000; 309 } 310 return ch->spd; 311 } 312 313 static int 314 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 315 { 316 struct sc_chinfo *ch = data; 317 struct sc_info *sc = ch->parent; 318 319 ch->blksz = blocksize; 320 ich_filldtbl(ch); 321 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 322 323 return ch->blksz; 324 } 325 326 static int 327 ichchan_trigger(kobj_t obj, void *data, int go) 328 { 329 struct sc_chinfo *ch = data; 330 struct sc_info *sc = ch->parent; 331 332 switch (go) { 333 case PCMTRIG_START: 334 ch->run = 1; 335 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 336 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 337 break; 338 339 case PCMTRIG_ABORT: 340 ich_resetchan(sc, ch->num); 341 ch->run = 0; 342 break; 343 } 344 return 0; 345 } 346 347 static int 348 ichchan_getptr(kobj_t obj, void *data) 349 { 350 struct sc_chinfo *ch = data; 351 struct sc_info *sc = ch->parent; 352 u_int32_t pos; 353 354 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 355 356 pos = ch->civ * ch->blksz; 357 358 return pos; 359 } 360 361 static struct pcmchan_caps * 362 ichchan_getcaps(kobj_t obj, void *data) 363 { 364 struct sc_chinfo *ch = data; 365 366 return ch->spdreg? &ich_vrcaps : &ich_caps; 367 } 368 369 static kobj_method_t ichchan_methods[] = { 370 KOBJMETHOD(channel_init, ichchan_init), 371 KOBJMETHOD(channel_setformat, ichchan_setformat), 372 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 373 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 374 KOBJMETHOD(channel_trigger, ichchan_trigger), 375 KOBJMETHOD(channel_getptr, ichchan_getptr), 376 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 377 { 0, 0 } 378 }; 379 CHANNEL_DECLARE(ichchan); 380 381 /* -------------------------------------------------------------------- */ 382 /* The interrupt handler */ 383 384 static void 385 ich_intr(void *p) 386 { 387 struct sc_info *sc = (struct sc_info *)p; 388 struct sc_chinfo *ch; 389 u_int32_t cbi, lbi, lvi, st, gs; 390 int i; 391 392 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 393 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 394 /* Clear resume interrupt(s) - nothing doing with them */ 395 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 396 } 397 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 398 399 for (i = 0; i < 3; i++) { 400 ch = &sc->ch[i]; 401 if ((ch->imask & gs) == 0) 402 continue; 403 gs &= ~ch->imask; 404 st = ich_rd(sc, ch->regbase + 405 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 406 2); 407 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 408 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 409 /* block complete - update buffer */ 410 if (ch->run) 411 chn_intr(ch->channel); 412 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 413 cbi = ch->civ % ch->blkcnt; 414 if (cbi == 0) 415 cbi = ch->blkcnt - 1; 416 else 417 cbi--; 418 lbi = lvi % ch->blkcnt; 419 if (cbi >= lbi) 420 lvi += cbi - lbi; 421 else 422 lvi += cbi + ch->blkcnt - lbi; 423 lvi %= ICH_DTBL_LENGTH; 424 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 425 426 } 427 /* clear status bit */ 428 ich_wr(sc, ch->regbase + 429 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 430 st, 2); 431 } 432 if (gs != 0) { 433 device_printf(sc->dev, 434 "Unhandled interrupt, gs_intr = %x\n", gs); 435 } 436 } 437 438 /* ------------------------------------------------------------------------- */ 439 /* Sysctl to control ac97 speed (some boards overclocked ac97). */ 440 441 static int 442 ich_initsys(struct sc_info* sc) 443 { 444 #ifdef SND_DYNSYSCTL 445 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 446 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 447 OID_AUTO, "ac97rate", CTLFLAG_RW, 448 &sc->ac97rate, 48000, 449 "AC97 link rate (default = 48000)"); 450 #endif /* SND_DYNSYSCTL */ 451 return 0; 452 } 453 454 /* -------------------------------------------------------------------- */ 455 /* Calibrate card (some boards are overclocked and need scaling) */ 456 457 static 458 unsigned int ich_calibrate(struct sc_info *sc) 459 { 460 struct sc_chinfo *ch = &sc->ch[1]; 461 struct timeval t1, t2; 462 u_int8_t ociv, nciv; 463 u_int32_t wait_us, actual_48k_rate, bytes; 464 465 /* 466 * Grab audio from input for fixed interval and compare how 467 * much we actually get with what we expect. Interval needs 468 * to be sufficiently short that no interrupts are 469 * generated. 470 */ 471 472 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 473 474 bytes = sndbuf_getsize(ch->buffer) / 2; 475 ichchan_setblocksize(0, ch, bytes); 476 477 /* 478 * our data format is stereo, 16 bit so each sample is 4 bytes. 479 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 480 * we're going to start recording with interrupts disabled and measure 481 * the time taken for one block to complete. we know the block size, 482 * we know the time in microseconds, we calculate the sample rate: 483 * 484 * actual_rate [bps] = bytes / (time [s] * 4) 485 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 486 * actual_rate [Hz] = (bytes * 250000) / time [us] 487 */ 488 489 /* prepare */ 490 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 491 nciv = ociv; 492 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 493 494 /* start */ 495 microtime(&t1); 496 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 497 498 /* wait */ 499 while (nciv == ociv) { 500 microtime(&t2); 501 if (t2.tv_sec - t1.tv_sec > 1) 502 break; 503 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 504 } 505 microtime(&t2); 506 507 /* stop */ 508 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 509 510 /* reset */ 511 DELAY(100); 512 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 513 514 /* turn time delta into us */ 515 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 516 517 if (nciv == ociv) { 518 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 519 return 0; 520 } 521 522 actual_48k_rate = (bytes * 250000) / wait_us; 523 524 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 525 sc->ac97rate = actual_48k_rate; 526 } else { 527 sc->ac97rate = 48000; 528 } 529 530 if (bootverbose || sc->ac97rate != 48000) { 531 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 532 if (sc->ac97rate != actual_48k_rate) 533 printf(", will use %d Hz", sc->ac97rate); 534 printf("\n"); 535 } 536 537 return sc->ac97rate; 538 } 539 540 /* -------------------------------------------------------------------- */ 541 /* Probe and attach the card */ 542 543 static void 544 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 545 { 546 return; 547 } 548 549 static int 550 ich_init(struct sc_info *sc) 551 { 552 u_int32_t stat; 553 int sz; 554 555 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 556 DELAY(600000); 557 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 558 559 if ((stat & ICH_GLOB_STA_PCR) == 0) 560 return ENXIO; 561 562 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 563 564 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 565 return ENXIO; 566 if (sc->hasmic && ich_resetchan(sc, 2)) 567 return ENXIO; 568 569 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 570 return ENOSPC; 571 572 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 573 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) { 574 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 575 return ENOSPC; 576 } 577 578 return 0; 579 } 580 581 static int 582 ich_pci_probe(device_t dev) 583 { 584 switch(pci_get_devid(dev)) { 585 case 0x71958086: 586 device_set_desc(dev, "Intel 443MX"); 587 return 0; 588 589 case 0x24158086: 590 device_set_desc(dev, "Intel 82801AA (ICH)"); 591 return 0; 592 593 case 0x24258086: 594 device_set_desc(dev, "Intel 82801AB (ICH)"); 595 return 0; 596 597 case 0x24458086: 598 device_set_desc(dev, "Intel 82801BA (ICH2)"); 599 return 0; 600 601 case 0x24858086: 602 device_set_desc(dev, "Intel 82801CA (ICH3)"); 603 return 0; 604 605 case SIS7012ID: 606 device_set_desc(dev, "SiS 7012"); 607 return 0; 608 609 case 0x01b110de: 610 device_set_desc(dev, "Nvidia nForce AC97 controller"); 611 return 0; 612 613 default: 614 return ENXIO; 615 } 616 } 617 618 static int 619 ich_pci_attach(device_t dev) 620 { 621 u_int32_t data; 622 u_int16_t extcaps; 623 struct sc_info *sc; 624 char status[SND_STATUSLEN]; 625 626 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 627 device_printf(dev, "cannot allocate softc\n"); 628 return ENXIO; 629 } 630 631 bzero(sc, sizeof(*sc)); 632 sc->dev = dev; 633 634 /* 635 * The SiS 7012 register set isn't quite like the standard ich. 636 * There really should be a general "quirks" mechanism. 637 */ 638 if (pci_get_devid(dev) == SIS7012ID) { 639 sc->swap_reg = 1; 640 sc->sample_size = 1; 641 } else { 642 sc->swap_reg = 0; 643 sc->sample_size = 2; 644 } 645 646 data = pci_read_config(dev, PCIR_COMMAND, 2); 647 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 648 pci_write_config(dev, PCIR_COMMAND, data, 2); 649 data = pci_read_config(dev, PCIR_COMMAND, 2); 650 651 sc->nambarid = PCIR_NAMBAR; 652 sc->nabmbarid = PCIR_NABMBAR; 653 sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 654 sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 655 656 if (!sc->nambar || !sc->nabmbar) { 657 device_printf(dev, "unable to map IO port space\n"); 658 goto bad; 659 } 660 661 sc->nambart = rman_get_bustag(sc->nambar); 662 sc->nambarh = rman_get_bushandle(sc->nambar); 663 sc->nabmbart = rman_get_bustag(sc->nabmbar); 664 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 665 666 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 667 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 668 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) { 669 device_printf(dev, "unable to create dma tag\n"); 670 goto bad; 671 } 672 673 sc->irqid = 0; 674 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 675 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 676 device_printf(dev, "unable to map interrupt\n"); 677 goto bad; 678 } 679 680 if (ich_init(sc)) { 681 device_printf(dev, "unable to initialize the card\n"); 682 goto bad; 683 } 684 685 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 686 if (sc->codec == NULL) 687 goto bad; 688 mixer_init(dev, ac97_getmixerclass(), sc->codec); 689 690 /* check and set VRA function */ 691 extcaps = ac97_getextcaps(sc->codec); 692 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 693 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 694 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 695 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 696 697 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 698 goto bad; 699 700 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 701 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 702 if (sc->hasmic) 703 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 704 705 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 706 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 707 708 pcm_setstatus(dev, status); 709 710 ich_initsys(sc); 711 ich_calibrate(sc); 712 713 return 0; 714 715 bad: 716 if (sc->codec) 717 ac97_destroy(sc->codec); 718 if (sc->ih) 719 bus_teardown_intr(dev, sc->irq, sc->ih); 720 if (sc->irq) 721 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 722 if (sc->nambar) 723 bus_release_resource(dev, SYS_RES_IOPORT, 724 sc->nambarid, sc->nambar); 725 if (sc->nabmbar) 726 bus_release_resource(dev, SYS_RES_IOPORT, 727 sc->nabmbarid, sc->nabmbar); 728 free(sc, M_DEVBUF); 729 return ENXIO; 730 } 731 732 static int 733 ich_pci_detach(device_t dev) 734 { 735 struct sc_info *sc; 736 int r; 737 738 r = pcm_unregister(dev); 739 if (r) 740 return r; 741 sc = pcm_getdevinfo(dev); 742 743 bus_teardown_intr(dev, sc->irq, sc->ih); 744 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 745 bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 746 bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 747 bus_dma_tag_destroy(sc->dmat); 748 free(sc, M_DEVBUF); 749 return 0; 750 } 751 752 static int 753 ich_pci_suspend(device_t dev) 754 { 755 struct sc_info *sc; 756 int i; 757 758 sc = pcm_getdevinfo(dev); 759 for (i = 0 ; i < 3; i++) { 760 sc->ch[i].run_save = sc->ch[i].run; 761 if (sc->ch[i].run) { 762 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 763 } 764 } 765 return 0; 766 } 767 768 static int 769 ich_pci_resume(device_t dev) 770 { 771 struct sc_info *sc; 772 int i; 773 774 sc = pcm_getdevinfo(dev); 775 776 /* Reinit audio device */ 777 if (ich_init(sc) == -1) { 778 device_printf(dev, "unable to reinitialize the card\n"); 779 return ENXIO; 780 } 781 /* Reinit mixer */ 782 if (mixer_reinit(dev) == -1) { 783 device_printf(dev, "unable to reinitialize the mixer\n"); 784 return ENXIO; 785 } 786 /* Re-start DMA engines */ 787 for (i = 0 ; i < 3; i++) { 788 struct sc_chinfo *ch = &sc->ch[i]; 789 if (sc->ch[i].run_save) { 790 ichchan_setblocksize(0, ch, ch->blksz); 791 ichchan_setspeed(0, ch, ch->spd); 792 ichchan_trigger(0, ch, PCMTRIG_START); 793 } 794 } 795 return 0; 796 } 797 798 static device_method_t ich_methods[] = { 799 /* Device interface */ 800 DEVMETHOD(device_probe, ich_pci_probe), 801 DEVMETHOD(device_attach, ich_pci_attach), 802 DEVMETHOD(device_detach, ich_pci_detach), 803 DEVMETHOD(device_suspend, ich_pci_suspend), 804 DEVMETHOD(device_resume, ich_pci_resume), 805 { 0, 0 } 806 }; 807 808 static driver_t ich_driver = { 809 "pcm", 810 ich_methods, 811 PCM_SOFTC_SIZE, 812 }; 813 814 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 815 MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 816 MODULE_VERSION(snd_ich, 1); 817