1 /* 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <dev/sound/pcm/sound.h> 29 #include <dev/sound/pcm/ac97.h> 30 #include <dev/sound/pci/ich.h> 31 32 #include <pci/pcireg.h> 33 #include <pci/pcivar.h> 34 35 SND_DECLARE_FILE("$FreeBSD$"); 36 37 /* -------------------------------------------------------------------- */ 38 39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40 #define ICH_DTBL_LENGTH 32 41 #define ICH_DEFAULT_BUFSZ 16384 42 #define ICH_MAX_BUFSZ 65536 43 44 #define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45 46 /* buffer descriptor */ 47 struct ich_desc { 48 volatile u_int32_t buffer; 49 volatile u_int32_t length; 50 }; 51 52 struct sc_info; 53 54 /* channel registers */ 55 struct sc_chinfo { 56 u_int32_t num:8, run:1, run_save:1; 57 u_int32_t blksz, blkcnt, spd; 58 u_int32_t regbase, spdreg; 59 u_int32_t imask; 60 u_int32_t civ; 61 62 struct snd_dbuf *buffer; 63 struct pcm_channel *channel; 64 struct sc_info *parent; 65 66 struct ich_desc *dtbl; 67 }; 68 69 /* device private data */ 70 struct sc_info { 71 device_t dev; 72 int hasvra, hasvrm, hasmic; 73 unsigned int chnum, bufsz; 74 int sample_size, swap_reg; 75 76 struct resource *nambar, *nabmbar, *irq; 77 int nambarid, nabmbarid, irqid; 78 bus_space_tag_t nambart, nabmbart; 79 bus_space_handle_t nambarh, nabmbarh; 80 bus_dma_tag_t dmat; 81 bus_dmamap_t dtmap; 82 void *ih; 83 84 struct ac97_info *codec; 85 struct sc_chinfo ch[3]; 86 int ac97rate; 87 struct ich_desc *dtbl; 88 }; 89 90 /* -------------------------------------------------------------------- */ 91 92 static u_int32_t ich_fmt[] = { 93 AFMT_STEREO | AFMT_S16_LE, 94 0 95 }; 96 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 97 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 98 99 /* -------------------------------------------------------------------- */ 100 /* Hardware */ 101 static u_int32_t 102 ich_rd(struct sc_info *sc, int regno, int size) 103 { 104 switch (size) { 105 case 1: 106 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 107 case 2: 108 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 109 case 4: 110 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 111 default: 112 return 0xffffffff; 113 } 114 } 115 116 static void 117 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 118 { 119 switch (size) { 120 case 1: 121 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 122 break; 123 case 2: 124 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 125 break; 126 case 4: 127 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 128 break; 129 } 130 } 131 132 /* ac97 codec */ 133 static int 134 ich_waitcd(void *devinfo) 135 { 136 int i; 137 u_int32_t data; 138 struct sc_info *sc = (struct sc_info *)devinfo; 139 140 for (i = 0; i < ICH_TIMEOUT; i++) { 141 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 142 if ((data & 0x01) == 0) 143 return 0; 144 } 145 device_printf(sc->dev, "CODEC semaphore timeout\n"); 146 return ETIMEDOUT; 147 } 148 149 static int 150 ich_rdcd(kobj_t obj, void *devinfo, int regno) 151 { 152 struct sc_info *sc = (struct sc_info *)devinfo; 153 154 regno &= 0xff; 155 ich_waitcd(sc); 156 157 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 158 } 159 160 static int 161 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 162 { 163 struct sc_info *sc = (struct sc_info *)devinfo; 164 165 regno &= 0xff; 166 ich_waitcd(sc); 167 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 168 169 return 0; 170 } 171 172 static kobj_method_t ich_ac97_methods[] = { 173 KOBJMETHOD(ac97_read, ich_rdcd), 174 KOBJMETHOD(ac97_write, ich_wrcd), 175 { 0, 0 } 176 }; 177 AC97_DECLARE(ich_ac97); 178 179 /* -------------------------------------------------------------------- */ 180 /* common routines */ 181 182 static void 183 ich_filldtbl(struct sc_chinfo *ch) 184 { 185 u_int32_t base; 186 int i; 187 188 base = vtophys(sndbuf_getbuf(ch->buffer)); 189 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 190 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 191 ch->blkcnt = 2; 192 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 193 } 194 195 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 196 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 197 ch->dtbl[i].length = ICH_BDC_IOC 198 | (ch->blksz / ch->parent->sample_size); 199 } 200 } 201 202 static int 203 ich_resetchan(struct sc_info *sc, int num) 204 { 205 int i, cr, regbase; 206 207 if (num == 0) 208 regbase = ICH_REG_PO_BASE; 209 else if (num == 1) 210 regbase = ICH_REG_PI_BASE; 211 else if (num == 2) 212 regbase = ICH_REG_MC_BASE; 213 else 214 return ENXIO; 215 216 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 217 DELAY(100); 218 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 219 for (i = 0; i < ICH_TIMEOUT; i++) { 220 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 221 if (cr == 0) 222 return 0; 223 } 224 225 device_printf(sc->dev, "cannot reset channel %d\n", num); 226 return ENXIO; 227 } 228 229 /* -------------------------------------------------------------------- */ 230 /* channel interface */ 231 232 static void * 233 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 234 { 235 struct sc_info *sc = devinfo; 236 struct sc_chinfo *ch; 237 unsigned int num; 238 239 num = sc->chnum++; 240 ch = &sc->ch[num]; 241 ch->num = num; 242 ch->buffer = b; 243 ch->channel = c; 244 ch->parent = sc; 245 ch->run = 0; 246 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 247 ch->blkcnt = 2; 248 ch->blksz = sc->bufsz / ch->blkcnt; 249 250 switch(ch->num) { 251 case 0: /* play */ 252 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 253 ch->regbase = ICH_REG_PO_BASE; 254 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 255 ch->imask = ICH_GLOB_STA_POINT; 256 break; 257 258 case 1: /* record */ 259 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 260 ch->regbase = ICH_REG_PI_BASE; 261 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 262 ch->imask = ICH_GLOB_STA_PIINT; 263 break; 264 265 case 2: /* mic */ 266 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 267 ch->regbase = ICH_REG_MC_BASE; 268 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 269 ch->imask = ICH_GLOB_STA_MINT; 270 break; 271 272 default: 273 return NULL; 274 } 275 276 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 277 return NULL; 278 279 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 280 281 return ch; 282 } 283 284 static int 285 ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 286 { 287 return 0; 288 } 289 290 static int 291 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 292 { 293 struct sc_chinfo *ch = data; 294 struct sc_info *sc = ch->parent; 295 296 if (ch->spdreg) { 297 int r; 298 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 299 sc->ac97rate = 48000; 300 r = (speed * 48000) / sc->ac97rate; 301 ch->spd = (ac97_setrate(sc->codec, ch->spdreg, r) * sc->ac97rate) / 48000; 302 } else { 303 ch->spd = 48000; 304 } 305 return ch->spd; 306 } 307 308 static int 309 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 310 { 311 struct sc_chinfo *ch = data; 312 struct sc_info *sc = ch->parent; 313 314 ch->blksz = blocksize; 315 ich_filldtbl(ch); 316 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 317 318 return ch->blksz; 319 } 320 321 static int 322 ichchan_trigger(kobj_t obj, void *data, int go) 323 { 324 struct sc_chinfo *ch = data; 325 struct sc_info *sc = ch->parent; 326 327 switch (go) { 328 case PCMTRIG_START: 329 ch->run = 1; 330 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 331 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 332 break; 333 334 case PCMTRIG_ABORT: 335 ich_resetchan(sc, ch->num); 336 ch->run = 0; 337 break; 338 } 339 return 0; 340 } 341 342 static int 343 ichchan_getptr(kobj_t obj, void *data) 344 { 345 struct sc_chinfo *ch = data; 346 struct sc_info *sc = ch->parent; 347 u_int32_t pos; 348 349 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 350 351 pos = ch->civ * ch->blksz; 352 353 return pos; 354 } 355 356 static struct pcmchan_caps * 357 ichchan_getcaps(kobj_t obj, void *data) 358 { 359 struct sc_chinfo *ch = data; 360 361 return ch->spdreg? &ich_vrcaps : &ich_caps; 362 } 363 364 static kobj_method_t ichchan_methods[] = { 365 KOBJMETHOD(channel_init, ichchan_init), 366 KOBJMETHOD(channel_setformat, ichchan_setformat), 367 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 368 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 369 KOBJMETHOD(channel_trigger, ichchan_trigger), 370 KOBJMETHOD(channel_getptr, ichchan_getptr), 371 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 372 { 0, 0 } 373 }; 374 CHANNEL_DECLARE(ichchan); 375 376 /* -------------------------------------------------------------------- */ 377 /* The interrupt handler */ 378 379 static void 380 ich_intr(void *p) 381 { 382 struct sc_info *sc = (struct sc_info *)p; 383 struct sc_chinfo *ch; 384 u_int32_t cbi, lbi, lvi, st, gs; 385 int i; 386 387 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 388 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 389 /* Clear resume interrupt(s) - nothing doing with them */ 390 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 391 } 392 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 393 394 for (i = 0; i < 3; i++) { 395 ch = &sc->ch[i]; 396 if ((ch->imask & gs) == 0) 397 continue; 398 gs &= ~ch->imask; 399 st = ich_rd(sc, ch->regbase + 400 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 401 2); 402 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 403 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 404 /* block complete - update buffer */ 405 if (ch->run) 406 chn_intr(ch->channel); 407 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 408 cbi = ch->civ % ch->blkcnt; 409 if (cbi == 0) 410 cbi = ch->blkcnt - 1; 411 else 412 cbi--; 413 lbi = lvi % ch->blkcnt; 414 if (cbi >= lbi) 415 lvi += cbi - lbi; 416 else 417 lvi += cbi + ch->blkcnt - lbi; 418 lvi %= ICH_DTBL_LENGTH; 419 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 420 421 } 422 /* clear status bit */ 423 ich_wr(sc, ch->regbase + 424 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 425 st, 2); 426 } 427 if (gs != 0) { 428 device_printf(sc->dev, 429 "Unhandled interrupt, gs_intr = %x\n", gs); 430 } 431 } 432 433 /* ------------------------------------------------------------------------- */ 434 /* Sysctl to control ac97 speed (some boards overclocked ac97). */ 435 436 static int 437 ich_initsys(struct sc_info* sc) 438 { 439 #ifdef SND_DYNSYSCTL 440 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 441 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 442 OID_AUTO, "ac97rate", CTLFLAG_RW, 443 &sc->ac97rate, 48000, 444 "AC97 link rate (default = 48000)"); 445 #endif /* SND_DYNSYSCTL */ 446 return 0; 447 } 448 449 /* -------------------------------------------------------------------- */ 450 /* Calibrate card (some boards are overclocked and need scaling) */ 451 452 static 453 unsigned int ich_calibrate(struct sc_info *sc) 454 { 455 struct sc_chinfo *ch = &sc->ch[1]; 456 struct timeval t1, t2; 457 u_int8_t ociv, nciv; 458 u_int32_t wait_us, actual_48k_rate, bytes; 459 460 /* 461 * Grab audio from input for fixed interval and compare how 462 * much we actually get with what we expect. Interval needs 463 * to be sufficiently short that no interrupts are 464 * generated. 465 */ 466 467 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 468 469 bytes = sndbuf_getsize(ch->buffer) / 2; 470 ichchan_setblocksize(0, ch, bytes); 471 472 /* 473 * our data format is stereo, 16 bit so each sample is 4 bytes. 474 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 475 * we're going to start recording with interrupts disabled and measure 476 * the time taken for one block to complete. we know the block size, 477 * we know the time in microseconds, we calculate the sample rate: 478 * 479 * actual_rate [bps] = bytes / (time [s] * 4) 480 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 481 * actual_rate [Hz] = (bytes * 250000) / time [us] 482 */ 483 484 /* prepare */ 485 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 486 nciv = ociv; 487 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 488 489 /* start */ 490 microtime(&t1); 491 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 492 493 /* wait */ 494 while (nciv == ociv) { 495 microtime(&t2); 496 if (t2.tv_sec - t1.tv_sec > 1) 497 break; 498 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 499 } 500 microtime(&t2); 501 502 /* stop */ 503 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 504 505 /* reset */ 506 DELAY(100); 507 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 508 509 /* turn time delta into us */ 510 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 511 512 if (nciv == ociv) { 513 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 514 return 0; 515 } 516 517 actual_48k_rate = (bytes * 250000) / wait_us; 518 519 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 520 sc->ac97rate = actual_48k_rate; 521 } else { 522 sc->ac97rate = 48000; 523 } 524 525 if (bootverbose || sc->ac97rate != 48000) { 526 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 527 if (sc->ac97rate != actual_48k_rate) 528 printf(", will use %d Hz", sc->ac97rate); 529 printf("\n"); 530 } 531 532 return sc->ac97rate; 533 } 534 535 /* -------------------------------------------------------------------- */ 536 /* Probe and attach the card */ 537 538 static void 539 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 540 { 541 return; 542 } 543 544 static int 545 ich_init(struct sc_info *sc) 546 { 547 u_int32_t stat; 548 int sz; 549 550 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 551 DELAY(600000); 552 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 553 554 if ((stat & ICH_GLOB_STA_PCR) == 0) 555 return ENXIO; 556 557 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 558 559 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 560 return ENXIO; 561 if (sc->hasmic && ich_resetchan(sc, 2)) 562 return ENXIO; 563 564 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 565 return ENOSPC; 566 567 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 568 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) { 569 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 570 return ENOSPC; 571 } 572 573 return 0; 574 } 575 576 static int 577 ich_pci_probe(device_t dev) 578 { 579 switch(pci_get_devid(dev)) { 580 case 0x71958086: 581 device_set_desc(dev, "Intel 443MX"); 582 return 0; 583 584 case 0x24158086: 585 device_set_desc(dev, "Intel 82801AA (ICH)"); 586 return 0; 587 588 case 0x24258086: 589 device_set_desc(dev, "Intel 82801AB (ICH)"); 590 return 0; 591 592 case 0x24458086: 593 device_set_desc(dev, "Intel 82801BA (ICH2)"); 594 return 0; 595 596 case 0x24858086: 597 device_set_desc(dev, "Intel 82801CA (ICH3)"); 598 return 0; 599 600 case SIS7012ID: 601 device_set_desc(dev, "SiS 7012"); 602 return 0; 603 604 default: 605 return ENXIO; 606 } 607 } 608 609 static int 610 ich_pci_attach(device_t dev) 611 { 612 u_int32_t data; 613 u_int16_t extcaps; 614 struct sc_info *sc; 615 char status[SND_STATUSLEN]; 616 617 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 618 device_printf(dev, "cannot allocate softc\n"); 619 return ENXIO; 620 } 621 622 bzero(sc, sizeof(*sc)); 623 sc->dev = dev; 624 625 /* 626 * The SiS 7012 register set isn't quite like the standard ich. 627 * There really should be a general "quirks" mechanism. 628 */ 629 if (pci_get_devid(dev) == SIS7012ID) { 630 sc->swap_reg = 1; 631 sc->sample_size = 1; 632 } else { 633 sc->swap_reg = 0; 634 sc->sample_size = 2; 635 } 636 637 data = pci_read_config(dev, PCIR_COMMAND, 2); 638 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 639 pci_write_config(dev, PCIR_COMMAND, data, 2); 640 data = pci_read_config(dev, PCIR_COMMAND, 2); 641 642 sc->nambarid = PCIR_NAMBAR; 643 sc->nabmbarid = PCIR_NABMBAR; 644 sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 645 sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 646 647 if (!sc->nambar || !sc->nabmbar) { 648 device_printf(dev, "unable to map IO port space\n"); 649 goto bad; 650 } 651 652 sc->nambart = rman_get_bustag(sc->nambar); 653 sc->nambarh = rman_get_bushandle(sc->nambar); 654 sc->nabmbart = rman_get_bustag(sc->nabmbar); 655 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 656 657 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 658 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 659 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) { 660 device_printf(dev, "unable to create dma tag\n"); 661 goto bad; 662 } 663 664 sc->irqid = 0; 665 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 666 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 667 device_printf(dev, "unable to map interrupt\n"); 668 goto bad; 669 } 670 671 if (ich_init(sc)) { 672 device_printf(dev, "unable to initialize the card\n"); 673 goto bad; 674 } 675 676 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 677 if (sc->codec == NULL) 678 goto bad; 679 mixer_init(dev, ac97_getmixerclass(), sc->codec); 680 681 /* check and set VRA function */ 682 extcaps = ac97_getextcaps(sc->codec); 683 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 684 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 685 sc->hasmic = extcaps & AC97_CAP_MICCHANNEL; 686 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm | sc->hasmic); 687 688 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 689 goto bad; 690 691 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 692 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 693 if (sc->hasmic) 694 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 695 696 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 697 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 698 699 pcm_setstatus(dev, status); 700 701 ich_initsys(sc); 702 ich_calibrate(sc); 703 704 return 0; 705 706 bad: 707 if (sc->codec) 708 ac97_destroy(sc->codec); 709 if (sc->ih) 710 bus_teardown_intr(dev, sc->irq, sc->ih); 711 if (sc->irq) 712 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 713 if (sc->nambar) 714 bus_release_resource(dev, SYS_RES_IOPORT, 715 sc->nambarid, sc->nambar); 716 if (sc->nabmbar) 717 bus_release_resource(dev, SYS_RES_IOPORT, 718 sc->nabmbarid, sc->nabmbar); 719 free(sc, M_DEVBUF); 720 return ENXIO; 721 } 722 723 static int 724 ich_pci_detach(device_t dev) 725 { 726 struct sc_info *sc; 727 int r; 728 729 r = pcm_unregister(dev); 730 if (r) 731 return r; 732 sc = pcm_getdevinfo(dev); 733 734 bus_teardown_intr(dev, sc->irq, sc->ih); 735 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 736 bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 737 bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 738 bus_dma_tag_destroy(sc->dmat); 739 free(sc, M_DEVBUF); 740 return 0; 741 } 742 743 static int 744 ich_pci_suspend(device_t dev) 745 { 746 struct sc_info *sc; 747 int i; 748 749 sc = pcm_getdevinfo(dev); 750 for (i = 0 ; i < 3; i++) { 751 sc->ch[i].run_save = sc->ch[i].run; 752 if (sc->ch[i].run) { 753 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 754 } 755 } 756 757 /* ACLINK shut off */ 758 ich_wr(sc,ICH_REG_GLOB_CNT, ICH_GLOB_CTL_SHUT, 4); 759 return 0; 760 } 761 762 static int 763 ich_pci_resume(device_t dev) 764 { 765 struct sc_info *sc; 766 int i; 767 768 sc = pcm_getdevinfo(dev); 769 770 /* Reinit audio device */ 771 if (ich_init(sc) == -1) { 772 device_printf(dev, "unable to reinitialize the card\n"); 773 return ENXIO; 774 } 775 /* Reinit mixer */ 776 if (mixer_reinit(dev) == -1) { 777 device_printf(dev, "unable to reinitialize the mixer\n"); 778 return ENXIO; 779 } 780 /* Re-start DMA engines */ 781 for (i = 0 ; i < 3; i++) { 782 struct sc_chinfo *ch = &sc->ch[i]; 783 if (sc->ch[i].run_save) { 784 ichchan_setblocksize(0, ch, ch->blksz); 785 ichchan_setspeed(0, ch, ch->spd); 786 ichchan_trigger(0, ch, PCMTRIG_START); 787 } 788 } 789 return 0; 790 } 791 792 static device_method_t ich_methods[] = { 793 /* Device interface */ 794 DEVMETHOD(device_probe, ich_pci_probe), 795 DEVMETHOD(device_attach, ich_pci_attach), 796 DEVMETHOD(device_detach, ich_pci_detach), 797 DEVMETHOD(device_suspend, ich_pci_suspend), 798 DEVMETHOD(device_resume, ich_pci_resume), 799 { 0, 0 } 800 }; 801 802 static driver_t ich_driver = { 803 "pcm", 804 ich_methods, 805 PCM_SOFTC_SIZE, 806 }; 807 808 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 809 MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 810 MODULE_VERSION(snd_ich, 1); 811