1 /* 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <dev/sound/pcm/sound.h> 29 #include <dev/sound/pcm/ac97.h> 30 #include <dev/sound/pci/ich.h> 31 32 #include <pci/pcireg.h> 33 #include <pci/pcivar.h> 34 35 SND_DECLARE_FILE("$FreeBSD$"); 36 37 /* -------------------------------------------------------------------- */ 38 39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40 #define ICH_DTBL_LENGTH 32 41 #define ICH_DEFAULT_BUFSZ 16384 42 #define ICH_MAX_BUFSZ 65536 43 44 #define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45 46 /* buffer descriptor */ 47 struct ich_desc { 48 volatile u_int32_t buffer; 49 volatile u_int32_t length; 50 }; 51 52 struct sc_info; 53 54 /* channel registers */ 55 struct sc_chinfo { 56 u_int32_t num:8, run:1, run_save:1; 57 u_int32_t blksz, blkcnt, spd; 58 u_int32_t regbase, spdreg; 59 u_int32_t imask; 60 u_int32_t civ; 61 62 struct snd_dbuf *buffer; 63 struct pcm_channel *channel; 64 struct sc_info *parent; 65 66 struct ich_desc *dtbl; 67 }; 68 69 /* device private data */ 70 struct sc_info { 71 device_t dev; 72 int hasvra, hasvrm, hasmic; 73 unsigned int chnum, bufsz; 74 int sample_size, swap_reg; 75 76 struct resource *nambar, *nabmbar, *irq; 77 int nambarid, nabmbarid, irqid; 78 bus_space_tag_t nambart, nabmbart; 79 bus_space_handle_t nambarh, nabmbarh; 80 bus_dma_tag_t dmat; 81 bus_dmamap_t dtmap; 82 void *ih; 83 84 struct ac97_info *codec; 85 struct sc_chinfo ch[3]; 86 int ac97rate; 87 struct ich_desc *dtbl; 88 struct intr_config_hook intrhook; 89 int use_intrhook; 90 }; 91 92 /* -------------------------------------------------------------------- */ 93 94 static u_int32_t ich_fmt[] = { 95 AFMT_STEREO | AFMT_S16_LE, 96 0 97 }; 98 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 99 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 100 101 /* -------------------------------------------------------------------- */ 102 /* Hardware */ 103 static u_int32_t 104 ich_rd(struct sc_info *sc, int regno, int size) 105 { 106 switch (size) { 107 case 1: 108 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 109 case 2: 110 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 111 case 4: 112 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 113 default: 114 return 0xffffffff; 115 } 116 } 117 118 static void 119 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 120 { 121 switch (size) { 122 case 1: 123 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 124 break; 125 case 2: 126 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 127 break; 128 case 4: 129 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 130 break; 131 } 132 } 133 134 /* ac97 codec */ 135 static int 136 ich_waitcd(void *devinfo) 137 { 138 int i; 139 u_int32_t data; 140 struct sc_info *sc = (struct sc_info *)devinfo; 141 142 for (i = 0; i < ICH_TIMEOUT; i++) { 143 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 144 if ((data & 0x01) == 0) 145 return 0; 146 } 147 device_printf(sc->dev, "CODEC semaphore timeout\n"); 148 return ETIMEDOUT; 149 } 150 151 static int 152 ich_rdcd(kobj_t obj, void *devinfo, int regno) 153 { 154 struct sc_info *sc = (struct sc_info *)devinfo; 155 156 regno &= 0xff; 157 ich_waitcd(sc); 158 159 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 160 } 161 162 static int 163 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 164 { 165 struct sc_info *sc = (struct sc_info *)devinfo; 166 167 regno &= 0xff; 168 ich_waitcd(sc); 169 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 170 171 return 0; 172 } 173 174 static kobj_method_t ich_ac97_methods[] = { 175 KOBJMETHOD(ac97_read, ich_rdcd), 176 KOBJMETHOD(ac97_write, ich_wrcd), 177 { 0, 0 } 178 }; 179 AC97_DECLARE(ich_ac97); 180 181 /* -------------------------------------------------------------------- */ 182 /* common routines */ 183 184 static void 185 ich_filldtbl(struct sc_chinfo *ch) 186 { 187 u_int32_t base; 188 int i; 189 190 base = vtophys(sndbuf_getbuf(ch->buffer)); 191 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 192 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 193 ch->blkcnt = 2; 194 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 195 } 196 197 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 198 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 199 ch->dtbl[i].length = ICH_BDC_IOC 200 | (ch->blksz / ch->parent->sample_size); 201 } 202 } 203 204 static int 205 ich_resetchan(struct sc_info *sc, int num) 206 { 207 int i, cr, regbase; 208 209 if (num == 0) 210 regbase = ICH_REG_PO_BASE; 211 else if (num == 1) 212 regbase = ICH_REG_PI_BASE; 213 else if (num == 2) 214 regbase = ICH_REG_MC_BASE; 215 else 216 return ENXIO; 217 218 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 219 DELAY(100); 220 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 221 for (i = 0; i < ICH_TIMEOUT; i++) { 222 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 223 if (cr == 0) 224 return 0; 225 } 226 227 device_printf(sc->dev, "cannot reset channel %d\n", num); 228 return ENXIO; 229 } 230 231 /* -------------------------------------------------------------------- */ 232 /* channel interface */ 233 234 static void * 235 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 236 { 237 struct sc_info *sc = devinfo; 238 struct sc_chinfo *ch; 239 unsigned int num; 240 241 num = sc->chnum++; 242 ch = &sc->ch[num]; 243 ch->num = num; 244 ch->buffer = b; 245 ch->channel = c; 246 ch->parent = sc; 247 ch->run = 0; 248 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 249 ch->blkcnt = 2; 250 ch->blksz = sc->bufsz / ch->blkcnt; 251 252 switch(ch->num) { 253 case 0: /* play */ 254 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 255 ch->regbase = ICH_REG_PO_BASE; 256 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 257 ch->imask = ICH_GLOB_STA_POINT; 258 break; 259 260 case 1: /* record */ 261 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 262 ch->regbase = ICH_REG_PI_BASE; 263 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 264 ch->imask = ICH_GLOB_STA_PIINT; 265 break; 266 267 case 2: /* mic */ 268 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 269 ch->regbase = ICH_REG_MC_BASE; 270 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 271 ch->imask = ICH_GLOB_STA_MINT; 272 break; 273 274 default: 275 return NULL; 276 } 277 278 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 279 return NULL; 280 281 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 282 283 return ch; 284 } 285 286 static int 287 ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 288 { 289 return 0; 290 } 291 292 static int 293 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 294 { 295 struct sc_chinfo *ch = data; 296 struct sc_info *sc = ch->parent; 297 298 if (ch->spdreg) { 299 int r; 300 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 301 sc->ac97rate = 48000; 302 r = (speed * 48000) / sc->ac97rate; 303 /* 304 * Cast the return value of ac97_setrate() to u_int so that 305 * the math don't overflow into the negative range. 306 */ 307 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 308 sc->ac97rate) / 48000; 309 } else { 310 ch->spd = 48000; 311 } 312 return ch->spd; 313 } 314 315 static int 316 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 317 { 318 struct sc_chinfo *ch = data; 319 struct sc_info *sc = ch->parent; 320 321 ch->blksz = blocksize; 322 ich_filldtbl(ch); 323 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 324 325 return ch->blksz; 326 } 327 328 static int 329 ichchan_trigger(kobj_t obj, void *data, int go) 330 { 331 struct sc_chinfo *ch = data; 332 struct sc_info *sc = ch->parent; 333 334 switch (go) { 335 case PCMTRIG_START: 336 ch->run = 1; 337 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 338 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 339 break; 340 341 case PCMTRIG_ABORT: 342 ich_resetchan(sc, ch->num); 343 ch->run = 0; 344 break; 345 } 346 return 0; 347 } 348 349 static int 350 ichchan_getptr(kobj_t obj, void *data) 351 { 352 struct sc_chinfo *ch = data; 353 struct sc_info *sc = ch->parent; 354 u_int32_t pos; 355 356 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 357 358 pos = ch->civ * ch->blksz; 359 360 return pos; 361 } 362 363 static struct pcmchan_caps * 364 ichchan_getcaps(kobj_t obj, void *data) 365 { 366 struct sc_chinfo *ch = data; 367 368 return ch->spdreg? &ich_vrcaps : &ich_caps; 369 } 370 371 static kobj_method_t ichchan_methods[] = { 372 KOBJMETHOD(channel_init, ichchan_init), 373 KOBJMETHOD(channel_setformat, ichchan_setformat), 374 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 375 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 376 KOBJMETHOD(channel_trigger, ichchan_trigger), 377 KOBJMETHOD(channel_getptr, ichchan_getptr), 378 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 379 { 0, 0 } 380 }; 381 CHANNEL_DECLARE(ichchan); 382 383 /* -------------------------------------------------------------------- */ 384 /* The interrupt handler */ 385 386 static void 387 ich_intr(void *p) 388 { 389 struct sc_info *sc = (struct sc_info *)p; 390 struct sc_chinfo *ch; 391 u_int32_t cbi, lbi, lvi, st, gs; 392 int i; 393 394 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 395 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 396 /* Clear resume interrupt(s) - nothing doing with them */ 397 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 398 } 399 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 400 401 for (i = 0; i < 3; i++) { 402 ch = &sc->ch[i]; 403 if ((ch->imask & gs) == 0) 404 continue; 405 gs &= ~ch->imask; 406 st = ich_rd(sc, ch->regbase + 407 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 408 2); 409 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 410 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 411 /* block complete - update buffer */ 412 if (ch->run) 413 chn_intr(ch->channel); 414 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 415 cbi = ch->civ % ch->blkcnt; 416 if (cbi == 0) 417 cbi = ch->blkcnt - 1; 418 else 419 cbi--; 420 lbi = lvi % ch->blkcnt; 421 if (cbi >= lbi) 422 lvi += cbi - lbi; 423 else 424 lvi += cbi + ch->blkcnt - lbi; 425 lvi %= ICH_DTBL_LENGTH; 426 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 427 428 } 429 /* clear status bit */ 430 ich_wr(sc, ch->regbase + 431 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 432 st, 2); 433 } 434 if (gs != 0) { 435 device_printf(sc->dev, 436 "Unhandled interrupt, gs_intr = %x\n", gs); 437 } 438 } 439 440 /* ------------------------------------------------------------------------- */ 441 /* Sysctl to control ac97 speed (some boards overclocked ac97). */ 442 443 static int 444 ich_initsys(struct sc_info* sc) 445 { 446 #ifdef SND_DYNSYSCTL 447 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 448 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 449 OID_AUTO, "ac97rate", CTLFLAG_RW, 450 &sc->ac97rate, 48000, 451 "AC97 link rate (default = 48000)"); 452 #endif /* SND_DYNSYSCTL */ 453 return 0; 454 } 455 456 /* -------------------------------------------------------------------- */ 457 /* Calibrate card (some boards are overclocked and need scaling) */ 458 459 static 460 void ich_calibrate(void *arg) 461 { 462 struct sc_info *sc; 463 struct sc_chinfo *ch; 464 struct timeval t1, t2; 465 u_int8_t ociv, nciv; 466 u_int32_t wait_us, actual_48k_rate, bytes; 467 468 sc = (struct sc_info *)arg; 469 ch = &sc->ch[1]; 470 471 if (sc->use_intrhook) 472 config_intrhook_disestablish(&sc->intrhook); 473 474 /* 475 * Grab audio from input for fixed interval and compare how 476 * much we actually get with what we expect. Interval needs 477 * to be sufficiently short that no interrupts are 478 * generated. 479 */ 480 481 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 482 483 bytes = sndbuf_getsize(ch->buffer) / 2; 484 ichchan_setblocksize(0, ch, bytes); 485 486 /* 487 * our data format is stereo, 16 bit so each sample is 4 bytes. 488 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 489 * we're going to start recording with interrupts disabled and measure 490 * the time taken for one block to complete. we know the block size, 491 * we know the time in microseconds, we calculate the sample rate: 492 * 493 * actual_rate [bps] = bytes / (time [s] * 4) 494 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 495 * actual_rate [Hz] = (bytes * 250000) / time [us] 496 */ 497 498 /* prepare */ 499 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 500 nciv = ociv; 501 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 502 503 /* start */ 504 microtime(&t1); 505 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 506 507 /* wait */ 508 while (nciv == ociv) { 509 microtime(&t2); 510 if (t2.tv_sec - t1.tv_sec > 1) 511 break; 512 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 513 } 514 microtime(&t2); 515 516 /* stop */ 517 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 518 519 /* reset */ 520 DELAY(100); 521 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 522 523 /* turn time delta into us */ 524 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 525 526 if (nciv == ociv) { 527 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 528 return; 529 } 530 531 actual_48k_rate = (bytes * 250000) / wait_us; 532 533 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 534 sc->ac97rate = actual_48k_rate; 535 } else { 536 sc->ac97rate = 48000; 537 } 538 539 if (bootverbose || sc->ac97rate != 48000) { 540 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 541 if (sc->ac97rate != actual_48k_rate) 542 printf(", will use %d Hz", sc->ac97rate); 543 printf("\n"); 544 } 545 546 return; 547 } 548 549 /* -------------------------------------------------------------------- */ 550 /* Probe and attach the card */ 551 552 static void 553 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 554 { 555 return; 556 } 557 558 static int 559 ich_init(struct sc_info *sc) 560 { 561 u_int32_t stat; 562 int sz; 563 564 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 565 DELAY(600000); 566 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 567 568 if ((stat & ICH_GLOB_STA_PCR) == 0) 569 return ENXIO; 570 571 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 572 573 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 574 return ENXIO; 575 if (sc->hasmic && ich_resetchan(sc, 2)) 576 return ENXIO; 577 578 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 579 return ENOSPC; 580 581 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 582 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) { 583 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 584 return ENOSPC; 585 } 586 587 return 0; 588 } 589 590 static int 591 ich_pci_probe(device_t dev) 592 { 593 switch(pci_get_devid(dev)) { 594 case 0x71958086: 595 device_set_desc(dev, "Intel 443MX"); 596 return 0; 597 598 case 0x24158086: 599 device_set_desc(dev, "Intel 82801AA (ICH)"); 600 return 0; 601 602 case 0x24258086: 603 device_set_desc(dev, "Intel 82801AB (ICH)"); 604 return 0; 605 606 case 0x24458086: 607 device_set_desc(dev, "Intel 82801BA (ICH2)"); 608 return 0; 609 610 case 0x24858086: 611 device_set_desc(dev, "Intel 82801CA (ICH3)"); 612 return 0; 613 614 case SIS7012ID: 615 device_set_desc(dev, "SiS 7012"); 616 return 0; 617 618 case 0x01b110de: 619 device_set_desc(dev, "Nvidia nForce AC97 controller"); 620 return 0; 621 622 default: 623 return ENXIO; 624 } 625 } 626 627 static int 628 ich_pci_attach(device_t dev) 629 { 630 u_int32_t data; 631 u_int16_t extcaps; 632 struct sc_info *sc; 633 char status[SND_STATUSLEN]; 634 635 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 636 device_printf(dev, "cannot allocate softc\n"); 637 return ENXIO; 638 } 639 640 bzero(sc, sizeof(*sc)); 641 sc->dev = dev; 642 643 /* 644 * The SiS 7012 register set isn't quite like the standard ich. 645 * There really should be a general "quirks" mechanism. 646 */ 647 if (pci_get_devid(dev) == SIS7012ID) { 648 sc->swap_reg = 1; 649 sc->sample_size = 1; 650 } else { 651 sc->swap_reg = 0; 652 sc->sample_size = 2; 653 } 654 655 data = pci_read_config(dev, PCIR_COMMAND, 2); 656 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 657 pci_write_config(dev, PCIR_COMMAND, data, 2); 658 data = pci_read_config(dev, PCIR_COMMAND, 2); 659 660 sc->nambarid = PCIR_NAMBAR; 661 sc->nabmbarid = PCIR_NABMBAR; 662 sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 663 sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 664 665 if (!sc->nambar || !sc->nabmbar) { 666 device_printf(dev, "unable to map IO port space\n"); 667 goto bad; 668 } 669 670 sc->nambart = rman_get_bustag(sc->nambar); 671 sc->nambarh = rman_get_bushandle(sc->nambar); 672 sc->nabmbart = rman_get_bustag(sc->nabmbar); 673 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 674 675 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 676 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 677 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) { 678 device_printf(dev, "unable to create dma tag\n"); 679 goto bad; 680 } 681 682 sc->irqid = 0; 683 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 684 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 685 device_printf(dev, "unable to map interrupt\n"); 686 goto bad; 687 } 688 689 if (ich_init(sc)) { 690 device_printf(dev, "unable to initialize the card\n"); 691 goto bad; 692 } 693 694 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 695 if (sc->codec == NULL) 696 goto bad; 697 mixer_init(dev, ac97_getmixerclass(), sc->codec); 698 699 /* check and set VRA function */ 700 extcaps = ac97_getextcaps(sc->codec); 701 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 702 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 703 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 704 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 705 706 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 707 goto bad; 708 709 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 710 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 711 if (sc->hasmic) 712 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 713 714 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 715 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 716 717 pcm_setstatus(dev, status); 718 719 ich_initsys(sc); 720 721 sc->intrhook.ich_func = ich_calibrate; 722 sc->intrhook.ich_arg = sc; 723 sc->use_intrhook = 1; 724 if (config_intrhook_establish(&sc->intrhook) != 0) { 725 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 726 sc->use_intrhook = 0; 727 ich_calibrate(sc); 728 } 729 730 return 0; 731 732 bad: 733 if (sc->codec) 734 ac97_destroy(sc->codec); 735 if (sc->ih) 736 bus_teardown_intr(dev, sc->irq, sc->ih); 737 if (sc->irq) 738 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 739 if (sc->nambar) 740 bus_release_resource(dev, SYS_RES_IOPORT, 741 sc->nambarid, sc->nambar); 742 if (sc->nabmbar) 743 bus_release_resource(dev, SYS_RES_IOPORT, 744 sc->nabmbarid, sc->nabmbar); 745 free(sc, M_DEVBUF); 746 return ENXIO; 747 } 748 749 static int 750 ich_pci_detach(device_t dev) 751 { 752 struct sc_info *sc; 753 int r; 754 755 r = pcm_unregister(dev); 756 if (r) 757 return r; 758 sc = pcm_getdevinfo(dev); 759 760 bus_teardown_intr(dev, sc->irq, sc->ih); 761 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 762 bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 763 bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 764 bus_dma_tag_destroy(sc->dmat); 765 free(sc, M_DEVBUF); 766 return 0; 767 } 768 769 static int 770 ich_pci_suspend(device_t dev) 771 { 772 struct sc_info *sc; 773 int i; 774 775 sc = pcm_getdevinfo(dev); 776 for (i = 0 ; i < 3; i++) { 777 sc->ch[i].run_save = sc->ch[i].run; 778 if (sc->ch[i].run) { 779 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 780 } 781 } 782 return 0; 783 } 784 785 static int 786 ich_pci_resume(device_t dev) 787 { 788 struct sc_info *sc; 789 int i; 790 791 sc = pcm_getdevinfo(dev); 792 793 /* Reinit audio device */ 794 if (ich_init(sc) == -1) { 795 device_printf(dev, "unable to reinitialize the card\n"); 796 return ENXIO; 797 } 798 /* Reinit mixer */ 799 if (mixer_reinit(dev) == -1) { 800 device_printf(dev, "unable to reinitialize the mixer\n"); 801 return ENXIO; 802 } 803 /* Re-start DMA engines */ 804 for (i = 0 ; i < 3; i++) { 805 struct sc_chinfo *ch = &sc->ch[i]; 806 if (sc->ch[i].run_save) { 807 ichchan_setblocksize(0, ch, ch->blksz); 808 ichchan_setspeed(0, ch, ch->spd); 809 ichchan_trigger(0, ch, PCMTRIG_START); 810 } 811 } 812 return 0; 813 } 814 815 static device_method_t ich_methods[] = { 816 /* Device interface */ 817 DEVMETHOD(device_probe, ich_pci_probe), 818 DEVMETHOD(device_attach, ich_pci_attach), 819 DEVMETHOD(device_detach, ich_pci_detach), 820 DEVMETHOD(device_suspend, ich_pci_suspend), 821 DEVMETHOD(device_resume, ich_pci_resume), 822 { 0, 0 } 823 }; 824 825 static driver_t ich_driver = { 826 "pcm", 827 ich_methods, 828 PCM_SOFTC_SIZE, 829 }; 830 831 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 832 MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 833 MODULE_VERSION(snd_ich, 1); 834