1 /*- 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <dev/sound/pcm/sound.h> 29 #include <dev/sound/pcm/ac97.h> 30 #include <dev/sound/pci/ich.h> 31 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 SND_DECLARE_FILE("$FreeBSD$"); 36 37 /* -------------------------------------------------------------------- */ 38 39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40 #define ICH_DTBL_LENGTH 32 41 #define ICH_DEFAULT_BUFSZ 16384 42 #define ICH_MAX_BUFSZ 65536 43 44 #define INTEL_VENDORID 0x8086 45 #define SIS_VENDORID 0x1039 46 #define NVIDIA_VENDORID 0x10de 47 #define AMD_VENDORID 0x1022 48 49 #define INTEL_82440MX 0x7195 50 #define INTEL_82801AA 0x2415 51 #define INTEL_82801AB 0x2425 52 #define INTEL_82801BA 0x2445 53 #define INTEL_82801CA 0x2485 54 #define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */ 55 #define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */ 56 #define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */ 57 #define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */ 58 #define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */ 59 #define SIS_7012 0x7012 /* SiS 7012 needs special handling */ 60 #define NVIDIA_NFORCE 0x01b1 61 #define NVIDIA_NFORCE2 0x006a 62 #define NVIDIA_NFORCE2_400 0x008a 63 #define NVIDIA_NFORCE3 0x00da 64 #define NVIDIA_NFORCE3_250 0x00ea 65 #define NVIDIA_NFORCE4 0x0059 66 #define NVIDIA_NFORCE_410_MCP 0x026b 67 #define AMD_768 0x7445 68 #define AMD_8111 0x746d 69 70 #define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock) 71 #define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock) 72 #define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) 73 74 static const struct ich_type { 75 uint16_t vendor; 76 uint16_t devid; 77 uint32_t options; 78 #define PROBE_LOW 0x01 79 char *name; 80 } ich_devs[] = { 81 { INTEL_VENDORID, INTEL_82440MX, 0, 82 "Intel 440MX" }, 83 { INTEL_VENDORID, INTEL_82801AA, 0, 84 "Intel ICH (82801AA)" }, 85 { INTEL_VENDORID, INTEL_82801AB, 0, 86 "Intel ICH (82801AB)" }, 87 { INTEL_VENDORID, INTEL_82801BA, 0, 88 "Intel ICH2 (82801BA)" }, 89 { INTEL_VENDORID, INTEL_82801CA, 0, 90 "Intel ICH3 (82801CA)" }, 91 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW, 92 "Intel ICH4 (82801DB)" }, 93 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW, 94 "Intel ICH5 (82801EB)" }, 95 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW, 96 "Intel 6300ESB" }, 97 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW, 98 "Intel ICH6 (82801FB)" }, 99 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW, 100 "Intel ICH7 (82801GB)" }, 101 { SIS_VENDORID, SIS_7012, 0, 102 "SiS 7012" }, 103 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0, 104 "nVidia nForce" }, 105 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0, 106 "nVidia nForce2" }, 107 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0, 108 "nVidia nForce2 400" }, 109 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0, 110 "nVidia nForce3" }, 111 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0, 112 "nVidia nForce3 250" }, 113 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0, 114 "nVidia nForce4" }, 115 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0, 116 "nVidia nForce 410 MCP" }, 117 { AMD_VENDORID, AMD_768, 0, 118 "AMD-768" }, 119 { AMD_VENDORID, AMD_8111, 0, 120 "AMD-8111" } 121 }; 122 123 /* buffer descriptor */ 124 struct ich_desc { 125 volatile u_int32_t buffer; 126 volatile u_int32_t length; 127 }; 128 129 struct sc_info; 130 131 /* channel registers */ 132 struct sc_chinfo { 133 u_int32_t num:8, run:1, run_save:1; 134 u_int32_t blksz, blkcnt, spd; 135 u_int32_t regbase, spdreg; 136 u_int32_t imask; 137 u_int32_t civ; 138 139 struct snd_dbuf *buffer; 140 struct pcm_channel *channel; 141 struct sc_info *parent; 142 143 struct ich_desc *dtbl; 144 bus_addr_t desc_addr; 145 }; 146 147 /* device private data */ 148 struct sc_info { 149 device_t dev; 150 int hasvra, hasvrm, hasmic; 151 unsigned int chnum, bufsz; 152 int sample_size, swap_reg; 153 154 struct resource *nambar, *nabmbar, *irq; 155 int regtype, nambarid, nabmbarid, irqid; 156 bus_space_tag_t nambart, nabmbart; 157 bus_space_handle_t nambarh, nabmbarh; 158 bus_dma_tag_t dmat; 159 bus_dmamap_t dtmap; 160 void *ih; 161 162 struct ac97_info *codec; 163 struct sc_chinfo ch[3]; 164 int ac97rate; 165 struct ich_desc *dtbl; 166 bus_addr_t desc_addr; 167 struct intr_config_hook intrhook; 168 int use_intrhook; 169 uint16_t vendor; 170 uint16_t devid; 171 uint32_t flags; 172 #define IGNORE_PCR 0x01 173 struct mtx *ich_lock; 174 }; 175 176 /* -------------------------------------------------------------------- */ 177 178 static u_int32_t ich_fmt[] = { 179 AFMT_STEREO | AFMT_S16_LE, 180 0 181 }; 182 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 183 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 184 185 /* -------------------------------------------------------------------- */ 186 /* Hardware */ 187 static __inline u_int32_t 188 ich_rd(struct sc_info *sc, int regno, int size) 189 { 190 switch (size) { 191 case 1: 192 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 193 case 2: 194 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 195 case 4: 196 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 197 default: 198 return 0xffffffff; 199 } 200 } 201 202 static __inline void 203 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 204 { 205 switch (size) { 206 case 1: 207 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 208 break; 209 case 2: 210 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 211 break; 212 case 4: 213 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 214 break; 215 } 216 } 217 218 /* ac97 codec */ 219 static int 220 ich_waitcd(void *devinfo) 221 { 222 int i; 223 u_int32_t data; 224 struct sc_info *sc = (struct sc_info *)devinfo; 225 226 for (i = 0; i < ICH_TIMEOUT; i++) { 227 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 228 if ((data & 0x01) == 0) 229 return 0; 230 DELAY(1); 231 } 232 if ((sc->flags & IGNORE_PCR) != 0) 233 return (0); 234 device_printf(sc->dev, "CODEC semaphore timeout\n"); 235 return ETIMEDOUT; 236 } 237 238 static int 239 ich_rdcd(kobj_t obj, void *devinfo, int regno) 240 { 241 struct sc_info *sc = (struct sc_info *)devinfo; 242 243 regno &= 0xff; 244 ich_waitcd(sc); 245 246 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 247 } 248 249 static int 250 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 251 { 252 struct sc_info *sc = (struct sc_info *)devinfo; 253 254 regno &= 0xff; 255 ich_waitcd(sc); 256 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 257 258 return 0; 259 } 260 261 static kobj_method_t ich_ac97_methods[] = { 262 KOBJMETHOD(ac97_read, ich_rdcd), 263 KOBJMETHOD(ac97_write, ich_wrcd), 264 { 0, 0 } 265 }; 266 AC97_DECLARE(ich_ac97); 267 268 /* -------------------------------------------------------------------- */ 269 /* common routines */ 270 271 static void 272 ich_filldtbl(struct sc_chinfo *ch) 273 { 274 struct sc_info *sc = ch->parent; 275 u_int32_t base; 276 int i; 277 278 base = sndbuf_getbufaddr(ch->buffer); 279 if (ch->blksz > sc->bufsz / ch->blkcnt) 280 ch->blksz = sc->bufsz / ch->blkcnt; 281 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz); 282 ch->blksz = sndbuf_getblksz(ch->buffer); 283 284 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 285 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 286 ch->dtbl[i].length = ICH_BDC_IOC 287 | (ch->blksz / ch->parent->sample_size); 288 } 289 } 290 291 static int 292 ich_resetchan(struct sc_info *sc, int num) 293 { 294 int i, cr, regbase; 295 296 if (num == 0) 297 regbase = ICH_REG_PO_BASE; 298 else if (num == 1) 299 regbase = ICH_REG_PI_BASE; 300 else if (num == 2) 301 regbase = ICH_REG_MC_BASE; 302 else 303 return ENXIO; 304 305 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 306 #if 1 307 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 308 DELAY(100); 309 #else 310 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 311 #endif 312 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 313 for (i = 0; i < ICH_TIMEOUT; i++) { 314 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 315 if (cr == 0) 316 return 0; 317 } 318 319 device_printf(sc->dev, "cannot reset channel %d\n", num); 320 return ENXIO; 321 } 322 323 /* -------------------------------------------------------------------- */ 324 /* channel interface */ 325 326 static void * 327 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 328 { 329 struct sc_info *sc = devinfo; 330 struct sc_chinfo *ch; 331 unsigned int num; 332 333 ICH_LOCK(sc); 334 num = sc->chnum++; 335 ch = &sc->ch[num]; 336 ch->num = num; 337 ch->buffer = b; 338 ch->channel = c; 339 ch->parent = sc; 340 ch->run = 0; 341 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 342 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 343 sizeof(struct ich_desc); 344 ch->blkcnt = 2; 345 ch->blksz = sc->bufsz / ch->blkcnt; 346 347 switch(ch->num) { 348 case 0: /* play */ 349 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 350 ch->regbase = ICH_REG_PO_BASE; 351 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 352 ch->imask = ICH_GLOB_STA_POINT; 353 break; 354 355 case 1: /* record */ 356 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 357 ch->regbase = ICH_REG_PI_BASE; 358 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 359 ch->imask = ICH_GLOB_STA_PIINT; 360 break; 361 362 case 2: /* mic */ 363 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 364 ch->regbase = ICH_REG_MC_BASE; 365 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 366 ch->imask = ICH_GLOB_STA_MINT; 367 break; 368 369 default: 370 return NULL; 371 } 372 373 ICH_UNLOCK(sc); 374 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0) 375 return NULL; 376 377 ICH_LOCK(sc); 378 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 379 ICH_UNLOCK(sc); 380 381 return ch; 382 } 383 384 static int 385 ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 386 { 387 return 0; 388 } 389 390 static int 391 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 392 { 393 struct sc_chinfo *ch = data; 394 struct sc_info *sc = ch->parent; 395 396 if (ch->spdreg) { 397 int r, ac97rate; 398 399 ICH_LOCK(sc); 400 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 401 sc->ac97rate = 48000; 402 ac97rate = sc->ac97rate; 403 ICH_UNLOCK(sc); 404 r = (speed * 48000) / ac97rate; 405 /* 406 * Cast the return value of ac97_setrate() to u_int so that 407 * the math don't overflow into the negative range. 408 */ 409 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 410 ac97rate) / 48000; 411 } else { 412 ch->spd = 48000; 413 } 414 return ch->spd; 415 } 416 417 static int 418 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 419 { 420 struct sc_chinfo *ch = data; 421 struct sc_info *sc = ch->parent; 422 423 ch->blksz = blocksize; 424 ich_filldtbl(ch); 425 ICH_LOCK(sc); 426 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 427 ICH_UNLOCK(sc); 428 429 return ch->blksz; 430 } 431 432 static int 433 ichchan_trigger(kobj_t obj, void *data, int go) 434 { 435 struct sc_chinfo *ch = data; 436 struct sc_info *sc = ch->parent; 437 438 switch (go) { 439 case PCMTRIG_START: 440 ch->run = 1; 441 ICH_LOCK(sc); 442 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 443 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 444 ICH_UNLOCK(sc); 445 break; 446 447 case PCMTRIG_ABORT: 448 ICH_LOCK(sc); 449 ich_resetchan(sc, ch->num); 450 ICH_UNLOCK(sc); 451 ch->run = 0; 452 break; 453 } 454 return 0; 455 } 456 457 static int 458 ichchan_getptr(kobj_t obj, void *data) 459 { 460 struct sc_chinfo *ch = data; 461 struct sc_info *sc = ch->parent; 462 u_int32_t pos; 463 464 ICH_LOCK(sc); 465 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 466 ICH_UNLOCK(sc); 467 468 pos = ch->civ * ch->blksz; 469 470 return pos; 471 } 472 473 static struct pcmchan_caps * 474 ichchan_getcaps(kobj_t obj, void *data) 475 { 476 struct sc_chinfo *ch = data; 477 478 return ch->spdreg? &ich_vrcaps : &ich_caps; 479 } 480 481 static kobj_method_t ichchan_methods[] = { 482 KOBJMETHOD(channel_init, ichchan_init), 483 KOBJMETHOD(channel_setformat, ichchan_setformat), 484 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 485 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 486 KOBJMETHOD(channel_trigger, ichchan_trigger), 487 KOBJMETHOD(channel_getptr, ichchan_getptr), 488 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 489 { 0, 0 } 490 }; 491 CHANNEL_DECLARE(ichchan); 492 493 /* -------------------------------------------------------------------- */ 494 /* The interrupt handler */ 495 496 static void 497 ich_intr(void *p) 498 { 499 struct sc_info *sc = (struct sc_info *)p; 500 struct sc_chinfo *ch; 501 u_int32_t cbi, lbi, lvi, st, gs; 502 int i; 503 504 ICH_LOCK(sc); 505 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 506 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 507 /* Clear resume interrupt(s) - nothing doing with them */ 508 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 509 } 510 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 511 512 for (i = 0; i < 3; i++) { 513 ch = &sc->ch[i]; 514 if ((ch->imask & gs) == 0) 515 continue; 516 gs &= ~ch->imask; 517 st = ich_rd(sc, ch->regbase + 518 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 519 2); 520 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 521 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 522 /* block complete - update buffer */ 523 if (ch->run) { 524 ICH_UNLOCK(sc); 525 chn_intr(ch->channel); 526 ICH_LOCK(sc); 527 } 528 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 529 cbi = ch->civ % ch->blkcnt; 530 if (cbi == 0) 531 cbi = ch->blkcnt - 1; 532 else 533 cbi--; 534 lbi = lvi % ch->blkcnt; 535 if (cbi >= lbi) 536 lvi += cbi - lbi; 537 else 538 lvi += cbi + ch->blkcnt - lbi; 539 lvi %= ICH_DTBL_LENGTH; 540 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 541 542 } 543 /* clear status bit */ 544 ich_wr(sc, ch->regbase + 545 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 546 st, 2); 547 } 548 ICH_UNLOCK(sc); 549 if (gs != 0) { 550 device_printf(sc->dev, 551 "Unhandled interrupt, gs_intr = %x\n", gs); 552 } 553 } 554 555 /* ------------------------------------------------------------------------- */ 556 /* Sysctl to control ac97 speed (some boards appear to end up using 557 * XTAL_IN rather than BIT_CLK for link timing). 558 */ 559 560 static int 561 ich_initsys(struct sc_info* sc) 562 { 563 #ifdef SND_DYNSYSCTL 564 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 565 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 566 OID_AUTO, "ac97rate", CTLFLAG_RW, 567 &sc->ac97rate, 48000, 568 "AC97 link rate (default = 48000)"); 569 #endif /* SND_DYNSYSCTL */ 570 return 0; 571 } 572 573 /* -------------------------------------------------------------------- */ 574 /* Calibrate card to determine the clock source. The source maybe a 575 * function of the ac97 codec initialization code (to be investigated). 576 */ 577 578 static 579 void ich_calibrate(void *arg) 580 { 581 struct sc_info *sc; 582 struct sc_chinfo *ch; 583 struct timeval t1, t2; 584 u_int8_t ociv, nciv; 585 u_int32_t wait_us, actual_48k_rate, bytes; 586 587 sc = (struct sc_info *)arg; 588 ch = &sc->ch[1]; 589 590 if (sc->use_intrhook) 591 config_intrhook_disestablish(&sc->intrhook); 592 593 /* 594 * Grab audio from input for fixed interval and compare how 595 * much we actually get with what we expect. Interval needs 596 * to be sufficiently short that no interrupts are 597 * generated. 598 */ 599 600 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 601 602 bytes = sndbuf_getsize(ch->buffer) / 2; 603 ichchan_setblocksize(0, ch, bytes); 604 605 /* 606 * our data format is stereo, 16 bit so each sample is 4 bytes. 607 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 608 * we're going to start recording with interrupts disabled and measure 609 * the time taken for one block to complete. we know the block size, 610 * we know the time in microseconds, we calculate the sample rate: 611 * 612 * actual_rate [bps] = bytes / (time [s] * 4) 613 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 614 * actual_rate [Hz] = (bytes * 250000) / time [us] 615 */ 616 617 /* prepare */ 618 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 619 nciv = ociv; 620 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 621 622 /* start */ 623 microtime(&t1); 624 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 625 626 /* wait */ 627 while (nciv == ociv) { 628 microtime(&t2); 629 if (t2.tv_sec - t1.tv_sec > 1) 630 break; 631 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 632 } 633 microtime(&t2); 634 635 /* stop */ 636 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 637 638 /* reset */ 639 DELAY(100); 640 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 641 642 /* turn time delta into us */ 643 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 644 645 if (nciv == ociv) { 646 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 647 return; 648 } 649 650 actual_48k_rate = (bytes * 250000) / wait_us; 651 652 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 653 sc->ac97rate = actual_48k_rate; 654 } else { 655 sc->ac97rate = 48000; 656 } 657 658 if (bootverbose || sc->ac97rate != 48000) { 659 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 660 if (sc->ac97rate != actual_48k_rate) 661 printf(", will use %d Hz", sc->ac97rate); 662 printf("\n"); 663 } 664 665 return; 666 } 667 668 /* -------------------------------------------------------------------- */ 669 /* Probe and attach the card */ 670 671 static void 672 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 673 { 674 struct sc_info *sc = (struct sc_info *)arg; 675 sc->desc_addr = segs->ds_addr; 676 return; 677 } 678 679 static int 680 ich_init(struct sc_info *sc) 681 { 682 u_int32_t stat; 683 684 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 685 DELAY(600000); 686 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 687 688 if ((stat & ICH_GLOB_STA_PCR) == 0) { 689 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 690 if (sc->vendor == INTEL_VENDORID && ( 691 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB || 692 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB || 693 sc->devid == INTEL_82801GB)) { 694 sc->flags |= IGNORE_PCR; 695 device_printf(sc->dev, "primary codec not ready!\n"); 696 } 697 } 698 699 #if 0 700 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 701 #else 702 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 703 #endif 704 705 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 706 return ENXIO; 707 if (sc->hasmic && ich_resetchan(sc, 2)) 708 return ENXIO; 709 710 return 0; 711 } 712 713 static int 714 ich_pci_probe(device_t dev) 715 { 716 int i; 717 uint16_t devid, vendor; 718 719 vendor = pci_get_vendor(dev); 720 devid = pci_get_device(dev); 721 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) { 722 if (vendor == ich_devs[i].vendor && 723 devid == ich_devs[i].devid) { 724 device_set_desc(dev, ich_devs[i].name); 725 /* allow a better driver to override us */ 726 if ((ich_devs[i].options & PROBE_LOW) != 0) 727 return (BUS_PROBE_LOW_PRIORITY); 728 return (BUS_PROBE_DEFAULT); 729 } 730 } 731 return (ENXIO); 732 } 733 734 static int 735 ich_pci_attach(device_t dev) 736 { 737 uint32_t subdev; 738 u_int16_t extcaps; 739 uint16_t devid, vendor; 740 struct sc_info *sc; 741 char status[SND_STATUSLEN]; 742 743 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 744 device_printf(dev, "cannot allocate softc\n"); 745 return ENXIO; 746 } 747 748 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 749 sc->dev = dev; 750 751 vendor = sc->vendor = pci_get_vendor(dev); 752 devid = sc->devid = pci_get_device(dev); 753 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev); 754 /* 755 * The SiS 7012 register set isn't quite like the standard ich. 756 * There really should be a general "quirks" mechanism. 757 */ 758 if (vendor == SIS_VENDORID && devid == SIS_7012) { 759 sc->swap_reg = 1; 760 sc->sample_size = 1; 761 } else { 762 sc->swap_reg = 0; 763 sc->sample_size = 2; 764 } 765 766 /* 767 * Enable bus master. On ich4/5 this may prevent the detection of 768 * the primary codec becoming ready in ich_init(). 769 */ 770 pci_enable_busmaster(dev); 771 772 /* 773 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 774 * read-only. Need to enable "legacy support", by poking into 775 * pci config space. The driver should use MMBAR and MBBAR, 776 * but doing so will mess things up here. ich4 has enough new 777 * features it warrants it's own driver. 778 */ 779 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB || 780 devid == INTEL_82801EB || devid == INTEL_6300ESB || 781 devid == INTEL_82801FB || devid == INTEL_82801GB)) { 782 sc->nambarid = PCIR_MMBAR; 783 sc->nabmbarid = PCIR_MBBAR; 784 sc->regtype = SYS_RES_MEMORY; 785 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 786 } else { 787 sc->nambarid = PCIR_NAMBAR; 788 sc->nabmbarid = PCIR_NABMBAR; 789 sc->regtype = SYS_RES_IOPORT; 790 } 791 792 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 793 &sc->nambarid, RF_ACTIVE); 794 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 795 &sc->nabmbarid, RF_ACTIVE); 796 797 if (!sc->nambar || !sc->nabmbar) { 798 device_printf(dev, "unable to map IO port space\n"); 799 goto bad; 800 } 801 802 sc->nambart = rman_get_bustag(sc->nambar); 803 sc->nambarh = rman_get_bushandle(sc->nambar); 804 sc->nabmbart = rman_get_bustag(sc->nabmbar); 805 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 806 807 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 808 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 809 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 810 NULL, NULL, &sc->dmat) != 0) { 811 device_printf(dev, "unable to create dma tag\n"); 812 goto bad; 813 } 814 815 sc->irqid = 0; 816 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 817 RF_ACTIVE | RF_SHAREABLE); 818 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 819 device_printf(dev, "unable to map interrupt\n"); 820 goto bad; 821 } 822 823 if (ich_init(sc)) { 824 device_printf(dev, "unable to initialize the card\n"); 825 goto bad; 826 } 827 828 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, 829 BUS_DMA_NOWAIT, &sc->dtmap)) 830 goto bad; 831 832 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, 833 sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3, 834 ich_setmap, sc, 0)) 835 goto bad; 836 837 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 838 if (sc->codec == NULL) 839 goto bad; 840 841 /* 842 * Turn on inverted external amplifier sense flags for few 843 * 'special' boards. 844 */ 845 switch (subdev) { 846 case 0x202f161f: /* Gateway 7326GZ */ 847 case 0x203a161f: /* Gateway 4028GZ */ 848 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 849 case 0x8144104d: /* Sony VAIO PCG-TR* */ 850 case 0x8197104d: /* Sony S1XP */ 851 case 0x81c0104d: /* Sony VAIO type T */ 852 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */ 853 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV); 854 break; 855 default: 856 break; 857 } 858 859 mixer_init(dev, ac97_getmixerclass(), sc->codec); 860 861 /* check and set VRA function */ 862 extcaps = ac97_getextcaps(sc->codec); 863 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 864 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 865 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 866 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 867 868 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 869 goto bad; 870 871 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 872 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 873 if (sc->hasmic) 874 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 875 876 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 877 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 878 879 pcm_setstatus(dev, status); 880 881 ich_initsys(sc); 882 883 sc->intrhook.ich_func = ich_calibrate; 884 sc->intrhook.ich_arg = sc; 885 sc->use_intrhook = 1; 886 if (config_intrhook_establish(&sc->intrhook) != 0) { 887 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 888 sc->use_intrhook = 0; 889 ich_calibrate(sc); 890 } 891 892 return 0; 893 894 bad: 895 if (sc->codec) 896 ac97_destroy(sc->codec); 897 if (sc->ih) 898 bus_teardown_intr(dev, sc->irq, sc->ih); 899 if (sc->irq) 900 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 901 if (sc->nambar) 902 bus_release_resource(dev, sc->regtype, 903 sc->nambarid, sc->nambar); 904 if (sc->nabmbar) 905 bus_release_resource(dev, sc->regtype, 906 sc->nabmbarid, sc->nabmbar); 907 if (sc->dtmap) 908 bus_dmamap_unload(sc->dmat, sc->dtmap); 909 if (sc->dmat) 910 bus_dma_tag_destroy(sc->dmat); 911 if (sc->ich_lock) 912 snd_mtxfree(sc->ich_lock); 913 free(sc, M_DEVBUF); 914 return ENXIO; 915 } 916 917 static int 918 ich_pci_detach(device_t dev) 919 { 920 struct sc_info *sc; 921 int r; 922 923 r = pcm_unregister(dev); 924 if (r) 925 return r; 926 sc = pcm_getdevinfo(dev); 927 928 bus_teardown_intr(dev, sc->irq, sc->ih); 929 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 930 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 931 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 932 bus_dmamap_unload(sc->dmat, sc->dtmap); 933 bus_dma_tag_destroy(sc->dmat); 934 snd_mtxfree(sc->ich_lock); 935 free(sc, M_DEVBUF); 936 return 0; 937 } 938 939 static void 940 ich_pci_codec_reset(struct sc_info *sc) 941 { 942 int i; 943 uint32_t control; 944 945 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 946 control &= ~(ICH_GLOB_CTL_SHUT); 947 control |= (control & ICH_GLOB_CTL_COLD) ? 948 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 949 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 950 951 for (i = 500000; i; i--) { 952 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 953 break; /* or ICH_SCR? */ 954 DELAY(1); 955 } 956 957 if (i <= 0) 958 printf("%s: time out\n", __func__); 959 } 960 961 static int 962 ich_pci_suspend(device_t dev) 963 { 964 struct sc_info *sc; 965 int i; 966 967 sc = pcm_getdevinfo(dev); 968 ICH_LOCK(sc); 969 for (i = 0 ; i < 3; i++) { 970 sc->ch[i].run_save = sc->ch[i].run; 971 if (sc->ch[i].run) { 972 ICH_UNLOCK(sc); 973 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 974 ICH_LOCK(sc); 975 } 976 } 977 ICH_UNLOCK(sc); 978 return 0; 979 } 980 981 static int 982 ich_pci_resume(device_t dev) 983 { 984 struct sc_info *sc; 985 int i; 986 987 sc = pcm_getdevinfo(dev); 988 989 if (sc->regtype == SYS_RES_IOPORT) 990 pci_enable_io(dev, SYS_RES_IOPORT); 991 else 992 pci_enable_io(dev, SYS_RES_MEMORY); 993 pci_enable_busmaster(dev); 994 995 ICH_LOCK(sc); 996 /* Reinit audio device */ 997 if (ich_init(sc) == -1) { 998 device_printf(dev, "unable to reinitialize the card\n"); 999 ICH_UNLOCK(sc); 1000 return ENXIO; 1001 } 1002 /* Reinit mixer */ 1003 ich_pci_codec_reset(sc); 1004 ICH_UNLOCK(sc); 1005 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1006 if (mixer_reinit(dev) == -1) { 1007 device_printf(dev, "unable to reinitialize the mixer\n"); 1008 return ENXIO; 1009 } 1010 /* Re-start DMA engines */ 1011 for (i = 0 ; i < 3; i++) { 1012 struct sc_chinfo *ch = &sc->ch[i]; 1013 if (sc->ch[i].run_save) { 1014 ichchan_setblocksize(0, ch, ch->blksz); 1015 ichchan_setspeed(0, ch, ch->spd); 1016 ichchan_trigger(0, ch, PCMTRIG_START); 1017 } 1018 } 1019 return 0; 1020 } 1021 1022 static device_method_t ich_methods[] = { 1023 /* Device interface */ 1024 DEVMETHOD(device_probe, ich_pci_probe), 1025 DEVMETHOD(device_attach, ich_pci_attach), 1026 DEVMETHOD(device_detach, ich_pci_detach), 1027 DEVMETHOD(device_suspend, ich_pci_suspend), 1028 DEVMETHOD(device_resume, ich_pci_resume), 1029 { 0, 0 } 1030 }; 1031 1032 static driver_t ich_driver = { 1033 "pcm", 1034 ich_methods, 1035 PCM_SOFTC_SIZE, 1036 }; 1037 1038 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 1039 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1040 MODULE_VERSION(snd_ich, 1); 1041