1 /* 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <dev/sound/pcm/sound.h> 29 #include <dev/sound/pcm/ac97.h> 30 #include <dev/sound/pci/ich.h> 31 32 #include <pci/pcireg.h> 33 #include <pci/pcivar.h> 34 35 SND_DECLARE_FILE("$FreeBSD$"); 36 37 /* -------------------------------------------------------------------- */ 38 39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40 #define ICH_DTBL_LENGTH 32 41 #define ICH_DEFAULT_BUFSZ 16384 42 #define ICH_MAX_BUFSZ 65536 43 44 #define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45 #define ICH4ID 0x24c58086 /* ICH4 needs special handling too */ 46 47 /* buffer descriptor */ 48 struct ich_desc { 49 volatile u_int32_t buffer; 50 volatile u_int32_t length; 51 }; 52 53 struct sc_info; 54 55 /* channel registers */ 56 struct sc_chinfo { 57 u_int32_t num:8, run:1, run_save:1; 58 u_int32_t blksz, blkcnt, spd; 59 u_int32_t regbase, spdreg; 60 u_int32_t imask; 61 u_int32_t civ; 62 63 struct snd_dbuf *buffer; 64 struct pcm_channel *channel; 65 struct sc_info *parent; 66 67 struct ich_desc *dtbl; 68 bus_addr_t desc_addr; 69 }; 70 71 /* device private data */ 72 struct sc_info { 73 device_t dev; 74 int hasvra, hasvrm, hasmic; 75 unsigned int chnum, bufsz; 76 int sample_size, swap_reg; 77 78 struct resource *nambar, *nabmbar, *irq; 79 int nambarid, nabmbarid, irqid; 80 bus_space_tag_t nambart, nabmbart; 81 bus_space_handle_t nambarh, nabmbarh; 82 bus_dma_tag_t dmat; 83 bus_dmamap_t dtmap; 84 void *ih; 85 86 struct ac97_info *codec; 87 struct sc_chinfo ch[3]; 88 int ac97rate; 89 struct ich_desc *dtbl; 90 bus_addr_t desc_addr; 91 struct intr_config_hook intrhook; 92 int use_intrhook; 93 }; 94 95 /* -------------------------------------------------------------------- */ 96 97 static u_int32_t ich_fmt[] = { 98 AFMT_STEREO | AFMT_S16_LE, 99 0 100 }; 101 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 102 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 103 104 /* -------------------------------------------------------------------- */ 105 /* Hardware */ 106 static u_int32_t 107 ich_rd(struct sc_info *sc, int regno, int size) 108 { 109 switch (size) { 110 case 1: 111 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 112 case 2: 113 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 114 case 4: 115 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 116 default: 117 return 0xffffffff; 118 } 119 } 120 121 static void 122 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 123 { 124 switch (size) { 125 case 1: 126 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 127 break; 128 case 2: 129 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 130 break; 131 case 4: 132 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 133 break; 134 } 135 } 136 137 /* ac97 codec */ 138 static int 139 ich_waitcd(void *devinfo) 140 { 141 int i; 142 u_int32_t data; 143 struct sc_info *sc = (struct sc_info *)devinfo; 144 145 for (i = 0; i < ICH_TIMEOUT; i++) { 146 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 147 if ((data & 0x01) == 0) 148 return 0; 149 } 150 device_printf(sc->dev, "CODEC semaphore timeout\n"); 151 return ETIMEDOUT; 152 } 153 154 static int 155 ich_rdcd(kobj_t obj, void *devinfo, int regno) 156 { 157 struct sc_info *sc = (struct sc_info *)devinfo; 158 159 regno &= 0xff; 160 ich_waitcd(sc); 161 162 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 163 } 164 165 static int 166 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 167 { 168 struct sc_info *sc = (struct sc_info *)devinfo; 169 170 regno &= 0xff; 171 ich_waitcd(sc); 172 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 173 174 return 0; 175 } 176 177 static kobj_method_t ich_ac97_methods[] = { 178 KOBJMETHOD(ac97_read, ich_rdcd), 179 KOBJMETHOD(ac97_write, ich_wrcd), 180 { 0, 0 } 181 }; 182 AC97_DECLARE(ich_ac97); 183 184 /* -------------------------------------------------------------------- */ 185 /* common routines */ 186 187 static void 188 ich_filldtbl(struct sc_chinfo *ch) 189 { 190 u_int32_t base; 191 int i; 192 193 base = sndbuf_getbufaddr(ch->buffer); 194 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 195 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 196 ch->blkcnt = 2; 197 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 198 } 199 200 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 201 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 202 ch->dtbl[i].length = ICH_BDC_IOC 203 | (ch->blksz / ch->parent->sample_size); 204 } 205 } 206 207 static int 208 ich_resetchan(struct sc_info *sc, int num) 209 { 210 int i, cr, regbase; 211 212 if (num == 0) 213 regbase = ICH_REG_PO_BASE; 214 else if (num == 1) 215 regbase = ICH_REG_PI_BASE; 216 else if (num == 2) 217 regbase = ICH_REG_MC_BASE; 218 else 219 return ENXIO; 220 221 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 222 DELAY(100); 223 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 224 for (i = 0; i < ICH_TIMEOUT; i++) { 225 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 226 if (cr == 0) 227 return 0; 228 } 229 230 device_printf(sc->dev, "cannot reset channel %d\n", num); 231 return ENXIO; 232 } 233 234 /* -------------------------------------------------------------------- */ 235 /* channel interface */ 236 237 static void * 238 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 239 { 240 struct sc_info *sc = devinfo; 241 struct sc_chinfo *ch; 242 unsigned int num; 243 244 num = sc->chnum++; 245 ch = &sc->ch[num]; 246 ch->num = num; 247 ch->buffer = b; 248 ch->channel = c; 249 ch->parent = sc; 250 ch->run = 0; 251 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 252 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 253 sizeof(struct ich_desc); 254 ch->blkcnt = 2; 255 ch->blksz = sc->bufsz / ch->blkcnt; 256 257 switch(ch->num) { 258 case 0: /* play */ 259 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 260 ch->regbase = ICH_REG_PO_BASE; 261 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 262 ch->imask = ICH_GLOB_STA_POINT; 263 break; 264 265 case 1: /* record */ 266 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 267 ch->regbase = ICH_REG_PI_BASE; 268 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 269 ch->imask = ICH_GLOB_STA_PIINT; 270 break; 271 272 case 2: /* mic */ 273 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 274 ch->regbase = ICH_REG_MC_BASE; 275 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 276 ch->imask = ICH_GLOB_STA_MINT; 277 break; 278 279 default: 280 return NULL; 281 } 282 283 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 284 return NULL; 285 286 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 287 288 return ch; 289 } 290 291 static int 292 ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 293 { 294 return 0; 295 } 296 297 static int 298 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 299 { 300 struct sc_chinfo *ch = data; 301 struct sc_info *sc = ch->parent; 302 303 if (ch->spdreg) { 304 int r; 305 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 306 sc->ac97rate = 48000; 307 r = (speed * 48000) / sc->ac97rate; 308 /* 309 * Cast the return value of ac97_setrate() to u_int so that 310 * the math don't overflow into the negative range. 311 */ 312 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 313 sc->ac97rate) / 48000; 314 } else { 315 ch->spd = 48000; 316 } 317 return ch->spd; 318 } 319 320 static int 321 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 322 { 323 struct sc_chinfo *ch = data; 324 struct sc_info *sc = ch->parent; 325 326 ch->blksz = blocksize; 327 ich_filldtbl(ch); 328 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 329 330 return ch->blksz; 331 } 332 333 static int 334 ichchan_trigger(kobj_t obj, void *data, int go) 335 { 336 struct sc_chinfo *ch = data; 337 struct sc_info *sc = ch->parent; 338 339 switch (go) { 340 case PCMTRIG_START: 341 ch->run = 1; 342 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 343 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 344 break; 345 346 case PCMTRIG_ABORT: 347 ich_resetchan(sc, ch->num); 348 ch->run = 0; 349 break; 350 } 351 return 0; 352 } 353 354 static int 355 ichchan_getptr(kobj_t obj, void *data) 356 { 357 struct sc_chinfo *ch = data; 358 struct sc_info *sc = ch->parent; 359 u_int32_t pos; 360 361 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 362 363 pos = ch->civ * ch->blksz; 364 365 return pos; 366 } 367 368 static struct pcmchan_caps * 369 ichchan_getcaps(kobj_t obj, void *data) 370 { 371 struct sc_chinfo *ch = data; 372 373 return ch->spdreg? &ich_vrcaps : &ich_caps; 374 } 375 376 static kobj_method_t ichchan_methods[] = { 377 KOBJMETHOD(channel_init, ichchan_init), 378 KOBJMETHOD(channel_setformat, ichchan_setformat), 379 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 380 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 381 KOBJMETHOD(channel_trigger, ichchan_trigger), 382 KOBJMETHOD(channel_getptr, ichchan_getptr), 383 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 384 { 0, 0 } 385 }; 386 CHANNEL_DECLARE(ichchan); 387 388 /* -------------------------------------------------------------------- */ 389 /* The interrupt handler */ 390 391 static void 392 ich_intr(void *p) 393 { 394 struct sc_info *sc = (struct sc_info *)p; 395 struct sc_chinfo *ch; 396 u_int32_t cbi, lbi, lvi, st, gs; 397 int i; 398 399 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 400 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 401 /* Clear resume interrupt(s) - nothing doing with them */ 402 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 403 } 404 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 405 406 for (i = 0; i < 3; i++) { 407 ch = &sc->ch[i]; 408 if ((ch->imask & gs) == 0) 409 continue; 410 gs &= ~ch->imask; 411 st = ich_rd(sc, ch->regbase + 412 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 413 2); 414 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 415 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 416 /* block complete - update buffer */ 417 if (ch->run) 418 chn_intr(ch->channel); 419 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 420 cbi = ch->civ % ch->blkcnt; 421 if (cbi == 0) 422 cbi = ch->blkcnt - 1; 423 else 424 cbi--; 425 lbi = lvi % ch->blkcnt; 426 if (cbi >= lbi) 427 lvi += cbi - lbi; 428 else 429 lvi += cbi + ch->blkcnt - lbi; 430 lvi %= ICH_DTBL_LENGTH; 431 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 432 433 } 434 /* clear status bit */ 435 ich_wr(sc, ch->regbase + 436 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 437 st, 2); 438 } 439 if (gs != 0) { 440 device_printf(sc->dev, 441 "Unhandled interrupt, gs_intr = %x\n", gs); 442 } 443 } 444 445 /* ------------------------------------------------------------------------- */ 446 /* Sysctl to control ac97 speed (some boards appear to end up using 447 * XTAL_IN rather than BIT_CLK for link timing). 448 */ 449 450 static int 451 ich_initsys(struct sc_info* sc) 452 { 453 #ifdef SND_DYNSYSCTL 454 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 455 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 456 OID_AUTO, "ac97rate", CTLFLAG_RW, 457 &sc->ac97rate, 48000, 458 "AC97 link rate (default = 48000)"); 459 #endif /* SND_DYNSYSCTL */ 460 return 0; 461 } 462 463 /* -------------------------------------------------------------------- */ 464 /* Calibrate card to determine the clock source. The source maybe a 465 * function of the ac97 codec initialization code (to be investigated). 466 */ 467 468 static 469 void ich_calibrate(void *arg) 470 { 471 struct sc_info *sc; 472 struct sc_chinfo *ch; 473 struct timeval t1, t2; 474 u_int8_t ociv, nciv; 475 u_int32_t wait_us, actual_48k_rate, bytes; 476 477 sc = (struct sc_info *)arg; 478 ch = &sc->ch[1]; 479 480 if (sc->use_intrhook) 481 config_intrhook_disestablish(&sc->intrhook); 482 483 /* 484 * Grab audio from input for fixed interval and compare how 485 * much we actually get with what we expect. Interval needs 486 * to be sufficiently short that no interrupts are 487 * generated. 488 */ 489 490 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 491 492 bytes = sndbuf_getsize(ch->buffer) / 2; 493 ichchan_setblocksize(0, ch, bytes); 494 495 /* 496 * our data format is stereo, 16 bit so each sample is 4 bytes. 497 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 498 * we're going to start recording with interrupts disabled and measure 499 * the time taken for one block to complete. we know the block size, 500 * we know the time in microseconds, we calculate the sample rate: 501 * 502 * actual_rate [bps] = bytes / (time [s] * 4) 503 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 504 * actual_rate [Hz] = (bytes * 250000) / time [us] 505 */ 506 507 /* prepare */ 508 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 509 nciv = ociv; 510 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 511 512 /* start */ 513 microtime(&t1); 514 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 515 516 /* wait */ 517 while (nciv == ociv) { 518 microtime(&t2); 519 if (t2.tv_sec - t1.tv_sec > 1) 520 break; 521 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 522 } 523 microtime(&t2); 524 525 /* stop */ 526 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 527 528 /* reset */ 529 DELAY(100); 530 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 531 532 /* turn time delta into us */ 533 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 534 535 if (nciv == ociv) { 536 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 537 return; 538 } 539 540 actual_48k_rate = (bytes * 250000) / wait_us; 541 542 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 543 sc->ac97rate = actual_48k_rate; 544 } else { 545 sc->ac97rate = 48000; 546 } 547 548 if (bootverbose || sc->ac97rate != 48000) { 549 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 550 if (sc->ac97rate != actual_48k_rate) 551 printf(", will use %d Hz", sc->ac97rate); 552 printf("\n"); 553 } 554 555 return; 556 } 557 558 /* -------------------------------------------------------------------- */ 559 /* Probe and attach the card */ 560 561 static void 562 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 563 { 564 struct sc_info *sc = (struct sc_info *)arg; 565 sc->desc_addr = segs->ds_addr; 566 return; 567 } 568 569 static int 570 ich_init(struct sc_info *sc) 571 { 572 u_int32_t stat; 573 int sz; 574 575 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 576 DELAY(600000); 577 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 578 579 if ((stat & ICH_GLOB_STA_PCR) == 0) { 580 /* ICH4 may fail when busmastering is enabled. Continue */ 581 if (pci_get_devid(sc->dev) != ICH4ID) { 582 return ENXIO; 583 } 584 } 585 586 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 587 588 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 589 return ENXIO; 590 if (sc->hasmic && ich_resetchan(sc, 2)) 591 return ENXIO; 592 593 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 594 return ENOSPC; 595 596 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 597 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, sc, 0)) { 598 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 599 return ENOSPC; 600 } 601 602 return 0; 603 } 604 605 static int 606 ich_pci_probe(device_t dev) 607 { 608 switch(pci_get_devid(dev)) { 609 case 0x71958086: 610 device_set_desc(dev, "Intel 443MX"); 611 return 0; 612 613 case 0x24158086: 614 device_set_desc(dev, "Intel 82801AA (ICH)"); 615 return 0; 616 617 case 0x24258086: 618 device_set_desc(dev, "Intel 82801AB (ICH)"); 619 return 0; 620 621 case 0x24458086: 622 device_set_desc(dev, "Intel 82801BA (ICH2)"); 623 return 0; 624 625 case 0x24858086: 626 device_set_desc(dev, "Intel 82801CA (ICH3)"); 627 return 0; 628 629 case ICH4ID: 630 device_set_desc(dev, "Intel 82801DB (ICH4)"); 631 return 0; 632 633 case SIS7012ID: 634 device_set_desc(dev, "SiS 7012"); 635 return 0; 636 637 case 0x01b110de: 638 device_set_desc(dev, "Nvidia nForce AC97 controller"); 639 return 0; 640 641 case 0x006a10de: 642 device_set_desc(dev, "Nvidia nForce2 AC97 controller"); 643 return 0; 644 645 default: 646 return ENXIO; 647 } 648 } 649 650 static int 651 ich_pci_attach(device_t dev) 652 { 653 u_int16_t extcaps; 654 struct sc_info *sc; 655 char status[SND_STATUSLEN]; 656 657 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 658 device_printf(dev, "cannot allocate softc\n"); 659 return ENXIO; 660 } 661 662 bzero(sc, sizeof(*sc)); 663 sc->dev = dev; 664 665 /* 666 * The SiS 7012 register set isn't quite like the standard ich. 667 * There really should be a general "quirks" mechanism. 668 */ 669 if (pci_get_devid(dev) == SIS7012ID) { 670 sc->swap_reg = 1; 671 sc->sample_size = 1; 672 } else { 673 sc->swap_reg = 0; 674 sc->sample_size = 2; 675 } 676 677 /* 678 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 679 * read-only. Need to enable "legacy support", by poking into 680 * pci config space. The driver should use MMBAR and MBBAR, 681 * but doing so will mess things up here. ich4 has enough new 682 * features it warrants it's own driver. 683 */ 684 if (pci_get_devid(dev) == ICH4ID) { 685 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 686 } 687 688 pci_enable_io(dev, SYS_RES_IOPORT); 689 /* 690 * Enable bus master. On ich4 this may prevent the detection of 691 * the primary codec becoming ready in ich_init(). 692 */ 693 pci_enable_busmaster(dev); 694 695 sc->nambarid = PCIR_NAMBAR; 696 sc->nabmbarid = PCIR_NABMBAR; 697 sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 698 sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 699 700 if (!sc->nambar || !sc->nabmbar) { 701 device_printf(dev, "unable to map IO port space\n"); 702 goto bad; 703 } 704 705 sc->nambart = rman_get_bustag(sc->nambar); 706 sc->nambarh = rman_get_bushandle(sc->nambar); 707 sc->nabmbart = rman_get_bustag(sc->nabmbar); 708 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 709 710 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 711 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 712 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) { 713 device_printf(dev, "unable to create dma tag\n"); 714 goto bad; 715 } 716 717 sc->irqid = 0; 718 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 719 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 720 device_printf(dev, "unable to map interrupt\n"); 721 goto bad; 722 } 723 724 if (ich_init(sc)) { 725 device_printf(dev, "unable to initialize the card\n"); 726 goto bad; 727 } 728 729 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 730 if (sc->codec == NULL) 731 goto bad; 732 mixer_init(dev, ac97_getmixerclass(), sc->codec); 733 734 /* check and set VRA function */ 735 extcaps = ac97_getextcaps(sc->codec); 736 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 737 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 738 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 739 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 740 741 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 742 goto bad; 743 744 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 745 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 746 if (sc->hasmic) 747 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 748 749 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 750 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 751 752 pcm_setstatus(dev, status); 753 754 ich_initsys(sc); 755 756 sc->intrhook.ich_func = ich_calibrate; 757 sc->intrhook.ich_arg = sc; 758 sc->use_intrhook = 1; 759 if (config_intrhook_establish(&sc->intrhook) != 0) { 760 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 761 sc->use_intrhook = 0; 762 ich_calibrate(sc); 763 } 764 765 return 0; 766 767 bad: 768 if (sc->codec) 769 ac97_destroy(sc->codec); 770 if (sc->ih) 771 bus_teardown_intr(dev, sc->irq, sc->ih); 772 if (sc->irq) 773 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 774 if (sc->nambar) 775 bus_release_resource(dev, SYS_RES_IOPORT, 776 sc->nambarid, sc->nambar); 777 if (sc->nabmbar) 778 bus_release_resource(dev, SYS_RES_IOPORT, 779 sc->nabmbarid, sc->nabmbar); 780 free(sc, M_DEVBUF); 781 return ENXIO; 782 } 783 784 static int 785 ich_pci_detach(device_t dev) 786 { 787 struct sc_info *sc; 788 int r; 789 790 r = pcm_unregister(dev); 791 if (r) 792 return r; 793 sc = pcm_getdevinfo(dev); 794 795 bus_teardown_intr(dev, sc->irq, sc->ih); 796 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 797 bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 798 bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 799 bus_dma_tag_destroy(sc->dmat); 800 free(sc, M_DEVBUF); 801 return 0; 802 } 803 804 static int 805 ich_pci_suspend(device_t dev) 806 { 807 struct sc_info *sc; 808 int i; 809 810 sc = pcm_getdevinfo(dev); 811 for (i = 0 ; i < 3; i++) { 812 sc->ch[i].run_save = sc->ch[i].run; 813 if (sc->ch[i].run) { 814 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 815 } 816 } 817 return 0; 818 } 819 820 static int 821 ich_pci_resume(device_t dev) 822 { 823 struct sc_info *sc; 824 int i; 825 826 sc = pcm_getdevinfo(dev); 827 828 /* Reinit audio device */ 829 if (ich_init(sc) == -1) { 830 device_printf(dev, "unable to reinitialize the card\n"); 831 return ENXIO; 832 } 833 /* Reinit mixer */ 834 if (mixer_reinit(dev) == -1) { 835 device_printf(dev, "unable to reinitialize the mixer\n"); 836 return ENXIO; 837 } 838 /* Re-start DMA engines */ 839 for (i = 0 ; i < 3; i++) { 840 struct sc_chinfo *ch = &sc->ch[i]; 841 if (sc->ch[i].run_save) { 842 ichchan_setblocksize(0, ch, ch->blksz); 843 ichchan_setspeed(0, ch, ch->spd); 844 ichchan_trigger(0, ch, PCMTRIG_START); 845 } 846 } 847 return 0; 848 } 849 850 static device_method_t ich_methods[] = { 851 /* Device interface */ 852 DEVMETHOD(device_probe, ich_pci_probe), 853 DEVMETHOD(device_attach, ich_pci_attach), 854 DEVMETHOD(device_detach, ich_pci_detach), 855 DEVMETHOD(device_suspend, ich_pci_suspend), 856 DEVMETHOD(device_resume, ich_pci_resume), 857 { 0, 0 } 858 }; 859 860 static driver_t ich_driver = { 861 "pcm", 862 ich_methods, 863 PCM_SOFTC_SIZE, 864 }; 865 866 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 867 MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 868 MODULE_VERSION(snd_ich, 1); 869