1 /* 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <dev/sound/pcm/sound.h> 29 #include <dev/sound/pcm/ac97.h> 30 #include <dev/sound/pci/ich.h> 31 32 #include <pci/pcireg.h> 33 #include <pci/pcivar.h> 34 35 SND_DECLARE_FILE("$FreeBSD$"); 36 37 /* -------------------------------------------------------------------- */ 38 39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40 #define ICH_DTBL_LENGTH 32 41 #define ICH_DEFAULT_BUFSZ 16384 42 #define ICH_MAX_BUFSZ 65536 43 44 /* buffer descriptor */ 45 struct ich_desc { 46 volatile u_int32_t buffer; 47 volatile u_int32_t length; 48 }; 49 50 struct sc_info; 51 52 /* channel registers */ 53 struct sc_chinfo { 54 u_int32_t num:8, run:1, run_save:1; 55 u_int32_t blksz, blkcnt, spd; 56 u_int32_t regbase, spdreg; 57 u_int32_t imask; 58 u_int32_t civ; 59 60 struct snd_dbuf *buffer; 61 struct pcm_channel *channel; 62 struct sc_info *parent; 63 64 struct ich_desc *dtbl; 65 }; 66 67 /* device private data */ 68 struct sc_info { 69 device_t dev; 70 int hasvra, hasvrm, hasmic; 71 unsigned int chnum, bufsz; 72 73 struct resource *nambar, *nabmbar, *irq; 74 int nambarid, nabmbarid, irqid; 75 bus_space_tag_t nambart, nabmbart; 76 bus_space_handle_t nambarh, nabmbarh; 77 bus_dma_tag_t dmat; 78 bus_dmamap_t dtmap; 79 void *ih; 80 81 struct ac97_info *codec; 82 struct sc_chinfo ch[3]; 83 int ac97rate; 84 struct ich_desc *dtbl; 85 }; 86 87 /* -------------------------------------------------------------------- */ 88 89 static u_int32_t ich_fmt[] = { 90 AFMT_STEREO | AFMT_S16_LE, 91 0 92 }; 93 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 94 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 95 96 /* -------------------------------------------------------------------- */ 97 /* Hardware */ 98 static u_int32_t 99 ich_rd(struct sc_info *sc, int regno, int size) 100 { 101 switch (size) { 102 case 1: 103 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 104 case 2: 105 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 106 case 4: 107 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 108 default: 109 return 0xffffffff; 110 } 111 } 112 113 static void 114 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 115 { 116 switch (size) { 117 case 1: 118 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 119 break; 120 case 2: 121 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 122 break; 123 case 4: 124 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 125 break; 126 } 127 } 128 129 /* ac97 codec */ 130 static int 131 ich_waitcd(void *devinfo) 132 { 133 int i; 134 u_int32_t data; 135 struct sc_info *sc = (struct sc_info *)devinfo; 136 137 for (i = 0; i < ICH_TIMEOUT; i++) { 138 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 139 if ((data & 0x01) == 0) 140 return 0; 141 } 142 device_printf(sc->dev, "CODEC semaphore timeout\n"); 143 return ETIMEDOUT; 144 } 145 146 static int 147 ich_rdcd(kobj_t obj, void *devinfo, int regno) 148 { 149 struct sc_info *sc = (struct sc_info *)devinfo; 150 151 regno &= 0xff; 152 ich_waitcd(sc); 153 154 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 155 } 156 157 static int 158 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 159 { 160 struct sc_info *sc = (struct sc_info *)devinfo; 161 162 regno &= 0xff; 163 ich_waitcd(sc); 164 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 165 166 return 0; 167 } 168 169 static kobj_method_t ich_ac97_methods[] = { 170 KOBJMETHOD(ac97_read, ich_rdcd), 171 KOBJMETHOD(ac97_write, ich_wrcd), 172 { 0, 0 } 173 }; 174 AC97_DECLARE(ich_ac97); 175 176 /* -------------------------------------------------------------------- */ 177 /* common routines */ 178 179 static void 180 ich_filldtbl(struct sc_chinfo *ch) 181 { 182 u_int32_t base; 183 int i; 184 185 base = vtophys(sndbuf_getbuf(ch->buffer)); 186 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 187 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 188 ch->blkcnt = 2; 189 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 190 } 191 192 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 193 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 194 ch->dtbl[i].length = ICH_BDC_IOC | (ch->blksz / 2); 195 } 196 } 197 198 static int 199 ich_resetchan(struct sc_info *sc, int num) 200 { 201 int i, cr, regbase; 202 203 if (num == 0) 204 regbase = ICH_REG_PO_BASE; 205 else if (num == 1) 206 regbase = ICH_REG_PI_BASE; 207 else if (num == 2) 208 regbase = ICH_REG_MC_BASE; 209 else 210 return ENXIO; 211 212 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 213 DELAY(100); 214 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 215 for (i = 0; i < ICH_TIMEOUT; i++) { 216 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 217 if (cr == 0) 218 return 0; 219 } 220 221 device_printf(sc->dev, "cannot reset channel %d\n", num); 222 return ENXIO; 223 } 224 225 /* -------------------------------------------------------------------- */ 226 /* channel interface */ 227 228 static void * 229 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 230 { 231 struct sc_info *sc = devinfo; 232 struct sc_chinfo *ch; 233 unsigned int num; 234 235 num = sc->chnum++; 236 ch = &sc->ch[num]; 237 ch->num = num; 238 ch->buffer = b; 239 ch->channel = c; 240 ch->parent = sc; 241 ch->run = 0; 242 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 243 ch->blkcnt = 2; 244 ch->blksz = sc->bufsz / ch->blkcnt; 245 246 switch(ch->num) { 247 case 0: /* play */ 248 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 249 ch->regbase = ICH_REG_PO_BASE; 250 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 251 ch->imask = ICH_GLOB_STA_POINT; 252 break; 253 254 case 1: /* record */ 255 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 256 ch->regbase = ICH_REG_PI_BASE; 257 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 258 ch->imask = ICH_GLOB_STA_PIINT; 259 break; 260 261 case 2: /* mic */ 262 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 263 ch->regbase = ICH_REG_MC_BASE; 264 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 265 ch->imask = ICH_GLOB_STA_MINT; 266 break; 267 268 default: 269 return NULL; 270 } 271 272 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 273 return NULL; 274 275 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 276 277 return ch; 278 } 279 280 static int 281 ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 282 { 283 return 0; 284 } 285 286 static int 287 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 288 { 289 struct sc_chinfo *ch = data; 290 struct sc_info *sc = ch->parent; 291 292 if (ch->spdreg) { 293 int r; 294 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 295 sc->ac97rate = 48000; 296 r = speed * 48000 / sc->ac97rate; 297 ch->spd = ac97_setrate(sc->codec, ch->spdreg, r) * 298 sc->ac97rate / 48000; 299 } else { 300 ch->spd = 48000; 301 } 302 return ch->spd; 303 } 304 305 static int 306 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 307 { 308 struct sc_chinfo *ch = data; 309 struct sc_info *sc = ch->parent; 310 311 ch->blksz = blocksize; 312 ich_filldtbl(ch); 313 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 314 315 return ch->blksz; 316 } 317 318 static int 319 ichchan_trigger(kobj_t obj, void *data, int go) 320 { 321 struct sc_chinfo *ch = data; 322 struct sc_info *sc = ch->parent; 323 324 switch (go) { 325 case PCMTRIG_START: 326 ch->run = 1; 327 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 328 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE | ICH_X_CR_FEIE, 1); 329 break; 330 331 case PCMTRIG_ABORT: 332 ich_resetchan(sc, ch->num); 333 ch->run = 0; 334 break; 335 } 336 return 0; 337 } 338 339 static int 340 ichchan_getptr(kobj_t obj, void *data) 341 { 342 struct sc_chinfo *ch = data; 343 struct sc_info *sc = ch->parent; 344 u_int32_t pos; 345 346 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 347 348 pos = ch->civ * ch->blksz; 349 350 return pos; 351 } 352 353 static struct pcmchan_caps * 354 ichchan_getcaps(kobj_t obj, void *data) 355 { 356 struct sc_chinfo *ch = data; 357 358 return ch->spdreg? &ich_vrcaps : &ich_caps; 359 } 360 361 static kobj_method_t ichchan_methods[] = { 362 KOBJMETHOD(channel_init, ichchan_init), 363 KOBJMETHOD(channel_setformat, ichchan_setformat), 364 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 365 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 366 KOBJMETHOD(channel_trigger, ichchan_trigger), 367 KOBJMETHOD(channel_getptr, ichchan_getptr), 368 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 369 { 0, 0 } 370 }; 371 CHANNEL_DECLARE(ichchan); 372 373 /* -------------------------------------------------------------------- */ 374 /* The interrupt handler */ 375 376 static void 377 ich_intr(void *p) 378 { 379 struct sc_info *sc = (struct sc_info *)p; 380 struct sc_chinfo *ch; 381 u_int32_t cbi, lbi, lvi, st, gs; 382 int i; 383 384 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 385 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 386 /* Clear resume interrupt(s) - nothing doing with them */ 387 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 388 } 389 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 390 391 for (i = 0; i < 3; i++) { 392 ch = &sc->ch[i]; 393 if ((ch->imask & gs) == 0) 394 continue; 395 gs &= ~ch->imask; 396 st = ich_rd(sc, ch->regbase + ICH_REG_X_SR, 2); 397 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 398 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 399 /* block complete - update buffer */ 400 if (ch->run) 401 chn_intr(ch->channel); 402 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 403 cbi = ch->civ % ch->blkcnt; 404 if (cbi == 0) 405 cbi = ch->blkcnt - 1; 406 else 407 cbi--; 408 lbi = lvi % ch->blkcnt; 409 if (cbi >= lbi) 410 lvi += cbi - lbi; 411 else 412 lvi += cbi + ch->blkcnt - lbi; 413 lvi %= ICH_DTBL_LENGTH; 414 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 415 416 } 417 /* clear status bit */ 418 ich_wr(sc, ch->regbase + ICH_REG_X_SR, st, 2); 419 } 420 if (gs != 0) { 421 device_printf(sc->dev, 422 "Unhandled interrupt, gs_intr = %x\n", gs); 423 } 424 } 425 426 /* ------------------------------------------------------------------------- */ 427 /* Sysctl to control ac97 speed (some boards overclocked ac97). */ 428 429 static int 430 ich_initsys(struct sc_info* sc) 431 { 432 #ifdef SND_DYNSYSCTL 433 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 434 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 435 OID_AUTO, "ac97rate", CTLFLAG_RW, 436 &sc->ac97rate, 48000, 437 "AC97 link rate (default = 48000)"); 438 #endif /* SND_DYNSYSCTL */ 439 return 0; 440 } 441 442 /* -------------------------------------------------------------------- */ 443 /* Calibrate card (some boards are overclocked and need scaling) */ 444 445 static 446 unsigned int ich_calibrate(struct sc_info *sc) 447 { 448 /* Grab audio from input for fixed interval and compare how 449 * much we actually get with what we expect. Interval needs 450 * to be sufficiently short that no interrupts are 451 * generated. */ 452 struct sc_chinfo *ch = &sc->ch[1]; 453 u_int16_t target_picb, actual_picb; 454 u_int32_t wait_us, actual_48k_rate; 455 456 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 457 458 ichchan_setspeed(0, ch, 48000); 459 ichchan_setblocksize(0, ch, ICH_DEFAULT_BUFSZ); 460 461 target_picb = ch->dtbl[0].length / 2; /* half interrupt interval */ 462 wait_us = target_picb * 1000 / (2 * 48); /* (2 == stereo -> mono) */ 463 464 if (bootverbose) 465 device_printf(sc->dev, "Calibration interval %d us\n", 466 wait_us); 467 468 ichchan_trigger(0, ch, PCMTRIG_START); 469 DELAY(wait_us); 470 actual_picb = ich_rd(sc, ch->regbase + ICH_REG_X_PICB, 2); 471 ichchan_trigger(0, ch, PCMTRIG_ABORT); 472 473 actual_48k_rate = 48000 * (2 * target_picb - actual_picb) / 474 (target_picb); 475 476 if (actual_48k_rate > 48500 || actual_48k_rate < 47500) { 477 sc->ac97rate = actual_48k_rate; 478 } else { 479 sc->ac97rate = 48000; 480 } 481 482 if (bootverbose) 483 device_printf(sc->dev, 484 "Estimated AC97 link rate %d, using %d\n", 485 actual_48k_rate, sc->ac97rate); 486 487 return sc->ac97rate; 488 } 489 490 /* -------------------------------------------------------------------- */ 491 /* Probe and attach the card */ 492 493 static void 494 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 495 { 496 return; 497 } 498 499 static int 500 ich_init(struct sc_info *sc) 501 { 502 u_int32_t stat; 503 int sz; 504 505 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 506 DELAY(600000); 507 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 508 509 if ((stat & ICH_GLOB_STA_PCR) == 0) 510 return ENXIO; 511 512 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 513 514 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 515 return ENXIO; 516 if (sc->hasmic && ich_resetchan(sc, 2)) 517 return ENXIO; 518 519 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 520 return ENOSPC; 521 522 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 523 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) { 524 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 525 return ENOSPC; 526 } 527 528 return 0; 529 } 530 531 static int 532 ich_pci_probe(device_t dev) 533 { 534 switch(pci_get_devid(dev)) { 535 case 0x71958086: 536 device_set_desc(dev, "Intel 443MX"); 537 return 0; 538 539 case 0x24158086: 540 device_set_desc(dev, "Intel 82801AA (ICH)"); 541 return 0; 542 543 case 0x24258086: 544 device_set_desc(dev, "Intel 82801AB (ICH)"); 545 return 0; 546 547 case 0x24458086: 548 device_set_desc(dev, "Intel 82801BA (ICH2)"); 549 return 0; 550 551 case 0x24858086: 552 device_set_desc(dev, "Intel 82801CA (ICH3)"); 553 return 0; 554 555 default: 556 return ENXIO; 557 } 558 } 559 560 static int 561 ich_pci_attach(device_t dev) 562 { 563 u_int32_t data; 564 u_int16_t extcaps; 565 struct sc_info *sc; 566 char status[SND_STATUSLEN]; 567 568 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 569 device_printf(dev, "cannot allocate softc\n"); 570 return ENXIO; 571 } 572 573 bzero(sc, sizeof(*sc)); 574 sc->dev = dev; 575 576 data = pci_read_config(dev, PCIR_COMMAND, 2); 577 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 578 pci_write_config(dev, PCIR_COMMAND, data, 2); 579 data = pci_read_config(dev, PCIR_COMMAND, 2); 580 581 sc->nambarid = PCIR_NAMBAR; 582 sc->nabmbarid = PCIR_NABMBAR; 583 sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 584 sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 585 586 if (!sc->nambar || !sc->nabmbar) { 587 device_printf(dev, "unable to map IO port space\n"); 588 goto bad; 589 } 590 591 sc->nambart = rman_get_bustag(sc->nambar); 592 sc->nambarh = rman_get_bushandle(sc->nambar); 593 sc->nabmbart = rman_get_bustag(sc->nabmbar); 594 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 595 596 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 597 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 598 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) { 599 device_printf(dev, "unable to create dma tag\n"); 600 goto bad; 601 } 602 603 if (ich_init(sc)) { 604 device_printf(dev, "unable to initialize the card\n"); 605 goto bad; 606 } 607 608 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 609 if (sc->codec == NULL) 610 goto bad; 611 mixer_init(dev, ac97_getmixerclass(), sc->codec); 612 613 /* check and set VRA function */ 614 extcaps = ac97_getextcaps(sc->codec); 615 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 616 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 617 sc->hasmic = extcaps & AC97_CAP_MICCHANNEL; 618 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm | sc->hasmic); 619 620 sc->irqid = 0; 621 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 622 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 623 device_printf(dev, "unable to map interrupt\n"); 624 goto bad; 625 } 626 627 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 628 goto bad; 629 630 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 631 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 632 if (sc->hasmic) 633 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 634 635 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 636 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 637 638 pcm_setstatus(dev, status); 639 640 ich_initsys(sc); 641 ich_calibrate(sc); 642 643 return 0; 644 645 bad: 646 if (sc->codec) 647 ac97_destroy(sc->codec); 648 if (sc->nambar) 649 bus_release_resource(dev, SYS_RES_IOPORT, 650 sc->nambarid, sc->nambar); 651 if (sc->nabmbar) 652 bus_release_resource(dev, SYS_RES_IOPORT, 653 sc->nabmbarid, sc->nabmbar); 654 if (sc->ih) 655 bus_teardown_intr(dev, sc->irq, sc->ih); 656 if (sc->irq) 657 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 658 free(sc, M_DEVBUF); 659 return ENXIO; 660 } 661 662 static int 663 ich_pci_detach(device_t dev) 664 { 665 struct sc_info *sc; 666 int r; 667 668 r = pcm_unregister(dev); 669 if (r) 670 return r; 671 sc = pcm_getdevinfo(dev); 672 673 bus_teardown_intr(dev, sc->irq, sc->ih); 674 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 675 bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 676 bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 677 bus_dma_tag_destroy(sc->dmat); 678 free(sc, M_DEVBUF); 679 return 0; 680 } 681 682 static int 683 ich_pci_suspend(device_t dev) 684 { 685 struct sc_info *sc; 686 int i; 687 688 sc = pcm_getdevinfo(dev); 689 for (i = 0 ; i < 3; i++) { 690 sc->ch[i].run_save = sc->ch[i].run; 691 if (sc->ch[i].run) { 692 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 693 } 694 } 695 696 /* ACLINK shut off */ 697 ich_wr(sc,ICH_REG_GLOB_CNT, ICH_GLOB_CTL_SHUT, 4); 698 return 0; 699 } 700 701 static int 702 ich_pci_resume(device_t dev) 703 { 704 struct sc_info *sc; 705 int i; 706 707 sc = pcm_getdevinfo(dev); 708 709 /* Reinit audio device */ 710 if (ich_init(sc) == -1) { 711 device_printf(dev, "unable to reinitialize the card\n"); 712 return ENXIO; 713 } 714 /* Reinit mixer */ 715 if (mixer_reinit(dev) == -1) { 716 device_printf(dev, "unable to reinitialize the mixer\n"); 717 return ENXIO; 718 } 719 /* Re-start DMA engines */ 720 for (i = 0 ; i < 3; i++) { 721 struct sc_chinfo *ch = &sc->ch[i]; 722 if (sc->ch[i].run_save) { 723 ichchan_setblocksize(0, ch, ch->blksz); 724 ichchan_setspeed(0, ch, ch->spd); 725 ichchan_trigger(0, ch, PCMTRIG_START); 726 } 727 } 728 return 0; 729 } 730 731 static device_method_t ich_methods[] = { 732 /* Device interface */ 733 DEVMETHOD(device_probe, ich_pci_probe), 734 DEVMETHOD(device_attach, ich_pci_attach), 735 DEVMETHOD(device_detach, ich_pci_detach), 736 DEVMETHOD(device_suspend, ich_pci_suspend), 737 DEVMETHOD(device_resume, ich_pci_resume), 738 { 0, 0 } 739 }; 740 741 static driver_t ich_driver = { 742 "pcm", 743 ich_methods, 744 PCM_SOFTC_SIZE, 745 }; 746 747 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 748 MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 749 MODULE_VERSION(snd_ich, 1); 750