1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define PCI_VENDOR_XILINX 0x10ee 31 #define PCI_VENDOR_RME 0x1d18 /* Newer firmware versions. */ 32 #define PCI_DEVICE_XILINX_HDSPE 0x3fc6 /* AIO, MADI, AES, RayDAT */ 33 #define PCI_CLASS_REVISION 0x08 34 #define PCI_REVISION_AIO 212 35 #define PCI_REVISION_RAYDAT 211 36 37 #define HDSPE_AIO 0 38 #define HDSPE_RAYDAT 1 39 40 /* Hardware mixer */ 41 #define HDSPE_OUT_ENABLE_BASE 512 42 #define HDSPE_IN_ENABLE_BASE 768 43 #define HDSPE_MIXER_BASE 32768 44 #define HDSPE_MAX_GAIN 32768 45 46 /* Buffer */ 47 #define HDSPE_PAGE_ADDR_BUF_OUT 8192 48 #define HDSPE_PAGE_ADDR_BUF_IN (HDSPE_PAGE_ADDR_BUF_OUT + 64 * 16 * 4) 49 #define HDSPE_BUF_POSITION_MASK 0x000FFC0 50 51 /* Frequency */ 52 #define HDSPE_FREQ_0 (1 << 6) 53 #define HDSPE_FREQ_1 (1 << 7) 54 #define HDSPE_FREQ_DOUBLE (1 << 8) 55 #define HDSPE_FREQ_QUAD (1 << 31) 56 57 #define HDSPE_FREQ_32000 HDSPE_FREQ_0 58 #define HDSPE_FREQ_44100 HDSPE_FREQ_1 59 #define HDSPE_FREQ_48000 (HDSPE_FREQ_0 | HDSPE_FREQ_1) 60 #define HDSPE_FREQ_MASK (HDSPE_FREQ_0 | HDSPE_FREQ_1 | \ 61 HDSPE_FREQ_DOUBLE | HDSPE_FREQ_QUAD) 62 #define HDSPE_FREQ_MASK_DEFAULT HDSPE_FREQ_48000 63 #define HDSPE_FREQ_REG 256 64 #define HDSPE_FREQ_AIO 104857600000000ULL 65 66 #define HDSPE_SPEED_DEFAULT 48000 67 68 /* Latency */ 69 #define HDSPE_LAT_0 (1 << 1) 70 #define HDSPE_LAT_1 (1 << 2) 71 #define HDSPE_LAT_2 (1 << 3) 72 #define HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2) 73 #define HDSPE_LAT_BYTES_MAX (4096 * 4) 74 #define HDSPE_LAT_BYTES_MIN (32 * 4) 75 #define hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK) 76 77 /* Gain */ 78 #define HDSP_ADGain0 (1 << 25) 79 #define HDSP_ADGain1 (1 << 26) 80 #define HDSP_DAGain0 (1 << 27) 81 #define HDSP_DAGain1 (1 << 28) 82 #define HDSP_PhoneGain0 (1 << 29) 83 #define HDSP_PhoneGain1 (1 << 30) 84 85 #define HDSP_ADGainMask (HDSP_ADGain0 | HDSP_ADGain1) 86 #define HDSP_ADGainMinus10dBV (HDSP_ADGainMask) 87 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) 88 #define HDSP_ADGainLowGain 0 89 90 #define HDSP_DAGainMask (HDSP_DAGain0 | HDSP_DAGain1) 91 #define HDSP_DAGainHighGain (HDSP_DAGainMask) 92 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) 93 #define HDSP_DAGainMinus10dBV 0 94 95 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) 96 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask 97 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) 98 #define HDSP_PhoneGainMinus12dB 0 99 100 /* Settings */ 101 #define HDSPE_SETTINGS_REG 0 102 #define HDSPE_CONTROL_REG 64 103 #define HDSPE_STATUS_REG 0 104 #define HDSPE_STATUS1_REG 64 105 #define HDSPE_STATUS2_REG 192 106 #define HDSPE_ENABLE (1 << 0) 107 108 /* Interrupts */ 109 #define HDSPE_AUDIO_IRQ_PENDING (1 << 0) 110 #define HDSPE_AUDIO_INT_ENABLE (1 << 5) 111 #define HDSPE_INTERRUPT_ACK 96 112 113 /* Channels */ 114 #define HDSPE_MAX_SLOTS 64 /* Mono channels */ 115 #define HDSPE_MAX_CHANS (HDSPE_MAX_SLOTS / 2) /* Stereo pairs */ 116 117 #define HDSPE_CHANBUF_SAMPLES (16 * 1024) 118 #define HDSPE_CHANBUF_SIZE (4 * HDSPE_CHANBUF_SAMPLES) 119 #define HDSPE_DMASEGSIZE (HDSPE_CHANBUF_SIZE * HDSPE_MAX_SLOTS) 120 121 #define HDSPE_CHAN_AIO_LINE (1 << 0) 122 #define HDSPE_CHAN_AIO_PHONE (1 << 1) 123 #define HDSPE_CHAN_AIO_AES (1 << 2) 124 #define HDSPE_CHAN_AIO_SPDIF (1 << 3) 125 #define HDSPE_CHAN_AIO_ADAT (1 << 4) 126 #define HDSPE_CHAN_AIO_ALL_REC (HDSPE_CHAN_AIO_LINE | \ 127 HDSPE_CHAN_AIO_AES | \ 128 HDSPE_CHAN_AIO_SPDIF | \ 129 HDSPE_CHAN_AIO_ADAT) 130 #define HDSPE_CHAN_AIO_ALL (HDSPE_CHAN_AIO_ALL_REC | \ 131 HDSPE_CHAN_AIO_PHONE) \ 132 133 #define HDSPE_CHAN_RAY_AES (1 << 5) 134 #define HDSPE_CHAN_RAY_SPDIF (1 << 6) 135 #define HDSPE_CHAN_RAY_ADAT1 (1 << 7) 136 #define HDSPE_CHAN_RAY_ADAT2 (1 << 8) 137 #define HDSPE_CHAN_RAY_ADAT3 (1 << 9) 138 #define HDSPE_CHAN_RAY_ADAT4 (1 << 10) 139 #define HDSPE_CHAN_RAY_ALL (HDSPE_CHAN_RAY_AES | \ 140 HDSPE_CHAN_RAY_SPDIF | \ 141 HDSPE_CHAN_RAY_ADAT1 | \ 142 HDSPE_CHAN_RAY_ADAT2 | \ 143 HDSPE_CHAN_RAY_ADAT3 | \ 144 HDSPE_CHAN_RAY_ADAT4) 145 146 struct hdspe_channel { 147 uint32_t ports; 148 char *descr; 149 }; 150 151 /* Clock sources */ 152 #define HDSPE_SETTING_MASTER (1 << 0) 153 #define HDSPE_SETTING_CLOCK_MASK 0x1f 154 155 #define HDSPE_STATUS1_CLOCK_SHIFT 28 156 #define HDSPE_STATUS1_CLOCK_MASK (0x0f << HDSPE_STATUS1_CLOCK_SHIFT) 157 #define HDSPE_STATUS1_CLOCK(n) (((n) << HDSPE_STATUS1_CLOCK_SHIFT) & \ 158 HDSPE_STATUS1_CLOCK_MASK) 159 160 struct hdspe_clock_source { 161 char *name; 162 uint32_t setting; 163 uint32_t status; 164 uint32_t lock_bit; 165 uint32_t sync_bit; 166 }; 167 168 static MALLOC_DEFINE(M_HDSPE, "hdspe", "hdspe audio"); 169 170 /* Channel registers */ 171 struct sc_chinfo { 172 struct snd_dbuf *buffer; 173 struct pcm_channel *channel; 174 struct sc_pcminfo *parent; 175 176 /* Channel information */ 177 struct pcmchan_caps *caps; 178 uint32_t cap_fmts[4]; 179 uint32_t dir; 180 uint32_t format; 181 uint32_t ports; 182 uint32_t lvol; 183 uint32_t rvol; 184 185 /* Buffer */ 186 uint32_t *data; 187 uint32_t size; 188 uint32_t position; 189 190 /* Flags */ 191 uint32_t run; 192 }; 193 194 /* PCM device private data */ 195 struct sc_pcminfo { 196 device_t dev; 197 uint32_t (*ih) (struct sc_pcminfo *scp); 198 uint32_t chnum; 199 struct sc_chinfo chan[HDSPE_MAX_CHANS]; 200 struct sc_info *sc; 201 struct hdspe_channel *hc; 202 }; 203 204 /* HDSPe device private data */ 205 struct sc_info { 206 device_t dev; 207 struct mtx *lock; 208 209 uint32_t ctrl_register; 210 uint32_t settings_register; 211 uint32_t type; 212 213 /* Control/Status register */ 214 struct resource *cs; 215 int csid; 216 bus_space_tag_t cst; 217 bus_space_handle_t csh; 218 219 struct resource *irq; 220 int irqid; 221 void *ih; 222 bus_dma_tag_t dmat; 223 224 /* Play/Record DMA buffers */ 225 uint32_t *pbuf; 226 uint32_t *rbuf; 227 uint32_t bufsize; 228 bus_dmamap_t pmap; 229 bus_dmamap_t rmap; 230 uint32_t period; 231 uint32_t speed; 232 uint32_t force_period; 233 uint32_t force_speed; 234 }; 235 236 #define hdspe_read_1(sc, regno) \ 237 bus_space_read_1((sc)->cst, (sc)->csh, (regno)) 238 #define hdspe_read_2(sc, regno) \ 239 bus_space_read_2((sc)->cst, (sc)->csh, (regno)) 240 #define hdspe_read_4(sc, regno) \ 241 bus_space_read_4((sc)->cst, (sc)->csh, (regno)) 242 243 #define hdspe_write_1(sc, regno, data) \ 244 bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data)) 245 #define hdspe_write_2(sc, regno, data) \ 246 bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data)) 247 #define hdspe_write_4(sc, regno, data) \ 248 bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data)) 249