1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define PCI_VENDOR_XILINX 0x10ee 31 #define PCI_DEVICE_XILINX_HDSPE 0x3fc6 /* AIO, MADI, AES, RayDAT */ 32 #define PCI_CLASS_REVISION 0x08 33 #define PCI_REVISION_AIO 212 34 #define PCI_REVISION_RAYDAT 211 35 36 #define HDSPE_AIO 0 37 #define HDSPE_RAYDAT 1 38 39 /* Hardware mixer */ 40 #define HDSPE_OUT_ENABLE_BASE 512 41 #define HDSPE_IN_ENABLE_BASE 768 42 #define HDSPE_MIXER_BASE 32768 43 #define HDSPE_MAX_GAIN 32768 44 45 /* Buffer */ 46 #define HDSPE_PAGE_ADDR_BUF_OUT 8192 47 #define HDSPE_PAGE_ADDR_BUF_IN (HDSPE_PAGE_ADDR_BUF_OUT + 64 * 16 * 4) 48 #define HDSPE_BUF_POSITION_MASK 0x000FFC0 49 50 /* Frequency */ 51 #define HDSPE_FREQ_0 (1 << 6) 52 #define HDSPE_FREQ_1 (1 << 7) 53 #define HDSPE_FREQ_DOUBLE (1 << 8) 54 #define HDSPE_FREQ_QUAD (1 << 31) 55 56 #define HDSPE_FREQ_32000 HDSPE_FREQ_0 57 #define HDSPE_FREQ_44100 HDSPE_FREQ_1 58 #define HDSPE_FREQ_48000 (HDSPE_FREQ_0 | HDSPE_FREQ_1) 59 #define HDSPE_FREQ_MASK (HDSPE_FREQ_0 | HDSPE_FREQ_1 | \ 60 HDSPE_FREQ_DOUBLE | HDSPE_FREQ_QUAD) 61 #define HDSPE_FREQ_MASK_DEFAULT HDSPE_FREQ_48000 62 #define HDSPE_FREQ_REG 256 63 #define HDSPE_FREQ_AIO 104857600000000ULL 64 65 #define HDSPE_SPEED_DEFAULT 48000 66 67 /* Latency */ 68 #define HDSPE_LAT_0 (1 << 1) 69 #define HDSPE_LAT_1 (1 << 2) 70 #define HDSPE_LAT_2 (1 << 3) 71 #define HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2) 72 #define HDSPE_LAT_BYTES_MAX (4096 * 4) 73 #define HDSPE_LAT_BYTES_MIN (32 * 4) 74 #define hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK) 75 76 /* Gain */ 77 #define HDSP_ADGain0 (1 << 25) 78 #define HDSP_ADGain1 (1 << 26) 79 #define HDSP_DAGain0 (1 << 27) 80 #define HDSP_DAGain1 (1 << 28) 81 #define HDSP_PhoneGain0 (1 << 29) 82 #define HDSP_PhoneGain1 (1 << 30) 83 84 #define HDSP_ADGainMask (HDSP_ADGain0 | HDSP_ADGain1) 85 #define HDSP_ADGainMinus10dBV (HDSP_ADGainMask) 86 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) 87 #define HDSP_ADGainLowGain 0 88 89 #define HDSP_DAGainMask (HDSP_DAGain0 | HDSP_DAGain1) 90 #define HDSP_DAGainHighGain (HDSP_DAGainMask) 91 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) 92 #define HDSP_DAGainMinus10dBV 0 93 94 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) 95 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask 96 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) 97 #define HDSP_PhoneGainMinus12dB 0 98 99 /* Settings */ 100 #define HDSPE_SETTINGS_REG 0 101 #define HDSPE_CONTROL_REG 64 102 #define HDSPE_STATUS_REG 0 103 #define HDSPE_STATUS1_REG 64 104 #define HDSPE_STATUS2_REG 192 105 #define HDSPE_ENABLE (1 << 0) 106 107 /* Interrupts */ 108 #define HDSPE_AUDIO_IRQ_PENDING (1 << 0) 109 #define HDSPE_AUDIO_INT_ENABLE (1 << 5) 110 #define HDSPE_INTERRUPT_ACK 96 111 112 /* Channels */ 113 #define HDSPE_MAX_SLOTS 64 /* Mono channels */ 114 #define HDSPE_MAX_CHANS (HDSPE_MAX_SLOTS / 2) /* Stereo pairs */ 115 116 #define HDSPE_CHANBUF_SAMPLES (16 * 1024) 117 #define HDSPE_CHANBUF_SIZE (4 * HDSPE_CHANBUF_SAMPLES) 118 #define HDSPE_DMASEGSIZE (HDSPE_CHANBUF_SIZE * HDSPE_MAX_SLOTS) 119 120 #define HDSPE_CHAN_AIO_LINE (1 << 0) 121 #define HDSPE_CHAN_AIO_PHONE (1 << 1) 122 #define HDSPE_CHAN_AIO_AES (1 << 2) 123 #define HDSPE_CHAN_AIO_SPDIF (1 << 3) 124 #define HDSPE_CHAN_AIO_ADAT (1 << 4) 125 #define HDSPE_CHAN_AIO_ALL_REC (HDSPE_CHAN_AIO_LINE | \ 126 HDSPE_CHAN_AIO_AES | \ 127 HDSPE_CHAN_AIO_SPDIF | \ 128 HDSPE_CHAN_AIO_ADAT) 129 #define HDSPE_CHAN_AIO_ALL (HDSPE_CHAN_AIO_ALL_REC | \ 130 HDSPE_CHAN_AIO_PHONE) \ 131 132 #define HDSPE_CHAN_RAY_AES (1 << 5) 133 #define HDSPE_CHAN_RAY_SPDIF (1 << 6) 134 #define HDSPE_CHAN_RAY_ADAT1 (1 << 7) 135 #define HDSPE_CHAN_RAY_ADAT2 (1 << 8) 136 #define HDSPE_CHAN_RAY_ADAT3 (1 << 9) 137 #define HDSPE_CHAN_RAY_ADAT4 (1 << 10) 138 #define HDSPE_CHAN_RAY_ALL (HDSPE_CHAN_RAY_AES | \ 139 HDSPE_CHAN_RAY_SPDIF | \ 140 HDSPE_CHAN_RAY_ADAT1 | \ 141 HDSPE_CHAN_RAY_ADAT2 | \ 142 HDSPE_CHAN_RAY_ADAT3 | \ 143 HDSPE_CHAN_RAY_ADAT4) 144 145 struct hdspe_channel { 146 uint32_t ports; 147 char *descr; 148 }; 149 150 /* Clock sources */ 151 #define HDSPE_SETTING_MASTER (1 << 0) 152 #define HDSPE_SETTING_CLOCK_MASK 0x1f 153 154 #define HDSPE_STATUS1_CLOCK_SHIFT 28 155 #define HDSPE_STATUS1_CLOCK_MASK (0x0f << HDSPE_STATUS1_CLOCK_SHIFT) 156 #define HDSPE_STATUS1_CLOCK(n) (((n) << HDSPE_STATUS1_CLOCK_SHIFT) & \ 157 HDSPE_STATUS1_CLOCK_MASK) 158 159 struct hdspe_clock_source { 160 char *name; 161 uint32_t setting; 162 uint32_t status; 163 uint32_t lock_bit; 164 uint32_t sync_bit; 165 }; 166 167 static MALLOC_DEFINE(M_HDSPE, "hdspe", "hdspe audio"); 168 169 /* Channel registers */ 170 struct sc_chinfo { 171 struct snd_dbuf *buffer; 172 struct pcm_channel *channel; 173 struct sc_pcminfo *parent; 174 175 /* Channel information */ 176 struct pcmchan_caps *caps; 177 uint32_t cap_fmts[4]; 178 uint32_t dir; 179 uint32_t format; 180 uint32_t ports; 181 uint32_t lvol; 182 uint32_t rvol; 183 184 /* Buffer */ 185 uint32_t *data; 186 uint32_t size; 187 188 /* Flags */ 189 uint32_t run; 190 }; 191 192 /* PCM device private data */ 193 struct sc_pcminfo { 194 device_t dev; 195 uint32_t (*ih) (struct sc_pcminfo *scp); 196 uint32_t chnum; 197 struct sc_chinfo chan[HDSPE_MAX_CHANS]; 198 struct sc_info *sc; 199 struct hdspe_channel *hc; 200 }; 201 202 /* HDSPe device private data */ 203 struct sc_info { 204 device_t dev; 205 struct mtx *lock; 206 207 uint32_t ctrl_register; 208 uint32_t settings_register; 209 uint32_t type; 210 211 /* Control/Status register */ 212 struct resource *cs; 213 int csid; 214 bus_space_tag_t cst; 215 bus_space_handle_t csh; 216 217 struct resource *irq; 218 int irqid; 219 void *ih; 220 bus_dma_tag_t dmat; 221 222 /* Play/Record DMA buffers */ 223 uint32_t *pbuf; 224 uint32_t *rbuf; 225 uint32_t bufsize; 226 bus_dmamap_t pmap; 227 bus_dmamap_t rmap; 228 uint32_t period; 229 uint32_t speed; 230 uint32_t force_period; 231 uint32_t force_speed; 232 }; 233 234 #define hdspe_read_1(sc, regno) \ 235 bus_space_read_1((sc)->cst, (sc)->csh, (regno)) 236 #define hdspe_read_2(sc, regno) \ 237 bus_space_read_2((sc)->cst, (sc)->csh, (regno)) 238 #define hdspe_read_4(sc, regno) \ 239 bus_space_read_4((sc)->cst, (sc)->csh, (regno)) 240 241 #define hdspe_write_1(sc, regno, data) \ 242 bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data)) 243 #define hdspe_write_2(sc, regno, data) \ 244 bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data)) 245 #define hdspe_write_4(sc, regno, data) \ 246 bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data)) 247