1 /*- 2 * Copyright (c) 2012 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * RME HDSPe driver for FreeBSD. 29 * Supported cards: AIO, RayDAT. 30 */ 31 32 #include <dev/sound/pcm/sound.h> 33 #include <dev/sound/pci/hdspe.h> 34 #include <dev/sound/chip.h> 35 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 39 #include <mixer_if.h> 40 41 SND_DECLARE_FILE("$FreeBSD$"); 42 43 static struct hdspe_channel chan_map_aio[] = { 44 { 0, 1, "line", 1, 1 }, 45 { 6, 7, "phone", 1, 0 }, 46 { 8, 9, "aes", 1, 1 }, 47 { 10, 11, "s/pdif", 1, 1 }, 48 { 12, 16, "adat", 1, 1 }, 49 50 /* Single or double speed. */ 51 { 14, 18, "adat", 1, 1 }, 52 53 /* Single speed only. */ 54 { 13, 15, "adat", 1, 1 }, 55 { 17, 19, "adat", 1, 1 }, 56 57 { 0, 0, NULL, 0, 0 }, 58 }; 59 60 static struct hdspe_channel chan_map_rd[] = { 61 { 0, 1, "aes", 1, 1 }, 62 { 2, 3, "s/pdif", 1, 1 }, 63 { 4, 5, "adat", 1, 1 }, 64 { 6, 7, "adat", 1, 1 }, 65 { 8, 9, "adat", 1, 1 }, 66 { 10, 11, "adat", 1, 1 }, 67 68 /* Single or double speed. */ 69 { 12, 13, "adat", 1, 1 }, 70 { 14, 15, "adat", 1, 1 }, 71 { 16, 17, "adat", 1, 1 }, 72 { 18, 19, "adat", 1, 1 }, 73 74 /* Single speed only. */ 75 { 20, 21, "adat", 1, 1 }, 76 { 22, 23, "adat", 1, 1 }, 77 { 24, 25, "adat", 1, 1 }, 78 { 26, 27, "adat", 1, 1 }, 79 { 28, 29, "adat", 1, 1 }, 80 { 30, 31, "adat", 1, 1 }, 81 { 32, 33, "adat", 1, 1 }, 82 { 34, 35, "adat", 1, 1 }, 83 84 { 0, 0, NULL, 0, 0 }, 85 }; 86 87 static void 88 hdspe_intr(void *p) 89 { 90 struct sc_info *sc = (struct sc_info *)p; 91 struct sc_pcminfo *scp; 92 device_t *devlist; 93 int devcount, status; 94 int i, err; 95 96 snd_mtxlock(sc->lock); 97 98 status = hdspe_read_1(sc, HDSPE_STATUS_REG); 99 if (status & HDSPE_AUDIO_IRQ_PENDING) { 100 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) 101 return; 102 103 for (i = 0; i < devcount; i++) { 104 scp = device_get_ivars(devlist[i]); 105 if (scp->ih != NULL) 106 scp->ih(scp); 107 } 108 109 hdspe_write_1(sc, HDSPE_INTERRUPT_ACK, 0); 110 free(devlist, M_TEMP); 111 } 112 113 snd_mtxunlock(sc->lock); 114 } 115 116 static void 117 hdspe_dmapsetmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 118 { 119 #if 0 120 struct sc_info *sc = (struct sc_info *)arg; 121 device_printf(sc->dev, "hdspe_dmapsetmap()\n"); 122 #endif 123 } 124 125 static int 126 hdspe_alloc_resources(struct sc_info *sc) 127 { 128 129 /* Allocate resource. */ 130 sc->csid = PCIR_BAR(0); 131 sc->cs = bus_alloc_resource(sc->dev, SYS_RES_MEMORY, 132 &sc->csid, 0, ~0, 1, RF_ACTIVE); 133 134 if (!sc->cs) { 135 device_printf(sc->dev, "Unable to map SYS_RES_MEMORY.\n"); 136 return (ENXIO); 137 } 138 sc->cst = rman_get_bustag(sc->cs); 139 sc->csh = rman_get_bushandle(sc->cs); 140 141 142 /* Allocate interrupt resource. */ 143 sc->irqid = 0; 144 sc->irq = bus_alloc_resource(sc->dev, SYS_RES_IRQ, &sc->irqid, 145 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 146 147 if (!sc->irq || 148 bus_setup_intr(sc->dev, sc->irq, INTR_MPSAFE | INTR_TYPE_AV, 149 NULL, hdspe_intr, sc, &sc->ih)) { 150 device_printf(sc->dev, "Unable to alloc interrupt resource.\n"); 151 return (ENXIO); 152 } 153 154 /* Allocate DMA resources. */ 155 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(sc->dev), 156 /*alignment*/4, 157 /*boundary*/0, 158 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 159 /*highaddr*/BUS_SPACE_MAXADDR, 160 /*filter*/NULL, 161 /*filterarg*/NULL, 162 /*maxsize*/2 * HDSPE_DMASEGSIZE, 163 /*nsegments*/2, 164 /*maxsegsz*/HDSPE_DMASEGSIZE, 165 /*flags*/0, 166 /*lockfunc*/busdma_lock_mutex, 167 /*lockarg*/&Giant, 168 /*dmatag*/&sc->dmat) != 0) { 169 device_printf(sc->dev, "Unable to create dma tag.\n"); 170 return (ENXIO); 171 } 172 173 sc->bufsize = HDSPE_DMASEGSIZE; 174 175 /* pbuf (play buffer). */ 176 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->pbuf, 177 BUS_DMA_NOWAIT, &sc->pmap)) { 178 device_printf(sc->dev, "Can't alloc pbuf.\n"); 179 return (ENXIO); 180 } 181 182 if (bus_dmamap_load(sc->dmat, sc->pmap, sc->pbuf, sc->bufsize, 183 hdspe_dmapsetmap, sc, 0)) { 184 device_printf(sc->dev, "Can't load pbuf.\n"); 185 return (ENXIO); 186 } 187 188 /* rbuf (rec buffer). */ 189 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->rbuf, 190 BUS_DMA_NOWAIT, &sc->rmap)) { 191 device_printf(sc->dev, "Can't alloc rbuf.\n"); 192 return (ENXIO); 193 } 194 195 if (bus_dmamap_load(sc->dmat, sc->rmap, sc->rbuf, sc->bufsize, 196 hdspe_dmapsetmap, sc, 0)) { 197 device_printf(sc->dev, "Can't load rbuf.\n"); 198 return (ENXIO); 199 } 200 201 bzero(sc->pbuf, sc->bufsize); 202 bzero(sc->rbuf, sc->bufsize); 203 204 return (0); 205 } 206 207 static void 208 hdspe_map_dmabuf(struct sc_info *sc) 209 { 210 uint32_t paddr,raddr; 211 int i; 212 213 paddr = vtophys(sc->pbuf); 214 raddr = vtophys(sc->rbuf); 215 216 for (i = 0; i < HDSPE_MAX_SLOTS * 16; i++) { 217 hdspe_write_4(sc, HDSPE_PAGE_ADDR_BUF_OUT + 4 * i, 218 paddr + i * 4096); 219 hdspe_write_4(sc, HDSPE_PAGE_ADDR_BUF_IN + 4 * i, 220 raddr + i * 4096); 221 } 222 } 223 224 static int 225 hdspe_probe(device_t dev) 226 { 227 uint32_t rev; 228 229 if (pci_get_vendor(dev) == PCI_VENDOR_XILINX && 230 pci_get_device(dev) == PCI_DEVICE_XILINX_HDSPE) { 231 rev = pci_get_revid(dev); 232 switch (rev) { 233 case PCI_REVISION_AIO: 234 device_set_desc(dev, "RME HDSPe AIO"); 235 return 0; 236 case PCI_REVISION_RAYDAT: 237 device_set_desc(dev, "RME HDSPe RayDAT"); 238 return 0; 239 } 240 } 241 242 return (ENXIO); 243 } 244 245 static int 246 hdspe_init(struct sc_info *sc) 247 { 248 long long period; 249 250 /* Set defaults. */ 251 sc->ctrl_register |= HDSPM_CLOCK_MODE_MASTER; 252 253 /* Set latency. */ 254 sc->period = 32; 255 sc->ctrl_register = hdspe_encode_latency(7); 256 257 /* Set rate. */ 258 sc->speed = HDSPE_SPEED_DEFAULT; 259 sc->ctrl_register &= ~HDSPE_FREQ_MASK; 260 sc->ctrl_register |= HDSPE_FREQ_MASK_DEFAULT; 261 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); 262 263 switch (sc->type) { 264 case RAYDAT: 265 case AIO: 266 period = HDSPE_FREQ_AIO; 267 break; 268 default: 269 return (ENXIO); 270 } 271 272 /* Set DDS value. */ 273 period /= sc->speed; 274 hdspe_write_4(sc, HDSPE_FREQ_REG, period); 275 276 /* Other settings. */ 277 sc->settings_register = 0; 278 hdspe_write_4(sc, HDSPE_SETTINGS_REG, sc->settings_register); 279 280 return 0; 281 } 282 283 static int 284 hdspe_attach(device_t dev) 285 { 286 struct sc_info *sc; 287 struct sc_pcminfo *scp; 288 struct hdspe_channel *chan_map; 289 uint32_t rev; 290 int i, err; 291 292 #if 0 293 device_printf(dev, "hdspe_attach()\n"); 294 #endif 295 296 sc = device_get_softc(dev); 297 sc->lock = snd_mtxcreate(device_get_nameunit(dev), 298 "snd_hdspe softc"); 299 sc->dev = dev; 300 301 pci_enable_busmaster(dev); 302 rev = pci_get_revid(dev); 303 switch (rev) { 304 case PCI_REVISION_AIO: 305 sc->type = AIO; 306 chan_map = chan_map_aio; 307 break; 308 case PCI_REVISION_RAYDAT: 309 sc->type = RAYDAT; 310 chan_map = chan_map_rd; 311 break; 312 default: 313 return ENXIO; 314 } 315 316 /* Allocate resources. */ 317 err = hdspe_alloc_resources(sc); 318 if (err) { 319 device_printf(dev, "Unable to allocate system resources.\n"); 320 return ENXIO; 321 } 322 323 if (hdspe_init(sc) != 0) 324 return ENXIO; 325 326 for (i = 0; i < HDSPE_MAX_CHANS && chan_map[i].descr != NULL; i++) { 327 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 328 scp->hc = &chan_map[i]; 329 scp->sc = sc; 330 scp->dev = device_add_child(dev, "pcm", -1); 331 device_set_ivars(scp->dev, scp); 332 } 333 334 hdspe_map_dmabuf(sc); 335 336 return (bus_generic_attach(dev)); 337 } 338 339 static void 340 hdspe_dmafree(struct sc_info *sc) 341 { 342 343 bus_dmamap_unload(sc->dmat, sc->rmap); 344 bus_dmamap_unload(sc->dmat, sc->pmap); 345 bus_dmamem_free(sc->dmat, sc->rbuf, sc->rmap); 346 bus_dmamem_free(sc->dmat, sc->pbuf, sc->pmap); 347 sc->rmap = sc->pmap = NULL; 348 sc->rbuf = sc->pbuf = NULL; 349 } 350 351 static int 352 hdspe_detach(device_t dev) 353 { 354 struct sc_info *sc; 355 int err; 356 357 sc = device_get_softc(dev); 358 if (sc == NULL) { 359 device_printf(dev,"Can't detach: softc is null.\n"); 360 return 0; 361 } 362 363 err = device_delete_children(dev); 364 if (err) 365 return (err); 366 367 hdspe_dmafree(sc); 368 369 if (sc->ih) 370 bus_teardown_intr(dev, sc->irq, sc->ih); 371 if (sc->dmat) 372 bus_dma_tag_destroy(sc->dmat); 373 if (sc->irq) 374 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 375 if (sc->cs) 376 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->cs); 377 if (sc->lock) 378 snd_mtxfree(sc->lock); 379 380 return 0; 381 } 382 383 static device_method_t hdspe_methods[] = { 384 DEVMETHOD(device_probe, hdspe_probe), 385 DEVMETHOD(device_attach, hdspe_attach), 386 DEVMETHOD(device_detach, hdspe_detach), 387 { 0, 0 } 388 }; 389 390 static driver_t hdspe_driver = { 391 "hdspe", 392 hdspe_methods, 393 PCM_SOFTC_SIZE, 394 }; 395 396 static devclass_t hdspe_devclass; 397 398 DRIVER_MODULE(snd_hdspe, pci, hdspe_driver, hdspe_devclass, 0, 0); 399