1 /*- 2 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * RME HDSPe driver for FreeBSD. 29 * Supported cards: AIO, RayDAT. 30 */ 31 32 #include <dev/sound/pcm/sound.h> 33 #include <dev/sound/pci/hdspe.h> 34 #include <dev/sound/chip.h> 35 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 39 #include <mixer_if.h> 40 41 SND_DECLARE_FILE("$FreeBSD$"); 42 43 static struct hdspe_channel chan_map_aio[] = { 44 { 0, 1, "line", 1, 1 }, 45 { 6, 7, "phone", 1, 0 }, 46 { 8, 9, "aes", 1, 1 }, 47 { 10, 11, "s/pdif", 1, 1 }, 48 { 12, 16, "adat", 1, 1 }, 49 50 /* Single or double speed. */ 51 { 14, 18, "adat", 1, 1 }, 52 53 /* Single speed only. */ 54 { 13, 15, "adat", 1, 1 }, 55 { 17, 19, "adat", 1, 1 }, 56 57 { 0, 0, NULL, 0, 0 }, 58 }; 59 60 static struct hdspe_channel chan_map_rd[] = { 61 { 0, 1, "aes", 1, 1 }, 62 { 2, 3, "s/pdif", 1, 1 }, 63 { 4, 5, "adat", 1, 1 }, 64 { 6, 7, "adat", 1, 1 }, 65 { 8, 9, "adat", 1, 1 }, 66 { 10, 11, "adat", 1, 1 }, 67 68 /* Single or double speed. */ 69 { 12, 13, "adat", 1, 1 }, 70 { 14, 15, "adat", 1, 1 }, 71 { 16, 17, "adat", 1, 1 }, 72 { 18, 19, "adat", 1, 1 }, 73 74 /* Single speed only. */ 75 { 20, 21, "adat", 1, 1 }, 76 { 22, 23, "adat", 1, 1 }, 77 { 24, 25, "adat", 1, 1 }, 78 { 26, 27, "adat", 1, 1 }, 79 { 28, 29, "adat", 1, 1 }, 80 { 30, 31, "adat", 1, 1 }, 81 { 32, 33, "adat", 1, 1 }, 82 { 34, 35, "adat", 1, 1 }, 83 84 { 0, 0, NULL, 0, 0 }, 85 }; 86 87 static void 88 hdspe_intr(void *p) 89 { 90 struct sc_pcminfo *scp; 91 struct sc_info *sc; 92 device_t *devlist; 93 int devcount; 94 int status; 95 int err; 96 int i; 97 98 sc = (struct sc_info *)p; 99 100 snd_mtxlock(sc->lock); 101 102 status = hdspe_read_1(sc, HDSPE_STATUS_REG); 103 if (status & HDSPE_AUDIO_IRQ_PENDING) { 104 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) 105 return; 106 107 for (i = 0; i < devcount; i++) { 108 scp = device_get_ivars(devlist[i]); 109 if (scp->ih != NULL) 110 scp->ih(scp); 111 } 112 113 hdspe_write_1(sc, HDSPE_INTERRUPT_ACK, 0); 114 free(devlist, M_TEMP); 115 } 116 117 snd_mtxunlock(sc->lock); 118 } 119 120 static void 121 hdspe_dmapsetmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 122 { 123 struct sc_info *sc; 124 125 sc = (struct sc_info *)arg; 126 127 #if 0 128 device_printf(sc->dev, "hdspe_dmapsetmap()\n"); 129 #endif 130 } 131 132 static int 133 hdspe_alloc_resources(struct sc_info *sc) 134 { 135 136 /* Allocate resource. */ 137 sc->csid = PCIR_BAR(0); 138 sc->cs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 139 &sc->csid, RF_ACTIVE); 140 141 if (!sc->cs) { 142 device_printf(sc->dev, "Unable to map SYS_RES_MEMORY.\n"); 143 return (ENXIO); 144 } 145 146 sc->cst = rman_get_bustag(sc->cs); 147 sc->csh = rman_get_bushandle(sc->cs); 148 149 /* Allocate interrupt resource. */ 150 sc->irqid = 0; 151 sc->irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irqid, 152 RF_ACTIVE | RF_SHAREABLE); 153 154 if (!sc->irq || 155 bus_setup_intr(sc->dev, sc->irq, INTR_MPSAFE | INTR_TYPE_AV, 156 NULL, hdspe_intr, sc, &sc->ih)) { 157 device_printf(sc->dev, "Unable to alloc interrupt resource.\n"); 158 return (ENXIO); 159 } 160 161 /* Allocate DMA resources. */ 162 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(sc->dev), 163 /*alignment*/4, 164 /*boundary*/0, 165 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 166 /*highaddr*/BUS_SPACE_MAXADDR, 167 /*filter*/NULL, 168 /*filterarg*/NULL, 169 /*maxsize*/2 * HDSPE_DMASEGSIZE, 170 /*nsegments*/2, 171 /*maxsegsz*/HDSPE_DMASEGSIZE, 172 /*flags*/0, 173 /*lockfunc*/busdma_lock_mutex, 174 /*lockarg*/&Giant, 175 /*dmatag*/&sc->dmat) != 0) { 176 device_printf(sc->dev, "Unable to create dma tag.\n"); 177 return (ENXIO); 178 } 179 180 sc->bufsize = HDSPE_DMASEGSIZE; 181 182 /* pbuf (play buffer). */ 183 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->pbuf, 184 BUS_DMA_NOWAIT, &sc->pmap)) { 185 device_printf(sc->dev, "Can't alloc pbuf.\n"); 186 return (ENXIO); 187 } 188 189 if (bus_dmamap_load(sc->dmat, sc->pmap, sc->pbuf, sc->bufsize, 190 hdspe_dmapsetmap, sc, 0)) { 191 device_printf(sc->dev, "Can't load pbuf.\n"); 192 return (ENXIO); 193 } 194 195 /* rbuf (rec buffer). */ 196 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->rbuf, 197 BUS_DMA_NOWAIT, &sc->rmap)) { 198 device_printf(sc->dev, "Can't alloc rbuf.\n"); 199 return (ENXIO); 200 } 201 202 if (bus_dmamap_load(sc->dmat, sc->rmap, sc->rbuf, sc->bufsize, 203 hdspe_dmapsetmap, sc, 0)) { 204 device_printf(sc->dev, "Can't load rbuf.\n"); 205 return (ENXIO); 206 } 207 208 bzero(sc->pbuf, sc->bufsize); 209 bzero(sc->rbuf, sc->bufsize); 210 211 return (0); 212 } 213 214 static void 215 hdspe_map_dmabuf(struct sc_info *sc) 216 { 217 uint32_t paddr, raddr; 218 int i; 219 220 paddr = vtophys(sc->pbuf); 221 raddr = vtophys(sc->rbuf); 222 223 for (i = 0; i < HDSPE_MAX_SLOTS * 16; i++) { 224 hdspe_write_4(sc, HDSPE_PAGE_ADDR_BUF_OUT + 4 * i, 225 paddr + i * 4096); 226 hdspe_write_4(sc, HDSPE_PAGE_ADDR_BUF_IN + 4 * i, 227 raddr + i * 4096); 228 } 229 } 230 231 static int 232 hdspe_probe(device_t dev) 233 { 234 uint32_t rev; 235 236 if (pci_get_vendor(dev) == PCI_VENDOR_XILINX && 237 pci_get_device(dev) == PCI_DEVICE_XILINX_HDSPE) { 238 rev = pci_get_revid(dev); 239 switch (rev) { 240 case PCI_REVISION_AIO: 241 device_set_desc(dev, "RME HDSPe AIO"); 242 return (0); 243 case PCI_REVISION_RAYDAT: 244 device_set_desc(dev, "RME HDSPe RayDAT"); 245 return (0); 246 } 247 } 248 249 return (ENXIO); 250 } 251 252 static int 253 hdspe_init(struct sc_info *sc) 254 { 255 long long period; 256 257 /* Set defaults. */ 258 sc->ctrl_register |= HDSPM_CLOCK_MODE_MASTER; 259 260 /* Set latency. */ 261 sc->period = 32; 262 sc->ctrl_register = hdspe_encode_latency(7); 263 264 /* Set rate. */ 265 sc->speed = HDSPE_SPEED_DEFAULT; 266 sc->ctrl_register &= ~HDSPE_FREQ_MASK; 267 sc->ctrl_register |= HDSPE_FREQ_MASK_DEFAULT; 268 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); 269 270 switch (sc->type) { 271 case RAYDAT: 272 case AIO: 273 period = HDSPE_FREQ_AIO; 274 break; 275 default: 276 return (ENXIO); 277 } 278 279 /* Set DDS value. */ 280 period /= sc->speed; 281 hdspe_write_4(sc, HDSPE_FREQ_REG, period); 282 283 /* Other settings. */ 284 sc->settings_register = 0; 285 hdspe_write_4(sc, HDSPE_SETTINGS_REG, sc->settings_register); 286 287 return (0); 288 } 289 290 static int 291 hdspe_attach(device_t dev) 292 { 293 struct hdspe_channel *chan_map; 294 struct sc_pcminfo *scp; 295 struct sc_info *sc; 296 uint32_t rev; 297 int i, err; 298 299 #if 0 300 device_printf(dev, "hdspe_attach()\n"); 301 #endif 302 303 sc = device_get_softc(dev); 304 sc->lock = snd_mtxcreate(device_get_nameunit(dev), 305 "snd_hdspe softc"); 306 sc->dev = dev; 307 308 pci_enable_busmaster(dev); 309 rev = pci_get_revid(dev); 310 switch (rev) { 311 case PCI_REVISION_AIO: 312 sc->type = AIO; 313 chan_map = chan_map_aio; 314 break; 315 case PCI_REVISION_RAYDAT: 316 sc->type = RAYDAT; 317 chan_map = chan_map_rd; 318 break; 319 default: 320 return (ENXIO); 321 } 322 323 /* Allocate resources. */ 324 err = hdspe_alloc_resources(sc); 325 if (err) { 326 device_printf(dev, "Unable to allocate system resources.\n"); 327 return (ENXIO); 328 } 329 330 if (hdspe_init(sc) != 0) 331 return (ENXIO); 332 333 for (i = 0; i < HDSPE_MAX_CHANS && chan_map[i].descr != NULL; i++) { 334 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 335 scp->hc = &chan_map[i]; 336 scp->sc = sc; 337 scp->dev = device_add_child(dev, "pcm", -1); 338 device_set_ivars(scp->dev, scp); 339 } 340 341 hdspe_map_dmabuf(sc); 342 343 return (bus_generic_attach(dev)); 344 } 345 346 static void 347 hdspe_dmafree(struct sc_info *sc) 348 { 349 350 bus_dmamap_unload(sc->dmat, sc->rmap); 351 bus_dmamap_unload(sc->dmat, sc->pmap); 352 bus_dmamem_free(sc->dmat, sc->rbuf, sc->rmap); 353 bus_dmamem_free(sc->dmat, sc->pbuf, sc->pmap); 354 sc->rbuf = sc->pbuf = NULL; 355 } 356 357 static int 358 hdspe_detach(device_t dev) 359 { 360 struct sc_info *sc; 361 int err; 362 363 sc = device_get_softc(dev); 364 if (sc == NULL) { 365 device_printf(dev,"Can't detach: softc is null.\n"); 366 return (0); 367 } 368 369 err = device_delete_children(dev); 370 if (err) 371 return (err); 372 373 hdspe_dmafree(sc); 374 375 if (sc->ih) 376 bus_teardown_intr(dev, sc->irq, sc->ih); 377 if (sc->dmat) 378 bus_dma_tag_destroy(sc->dmat); 379 if (sc->irq) 380 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 381 if (sc->cs) 382 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->cs); 383 if (sc->lock) 384 snd_mtxfree(sc->lock); 385 386 return (0); 387 } 388 389 static device_method_t hdspe_methods[] = { 390 DEVMETHOD(device_probe, hdspe_probe), 391 DEVMETHOD(device_attach, hdspe_attach), 392 DEVMETHOD(device_detach, hdspe_detach), 393 { 0, 0 } 394 }; 395 396 static driver_t hdspe_driver = { 397 "hdspe", 398 hdspe_methods, 399 PCM_SOFTC_SIZE, 400 }; 401 402 static devclass_t hdspe_devclass; 403 404 DRIVER_MODULE(snd_hdspe, pci, hdspe_driver, hdspe_devclass, 0, 0); 405