1 /*- 2 * Copyright (c) 2012 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * RME HDSPe driver for FreeBSD. 29 * Supported cards: AIO, RayDAT. 30 */ 31 32 #include <dev/sound/pcm/sound.h> 33 #include <dev/sound/pci/hdspe.h> 34 #include <dev/sound/chip.h> 35 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 39 #include <mixer_if.h> 40 41 SND_DECLARE_FILE("$FreeBSD$"); 42 43 static struct hdspe_channel chan_map_aio[] = { 44 { 0, 1, "line", 1, 1 }, 45 { 6, 7, "phone", 1, 0 }, 46 { 8, 9, "aes", 1, 1 }, 47 { 10, 11, "s/pdif", 1, 1 }, 48 { 12, 16, "adat", 1, 1 }, 49 50 /* Single or double speed. */ 51 { 14, 18, "adat", 1, 1 }, 52 53 /* Single speed only. */ 54 { 13, 15, "adat", 1, 1 }, 55 { 17, 19, "adat", 1, 1 }, 56 57 { 0, 0, NULL, 0, 0 }, 58 }; 59 60 static struct hdspe_channel chan_map_rd[] = { 61 { 0, 1, "aes", 1, 1 }, 62 { 2, 3, "s/pdif", 1, 1 }, 63 { 4, 5, "adat", 1, 1 }, 64 { 6, 7, "adat", 1, 1 }, 65 { 8, 9, "adat", 1, 1 }, 66 { 10, 11, "adat", 1, 1 }, 67 68 /* Single or double speed. */ 69 { 12, 13, "adat", 1, 1 }, 70 { 14, 15, "adat", 1, 1 }, 71 { 16, 17, "adat", 1, 1 }, 72 { 18, 19, "adat", 1, 1 }, 73 74 /* Single speed only. */ 75 { 20, 21, "adat", 1, 1 }, 76 { 22, 23, "adat", 1, 1 }, 77 { 24, 25, "adat", 1, 1 }, 78 { 26, 27, "adat", 1, 1 }, 79 { 28, 29, "adat", 1, 1 }, 80 { 30, 31, "adat", 1, 1 }, 81 { 32, 33, "adat", 1, 1 }, 82 { 34, 35, "adat", 1, 1 }, 83 84 { 0, 0, NULL, 0, 0 }, 85 }; 86 87 static void 88 hdspe_intr(void *p) 89 { 90 struct sc_info *sc = (struct sc_info *)p; 91 struct sc_pcminfo *scp; 92 device_t *devlist; 93 int devcount, status; 94 int i, err; 95 96 snd_mtxlock(sc->lock); 97 98 status = hdspe_read_1(sc, HDSPE_STATUS_REG); 99 if (status & HDSPE_AUDIO_IRQ_PENDING) { 100 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) 101 return; 102 103 for (i = 0; i < devcount; i++) { 104 scp = device_get_ivars(devlist[i]); 105 if (scp->ih != NULL) 106 scp->ih(scp); 107 } 108 109 hdspe_write_1(sc, HDSPE_INTERRUPT_ACK, 0); 110 } 111 112 snd_mtxunlock(sc->lock); 113 } 114 115 static void 116 hdspe_dmapsetmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 117 { 118 #if 0 119 struct sc_info *sc = (struct sc_info *)arg; 120 device_printf(sc->dev, "hdspe_dmapsetmap()\n"); 121 #endif 122 } 123 124 static int 125 hdspe_alloc_resources(struct sc_info *sc) 126 { 127 128 /* Allocate resource. */ 129 sc->csid = PCIR_BAR(0); 130 sc->cs = bus_alloc_resource(sc->dev, SYS_RES_MEMORY, 131 &sc->csid, 0, ~0, 1, RF_ACTIVE); 132 133 if (!sc->cs) { 134 device_printf(sc->dev, "Unable to map SYS_RES_MEMORY.\n"); 135 return (ENXIO); 136 } 137 sc->cst = rman_get_bustag(sc->cs); 138 sc->csh = rman_get_bushandle(sc->cs); 139 140 141 /* Allocate interrupt resource. */ 142 sc->irqid = 0; 143 sc->irq = bus_alloc_resource(sc->dev, SYS_RES_IRQ, &sc->irqid, 144 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 145 146 if (!sc->irq || 147 bus_setup_intr(sc->dev, sc->irq, INTR_MPSAFE | INTR_TYPE_AV, 148 NULL, hdspe_intr, sc, &sc->ih)) { 149 device_printf(sc->dev, "Unable to alloc interrupt resource.\n"); 150 return (ENXIO); 151 } 152 153 /* Allocate DMA resources. */ 154 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(sc->dev), 155 /*alignment*/4, 156 /*boundary*/0, 157 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 158 /*highaddr*/BUS_SPACE_MAXADDR, 159 /*filter*/NULL, 160 /*filterarg*/NULL, 161 /*maxsize*/2 * HDSPE_DMASEGSIZE, 162 /*nsegments*/2, 163 /*maxsegsz*/HDSPE_DMASEGSIZE, 164 /*flags*/0, 165 /*lockfunc*/busdma_lock_mutex, 166 /*lockarg*/&Giant, 167 /*dmatag*/&sc->dmat) != 0) { 168 device_printf(sc->dev, "Unable to create dma tag.\n"); 169 return (ENXIO); 170 } 171 172 sc->bufsize = HDSPE_DMASEGSIZE; 173 174 /* pbuf (play buffer). */ 175 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->pbuf, 176 BUS_DMA_NOWAIT, &sc->pmap)) { 177 device_printf(sc->dev, "Can't alloc pbuf.\n"); 178 return (ENXIO); 179 } 180 181 if (bus_dmamap_load(sc->dmat, sc->pmap, sc->pbuf, sc->bufsize, 182 hdspe_dmapsetmap, sc, 0)) { 183 device_printf(sc->dev, "Can't load pbuf.\n"); 184 return (ENXIO); 185 } 186 187 /* rbuf (rec buffer). */ 188 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->rbuf, 189 BUS_DMA_NOWAIT, &sc->rmap)) { 190 device_printf(sc->dev, "Can't alloc rbuf.\n"); 191 return (ENXIO); 192 } 193 194 if (bus_dmamap_load(sc->dmat, sc->rmap, sc->rbuf, sc->bufsize, 195 hdspe_dmapsetmap, sc, 0)) { 196 device_printf(sc->dev, "Can't load rbuf.\n"); 197 return (ENXIO); 198 } 199 200 bzero(sc->pbuf, sc->bufsize); 201 bzero(sc->rbuf, sc->bufsize); 202 203 return (0); 204 } 205 206 static void 207 hdspe_map_dmabuf(struct sc_info *sc) 208 { 209 uint32_t paddr,raddr; 210 int i; 211 212 paddr = vtophys(sc->pbuf); 213 raddr = vtophys(sc->rbuf); 214 215 for (i = 0; i < HDSPE_MAX_SLOTS * 16; i++) { 216 hdspe_write_4(sc, HDSPE_PAGE_ADDR_BUF_OUT + 4 * i, 217 paddr + i * 4096); 218 hdspe_write_4(sc, HDSPE_PAGE_ADDR_BUF_IN + 4 * i, 219 raddr + i * 4096); 220 } 221 } 222 223 static int 224 hdspe_probe(device_t dev) 225 { 226 uint32_t rev; 227 228 if (pci_get_vendor(dev) == PCI_VENDOR_XILINX && 229 pci_get_device(dev) == PCI_DEVICE_XILINX_HDSPE) { 230 rev = pci_get_revid(dev); 231 switch (rev) { 232 case PCI_REVISION_AIO: 233 device_set_desc(dev, "RME HDSPe AIO"); 234 return 0; 235 case PCI_REVISION_RAYDAT: 236 device_set_desc(dev, "RME HDSPe RayDAT"); 237 return 0; 238 } 239 } 240 241 return (ENXIO); 242 } 243 244 static int 245 set_pci_config(device_t dev) 246 { 247 uint32_t data; 248 249 pci_enable_busmaster(dev); 250 251 data = pci_get_revid(dev); 252 data |= PCIM_CMD_PORTEN; 253 pci_write_config(dev, PCIR_COMMAND, data, 2); 254 255 return 0; 256 } 257 258 static int 259 hdspe_init(struct sc_info *sc) 260 { 261 long long period; 262 263 /* Set defaults. */ 264 sc->ctrl_register |= HDSPM_CLOCK_MODE_MASTER; 265 266 /* Set latency. */ 267 sc->period = 32; 268 sc->ctrl_register = hdspe_encode_latency(7); 269 270 /* Set rate. */ 271 sc->speed = HDSPE_SPEED_DEFAULT; 272 sc->ctrl_register &= ~HDSPE_FREQ_MASK; 273 sc->ctrl_register |= HDSPE_FREQ_MASK_DEFAULT; 274 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); 275 276 switch (sc->type) { 277 case RAYDAT: 278 case AIO: 279 period = HDSPE_FREQ_AIO; 280 break; 281 default: 282 return (ENXIO); 283 } 284 285 /* Set DDS value. */ 286 period /= sc->speed; 287 hdspe_write_4(sc, HDSPE_FREQ_REG, period); 288 289 /* Other settings. */ 290 sc->settings_register = 0; 291 hdspe_write_4(sc, HDSPE_SETTINGS_REG, sc->settings_register); 292 293 return 0; 294 } 295 296 static int 297 hdspe_attach(device_t dev) 298 { 299 struct sc_info *sc; 300 struct sc_pcminfo *scp; 301 struct hdspe_channel *chan_map; 302 uint32_t rev; 303 int i, err; 304 305 #if 0 306 device_printf(dev, "hdspe_attach()\n"); 307 #endif 308 309 set_pci_config(dev); 310 311 sc = device_get_softc(dev); 312 sc->lock = snd_mtxcreate(device_get_nameunit(dev), 313 "snd_hdspe softc"); 314 sc->dev = dev; 315 316 rev = pci_get_revid(dev); 317 switch (rev) { 318 case PCI_REVISION_AIO: 319 sc->type = AIO; 320 chan_map = chan_map_aio; 321 break; 322 case PCI_REVISION_RAYDAT: 323 sc->type = RAYDAT; 324 chan_map = chan_map_rd; 325 break; 326 default: 327 return ENXIO; 328 } 329 330 /* Allocate resources. */ 331 err = hdspe_alloc_resources(sc); 332 if (err) { 333 device_printf(dev, "Unable to allocate system resources.\n"); 334 return ENXIO; 335 } 336 337 if (hdspe_init(sc) != 0) 338 return ENXIO; 339 340 for (i = 0; i < HDSPE_MAX_CHANS && chan_map[i].descr != NULL; i++) { 341 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 342 scp->hc = &chan_map[i]; 343 scp->sc = sc; 344 scp->dev = device_add_child(dev, "pcm", -1); 345 device_set_ivars(scp->dev, scp); 346 } 347 348 hdspe_map_dmabuf(sc); 349 350 return 0; 351 } 352 353 static void 354 hdspe_dmafree(struct sc_info *sc) 355 { 356 357 bus_dmamap_unload(sc->dmat, sc->rmap); 358 bus_dmamap_unload(sc->dmat, sc->pmap); 359 bus_dmamem_free(sc->dmat, sc->rbuf, sc->rmap); 360 bus_dmamem_free(sc->dmat, sc->pbuf, sc->pmap); 361 sc->rmap = sc->pmap = NULL; 362 sc->rbuf = sc->pbuf = NULL; 363 } 364 365 static int 366 hdspe_detach(device_t dev) 367 { 368 struct sc_info *sc; 369 int err; 370 371 sc = device_get_softc(dev); 372 if (sc == NULL) { 373 device_printf(dev,"Can't detach: softc is null.\n"); 374 return 0; 375 } 376 377 err = device_delete_children(dev); 378 if (err) 379 return (err); 380 381 hdspe_dmafree(sc); 382 383 if (sc->ih) 384 bus_teardown_intr(dev, sc->irq, sc->ih); 385 if (sc->dmat) 386 bus_dma_tag_destroy(sc->dmat); 387 if (sc->irq) 388 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 389 if (sc->cs) 390 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->cs); 391 if (sc->lock) 392 snd_mtxfree(sc->lock); 393 394 return 0; 395 } 396 397 static device_method_t hdspe_methods[] = { 398 DEVMETHOD(device_probe, hdspe_probe), 399 DEVMETHOD(device_attach, hdspe_attach), 400 DEVMETHOD(device_detach, hdspe_detach), 401 { 0, 0 } 402 }; 403 404 static driver_t hdspe_driver = { 405 "hdspe", 406 hdspe_methods, 407 PCM_SOFTC_SIZE, 408 }; 409 410 DRIVER_MODULE(snd_hdspe, pci, hdspe_driver, pcm_devclass, 0, 0); 411