1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * RME HDSPe driver for FreeBSD. 31 * Supported cards: AIO, RayDAT. 32 */ 33 34 #include <dev/sound/pcm/sound.h> 35 #include <dev/sound/pci/hdspe.h> 36 #include <dev/sound/chip.h> 37 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <mixer_if.h> 42 43 static struct hdspe_channel chan_map_aio[] = { 44 { 0, 1, "line", 1, 1 }, 45 { 6, 7, "phone", 1, 0 }, 46 { 8, 9, "aes", 1, 1 }, 47 { 10, 11, "s/pdif", 1, 1 }, 48 { 12, 16, "adat", 1, 1 }, 49 50 /* Single or double speed. */ 51 { 14, 18, "adat", 1, 1 }, 52 53 /* Single speed only. */ 54 { 13, 15, "adat", 1, 1 }, 55 { 17, 19, "adat", 1, 1 }, 56 57 { 0, 0, NULL, 0, 0 }, 58 }; 59 60 static struct hdspe_channel chan_map_rd[] = { 61 { 0, 1, "aes", 1, 1 }, 62 { 2, 3, "s/pdif", 1, 1 }, 63 { 4, 5, "adat", 1, 1 }, 64 { 6, 7, "adat", 1, 1 }, 65 { 8, 9, "adat", 1, 1 }, 66 { 10, 11, "adat", 1, 1 }, 67 68 /* Single or double speed. */ 69 { 12, 13, "adat", 1, 1 }, 70 { 14, 15, "adat", 1, 1 }, 71 { 16, 17, "adat", 1, 1 }, 72 { 18, 19, "adat", 1, 1 }, 73 74 /* Single speed only. */ 75 { 20, 21, "adat", 1, 1 }, 76 { 22, 23, "adat", 1, 1 }, 77 { 24, 25, "adat", 1, 1 }, 78 { 26, 27, "adat", 1, 1 }, 79 { 28, 29, "adat", 1, 1 }, 80 { 30, 31, "adat", 1, 1 }, 81 { 32, 33, "adat", 1, 1 }, 82 { 34, 35, "adat", 1, 1 }, 83 84 { 0, 0, NULL, 0, 0 }, 85 }; 86 87 static void 88 hdspe_intr(void *p) 89 { 90 struct sc_pcminfo *scp; 91 struct sc_info *sc; 92 device_t *devlist; 93 int devcount; 94 int status; 95 int err; 96 int i; 97 98 sc = (struct sc_info *)p; 99 100 snd_mtxlock(sc->lock); 101 102 status = hdspe_read_1(sc, HDSPE_STATUS_REG); 103 if (status & HDSPE_AUDIO_IRQ_PENDING) { 104 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) 105 return; 106 107 for (i = 0; i < devcount; i++) { 108 scp = device_get_ivars(devlist[i]); 109 if (scp->ih != NULL) 110 scp->ih(scp); 111 } 112 113 hdspe_write_1(sc, HDSPE_INTERRUPT_ACK, 0); 114 free(devlist, M_TEMP); 115 } 116 117 snd_mtxunlock(sc->lock); 118 } 119 120 static void 121 hdspe_dmapsetmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 122 { 123 #if 0 124 device_printf(sc->dev, "hdspe_dmapsetmap()\n"); 125 #endif 126 } 127 128 static int 129 hdspe_alloc_resources(struct sc_info *sc) 130 { 131 132 /* Allocate resource. */ 133 sc->csid = PCIR_BAR(0); 134 sc->cs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 135 &sc->csid, RF_ACTIVE); 136 137 if (!sc->cs) { 138 device_printf(sc->dev, "Unable to map SYS_RES_MEMORY.\n"); 139 return (ENXIO); 140 } 141 142 sc->cst = rman_get_bustag(sc->cs); 143 sc->csh = rman_get_bushandle(sc->cs); 144 145 /* Allocate interrupt resource. */ 146 sc->irqid = 0; 147 sc->irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irqid, 148 RF_ACTIVE | RF_SHAREABLE); 149 150 if (!sc->irq || 151 bus_setup_intr(sc->dev, sc->irq, INTR_MPSAFE | INTR_TYPE_AV, 152 NULL, hdspe_intr, sc, &sc->ih)) { 153 device_printf(sc->dev, "Unable to alloc interrupt resource.\n"); 154 return (ENXIO); 155 } 156 157 /* Allocate DMA resources. */ 158 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(sc->dev), 159 /*alignment*/4, 160 /*boundary*/0, 161 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 162 /*highaddr*/BUS_SPACE_MAXADDR, 163 /*filter*/NULL, 164 /*filterarg*/NULL, 165 /*maxsize*/2 * HDSPE_DMASEGSIZE, 166 /*nsegments*/2, 167 /*maxsegsz*/HDSPE_DMASEGSIZE, 168 /*flags*/0, 169 /*lockfunc*/NULL, 170 /*lockarg*/NULL, 171 /*dmatag*/&sc->dmat) != 0) { 172 device_printf(sc->dev, "Unable to create dma tag.\n"); 173 return (ENXIO); 174 } 175 176 sc->bufsize = HDSPE_DMASEGSIZE; 177 178 /* pbuf (play buffer). */ 179 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->pbuf, BUS_DMA_WAITOK, 180 &sc->pmap)) { 181 device_printf(sc->dev, "Can't alloc pbuf.\n"); 182 return (ENXIO); 183 } 184 185 if (bus_dmamap_load(sc->dmat, sc->pmap, sc->pbuf, sc->bufsize, 186 hdspe_dmapsetmap, sc, BUS_DMA_NOWAIT)) { 187 device_printf(sc->dev, "Can't load pbuf.\n"); 188 return (ENXIO); 189 } 190 191 /* rbuf (rec buffer). */ 192 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->rbuf, BUS_DMA_WAITOK, 193 &sc->rmap)) { 194 device_printf(sc->dev, "Can't alloc rbuf.\n"); 195 return (ENXIO); 196 } 197 198 if (bus_dmamap_load(sc->dmat, sc->rmap, sc->rbuf, sc->bufsize, 199 hdspe_dmapsetmap, sc, BUS_DMA_NOWAIT)) { 200 device_printf(sc->dev, "Can't load rbuf.\n"); 201 return (ENXIO); 202 } 203 204 bzero(sc->pbuf, sc->bufsize); 205 bzero(sc->rbuf, sc->bufsize); 206 207 return (0); 208 } 209 210 static void 211 hdspe_map_dmabuf(struct sc_info *sc) 212 { 213 uint32_t paddr, raddr; 214 int i; 215 216 paddr = vtophys(sc->pbuf); 217 raddr = vtophys(sc->rbuf); 218 219 for (i = 0; i < HDSPE_MAX_SLOTS * 16; i++) { 220 hdspe_write_4(sc, HDSPE_PAGE_ADDR_BUF_OUT + 4 * i, 221 paddr + i * 4096); 222 hdspe_write_4(sc, HDSPE_PAGE_ADDR_BUF_IN + 4 * i, 223 raddr + i * 4096); 224 } 225 } 226 227 static int 228 hdspe_probe(device_t dev) 229 { 230 uint32_t rev; 231 232 if (pci_get_vendor(dev) == PCI_VENDOR_XILINX && 233 pci_get_device(dev) == PCI_DEVICE_XILINX_HDSPE) { 234 rev = pci_get_revid(dev); 235 switch (rev) { 236 case PCI_REVISION_AIO: 237 device_set_desc(dev, "RME HDSPe AIO"); 238 return (0); 239 case PCI_REVISION_RAYDAT: 240 device_set_desc(dev, "RME HDSPe RayDAT"); 241 return (0); 242 } 243 } 244 245 return (ENXIO); 246 } 247 248 static int 249 hdspe_init(struct sc_info *sc) 250 { 251 long long period; 252 253 /* Set defaults. */ 254 sc->ctrl_register |= HDSPM_CLOCK_MODE_MASTER; 255 256 /* Set latency. */ 257 sc->period = 32; 258 sc->ctrl_register = hdspe_encode_latency(7); 259 260 /* Set rate. */ 261 sc->speed = HDSPE_SPEED_DEFAULT; 262 sc->ctrl_register &= ~HDSPE_FREQ_MASK; 263 sc->ctrl_register |= HDSPE_FREQ_MASK_DEFAULT; 264 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); 265 266 switch (sc->type) { 267 case RAYDAT: 268 case AIO: 269 period = HDSPE_FREQ_AIO; 270 break; 271 default: 272 return (ENXIO); 273 } 274 275 /* Set DDS value. */ 276 period /= sc->speed; 277 hdspe_write_4(sc, HDSPE_FREQ_REG, period); 278 279 /* Other settings. */ 280 sc->settings_register = 0; 281 hdspe_write_4(sc, HDSPE_SETTINGS_REG, sc->settings_register); 282 283 return (0); 284 } 285 286 static int 287 hdspe_attach(device_t dev) 288 { 289 struct hdspe_channel *chan_map; 290 struct sc_pcminfo *scp; 291 struct sc_info *sc; 292 uint32_t rev; 293 int i, err; 294 295 #if 0 296 device_printf(dev, "hdspe_attach()\n"); 297 #endif 298 299 sc = device_get_softc(dev); 300 sc->lock = snd_mtxcreate(device_get_nameunit(dev), 301 "snd_hdspe softc"); 302 sc->dev = dev; 303 304 pci_enable_busmaster(dev); 305 rev = pci_get_revid(dev); 306 switch (rev) { 307 case PCI_REVISION_AIO: 308 sc->type = AIO; 309 chan_map = chan_map_aio; 310 break; 311 case PCI_REVISION_RAYDAT: 312 sc->type = RAYDAT; 313 chan_map = chan_map_rd; 314 break; 315 default: 316 return (ENXIO); 317 } 318 319 /* Allocate resources. */ 320 err = hdspe_alloc_resources(sc); 321 if (err) { 322 device_printf(dev, "Unable to allocate system resources.\n"); 323 return (ENXIO); 324 } 325 326 if (hdspe_init(sc) != 0) 327 return (ENXIO); 328 329 for (i = 0; i < HDSPE_MAX_CHANS && chan_map[i].descr != NULL; i++) { 330 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 331 scp->hc = &chan_map[i]; 332 scp->sc = sc; 333 scp->dev = device_add_child(dev, "pcm", -1); 334 device_set_ivars(scp->dev, scp); 335 } 336 337 hdspe_map_dmabuf(sc); 338 339 return (bus_generic_attach(dev)); 340 } 341 342 static void 343 hdspe_dmafree(struct sc_info *sc) 344 { 345 346 bus_dmamap_unload(sc->dmat, sc->rmap); 347 bus_dmamap_unload(sc->dmat, sc->pmap); 348 bus_dmamem_free(sc->dmat, sc->rbuf, sc->rmap); 349 bus_dmamem_free(sc->dmat, sc->pbuf, sc->pmap); 350 sc->rbuf = sc->pbuf = NULL; 351 } 352 353 static int 354 hdspe_detach(device_t dev) 355 { 356 struct sc_info *sc; 357 int err; 358 359 sc = device_get_softc(dev); 360 if (sc == NULL) { 361 device_printf(dev,"Can't detach: softc is null.\n"); 362 return (0); 363 } 364 365 err = device_delete_children(dev); 366 if (err) 367 return (err); 368 369 hdspe_dmafree(sc); 370 371 if (sc->ih) 372 bus_teardown_intr(dev, sc->irq, sc->ih); 373 if (sc->dmat) 374 bus_dma_tag_destroy(sc->dmat); 375 if (sc->irq) 376 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 377 if (sc->cs) 378 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->cs); 379 if (sc->lock) 380 snd_mtxfree(sc->lock); 381 382 return (0); 383 } 384 385 static device_method_t hdspe_methods[] = { 386 DEVMETHOD(device_probe, hdspe_probe), 387 DEVMETHOD(device_attach, hdspe_attach), 388 DEVMETHOD(device_detach, hdspe_detach), 389 { 0, 0 } 390 }; 391 392 static driver_t hdspe_driver = { 393 "hdspe", 394 hdspe_methods, 395 PCM_SOFTC_SIZE, 396 }; 397 398 DRIVER_MODULE(snd_hdspe, pci, hdspe_driver, 0, 0); 399