1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2021 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * RME HDSPe driver for FreeBSD (pcm-part). 32 * Supported cards: AIO, RayDAT. 33 */ 34 35 #include <dev/sound/pcm/sound.h> 36 #include <dev/sound/pci/hdspe.h> 37 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <mixer_if.h> 42 43 #define HDSPE_MATRIX_MAX 8 44 45 struct hdspe_latency { 46 uint32_t n; 47 uint32_t period; 48 float ms; 49 }; 50 51 static struct hdspe_latency latency_map[] = { 52 { 7, 32, 0.7 }, 53 { 0, 64, 1.5 }, 54 { 1, 128, 3 }, 55 { 2, 256, 6 }, 56 { 3, 512, 12 }, 57 { 4, 1024, 23 }, 58 { 5, 2048, 46 }, 59 { 6, 4096, 93 }, 60 61 { 0, 0, 0 }, 62 }; 63 64 struct hdspe_rate { 65 uint32_t speed; 66 uint32_t reg; 67 }; 68 69 static struct hdspe_rate rate_map[] = { 70 { 32000, (HDSPE_FREQ_32000) }, 71 { 44100, (HDSPE_FREQ_44100) }, 72 { 48000, (HDSPE_FREQ_48000) }, 73 { 64000, (HDSPE_FREQ_32000 | HDSPE_FREQ_DOUBLE) }, 74 { 88200, (HDSPE_FREQ_44100 | HDSPE_FREQ_DOUBLE) }, 75 { 96000, (HDSPE_FREQ_48000 | HDSPE_FREQ_DOUBLE) }, 76 { 128000, (HDSPE_FREQ_32000 | HDSPE_FREQ_QUAD) }, 77 { 176400, (HDSPE_FREQ_44100 | HDSPE_FREQ_QUAD) }, 78 { 192000, (HDSPE_FREQ_48000 | HDSPE_FREQ_QUAD) }, 79 80 { 0, 0 }, 81 }; 82 83 static uint32_t 84 hdspe_channel_play_ports(struct hdspe_channel *hc) 85 { 86 return (hc->ports & (HDSPE_CHAN_AIO_ALL | HDSPE_CHAN_RAY_ALL)); 87 } 88 89 static uint32_t 90 hdspe_channel_rec_ports(struct hdspe_channel *hc) 91 { 92 return (hc->ports & (HDSPE_CHAN_AIO_ALL_REC | HDSPE_CHAN_RAY_ALL)); 93 } 94 95 static unsigned int 96 hdspe_adat_width(uint32_t speed) 97 { 98 if (speed > 96000) 99 return (2); 100 if (speed > 48000) 101 return (4); 102 return (8); 103 } 104 105 static uint32_t 106 hdspe_port_first(uint32_t ports) 107 { 108 return (ports & (~(ports - 1))); /* Extract first bit set. */ 109 } 110 111 static uint32_t 112 hdspe_port_first_row(uint32_t ports) 113 { 114 uint32_t ends; 115 116 /* Restrict ports to one set with contiguous slots. */ 117 if (ports & HDSPE_CHAN_AIO_ALL) 118 ports &= HDSPE_CHAN_AIO_ALL; /* All AIO slots. */ 119 else if (ports & HDSPE_CHAN_RAY_ALL) 120 ports &= HDSPE_CHAN_RAY_ALL; /* All RayDAT slots. */ 121 122 /* Ends of port rows are followed by a port which is not in the set. */ 123 ends = ports & (~(ports >> 1)); 124 /* First row of contiguous ports ends in the first row end. */ 125 return (ports & (ends ^ (ends - 1))); 126 } 127 128 static unsigned int 129 hdspe_channel_count(uint32_t ports, uint32_t adat_width) 130 { 131 unsigned int count = 0; 132 133 if (ports & HDSPE_CHAN_AIO_ALL) { 134 /* AIO ports. */ 135 if (ports & HDSPE_CHAN_AIO_LINE) 136 count += 2; 137 if (ports & HDSPE_CHAN_AIO_EXT) 138 count += 4; 139 if (ports & HDSPE_CHAN_AIO_PHONE) 140 count += 2; 141 if (ports & HDSPE_CHAN_AIO_AES) 142 count += 2; 143 if (ports & HDSPE_CHAN_AIO_SPDIF) 144 count += 2; 145 if (ports & HDSPE_CHAN_AIO_ADAT) 146 count += adat_width; 147 } else if (ports & HDSPE_CHAN_RAY_ALL) { 148 /* RayDAT ports. */ 149 if (ports & HDSPE_CHAN_RAY_AES) 150 count += 2; 151 if (ports & HDSPE_CHAN_RAY_SPDIF) 152 count += 2; 153 if (ports & HDSPE_CHAN_RAY_ADAT1) 154 count += adat_width; 155 if (ports & HDSPE_CHAN_RAY_ADAT2) 156 count += adat_width; 157 if (ports & HDSPE_CHAN_RAY_ADAT3) 158 count += adat_width; 159 if (ports & HDSPE_CHAN_RAY_ADAT4) 160 count += adat_width; 161 } 162 163 return (count); 164 } 165 166 static unsigned int 167 hdspe_channel_offset(uint32_t subset, uint32_t ports, unsigned int adat_width) 168 { 169 uint32_t preceding; 170 171 /* Make sure we have a subset of ports. */ 172 subset &= ports; 173 /* Include all ports preceding the first one of the subset. */ 174 preceding = ports & (~subset & (subset - 1)); 175 176 if (preceding & HDSPE_CHAN_AIO_ALL) 177 preceding &= HDSPE_CHAN_AIO_ALL; /* Contiguous AIO slots. */ 178 else if (preceding & HDSPE_CHAN_RAY_ALL) 179 preceding &= HDSPE_CHAN_RAY_ALL; /* Contiguous RayDAT slots. */ 180 181 return (hdspe_channel_count(preceding, adat_width)); 182 } 183 184 static unsigned int 185 hdspe_port_slot_offset(uint32_t port, unsigned int adat_width) 186 { 187 /* Exctract the first port (lowest bit) if set of ports. */ 188 switch (hdspe_port_first(port)) { 189 /* AIO ports */ 190 case HDSPE_CHAN_AIO_LINE: 191 return (0); 192 case HDSPE_CHAN_AIO_EXT: 193 return (2); 194 case HDSPE_CHAN_AIO_PHONE: 195 return (6); 196 case HDSPE_CHAN_AIO_AES: 197 return (8); 198 case HDSPE_CHAN_AIO_SPDIF: 199 return (10); 200 case HDSPE_CHAN_AIO_ADAT: 201 return (12); 202 203 /* RayDAT ports */ 204 case HDSPE_CHAN_RAY_AES: 205 return (0); 206 case HDSPE_CHAN_RAY_SPDIF: 207 return (2); 208 case HDSPE_CHAN_RAY_ADAT1: 209 return (4); 210 case HDSPE_CHAN_RAY_ADAT2: 211 return (4 + adat_width); 212 case HDSPE_CHAN_RAY_ADAT3: 213 return (4 + 2 * adat_width); 214 case HDSPE_CHAN_RAY_ADAT4: 215 return (4 + 3 * adat_width); 216 default: 217 return (0); 218 } 219 } 220 221 static unsigned int 222 hdspe_port_slot_width(uint32_t ports, unsigned int adat_width) 223 { 224 uint32_t row; 225 226 /* Count number of contiguous slots from the first physical port. */ 227 row = hdspe_port_first_row(ports); 228 return (hdspe_channel_count(row, adat_width)); 229 } 230 231 static int 232 hdspe_hw_mixer(struct sc_chinfo *ch, unsigned int dst, 233 unsigned int src, unsigned short data) 234 { 235 struct sc_pcminfo *scp; 236 struct sc_info *sc; 237 int offs; 238 239 scp = ch->parent; 240 sc = scp->sc; 241 242 offs = 0; 243 if (ch->dir == PCMDIR_PLAY) 244 offs = 64; 245 246 hdspe_write_4(sc, HDSPE_MIXER_BASE + 247 ((offs + src + 128 * dst) * sizeof(uint32_t)), 248 data & 0xFFFF); 249 250 return (0); 251 }; 252 253 static int 254 hdspechan_setgain(struct sc_chinfo *ch) 255 { 256 struct sc_info *sc; 257 uint32_t port, ports; 258 unsigned int slot, end_slot; 259 unsigned short volume; 260 261 sc = ch->parent->sc; 262 263 /* Iterate through all physical ports of the channel. */ 264 ports = ch->ports; 265 port = hdspe_port_first(ports); 266 while (port != 0) { 267 /* Get slot range of the physical port. */ 268 slot = 269 hdspe_port_slot_offset(port, hdspe_adat_width(sc->speed)); 270 end_slot = slot + 271 hdspe_port_slot_width(port, hdspe_adat_width(sc->speed)); 272 273 /* Treat first slot as left channel. */ 274 volume = ch->lvol * HDSPE_MAX_GAIN / 100; 275 for (; slot < end_slot; slot++) { 276 hdspe_hw_mixer(ch, slot, slot, volume); 277 /* Subsequent slots all get the right channel volume. */ 278 volume = ch->rvol * HDSPE_MAX_GAIN / 100; 279 } 280 281 ports &= ~port; 282 port = hdspe_port_first(ports); 283 } 284 285 return (0); 286 } 287 288 static int 289 hdspemixer_init(struct snd_mixer *m) 290 { 291 struct sc_pcminfo *scp; 292 struct sc_info *sc; 293 int mask; 294 295 scp = mix_getdevinfo(m); 296 sc = scp->sc; 297 if (sc == NULL) 298 return (-1); 299 300 mask = SOUND_MASK_PCM; 301 302 if (hdspe_channel_play_ports(scp->hc)) 303 mask |= SOUND_MASK_VOLUME; 304 305 if (hdspe_channel_rec_ports(scp->hc)) 306 mask |= SOUND_MASK_RECLEV; 307 308 snd_mtxlock(sc->lock); 309 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL); 310 mix_setdevs(m, mask); 311 snd_mtxunlock(sc->lock); 312 313 return (0); 314 } 315 316 static int 317 hdspemixer_set(struct snd_mixer *m, unsigned dev, 318 unsigned left, unsigned right) 319 { 320 struct sc_pcminfo *scp; 321 struct sc_chinfo *ch; 322 int i; 323 324 scp = mix_getdevinfo(m); 325 326 #if 0 327 device_printf(scp->dev, "hdspemixer_set() %d %d\n", 328 left, right); 329 #endif 330 331 for (i = 0; i < scp->chnum; i++) { 332 ch = &scp->chan[i]; 333 if ((dev == SOUND_MIXER_VOLUME && ch->dir == PCMDIR_PLAY) || 334 (dev == SOUND_MIXER_RECLEV && ch->dir == PCMDIR_REC)) { 335 ch->lvol = left; 336 ch->rvol = right; 337 if (ch->run) 338 hdspechan_setgain(ch); 339 } 340 } 341 342 return (0); 343 } 344 345 static kobj_method_t hdspemixer_methods[] = { 346 KOBJMETHOD(mixer_init, hdspemixer_init), 347 KOBJMETHOD(mixer_set, hdspemixer_set), 348 KOBJMETHOD_END 349 }; 350 MIXER_DECLARE(hdspemixer); 351 352 static void 353 hdspechan_enable(struct sc_chinfo *ch, int value) 354 { 355 struct sc_pcminfo *scp; 356 struct sc_info *sc; 357 uint32_t row, ports; 358 int reg; 359 unsigned int slot, end_slot; 360 361 scp = ch->parent; 362 sc = scp->sc; 363 364 if (ch->dir == PCMDIR_PLAY) 365 reg = HDSPE_OUT_ENABLE_BASE; 366 else 367 reg = HDSPE_IN_ENABLE_BASE; 368 369 ch->run = value; 370 371 /* Iterate through rows of ports with contiguous slots. */ 372 ports = ch->ports; 373 row = hdspe_port_first_row(ports); 374 while (row != 0) { 375 slot = 376 hdspe_port_slot_offset(row, hdspe_adat_width(sc->speed)); 377 end_slot = slot + 378 hdspe_port_slot_width(row, hdspe_adat_width(sc->speed)); 379 380 for (; slot < end_slot; slot++) { 381 hdspe_write_1(sc, reg + (4 * slot), value); 382 } 383 384 ports &= ~row; 385 row = hdspe_port_first_row(ports); 386 } 387 } 388 389 static int 390 hdspe_running(struct sc_info *sc) 391 { 392 struct sc_pcminfo *scp; 393 struct sc_chinfo *ch; 394 device_t *devlist; 395 int devcount; 396 int i, j; 397 int err; 398 399 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) 400 goto bad; 401 402 for (i = 0; i < devcount; i++) { 403 scp = device_get_ivars(devlist[i]); 404 for (j = 0; j < scp->chnum; j++) { 405 ch = &scp->chan[j]; 406 if (ch->run) 407 goto bad; 408 } 409 } 410 411 free(devlist, M_TEMP); 412 413 return (0); 414 bad: 415 416 #if 0 417 device_printf(sc->dev, "hdspe is running\n"); 418 #endif 419 420 free(devlist, M_TEMP); 421 422 return (1); 423 } 424 425 static void 426 hdspe_start_audio(struct sc_info *sc) 427 { 428 429 sc->ctrl_register |= (HDSPE_AUDIO_INT_ENABLE | HDSPE_ENABLE); 430 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); 431 } 432 433 static void 434 hdspe_stop_audio(struct sc_info *sc) 435 { 436 437 if (hdspe_running(sc) == 1) 438 return; 439 440 sc->ctrl_register &= ~(HDSPE_AUDIO_INT_ENABLE | HDSPE_ENABLE); 441 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); 442 } 443 444 static void 445 buffer_mux_write(uint32_t *dma, uint32_t *pcm, unsigned int pos, 446 unsigned int samples, unsigned int slots, unsigned int channels) 447 { 448 int slot; 449 450 for (; samples > 0; samples--) { 451 for (slot = 0; slot < slots; slot++) { 452 dma[slot * HDSPE_CHANBUF_SAMPLES + pos] = 453 pcm[pos * channels + slot]; 454 } 455 pos = (pos + 1) % HDSPE_CHANBUF_SAMPLES; 456 } 457 } 458 459 static void 460 buffer_mux_port(uint32_t *dma, uint32_t *pcm, uint32_t subset, uint32_t ports, 461 unsigned int pos, unsigned int samples, unsigned int adat_width, 462 unsigned int pcm_width) 463 { 464 unsigned int slot_offset, slots; 465 unsigned int channels, chan_pos; 466 467 /* Translate DMA slot offset to DMA buffer offset. */ 468 slot_offset = hdspe_port_slot_offset(subset, adat_width); 469 dma += slot_offset * HDSPE_CHANBUF_SAMPLES; 470 471 /* Channel position of the port subset and total number of channels. */ 472 chan_pos = hdspe_channel_offset(subset, ports, pcm_width); 473 pcm += chan_pos; 474 channels = hdspe_channel_count(ports, pcm_width); 475 476 /* Only copy as much as supported by both hardware and pcm channel. */ 477 slots = hdspe_port_slot_width(subset, MIN(adat_width, pcm_width)); 478 479 /* Let the compiler inline and loop unroll common cases. */ 480 if (slots == 2) 481 buffer_mux_write(dma, pcm, pos, samples, 2, channels); 482 else if (slots == 4) 483 buffer_mux_write(dma, pcm, pos, samples, 4, channels); 484 else if (slots == 8) 485 buffer_mux_write(dma, pcm, pos, samples, 8, channels); 486 else 487 buffer_mux_write(dma, pcm, pos, samples, slots, channels); 488 } 489 490 static void 491 buffer_demux_read(uint32_t *dma, uint32_t *pcm, unsigned int pos, 492 unsigned int samples, unsigned int slots, unsigned int channels) 493 { 494 int slot; 495 496 for (; samples > 0; samples--) { 497 for (slot = 0; slot < slots; slot++) { 498 pcm[pos * channels + slot] = 499 dma[slot * HDSPE_CHANBUF_SAMPLES + pos]; 500 } 501 pos = (pos + 1) % HDSPE_CHANBUF_SAMPLES; 502 } 503 } 504 505 static void 506 buffer_demux_port(uint32_t *dma, uint32_t *pcm, uint32_t subset, uint32_t ports, 507 unsigned int pos, unsigned int samples, unsigned int adat_width, 508 unsigned int pcm_width) 509 { 510 unsigned int slot_offset, slots; 511 unsigned int channels, chan_pos; 512 513 /* Translate port slot offset to DMA buffer offset. */ 514 slot_offset = hdspe_port_slot_offset(subset, adat_width); 515 dma += slot_offset * HDSPE_CHANBUF_SAMPLES; 516 517 /* Channel position of the port subset and total number of channels. */ 518 chan_pos = hdspe_channel_offset(subset, ports, pcm_width); 519 pcm += chan_pos; 520 channels = hdspe_channel_count(ports, pcm_width); 521 522 /* Only copy as much as supported by both hardware and pcm channel. */ 523 slots = hdspe_port_slot_width(subset, MIN(adat_width, pcm_width)); 524 525 /* Let the compiler inline and loop unroll common cases. */ 526 if (slots == 2) 527 buffer_demux_read(dma, pcm, pos, samples, 2, channels); 528 else if (slots == 4) 529 buffer_demux_read(dma, pcm, pos, samples, 4, channels); 530 else if (slots == 8) 531 buffer_demux_read(dma, pcm, pos, samples, 8, channels); 532 else 533 buffer_demux_read(dma, pcm, pos, samples, slots, channels); 534 } 535 536 537 /* Copy data between DMA and PCM buffers. */ 538 static void 539 buffer_copy(struct sc_chinfo *ch) 540 { 541 struct sc_pcminfo *scp; 542 struct sc_info *sc; 543 uint32_t row, ports; 544 uint32_t dma_pos; 545 unsigned int pos, length, offset; 546 unsigned int n; 547 unsigned int adat_width, pcm_width; 548 549 scp = ch->parent; 550 sc = scp->sc; 551 552 n = AFMT_CHANNEL(ch->format); /* n channels */ 553 554 /* Let pcm formats differ from current hardware ADAT width. */ 555 adat_width = hdspe_adat_width(sc->speed); 556 if (n == hdspe_channel_count(ch->ports, 2)) 557 pcm_width = 2; 558 else if (n == hdspe_channel_count(ch->ports, 4)) 559 pcm_width = 4; 560 else 561 pcm_width = 8; 562 563 /* Derive buffer position and length to be copied. */ 564 if (ch->dir == PCMDIR_PLAY) { 565 /* Position per channel is n times smaller than PCM. */ 566 pos = sndbuf_getreadyptr(ch->buffer) / n; 567 length = sndbuf_getready(ch->buffer) / n; 568 /* Copy no more than 2 periods in advance. */ 569 if (length > (sc->period * 4 * 2)) 570 length = (sc->period * 4 * 2); 571 /* Skip what was already copied last time. */ 572 offset = (ch->position + HDSPE_CHANBUF_SIZE) - pos; 573 offset %= HDSPE_CHANBUF_SIZE; 574 if (offset <= length) { 575 pos = (pos + offset) % HDSPE_CHANBUF_SIZE; 576 length -= offset; 577 } 578 } else { 579 /* Position per channel is n times smaller than PCM. */ 580 pos = sndbuf_getfreeptr(ch->buffer) / n; 581 /* Get DMA buffer write position. */ 582 dma_pos = hdspe_read_2(sc, HDSPE_STATUS_REG); 583 dma_pos &= HDSPE_BUF_POSITION_MASK; 584 /* Copy what is newly available. */ 585 length = (dma_pos + HDSPE_CHANBUF_SIZE) - pos; 586 length %= HDSPE_CHANBUF_SIZE; 587 } 588 589 /* Position and length in samples (4 bytes). */ 590 pos /= 4; 591 length /= 4; 592 593 /* Iterate through rows of ports with contiguous slots. */ 594 ports = ch->ports; 595 if (pcm_width == adat_width) 596 row = hdspe_port_first_row(ports); 597 else 598 row = hdspe_port_first(ports); 599 600 while (row != 0) { 601 if (ch->dir == PCMDIR_PLAY) 602 buffer_mux_port(sc->pbuf, ch->data, row, ch->ports, pos, 603 length, adat_width, pcm_width); 604 else 605 buffer_demux_port(sc->rbuf, ch->data, row, ch->ports, 606 pos, length, adat_width, pcm_width); 607 608 ports &= ~row; 609 if (pcm_width == adat_width) 610 row = hdspe_port_first_row(ports); 611 else 612 row = hdspe_port_first(ports); 613 } 614 615 ch->position = ((pos + length) * 4) % HDSPE_CHANBUF_SIZE; 616 } 617 618 static int 619 clean(struct sc_chinfo *ch) 620 { 621 struct sc_pcminfo *scp; 622 struct sc_info *sc; 623 uint32_t *buf; 624 uint32_t row, ports; 625 unsigned int offset, slots; 626 627 scp = ch->parent; 628 sc = scp->sc; 629 buf = sc->rbuf; 630 631 if (ch->dir == PCMDIR_PLAY) 632 buf = sc->pbuf; 633 634 /* Iterate through rows of ports with contiguous slots. */ 635 ports = ch->ports; 636 row = hdspe_port_first_row(ports); 637 while (row != 0) { 638 offset = hdspe_port_slot_offset(row, 639 hdspe_adat_width(sc->speed)); 640 slots = hdspe_port_slot_width(row, hdspe_adat_width(sc->speed)); 641 642 bzero(buf + offset * HDSPE_CHANBUF_SAMPLES, 643 slots * HDSPE_CHANBUF_SIZE); 644 645 ports &= ~row; 646 row = hdspe_port_first_row(ports); 647 } 648 649 ch->position = 0; 650 651 return (0); 652 } 653 654 /* Channel interface. */ 655 static int 656 hdspechan_free(kobj_t obj, void *data) 657 { 658 struct sc_pcminfo *scp; 659 struct sc_chinfo *ch; 660 struct sc_info *sc; 661 662 ch = data; 663 scp = ch->parent; 664 sc = scp->sc; 665 666 #if 0 667 device_printf(scp->dev, "hdspechan_free()\n"); 668 #endif 669 670 snd_mtxlock(sc->lock); 671 if (ch->data != NULL) { 672 free(ch->data, M_HDSPE); 673 ch->data = NULL; 674 } 675 if (ch->caps != NULL) { 676 free(ch->caps, M_HDSPE); 677 ch->caps = NULL; 678 } 679 snd_mtxunlock(sc->lock); 680 681 return (0); 682 } 683 684 static void * 685 hdspechan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 686 struct pcm_channel *c, int dir) 687 { 688 struct sc_pcminfo *scp; 689 struct sc_chinfo *ch; 690 struct sc_info *sc; 691 int num; 692 693 scp = devinfo; 694 sc = scp->sc; 695 696 snd_mtxlock(sc->lock); 697 num = scp->chnum; 698 699 ch = &scp->chan[num]; 700 701 if (dir == PCMDIR_PLAY) 702 ch->ports = hdspe_channel_play_ports(scp->hc); 703 else 704 ch->ports = hdspe_channel_rec_ports(scp->hc); 705 706 ch->run = 0; 707 ch->lvol = 0; 708 ch->rvol = 0; 709 710 /* Support all possible ADAT widths as channel formats. */ 711 ch->cap_fmts[0] = 712 SND_FORMAT(AFMT_S32_LE, hdspe_channel_count(ch->ports, 2), 0); 713 ch->cap_fmts[1] = 714 SND_FORMAT(AFMT_S32_LE, hdspe_channel_count(ch->ports, 4), 0); 715 ch->cap_fmts[2] = 716 SND_FORMAT(AFMT_S32_LE, hdspe_channel_count(ch->ports, 8), 0); 717 ch->cap_fmts[3] = 0; 718 ch->caps = malloc(sizeof(struct pcmchan_caps), M_HDSPE, M_NOWAIT); 719 *(ch->caps) = (struct pcmchan_caps) {32000, 192000, ch->cap_fmts, 0}; 720 721 /* Allocate maximum buffer size. */ 722 ch->size = HDSPE_CHANBUF_SIZE * hdspe_channel_count(ch->ports, 8); 723 ch->data = malloc(ch->size, M_HDSPE, M_NOWAIT); 724 ch->position = 0; 725 726 ch->buffer = b; 727 ch->channel = c; 728 ch->parent = scp; 729 730 ch->dir = dir; 731 732 snd_mtxunlock(sc->lock); 733 734 if (sndbuf_setup(ch->buffer, ch->data, ch->size) != 0) { 735 device_printf(scp->dev, "Can't setup sndbuf.\n"); 736 hdspechan_free(obj, ch); 737 return (NULL); 738 } 739 740 return (ch); 741 } 742 743 static int 744 hdspechan_trigger(kobj_t obj, void *data, int go) 745 { 746 struct sc_pcminfo *scp; 747 struct sc_chinfo *ch; 748 struct sc_info *sc; 749 750 ch = data; 751 scp = ch->parent; 752 sc = scp->sc; 753 754 snd_mtxlock(sc->lock); 755 switch (go) { 756 case PCMTRIG_START: 757 #if 0 758 device_printf(scp->dev, "hdspechan_trigger(): start\n"); 759 #endif 760 hdspechan_enable(ch, 1); 761 hdspechan_setgain(ch); 762 hdspe_start_audio(sc); 763 break; 764 765 case PCMTRIG_STOP: 766 case PCMTRIG_ABORT: 767 #if 0 768 device_printf(scp->dev, "hdspechan_trigger(): stop or abort\n"); 769 #endif 770 clean(ch); 771 hdspechan_enable(ch, 0); 772 hdspe_stop_audio(sc); 773 break; 774 775 case PCMTRIG_EMLDMAWR: 776 case PCMTRIG_EMLDMARD: 777 if(ch->run) 778 buffer_copy(ch); 779 break; 780 } 781 782 snd_mtxunlock(sc->lock); 783 784 return (0); 785 } 786 787 static uint32_t 788 hdspechan_getptr(kobj_t obj, void *data) 789 { 790 struct sc_pcminfo *scp; 791 struct sc_chinfo *ch; 792 struct sc_info *sc; 793 uint32_t ret, pos; 794 795 ch = data; 796 scp = ch->parent; 797 sc = scp->sc; 798 799 snd_mtxlock(sc->lock); 800 ret = hdspe_read_2(sc, HDSPE_STATUS_REG); 801 snd_mtxunlock(sc->lock); 802 803 pos = ret & HDSPE_BUF_POSITION_MASK; 804 pos *= AFMT_CHANNEL(ch->format); /* Hardbuf with multiple channels. */ 805 806 return (pos); 807 } 808 809 static int 810 hdspechan_setformat(kobj_t obj, void *data, uint32_t format) 811 { 812 struct sc_chinfo *ch; 813 814 ch = data; 815 816 #if 0 817 struct sc_pcminfo *scp = ch->parent; 818 device_printf(scp->dev, "hdspechan_setformat(%d)\n", format); 819 #endif 820 821 ch->format = format; 822 823 return (0); 824 } 825 826 static uint32_t 827 hdspechan_setspeed(kobj_t obj, void *data, uint32_t speed) 828 { 829 struct sc_pcminfo *scp; 830 struct hdspe_rate *hr; 831 struct sc_chinfo *ch; 832 struct sc_info *sc; 833 long long period; 834 int threshold; 835 int i; 836 837 ch = data; 838 scp = ch->parent; 839 sc = scp->sc; 840 hr = NULL; 841 842 #if 0 843 device_printf(scp->dev, "hdspechan_setspeed(%d)\n", speed); 844 #endif 845 846 if (hdspe_running(sc) == 1) 847 goto end; 848 849 if (sc->force_speed > 0) 850 speed = sc->force_speed; 851 852 /* First look for equal frequency. */ 853 for (i = 0; rate_map[i].speed != 0; i++) { 854 if (rate_map[i].speed == speed) 855 hr = &rate_map[i]; 856 } 857 858 /* If no match, just find nearest. */ 859 if (hr == NULL) { 860 for (i = 0; rate_map[i].speed != 0; i++) { 861 hr = &rate_map[i]; 862 threshold = hr->speed + ((rate_map[i + 1].speed != 0) ? 863 ((rate_map[i + 1].speed - hr->speed) >> 1) : 0); 864 if (speed < threshold) 865 break; 866 } 867 } 868 869 switch (sc->type) { 870 case HDSPE_RAYDAT: 871 case HDSPE_AIO: 872 period = HDSPE_FREQ_AIO; 873 break; 874 default: 875 /* Unsupported card. */ 876 goto end; 877 } 878 879 /* Write frequency on the device. */ 880 sc->ctrl_register &= ~HDSPE_FREQ_MASK; 881 sc->ctrl_register |= hr->reg; 882 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); 883 884 speed = hr->speed; 885 if (speed > 96000) 886 speed /= 4; 887 else if (speed > 48000) 888 speed /= 2; 889 890 /* Set DDS value. */ 891 period /= speed; 892 hdspe_write_4(sc, HDSPE_FREQ_REG, period); 893 894 sc->speed = hr->speed; 895 end: 896 897 return (sc->speed); 898 } 899 900 static uint32_t 901 hdspechan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 902 { 903 struct hdspe_latency *hl; 904 struct sc_pcminfo *scp; 905 struct sc_chinfo *ch; 906 struct sc_info *sc; 907 int threshold; 908 int i; 909 910 ch = data; 911 scp = ch->parent; 912 sc = scp->sc; 913 hl = NULL; 914 915 #if 0 916 device_printf(scp->dev, "hdspechan_setblocksize(%d)\n", blocksize); 917 #endif 918 919 if (hdspe_running(sc) == 1) 920 goto end; 921 922 if (blocksize > HDSPE_LAT_BYTES_MAX) 923 blocksize = HDSPE_LAT_BYTES_MAX; 924 else if (blocksize < HDSPE_LAT_BYTES_MIN) 925 blocksize = HDSPE_LAT_BYTES_MIN; 926 927 blocksize /= 4 /* samples */; 928 929 if (sc->force_period > 0) 930 blocksize = sc->force_period; 931 932 /* First look for equal latency. */ 933 for (i = 0; latency_map[i].period != 0; i++) { 934 if (latency_map[i].period == blocksize) 935 hl = &latency_map[i]; 936 } 937 938 /* If no match, just find nearest. */ 939 if (hl == NULL) { 940 for (i = 0; latency_map[i].period != 0; i++) { 941 hl = &latency_map[i]; 942 threshold = hl->period + ((latency_map[i + 1].period != 0) ? 943 ((latency_map[i + 1].period - hl->period) >> 1) : 0); 944 if (blocksize < threshold) 945 break; 946 } 947 } 948 949 snd_mtxlock(sc->lock); 950 sc->ctrl_register &= ~HDSPE_LAT_MASK; 951 sc->ctrl_register |= hdspe_encode_latency(hl->n); 952 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); 953 sc->period = hl->period; 954 snd_mtxunlock(sc->lock); 955 956 #if 0 957 device_printf(scp->dev, "New period=%d\n", sc->period); 958 #endif 959 960 sndbuf_resize(ch->buffer, 961 (HDSPE_CHANBUF_SIZE * AFMT_CHANNEL(ch->format)) / (sc->period * 4), 962 (sc->period * 4)); 963 end: 964 965 return (sndbuf_getblksz(ch->buffer)); 966 } 967 968 static uint32_t hdspe_bkp_fmt[] = { 969 SND_FORMAT(AFMT_S32_LE, 2, 0), 970 0 971 }; 972 973 static struct pcmchan_caps hdspe_bkp_caps = {32000, 192000, hdspe_bkp_fmt, 0}; 974 975 static struct pcmchan_caps * 976 hdspechan_getcaps(kobj_t obj, void *data) 977 { 978 struct sc_chinfo *ch; 979 980 ch = data; 981 982 #if 0 983 struct sc_pcminfo *scl = ch->parent; 984 device_printf(scp->dev, "hdspechan_getcaps()\n"); 985 #endif 986 987 if (ch->caps != NULL) 988 return (ch->caps); 989 990 return (&hdspe_bkp_caps); 991 } 992 993 static kobj_method_t hdspechan_methods[] = { 994 KOBJMETHOD(channel_init, hdspechan_init), 995 KOBJMETHOD(channel_free, hdspechan_free), 996 KOBJMETHOD(channel_setformat, hdspechan_setformat), 997 KOBJMETHOD(channel_setspeed, hdspechan_setspeed), 998 KOBJMETHOD(channel_setblocksize, hdspechan_setblocksize), 999 KOBJMETHOD(channel_trigger, hdspechan_trigger), 1000 KOBJMETHOD(channel_getptr, hdspechan_getptr), 1001 KOBJMETHOD(channel_getcaps, hdspechan_getcaps), 1002 KOBJMETHOD_END 1003 }; 1004 CHANNEL_DECLARE(hdspechan); 1005 1006 static int 1007 hdspe_pcm_probe(device_t dev) 1008 { 1009 1010 #if 0 1011 device_printf(dev,"hdspe_pcm_probe()\n"); 1012 #endif 1013 1014 return (0); 1015 } 1016 1017 static uint32_t 1018 hdspe_pcm_intr(struct sc_pcminfo *scp) 1019 { 1020 struct sc_chinfo *ch; 1021 struct sc_info *sc; 1022 int i; 1023 1024 sc = scp->sc; 1025 1026 for (i = 0; i < scp->chnum; i++) { 1027 ch = &scp->chan[i]; 1028 snd_mtxunlock(sc->lock); 1029 chn_intr(ch->channel); 1030 snd_mtxlock(sc->lock); 1031 } 1032 1033 return (0); 1034 } 1035 1036 static int 1037 hdspe_pcm_attach(device_t dev) 1038 { 1039 char status[SND_STATUSLEN]; 1040 struct sc_pcminfo *scp; 1041 const char *buf; 1042 uint32_t pcm_flags; 1043 int err; 1044 int play, rec; 1045 1046 scp = device_get_ivars(dev); 1047 scp->ih = &hdspe_pcm_intr; 1048 1049 if (scp->hc->ports & HDSPE_CHAN_AIO_ALL) 1050 buf = "AIO"; 1051 else if (scp->hc->ports & HDSPE_CHAN_RAY_ALL) 1052 buf = "RayDAT"; 1053 else 1054 buf = "?"; 1055 device_set_descf(dev, "HDSPe %s [%s]", buf, scp->hc->descr); 1056 1057 /* 1058 * We don't register interrupt handler with snd_setup_intr 1059 * in pcm device. Mark pcm device as MPSAFE manually. 1060 */ 1061 pcm_flags = pcm_getflags(dev) | SD_F_MPSAFE; 1062 if (hdspe_channel_count(scp->hc->ports, 8) > HDSPE_MATRIX_MAX) 1063 /* Disable vchan conversion, too many channels. */ 1064 pcm_flags |= SD_F_BITPERFECT; 1065 pcm_setflags(dev, pcm_flags); 1066 1067 pcm_init(dev, scp); 1068 1069 play = (hdspe_channel_play_ports(scp->hc)) ? 1 : 0; 1070 rec = (hdspe_channel_rec_ports(scp->hc)) ? 1 : 0; 1071 1072 scp->chnum = 0; 1073 if (play) { 1074 pcm_addchan(dev, PCMDIR_PLAY, &hdspechan_class, scp); 1075 scp->chnum++; 1076 } 1077 1078 if (rec) { 1079 pcm_addchan(dev, PCMDIR_REC, &hdspechan_class, scp); 1080 scp->chnum++; 1081 } 1082 1083 snprintf(status, SND_STATUSLEN, "port 0x%jx irq %jd on %s", 1084 rman_get_start(scp->sc->cs), 1085 rman_get_start(scp->sc->irq), 1086 device_get_nameunit(device_get_parent(dev))); 1087 err = pcm_register(dev, status); 1088 if (err) { 1089 device_printf(dev, "Can't register pcm.\n"); 1090 return (ENXIO); 1091 } 1092 1093 mixer_init(dev, &hdspemixer_class, scp); 1094 1095 return (0); 1096 } 1097 1098 static int 1099 hdspe_pcm_detach(device_t dev) 1100 { 1101 int err; 1102 1103 err = pcm_unregister(dev); 1104 if (err) { 1105 device_printf(dev, "Can't unregister device.\n"); 1106 return (err); 1107 } 1108 1109 return (0); 1110 } 1111 1112 static device_method_t hdspe_pcm_methods[] = { 1113 DEVMETHOD(device_probe, hdspe_pcm_probe), 1114 DEVMETHOD(device_attach, hdspe_pcm_attach), 1115 DEVMETHOD(device_detach, hdspe_pcm_detach), 1116 { 0, 0 } 1117 }; 1118 1119 static driver_t hdspe_pcm_driver = { 1120 "pcm", 1121 hdspe_pcm_methods, 1122 PCM_SOFTC_SIZE, 1123 }; 1124 1125 DRIVER_MODULE(snd_hdspe_pcm, hdspe, hdspe_pcm_driver, 0, 0); 1126 MODULE_DEPEND(snd_hdspe, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1127 MODULE_VERSION(snd_hdspe, 1); 1128