1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define PCI_VENDOR_XILINX 0x10ee 31 #define PCI_DEVICE_XILINX_HDSP 0x3fc5 /* HDSP 9652 */ 32 #define PCI_REVISION_9632 0x9b 33 #define PCI_REVISION_9652 0x6c 34 35 #define HDSP_9632 0 36 #define HDSP_9652 1 37 38 /* Hardware mixer */ 39 #define HDSP_OUT_ENABLE_BASE 128 40 #define HDSP_IN_ENABLE_BASE 384 41 #define HDSP_MIXER_BASE 4096 42 #define HDSP_MAX_GAIN 32768 43 #define HDSP_MIN_GAIN 0 44 #define HDSP_MIX_SLOTS_9632 16 45 #define HDSP_MIX_SLOTS_9652 26 46 #define HDSP_CONTROL2_9652_MIXER (1 << 11) 47 48 /* Buffer */ 49 #define HDSP_PAGE_ADDR_BUF_OUT 32 50 #define HDSP_PAGE_ADDR_BUF_IN 36 51 #define HDSP_BUF_POSITION_MASK 0x000FFC0 52 53 /* Frequency */ 54 #define HDSP_FREQ_0 (1 << 6) 55 #define HDSP_FREQ_1 (1 << 7) 56 #define HDSP_FREQ_DOUBLE (1 << 8) 57 #define HDSP_FREQ_QUAD (1 << 31) 58 59 #define HDSP_FREQ_32000 HDSP_FREQ_0 60 #define HDSP_FREQ_44100 HDSP_FREQ_1 61 #define HDSP_FREQ_48000 (HDSP_FREQ_0 | HDSP_FREQ_1) 62 #define HDSP_FREQ_MASK (HDSP_FREQ_0 | HDSP_FREQ_1 | \ 63 HDSP_FREQ_DOUBLE | HDSP_FREQ_QUAD) 64 #define HDSP_FREQ_MASK_DEFAULT HDSP_FREQ_48000 65 #define HDSP_FREQ_REG 0 66 #define HDSP_FREQ_9632 104857600000000ULL 67 #define hdsp_freq_multiplier(s) (((s) > 96000) ? 4 : \ 68 (((s) > 48000) ? 2 : 1)) 69 #define hdsp_freq_single(s) ((s) / hdsp_freq_multiplier(s)) 70 #define hdsp_freq_reg_value(s) (HDSP_FREQ_9632 / hdsp_freq_single(s)) 71 72 #define HDSP_SPEED_DEFAULT 48000 73 74 /* Latency */ 75 #define HDSP_LAT_0 (1 << 1) 76 #define HDSP_LAT_1 (1 << 2) 77 #define HDSP_LAT_2 (1 << 3) 78 #define HDSP_LAT_MASK (HDSP_LAT_0 | HDSP_LAT_1 | HDSP_LAT_2) 79 #define HDSP_LAT_BYTES_MAX (4096 * 4) 80 #define HDSP_LAT_BYTES_MIN (32 * 4) 81 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LAT_MASK) 82 83 /* Register addresses */ 84 #define HDSP_RESET_POINTER 0 85 #define HDSP_CONTROL_REG 64 86 #define HDSP_CONTROL2_REG 256 87 #define HDSP_STATUS_REG 0 88 #define HDSP_STATUS2_REG 192 89 90 /* Control register flags */ 91 #define HDSP_ENABLE (1 << 0) 92 #define HDSP_CONTROL_SPDIF_COAX (1 << 14) 93 #define HDSP_CONTROL_LINE_OUT (1 << 24) 94 #define HDSP_CONTROL_INPUT_GAIN0 (1 << 25) 95 #define HDSP_CONTROL_INPUT_GAIN1 (1 << 26) 96 #define HDSP_CONTROL_OUTPUT_GAIN0 (1 << 27) 97 #define HDSP_CONTROL_OUTPUT_GAIN1 (1 << 28) 98 #define HDSP_CONTROL_PHONES_GAIN0 (1 << 29) 99 #define HDSP_CONTROL_PHONES_GAIN1 (1 << 30) 100 101 /* Analog input gain level */ 102 #define HDSP_INPUT_LEVEL_MASK (HDSP_CONTROL_INPUT_GAIN0 | \ 103 HDSP_CONTROL_INPUT_GAIN1) 104 #define HDSP_INPUT_LEVEL_LOWGAIN 0 105 #define HDSP_INPUT_LEVEL_PLUS4DBU (HDSP_CONTROL_INPUT_GAIN0) 106 #define HDSP_INPUT_LEVEL_MINUS10DBV (HDSP_CONTROL_INPUT_GAIN0 | \ 107 HDSP_CONTROL_INPUT_GAIN1) 108 109 /* Analog output gain level */ 110 #define HDSP_OUTPUT_LEVEL_MASK (HDSP_CONTROL_OUTPUT_GAIN0 | \ 111 HDSP_CONTROL_OUTPUT_GAIN1) 112 #define HDSP_OUTPUT_LEVEL_MINUS10DBV 0 113 #define HDSP_OUTPUT_LEVEL_PLUS4DBU (HDSP_CONTROL_OUTPUT_GAIN0) 114 #define HDSP_OUTPUT_LEVEL_HIGHGAIN (HDSP_CONTROL_OUTPUT_GAIN0 | \ 115 HDSP_CONTROL_OUTPUT_GAIN1) 116 117 /* Phones output gain level */ 118 #define HDSP_PHONES_LEVEL_MASK (HDSP_CONTROL_PHONES_GAIN0 | \ 119 HDSP_CONTROL_PHONES_GAIN1) 120 #define HDSP_PHONES_LEVEL_MINUS12DB 0 121 #define HDSP_PHONES_LEVEL_MINUS6DB (HDSP_CONTROL_PHONES_GAIN0) 122 #define HDSP_PHONES_LEVEL_0DB (HDSP_CONTROL_PHONES_GAIN0 | \ 123 HDSP_CONTROL_PHONES_GAIN1) 124 125 /* Interrupts */ 126 #define HDSP_AUDIO_IRQ_PENDING (1 << 0) 127 #define HDSP_AUDIO_INT_ENABLE (1 << 5) 128 #define HDSP_INTERRUPT_ACK 96 129 130 /* Channels */ 131 #define HDSP_MAX_SLOTS 64 /* Mono channels */ 132 #define HDSP_MAX_CHANS (HDSP_MAX_SLOTS / 2) /* Stereo pairs */ 133 134 #define HDSP_CHANBUF_SAMPLES (16 * 1024) 135 #define HDSP_CHANBUF_SIZE (4 * HDSP_CHANBUF_SAMPLES) 136 #define HDSP_DMASEGSIZE (HDSP_CHANBUF_SIZE * HDSP_MAX_SLOTS) 137 138 #define HDSP_CHAN_9632_ADAT (1 << 0) 139 #define HDSP_CHAN_9632_SPDIF (1 << 1) 140 #define HDSP_CHAN_9632_LINE (1 << 2) 141 #define HDSP_CHAN_9632_EXT (1 << 3) /* Extension boards */ 142 #define HDSP_CHAN_9632_ALL (HDSP_CHAN_9632_ADAT | \ 143 HDSP_CHAN_9632_SPDIF | \ 144 HDSP_CHAN_9632_LINE | \ 145 HDSP_CHAN_9632_EXT) 146 147 #define HDSP_CHAN_9652_ADAT1 (1 << 5) 148 #define HDSP_CHAN_9652_ADAT2 (1 << 6) 149 #define HDSP_CHAN_9652_ADAT3 (1 << 7) 150 #define HDSP_CHAN_9652_ADAT_ALL (HDSP_CHAN_9652_ADAT1 | \ 151 HDSP_CHAN_9652_ADAT2 | \ 152 HDSP_CHAN_9652_ADAT3) 153 #define HDSP_CHAN_9652_SPDIF (1 << 8) 154 #define HDSP_CHAN_9652_ALL (HDSP_CHAN_9652_ADAT_ALL | \ 155 HDSP_CHAN_9652_SPDIF) 156 157 struct hdsp_channel { 158 uint32_t ports; 159 char *descr; 160 }; 161 162 enum hdsp_clock_type { 163 HDSP_CLOCK_INTERNAL, 164 HDSP_CLOCK_ADAT1, 165 HDSP_CLOCK_ADAT2, 166 HDSP_CLOCK_ADAT3, 167 HDSP_CLOCK_SPDIF, 168 HDSP_CLOCK_WORD, 169 HDSP_CLOCK_ADAT_SYNC 170 }; 171 172 /* Preferred clock source. */ 173 #define HDSP_CONTROL_MASTER (1 << 4) 174 #define HDSP_CONTROL_CLOCK_MASK (HDSP_CONTROL_MASTER | (1 << 13) | \ 175 (1 << 16) | (1 << 17)) 176 #define HDSP_CONTROL_CLOCK(n) (((n & 0x04) << 11) | ((n & 0x03) << 16)) 177 178 /* Autosync selected clock source. */ 179 #define HDSP_STATUS2_CLOCK(n) ((n & 0x07) << 8) 180 #define HDSP_STATUS2_CLOCK_MASK HDSP_STATUS2_CLOCK(0x07); 181 182 struct hdsp_clock_source { 183 char *name; 184 enum hdsp_clock_type type; 185 }; 186 187 static MALLOC_DEFINE(M_HDSP, "hdsp", "hdsp audio"); 188 189 /* Channel registers */ 190 struct sc_chinfo { 191 struct snd_dbuf *buffer; 192 struct pcm_channel *channel; 193 struct sc_pcminfo *parent; 194 195 /* Channel information */ 196 struct pcmchan_caps *caps; 197 uint32_t cap_fmts[4]; 198 uint32_t dir; 199 uint32_t format; 200 uint32_t ports; 201 uint32_t lvol; 202 uint32_t rvol; 203 204 /* Buffer */ 205 uint32_t *data; 206 uint32_t size; 207 uint32_t position; 208 209 /* Flags */ 210 uint32_t run; 211 }; 212 213 /* PCM device private data */ 214 struct sc_pcminfo { 215 device_t dev; 216 uint32_t (*ih) (struct sc_pcminfo *scp); 217 uint32_t chnum; 218 struct sc_chinfo chan[HDSP_MAX_CHANS]; 219 struct sc_info *sc; 220 struct hdsp_channel *hc; 221 }; 222 223 /* HDSP device private data */ 224 struct sc_info { 225 device_t dev; 226 struct mtx *lock; 227 228 uint32_t ctrl_register; 229 uint32_t type; 230 231 /* Control/Status register */ 232 struct resource *cs; 233 int csid; 234 bus_space_tag_t cst; 235 bus_space_handle_t csh; 236 237 struct resource *irq; 238 int irqid; 239 void *ih; 240 bus_dma_tag_t dmat; 241 242 /* Play/Record DMA buffers */ 243 uint32_t *pbuf; 244 uint32_t *rbuf; 245 uint32_t bufsize; 246 bus_dmamap_t pmap; 247 bus_dmamap_t rmap; 248 uint32_t period; 249 uint32_t speed; 250 uint32_t force_period; 251 uint32_t force_speed; 252 }; 253 254 #define hdsp_read_1(sc, regno) \ 255 bus_space_read_1((sc)->cst, (sc)->csh, (regno)) 256 #define hdsp_read_2(sc, regno) \ 257 bus_space_read_2((sc)->cst, (sc)->csh, (regno)) 258 #define hdsp_read_4(sc, regno) \ 259 bus_space_read_4((sc)->cst, (sc)->csh, (regno)) 260 261 #define hdsp_write_1(sc, regno, data) \ 262 bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data)) 263 #define hdsp_write_2(sc, regno, data) \ 264 bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data)) 265 #define hdsp_write_4(sc, regno, data) \ 266 bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data)) 267