1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * RME HDSP driver for FreeBSD. 32 * Supported cards: HDSP 9632, HDSP 9652. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/sysctl.h> 37 38 #include <dev/sound/pcm/sound.h> 39 #include <dev/sound/pci/hdsp.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <mixer_if.h> 45 46 static bool hdsp_unified_pcm = false; 47 48 static SYSCTL_NODE(_hw, OID_AUTO, hdsp, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 49 "PCI HDSP"); 50 51 SYSCTL_BOOL(_hw_hdsp, OID_AUTO, unified_pcm, CTLFLAG_RWTUN, 52 &hdsp_unified_pcm, 0, "Combine physical ports in one unified pcm device"); 53 54 static struct hdsp_clock_source hdsp_clock_source_table_9632[] = { 55 { "internal", HDSP_CLOCK_INTERNAL }, 56 { "adat", HDSP_CLOCK_ADAT1 }, 57 { "spdif", HDSP_CLOCK_SPDIF }, 58 { "word", HDSP_CLOCK_WORD }, 59 { NULL, HDSP_CLOCK_INTERNAL } 60 }; 61 62 static struct hdsp_clock_source hdsp_clock_source_table_9652[] = { 63 { "internal", HDSP_CLOCK_INTERNAL }, 64 { "adat1", HDSP_CLOCK_ADAT1 }, 65 { "adat2", HDSP_CLOCK_ADAT2 }, 66 { "adat3", HDSP_CLOCK_ADAT3 }, 67 { "spdif", HDSP_CLOCK_SPDIF }, 68 { "word", HDSP_CLOCK_WORD }, 69 { "adat_sync", HDSP_CLOCK_ADAT_SYNC }, 70 { NULL, HDSP_CLOCK_INTERNAL } 71 }; 72 73 static struct hdsp_channel chan_map_9632[] = { 74 { HDSP_CHAN_9632_ADAT, "adat" }, 75 { HDSP_CHAN_9632_SPDIF, "s/pdif" }, 76 { HDSP_CHAN_9632_LINE, "line" }, 77 { 0, NULL }, 78 }; 79 80 static struct hdsp_channel chan_map_9632_uni[] = { 81 { HDSP_CHAN_9632_ALL, "all" }, 82 { 0, NULL }, 83 }; 84 85 static struct hdsp_channel chan_map_9652[] = { 86 { HDSP_CHAN_9652_ADAT1, "adat1" }, 87 { HDSP_CHAN_9652_ADAT2, "adat2" }, 88 { HDSP_CHAN_9652_ADAT3, "adat3" }, 89 { HDSP_CHAN_9652_SPDIF, "s/pdif" }, 90 { 0, NULL }, 91 }; 92 93 static struct hdsp_channel chan_map_9652_uni[] = { 94 { HDSP_CHAN_9652_ALL, "all" }, 95 { 0, NULL }, 96 }; 97 98 static void 99 hdsp_intr(void *p) 100 { 101 struct sc_pcminfo *scp; 102 struct sc_info *sc; 103 device_t *devlist; 104 int devcount; 105 int status; 106 int err; 107 int i; 108 109 sc = (struct sc_info *)p; 110 111 snd_mtxlock(sc->lock); 112 113 status = hdsp_read_1(sc, HDSP_STATUS_REG); 114 if (status & HDSP_AUDIO_IRQ_PENDING) { 115 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) 116 return; 117 118 for (i = 0; i < devcount; i++) { 119 scp = device_get_ivars(devlist[i]); 120 if (scp->ih != NULL) 121 scp->ih(scp); 122 } 123 124 hdsp_write_1(sc, HDSP_INTERRUPT_ACK, 0); 125 free(devlist, M_TEMP); 126 } 127 128 snd_mtxunlock(sc->lock); 129 } 130 131 static void 132 hdsp_dmapsetmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 133 { 134 #if 0 135 device_printf(sc->dev, "hdsp_dmapsetmap()\n"); 136 #endif 137 } 138 139 static int 140 hdsp_alloc_resources(struct sc_info *sc) 141 { 142 143 /* Allocate resource. */ 144 sc->csid = PCIR_BAR(0); 145 sc->cs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 146 &sc->csid, RF_ACTIVE); 147 148 if (!sc->cs) { 149 device_printf(sc->dev, "Unable to map SYS_RES_MEMORY.\n"); 150 return (ENXIO); 151 } 152 153 sc->cst = rman_get_bustag(sc->cs); 154 sc->csh = rman_get_bushandle(sc->cs); 155 156 /* Allocate interrupt resource. */ 157 sc->irqid = 0; 158 sc->irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irqid, 159 RF_ACTIVE | RF_SHAREABLE); 160 161 if (!sc->irq || 162 bus_setup_intr(sc->dev, sc->irq, INTR_MPSAFE | INTR_TYPE_AV, 163 NULL, hdsp_intr, sc, &sc->ih)) { 164 device_printf(sc->dev, "Unable to alloc interrupt resource.\n"); 165 return (ENXIO); 166 } 167 168 /* Allocate DMA resources. */ 169 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(sc->dev), 170 /*alignment*/4, 171 /*boundary*/0, 172 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 173 /*highaddr*/BUS_SPACE_MAXADDR, 174 /*filter*/NULL, 175 /*filterarg*/NULL, 176 /*maxsize*/2 * HDSP_DMASEGSIZE, 177 /*nsegments*/2, 178 /*maxsegsz*/HDSP_DMASEGSIZE, 179 /*flags*/0, 180 /*lockfunc*/NULL, 181 /*lockarg*/NULL, 182 /*dmatag*/&sc->dmat) != 0) { 183 device_printf(sc->dev, "Unable to create dma tag.\n"); 184 return (ENXIO); 185 } 186 187 sc->bufsize = HDSP_DMASEGSIZE; 188 189 /* pbuf (play buffer). */ 190 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->pbuf, BUS_DMA_WAITOK, 191 &sc->pmap)) { 192 device_printf(sc->dev, "Can't alloc pbuf.\n"); 193 return (ENXIO); 194 } 195 196 if (bus_dmamap_load(sc->dmat, sc->pmap, sc->pbuf, sc->bufsize, 197 hdsp_dmapsetmap, sc, BUS_DMA_NOWAIT)) { 198 device_printf(sc->dev, "Can't load pbuf.\n"); 199 return (ENXIO); 200 } 201 202 /* rbuf (rec buffer). */ 203 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->rbuf, BUS_DMA_WAITOK, 204 &sc->rmap)) { 205 device_printf(sc->dev, "Can't alloc rbuf.\n"); 206 return (ENXIO); 207 } 208 209 if (bus_dmamap_load(sc->dmat, sc->rmap, sc->rbuf, sc->bufsize, 210 hdsp_dmapsetmap, sc, BUS_DMA_NOWAIT)) { 211 device_printf(sc->dev, "Can't load rbuf.\n"); 212 return (ENXIO); 213 } 214 215 bzero(sc->pbuf, sc->bufsize); 216 bzero(sc->rbuf, sc->bufsize); 217 218 return (0); 219 } 220 221 static void 222 hdsp_map_dmabuf(struct sc_info *sc) 223 { 224 uint32_t paddr, raddr; 225 226 paddr = vtophys(sc->pbuf); 227 raddr = vtophys(sc->rbuf); 228 229 hdsp_write_4(sc, HDSP_PAGE_ADDR_BUF_OUT, paddr); 230 hdsp_write_4(sc, HDSP_PAGE_ADDR_BUF_IN, raddr); 231 } 232 233 static int 234 hdsp_sysctl_sample_rate(SYSCTL_HANDLER_ARGS) 235 { 236 struct sc_info *sc = oidp->oid_arg1; 237 int error; 238 unsigned int speed, multiplier; 239 240 speed = sc->force_speed; 241 242 /* Process sysctl (unsigned) integer request. */ 243 error = sysctl_handle_int(oidp, &speed, 0, req); 244 if (error != 0 || req->newptr == NULL) 245 return (error); 246 247 /* Speed from 32000 to 192000, 0 falls back to pcm speed setting. */ 248 sc->force_speed = 0; 249 if (speed > 0) { 250 multiplier = 1; 251 if ((speed > (96000 + 128000) / 2) && sc->type == HDSP_9632) 252 multiplier = 4; 253 else if (speed > (48000 + 64000) / 2) 254 multiplier = 2; 255 256 if (speed < ((32000 + 44100) / 2) * multiplier) 257 sc->force_speed = 32000 * multiplier; 258 else if (speed < ((44100 + 48000) / 2) * multiplier) 259 sc->force_speed = 44100 * multiplier; 260 else 261 sc->force_speed = 48000 * multiplier; 262 } 263 264 return (0); 265 } 266 267 268 static int 269 hdsp_sysctl_period(SYSCTL_HANDLER_ARGS) 270 { 271 struct sc_info *sc = oidp->oid_arg1; 272 int error; 273 unsigned int period; 274 275 period = sc->force_period; 276 277 /* Process sysctl (unsigned) integer request. */ 278 error = sysctl_handle_int(oidp, &period, 0, req); 279 if (error != 0 || req->newptr == NULL) 280 return (error); 281 282 /* Period is from 2^5 to 2^14, 0 falls back to pcm latency settings. */ 283 sc->force_period = 0; 284 if (period > 0) { 285 sc->force_period = 32; 286 while (sc->force_period < period && sc->force_period < 4096) 287 sc->force_period <<= 1; 288 } 289 290 return (0); 291 } 292 293 static uint32_t 294 hdsp_control_clock_preference(enum hdsp_clock_type type) 295 { 296 switch (type) { 297 case HDSP_CLOCK_INTERNAL: 298 return (HDSP_CONTROL_MASTER); 299 case HDSP_CLOCK_ADAT1: 300 return (HDSP_CONTROL_CLOCK(0)); 301 case HDSP_CLOCK_ADAT2: 302 return (HDSP_CONTROL_CLOCK(1)); 303 case HDSP_CLOCK_ADAT3: 304 return (HDSP_CONTROL_CLOCK(2)); 305 case HDSP_CLOCK_SPDIF: 306 return (HDSP_CONTROL_CLOCK(3)); 307 case HDSP_CLOCK_WORD: 308 return (HDSP_CONTROL_CLOCK(4)); 309 case HDSP_CLOCK_ADAT_SYNC: 310 return (HDSP_CONTROL_CLOCK(5)); 311 default: 312 return (HDSP_CONTROL_MASTER); 313 } 314 } 315 316 static int 317 hdsp_sysctl_clock_preference(SYSCTL_HANDLER_ARGS) 318 { 319 struct sc_info *sc; 320 struct hdsp_clock_source *clock_table, *clock; 321 char buf[16] = "invalid"; 322 int error; 323 uint32_t control; 324 325 sc = oidp->oid_arg1; 326 327 /* Select sync ports table for device type. */ 328 if (sc->type == HDSP_9632) 329 clock_table = hdsp_clock_source_table_9632; 330 else if (sc->type == HDSP_9652) 331 clock_table = hdsp_clock_source_table_9652; 332 else 333 return (ENXIO); 334 335 /* Extract preferred clock source from control register. */ 336 control = sc->ctrl_register & HDSP_CONTROL_CLOCK_MASK; 337 for (clock = clock_table; clock->name != NULL; ++clock) { 338 if (hdsp_control_clock_preference(clock->type) == control) 339 break; 340 } 341 if (clock->name != NULL) 342 strlcpy(buf, clock->name, sizeof(buf)); 343 344 /* Process sysctl string request. */ 345 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 346 if (error != 0 || req->newptr == NULL) 347 return (error); 348 349 /* Find clock source matching the sysctl string. */ 350 for (clock = clock_table; clock->name != NULL; ++clock) { 351 if (strncasecmp(buf, clock->name, sizeof(buf)) == 0) 352 break; 353 } 354 355 /* Set preferred clock source in control register. */ 356 if (clock->name != NULL) { 357 control = hdsp_control_clock_preference(clock->type); 358 control &= HDSP_CONTROL_CLOCK_MASK; 359 snd_mtxlock(sc->lock); 360 sc->ctrl_register &= ~HDSP_CONTROL_CLOCK_MASK; 361 sc->ctrl_register |= control; 362 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); 363 snd_mtxunlock(sc->lock); 364 } 365 return (0); 366 } 367 368 static uint32_t 369 hdsp_status2_clock_source(enum hdsp_clock_type type) 370 { 371 switch (type) { 372 case HDSP_CLOCK_INTERNAL: 373 return (0); 374 case HDSP_CLOCK_ADAT1: 375 return (HDSP_STATUS2_CLOCK(0)); 376 case HDSP_CLOCK_ADAT2: 377 return (HDSP_STATUS2_CLOCK(1)); 378 case HDSP_CLOCK_ADAT3: 379 return (HDSP_STATUS2_CLOCK(2)); 380 case HDSP_CLOCK_SPDIF: 381 return (HDSP_STATUS2_CLOCK(3)); 382 case HDSP_CLOCK_WORD: 383 return (HDSP_STATUS2_CLOCK(4)); 384 case HDSP_CLOCK_ADAT_SYNC: 385 return (HDSP_STATUS2_CLOCK(5)); 386 default: 387 return (0); 388 } 389 } 390 391 static int 392 hdsp_sysctl_clock_source(SYSCTL_HANDLER_ARGS) 393 { 394 struct sc_info *sc; 395 struct hdsp_clock_source *clock_table, *clock; 396 char buf[16] = "invalid"; 397 uint32_t status2; 398 399 sc = oidp->oid_arg1; 400 401 /* Select sync ports table for device type. */ 402 if (sc->type == HDSP_9632) 403 clock_table = hdsp_clock_source_table_9632; 404 else if (sc->type == HDSP_9652) 405 clock_table = hdsp_clock_source_table_9652; 406 else 407 return (ENXIO); 408 409 /* Read current (autosync) clock source from status2 register. */ 410 snd_mtxlock(sc->lock); 411 status2 = hdsp_read_4(sc, HDSP_STATUS2_REG); 412 status2 &= HDSP_STATUS2_CLOCK_MASK; 413 snd_mtxunlock(sc->lock); 414 415 /* Translate status2 register value to clock source. */ 416 for (clock = clock_table; clock->name != NULL; ++clock) { 417 /* In clock master mode, override with internal clock source. */ 418 if (sc->ctrl_register & HDSP_CONTROL_MASTER) { 419 if (clock->type == HDSP_CLOCK_INTERNAL) 420 break; 421 } else if (hdsp_status2_clock_source(clock->type) == status2) 422 break; 423 } 424 425 /* Process sysctl string request. */ 426 if (clock->name != NULL) 427 strlcpy(buf, clock->name, sizeof(buf)); 428 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 429 } 430 431 static int 432 hdsp_sysctl_clock_list(SYSCTL_HANDLER_ARGS) 433 { 434 struct sc_info *sc; 435 struct hdsp_clock_source *clock_table, *clock; 436 char buf[256]; 437 int n; 438 439 sc = oidp->oid_arg1; 440 n = 0; 441 442 /* Select clock source table for device type. */ 443 if (sc->type == HDSP_9632) 444 clock_table = hdsp_clock_source_table_9632; 445 else if (sc->type == HDSP_9652) 446 clock_table = hdsp_clock_source_table_9652; 447 else 448 return (ENXIO); 449 450 /* List available clock sources. */ 451 buf[0] = 0; 452 for (clock = clock_table; clock->name != NULL; ++clock) { 453 if (n > 0) 454 n += strlcpy(buf + n, ",", sizeof(buf) - n); 455 n += strlcpy(buf + n, clock->name, sizeof(buf) - n); 456 } 457 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 458 } 459 460 static bool 461 hdsp_clock_source_locked(enum hdsp_clock_type type, uint32_t status, 462 uint32_t status2) 463 { 464 switch (type) { 465 case HDSP_CLOCK_INTERNAL: 466 return (true); 467 case HDSP_CLOCK_ADAT1: 468 return ((status >> 3) & 0x01); 469 case HDSP_CLOCK_ADAT2: 470 return ((status >> 2) & 0x01); 471 case HDSP_CLOCK_ADAT3: 472 return ((status >> 1) & 0x01); 473 case HDSP_CLOCK_SPDIF: 474 return (!((status >> 25) & 0x01)); 475 case HDSP_CLOCK_WORD: 476 return ((status2 >> 3) & 0x01); 477 case HDSP_CLOCK_ADAT_SYNC: 478 return ((status >> 5) & 0x01); 479 default: 480 return (false); 481 } 482 } 483 484 static bool 485 hdsp_clock_source_synced(enum hdsp_clock_type type, uint32_t status, 486 uint32_t status2) 487 { 488 switch (type) { 489 case HDSP_CLOCK_INTERNAL: 490 return (true); 491 case HDSP_CLOCK_ADAT1: 492 return ((status >> 18) & 0x01); 493 case HDSP_CLOCK_ADAT2: 494 return ((status >> 17) & 0x01); 495 case HDSP_CLOCK_ADAT3: 496 return ((status >> 16) & 0x01); 497 case HDSP_CLOCK_SPDIF: 498 return (((status >> 4) & 0x01) && !((status >> 25) & 0x01)); 499 case HDSP_CLOCK_WORD: 500 return ((status2 >> 4) & 0x01); 501 case HDSP_CLOCK_ADAT_SYNC: 502 return ((status >> 27) & 0x01); 503 default: 504 return (false); 505 } 506 } 507 508 static int 509 hdsp_sysctl_sync_status(SYSCTL_HANDLER_ARGS) 510 { 511 struct sc_info *sc; 512 struct hdsp_clock_source *clock_table, *clock; 513 char buf[256]; 514 char *state; 515 int n; 516 uint32_t status, status2; 517 518 sc = oidp->oid_arg1; 519 n = 0; 520 521 /* Select sync ports table for device type. */ 522 if (sc->type == HDSP_9632) 523 clock_table = hdsp_clock_source_table_9632; 524 else if (sc->type == HDSP_9652) 525 clock_table = hdsp_clock_source_table_9652; 526 else 527 return (ENXIO); 528 529 /* Read current lock and sync bits from status registers. */ 530 snd_mtxlock(sc->lock); 531 status = hdsp_read_4(sc, HDSP_STATUS_REG); 532 status2 = hdsp_read_4(sc, HDSP_STATUS2_REG); 533 snd_mtxunlock(sc->lock); 534 535 /* List clock sources with lock and sync state. */ 536 for (clock = clock_table; clock->name != NULL; ++clock) { 537 if (clock->type == HDSP_CLOCK_INTERNAL) 538 continue; 539 if (n > 0) 540 n += strlcpy(buf + n, ",", sizeof(buf) - n); 541 state = "none"; 542 if (hdsp_clock_source_locked(clock->type, status, status2)) { 543 if (hdsp_clock_source_synced(clock->type, status, 544 status2)) 545 state = "sync"; 546 else 547 state = "lock"; 548 } 549 n += snprintf(buf + n, sizeof(buf) - n, "%s(%s)", 550 clock->name, state); 551 } 552 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 553 } 554 555 static int 556 hdsp_probe(device_t dev) 557 { 558 uint32_t rev; 559 560 if (pci_get_vendor(dev) == PCI_VENDOR_XILINX && 561 pci_get_device(dev) == PCI_DEVICE_XILINX_HDSP) { 562 rev = pci_get_revid(dev); 563 switch (rev) { 564 case PCI_REVISION_9632: 565 device_set_desc(dev, "RME HDSP 9632"); 566 return (0); 567 case PCI_REVISION_9652: 568 device_set_desc(dev, "RME HDSP 9652"); 569 return (0); 570 } 571 } 572 573 return (ENXIO); 574 } 575 576 static int 577 hdsp_init(struct sc_info *sc) 578 { 579 unsigned mixer_controls; 580 581 /* Set latency. */ 582 sc->period = 256; 583 /* 584 * The pcm channel latency settings propagate unreliable blocksizes, 585 * different for recording and playback, and skewed due to rounding 586 * and total buffer size limits. 587 * Force period to a consistent default until these issues are fixed. 588 */ 589 sc->force_period = 256; 590 sc->ctrl_register = hdsp_encode_latency(2); 591 592 /* Set rate. */ 593 sc->speed = HDSP_SPEED_DEFAULT; 594 sc->force_speed = 0; 595 sc->ctrl_register &= ~HDSP_FREQ_MASK; 596 sc->ctrl_register |= HDSP_FREQ_MASK_DEFAULT; 597 598 /* Set internal clock source (master). */ 599 sc->ctrl_register &= ~HDSP_CONTROL_CLOCK_MASK; 600 sc->ctrl_register |= HDSP_CONTROL_MASTER; 601 602 /* SPDIF from coax in, line out. */ 603 sc->ctrl_register &= ~HDSP_CONTROL_SPDIF_COAX; 604 sc->ctrl_register |= HDSP_CONTROL_SPDIF_COAX; 605 sc->ctrl_register &= ~HDSP_CONTROL_LINE_OUT; 606 sc->ctrl_register |= HDSP_CONTROL_LINE_OUT; 607 608 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); 609 610 if (sc->type == HDSP_9652) 611 hdsp_write_4(sc, HDSP_CONTROL2_REG, HDSP_CONTROL2_9652_MIXER); 612 else 613 hdsp_write_4(sc, HDSP_CONTROL2_REG, 0); 614 615 switch (sc->type) { 616 case HDSP_9632: 617 /* Mixer matrix is 2 source rows (input, playback) per output. */ 618 mixer_controls = 2 * HDSP_MIX_SLOTS_9632 * HDSP_MIX_SLOTS_9632; 619 break; 620 case HDSP_9652: 621 /* Mixer matrix is 2 source rows (input, playback) per output. */ 622 mixer_controls = 2 * HDSP_MIX_SLOTS_9652 * HDSP_MIX_SLOTS_9652; 623 break; 624 default: 625 return (ENXIO); 626 } 627 628 /* Initialize mixer matrix by silencing all controls. */ 629 for (unsigned offset = 0; offset < mixer_controls * 2; offset += 4) { 630 /* Only accepts 4 byte values, pairs of 16 bit volume controls. */ 631 hdsp_write_4(sc, HDSP_MIXER_BASE + offset, 632 (HDSP_MIN_GAIN << 16) | HDSP_MIN_GAIN); 633 } 634 635 /* Reset pointer, rewrite frequency (same register) for 9632. */ 636 hdsp_write_4(sc, HDSP_RESET_POINTER, 0); 637 if (sc->type == HDSP_9632) { 638 /* Set DDS value. */ 639 hdsp_write_4(sc, HDSP_FREQ_REG, hdsp_freq_reg_value(sc->speed)); 640 } 641 642 return (0); 643 } 644 645 static int 646 hdsp_attach(device_t dev) 647 { 648 struct hdsp_channel *chan_map; 649 struct sc_pcminfo *scp; 650 struct sc_info *sc; 651 uint32_t rev; 652 int i, err; 653 654 #if 0 655 device_printf(dev, "hdsp_attach()\n"); 656 #endif 657 658 sc = device_get_softc(dev); 659 sc->lock = snd_mtxcreate(device_get_nameunit(dev), 660 "snd_hdsp softc"); 661 sc->dev = dev; 662 663 pci_enable_busmaster(dev); 664 rev = pci_get_revid(dev); 665 switch (rev) { 666 case PCI_REVISION_9632: 667 sc->type = HDSP_9632; 668 chan_map = hdsp_unified_pcm ? chan_map_9632_uni : chan_map_9632; 669 break; 670 case PCI_REVISION_9652: 671 sc->type = HDSP_9652; 672 chan_map = hdsp_unified_pcm ? chan_map_9652_uni : chan_map_9652; 673 break; 674 default: 675 return (ENXIO); 676 } 677 678 /* Allocate resources. */ 679 err = hdsp_alloc_resources(sc); 680 if (err) { 681 device_printf(dev, "Unable to allocate system resources.\n"); 682 return (ENXIO); 683 } 684 685 if (hdsp_init(sc) != 0) 686 return (ENXIO); 687 688 for (i = 0; i < HDSP_MAX_CHANS && chan_map[i].descr != NULL; i++) { 689 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 690 scp->hc = &chan_map[i]; 691 scp->sc = sc; 692 scp->dev = device_add_child(dev, "pcm", -1); 693 device_set_ivars(scp->dev, scp); 694 } 695 696 hdsp_map_dmabuf(sc); 697 698 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 699 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 700 "sync_status", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 701 sc, 0, hdsp_sysctl_sync_status, "A", 702 "List clock source signal lock and sync status"); 703 704 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 705 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 706 "clock_source", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 707 sc, 0, hdsp_sysctl_clock_source, "A", 708 "Currently effective clock source"); 709 710 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 711 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 712 "clock_preference", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 713 sc, 0, hdsp_sysctl_clock_preference, "A", 714 "Set 'internal' (master) or preferred autosync clock source"); 715 716 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 717 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 718 "clock_list", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 719 sc, 0, hdsp_sysctl_clock_list, "A", 720 "List of supported clock sources"); 721 722 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 723 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 724 "period", CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, 725 sc, 0, hdsp_sysctl_period, "A", 726 "Force period of samples per interrupt (32, 64, ... 4096)"); 727 728 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 729 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 730 "sample_rate", CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, 731 sc, 0, hdsp_sysctl_sample_rate, "A", 732 "Force sample rate (32000, 44100, 48000, ... 192000)"); 733 734 return (bus_generic_attach(dev)); 735 } 736 737 static void 738 hdsp_dmafree(struct sc_info *sc) 739 { 740 741 bus_dmamap_unload(sc->dmat, sc->rmap); 742 bus_dmamap_unload(sc->dmat, sc->pmap); 743 bus_dmamem_free(sc->dmat, sc->rbuf, sc->rmap); 744 bus_dmamem_free(sc->dmat, sc->pbuf, sc->pmap); 745 sc->rbuf = sc->pbuf = NULL; 746 } 747 748 static int 749 hdsp_detach(device_t dev) 750 { 751 struct sc_info *sc; 752 int err; 753 754 sc = device_get_softc(dev); 755 if (sc == NULL) { 756 device_printf(dev,"Can't detach: softc is null.\n"); 757 return (0); 758 } 759 760 err = device_delete_children(dev); 761 if (err) 762 return (err); 763 764 hdsp_dmafree(sc); 765 766 if (sc->ih) 767 bus_teardown_intr(dev, sc->irq, sc->ih); 768 if (sc->dmat) 769 bus_dma_tag_destroy(sc->dmat); 770 if (sc->irq) 771 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 772 if (sc->cs) 773 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->cs); 774 if (sc->lock) 775 snd_mtxfree(sc->lock); 776 777 return (0); 778 } 779 780 static device_method_t hdsp_methods[] = { 781 DEVMETHOD(device_probe, hdsp_probe), 782 DEVMETHOD(device_attach, hdsp_attach), 783 DEVMETHOD(device_detach, hdsp_detach), 784 { 0, 0 } 785 }; 786 787 static driver_t hdsp_driver = { 788 "hdsp", 789 hdsp_methods, 790 PCM_SOFTC_SIZE, 791 }; 792 793 DRIVER_MODULE(snd_hdsp, pci, hdsp_driver, 0, 0); 794