1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * RME HDSP driver for FreeBSD. 32 * Supported cards: HDSP 9632, HDSP 9652. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/sysctl.h> 37 38 #include <dev/sound/pcm/sound.h> 39 #include <dev/sound/pci/hdsp.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <mixer_if.h> 45 46 static bool hdsp_unified_pcm = false; 47 48 static SYSCTL_NODE(_hw, OID_AUTO, hdsp, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 49 "PCI HDSP"); 50 51 SYSCTL_BOOL(_hw_hdsp, OID_AUTO, unified_pcm, CTLFLAG_RWTUN, 52 &hdsp_unified_pcm, 0, "Combine physical ports in one unified pcm device"); 53 54 static struct hdsp_clock_source hdsp_clock_source_table_9632[] = { 55 { "internal", HDSP_CLOCK_INTERNAL }, 56 { "adat", HDSP_CLOCK_ADAT1 }, 57 { "spdif", HDSP_CLOCK_SPDIF }, 58 { "word", HDSP_CLOCK_WORD }, 59 { NULL, HDSP_CLOCK_INTERNAL } 60 }; 61 62 static struct hdsp_clock_source hdsp_clock_source_table_9652[] = { 63 { "internal", HDSP_CLOCK_INTERNAL }, 64 { "adat1", HDSP_CLOCK_ADAT1 }, 65 { "adat2", HDSP_CLOCK_ADAT2 }, 66 { "adat3", HDSP_CLOCK_ADAT3 }, 67 { "spdif", HDSP_CLOCK_SPDIF }, 68 { "word", HDSP_CLOCK_WORD }, 69 { "adat_sync", HDSP_CLOCK_ADAT_SYNC }, 70 { NULL, HDSP_CLOCK_INTERNAL } 71 }; 72 73 static struct hdsp_channel chan_map_9632[] = { 74 { HDSP_CHAN_9632_ADAT, "adat" }, 75 { HDSP_CHAN_9632_SPDIF, "s/pdif" }, 76 { HDSP_CHAN_9632_LINE, "line" }, 77 { HDSP_CHAN_9632_EXT, "ext" }, 78 { 0, NULL }, 79 }; 80 81 static struct hdsp_channel chan_map_9632_uni[] = { 82 { HDSP_CHAN_9632_ALL, "all" }, 83 { 0, NULL }, 84 }; 85 86 static struct hdsp_channel chan_map_9652[] = { 87 { HDSP_CHAN_9652_ADAT1, "adat1" }, 88 { HDSP_CHAN_9652_ADAT2, "adat2" }, 89 { HDSP_CHAN_9652_ADAT3, "adat3" }, 90 { HDSP_CHAN_9652_SPDIF, "s/pdif" }, 91 { 0, NULL }, 92 }; 93 94 static struct hdsp_channel chan_map_9652_uni[] = { 95 { HDSP_CHAN_9652_ALL, "all" }, 96 { 0, NULL }, 97 }; 98 99 static void 100 hdsp_intr(void *p) 101 { 102 struct sc_pcminfo *scp; 103 struct sc_info *sc; 104 device_t *devlist; 105 int devcount; 106 int status; 107 int err; 108 int i; 109 110 sc = (struct sc_info *)p; 111 112 snd_mtxlock(sc->lock); 113 114 status = hdsp_read_1(sc, HDSP_STATUS_REG); 115 if (status & HDSP_AUDIO_IRQ_PENDING) { 116 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) 117 return; 118 119 for (i = 0; i < devcount; i++) { 120 scp = device_get_ivars(devlist[i]); 121 if (scp->ih != NULL) 122 scp->ih(scp); 123 } 124 125 hdsp_write_1(sc, HDSP_INTERRUPT_ACK, 0); 126 free(devlist, M_TEMP); 127 } 128 129 snd_mtxunlock(sc->lock); 130 } 131 132 static void 133 hdsp_dmapsetmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 134 { 135 #if 0 136 device_printf(sc->dev, "hdsp_dmapsetmap()\n"); 137 #endif 138 } 139 140 static int 141 hdsp_alloc_resources(struct sc_info *sc) 142 { 143 144 /* Allocate resource. */ 145 sc->csid = PCIR_BAR(0); 146 sc->cs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 147 &sc->csid, RF_ACTIVE); 148 149 if (!sc->cs) { 150 device_printf(sc->dev, "Unable to map SYS_RES_MEMORY.\n"); 151 return (ENXIO); 152 } 153 154 sc->cst = rman_get_bustag(sc->cs); 155 sc->csh = rman_get_bushandle(sc->cs); 156 157 /* Allocate interrupt resource. */ 158 sc->irqid = 0; 159 sc->irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irqid, 160 RF_ACTIVE | RF_SHAREABLE); 161 162 if (!sc->irq || 163 bus_setup_intr(sc->dev, sc->irq, INTR_MPSAFE | INTR_TYPE_AV, 164 NULL, hdsp_intr, sc, &sc->ih)) { 165 device_printf(sc->dev, "Unable to alloc interrupt resource.\n"); 166 return (ENXIO); 167 } 168 169 /* Allocate DMA resources. */ 170 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(sc->dev), 171 /*alignment*/4, 172 /*boundary*/0, 173 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 174 /*highaddr*/BUS_SPACE_MAXADDR, 175 /*filter*/NULL, 176 /*filterarg*/NULL, 177 /*maxsize*/2 * HDSP_DMASEGSIZE, 178 /*nsegments*/2, 179 /*maxsegsz*/HDSP_DMASEGSIZE, 180 /*flags*/0, 181 /*lockfunc*/NULL, 182 /*lockarg*/NULL, 183 /*dmatag*/&sc->dmat) != 0) { 184 device_printf(sc->dev, "Unable to create dma tag.\n"); 185 return (ENXIO); 186 } 187 188 sc->bufsize = HDSP_DMASEGSIZE; 189 190 /* pbuf (play buffer). */ 191 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->pbuf, BUS_DMA_WAITOK, 192 &sc->pmap)) { 193 device_printf(sc->dev, "Can't alloc pbuf.\n"); 194 return (ENXIO); 195 } 196 197 if (bus_dmamap_load(sc->dmat, sc->pmap, sc->pbuf, sc->bufsize, 198 hdsp_dmapsetmap, sc, BUS_DMA_NOWAIT)) { 199 device_printf(sc->dev, "Can't load pbuf.\n"); 200 return (ENXIO); 201 } 202 203 /* rbuf (rec buffer). */ 204 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->rbuf, BUS_DMA_WAITOK, 205 &sc->rmap)) { 206 device_printf(sc->dev, "Can't alloc rbuf.\n"); 207 return (ENXIO); 208 } 209 210 if (bus_dmamap_load(sc->dmat, sc->rmap, sc->rbuf, sc->bufsize, 211 hdsp_dmapsetmap, sc, BUS_DMA_NOWAIT)) { 212 device_printf(sc->dev, "Can't load rbuf.\n"); 213 return (ENXIO); 214 } 215 216 bzero(sc->pbuf, sc->bufsize); 217 bzero(sc->rbuf, sc->bufsize); 218 219 return (0); 220 } 221 222 static void 223 hdsp_map_dmabuf(struct sc_info *sc) 224 { 225 uint32_t paddr, raddr; 226 227 paddr = vtophys(sc->pbuf); 228 raddr = vtophys(sc->rbuf); 229 230 hdsp_write_4(sc, HDSP_PAGE_ADDR_BUF_OUT, paddr); 231 hdsp_write_4(sc, HDSP_PAGE_ADDR_BUF_IN, raddr); 232 } 233 234 static const char * 235 hdsp_control_input_level(uint32_t control) 236 { 237 switch (control & HDSP_INPUT_LEVEL_MASK) { 238 case HDSP_INPUT_LEVEL_LOWGAIN: 239 return ("LowGain"); 240 case HDSP_INPUT_LEVEL_PLUS4DBU: 241 return ("+4dBu"); 242 case HDSP_INPUT_LEVEL_MINUS10DBV: 243 return ("-10dBV"); 244 default: 245 return (NULL); 246 } 247 } 248 249 static int 250 hdsp_sysctl_input_level(SYSCTL_HANDLER_ARGS) 251 { 252 struct sc_info *sc; 253 const char *label; 254 char buf[16] = "invalid"; 255 int error; 256 uint32_t control; 257 258 sc = oidp->oid_arg1; 259 260 /* Only available on HDSP 9632. */ 261 if (sc->type != HDSP_9632) 262 return (ENXIO); 263 264 /* Extract current input level from control register. */ 265 control = sc->ctrl_register & HDSP_INPUT_LEVEL_MASK; 266 label = hdsp_control_input_level(control); 267 if (label != NULL) 268 strlcpy(buf, label, sizeof(buf)); 269 270 /* Process sysctl string request. */ 271 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 272 if (error != 0 || req->newptr == NULL) 273 return (error); 274 275 /* Find input level matching the sysctl string. */ 276 label = hdsp_control_input_level(HDSP_INPUT_LEVEL_LOWGAIN); 277 if (strncasecmp(buf, label, sizeof(buf)) == 0) 278 control = HDSP_INPUT_LEVEL_LOWGAIN; 279 label = hdsp_control_input_level(HDSP_INPUT_LEVEL_PLUS4DBU); 280 if (strncasecmp(buf, label, sizeof(buf)) == 0) 281 control = HDSP_INPUT_LEVEL_PLUS4DBU; 282 label = hdsp_control_input_level(HDSP_INPUT_LEVEL_MINUS10DBV); 283 if (strncasecmp(buf, label, sizeof(buf)) == 0) 284 control = HDSP_INPUT_LEVEL_MINUS10DBV; 285 286 /* Set input level in control register. */ 287 control &= HDSP_INPUT_LEVEL_MASK; 288 if (control != (sc->ctrl_register & HDSP_INPUT_LEVEL_MASK)) { 289 snd_mtxlock(sc->lock); 290 sc->ctrl_register &= ~HDSP_INPUT_LEVEL_MASK; 291 sc->ctrl_register |= control; 292 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); 293 snd_mtxunlock(sc->lock); 294 } 295 return (0); 296 } 297 298 static const char * 299 hdsp_control_output_level(uint32_t control) 300 { 301 switch (control & HDSP_OUTPUT_LEVEL_MASK) { 302 case HDSP_OUTPUT_LEVEL_MINUS10DBV: 303 return ("-10dBV"); 304 case HDSP_OUTPUT_LEVEL_PLUS4DBU: 305 return ("+4dBu"); 306 case HDSP_OUTPUT_LEVEL_HIGHGAIN: 307 return ("HighGain"); 308 default: 309 return (NULL); 310 } 311 } 312 313 static int 314 hdsp_sysctl_output_level(SYSCTL_HANDLER_ARGS) 315 { 316 struct sc_info *sc; 317 const char *label; 318 char buf[16] = "invalid"; 319 int error; 320 uint32_t control; 321 322 sc = oidp->oid_arg1; 323 324 /* Only available on HDSP 9632. */ 325 if (sc->type != HDSP_9632) 326 return (ENXIO); 327 328 /* Extract current output level from control register. */ 329 control = sc->ctrl_register & HDSP_OUTPUT_LEVEL_MASK; 330 label = hdsp_control_output_level(control); 331 if (label != NULL) 332 strlcpy(buf, label, sizeof(buf)); 333 334 /* Process sysctl string request. */ 335 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 336 if (error != 0 || req->newptr == NULL) 337 return (error); 338 339 /* Find output level matching the sysctl string. */ 340 label = hdsp_control_output_level(HDSP_OUTPUT_LEVEL_MINUS10DBV); 341 if (strncasecmp(buf, label, sizeof(buf)) == 0) 342 control = HDSP_OUTPUT_LEVEL_MINUS10DBV; 343 label = hdsp_control_output_level(HDSP_OUTPUT_LEVEL_PLUS4DBU); 344 if (strncasecmp(buf, label, sizeof(buf)) == 0) 345 control = HDSP_OUTPUT_LEVEL_PLUS4DBU; 346 label = hdsp_control_output_level(HDSP_OUTPUT_LEVEL_HIGHGAIN); 347 if (strncasecmp(buf, label, sizeof(buf)) == 0) 348 control = HDSP_OUTPUT_LEVEL_HIGHGAIN; 349 350 /* Set output level in control register. */ 351 control &= HDSP_OUTPUT_LEVEL_MASK; 352 if (control != (sc->ctrl_register & HDSP_OUTPUT_LEVEL_MASK)) { 353 snd_mtxlock(sc->lock); 354 sc->ctrl_register &= ~HDSP_OUTPUT_LEVEL_MASK; 355 sc->ctrl_register |= control; 356 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); 357 snd_mtxunlock(sc->lock); 358 } 359 return (0); 360 } 361 362 static const char * 363 hdsp_control_phones_level(uint32_t control) 364 { 365 switch (control & HDSP_PHONES_LEVEL_MASK) { 366 case HDSP_PHONES_LEVEL_MINUS12DB: 367 return ("-12dB"); 368 case HDSP_PHONES_LEVEL_MINUS6DB: 369 return ("-6dB"); 370 case HDSP_PHONES_LEVEL_0DB: 371 return ("0dB"); 372 default: 373 return (NULL); 374 } 375 } 376 377 static int 378 hdsp_sysctl_phones_level(SYSCTL_HANDLER_ARGS) 379 { 380 struct sc_info *sc; 381 const char *label; 382 char buf[16] = "invalid"; 383 int error; 384 uint32_t control; 385 386 sc = oidp->oid_arg1; 387 388 /* Only available on HDSP 9632. */ 389 if (sc->type != HDSP_9632) 390 return (ENXIO); 391 392 /* Extract current phones level from control register. */ 393 control = sc->ctrl_register & HDSP_PHONES_LEVEL_MASK; 394 label = hdsp_control_phones_level(control); 395 if (label != NULL) 396 strlcpy(buf, label, sizeof(buf)); 397 398 /* Process sysctl string request. */ 399 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 400 if (error != 0 || req->newptr == NULL) 401 return (error); 402 403 /* Find phones level matching the sysctl string. */ 404 label = hdsp_control_phones_level(HDSP_PHONES_LEVEL_MINUS12DB); 405 if (strncasecmp(buf, label, sizeof(buf)) == 0) 406 control = HDSP_PHONES_LEVEL_MINUS12DB; 407 label = hdsp_control_phones_level(HDSP_PHONES_LEVEL_MINUS6DB); 408 if (strncasecmp(buf, label, sizeof(buf)) == 0) 409 control = HDSP_PHONES_LEVEL_MINUS6DB; 410 label = hdsp_control_phones_level(HDSP_PHONES_LEVEL_0DB); 411 if (strncasecmp(buf, label, sizeof(buf)) == 0) 412 control = HDSP_PHONES_LEVEL_0DB; 413 414 /* Set phones level in control register. */ 415 control &= HDSP_PHONES_LEVEL_MASK; 416 if (control != (sc->ctrl_register & HDSP_PHONES_LEVEL_MASK)) { 417 snd_mtxlock(sc->lock); 418 sc->ctrl_register &= ~HDSP_PHONES_LEVEL_MASK; 419 sc->ctrl_register |= control; 420 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); 421 snd_mtxunlock(sc->lock); 422 } 423 return (0); 424 } 425 426 static int 427 hdsp_sysctl_sample_rate(SYSCTL_HANDLER_ARGS) 428 { 429 struct sc_info *sc = oidp->oid_arg1; 430 int error; 431 unsigned int speed, multiplier; 432 433 speed = sc->force_speed; 434 435 /* Process sysctl (unsigned) integer request. */ 436 error = sysctl_handle_int(oidp, &speed, 0, req); 437 if (error != 0 || req->newptr == NULL) 438 return (error); 439 440 /* Speed from 32000 to 192000, 0 falls back to pcm speed setting. */ 441 sc->force_speed = 0; 442 if (speed > 0) { 443 multiplier = 1; 444 if ((speed > (96000 + 128000) / 2) && sc->type == HDSP_9632) 445 multiplier = 4; 446 else if (speed > (48000 + 64000) / 2) 447 multiplier = 2; 448 449 if (speed < ((32000 + 44100) / 2) * multiplier) 450 sc->force_speed = 32000 * multiplier; 451 else if (speed < ((44100 + 48000) / 2) * multiplier) 452 sc->force_speed = 44100 * multiplier; 453 else 454 sc->force_speed = 48000 * multiplier; 455 } 456 457 return (0); 458 } 459 460 461 static int 462 hdsp_sysctl_period(SYSCTL_HANDLER_ARGS) 463 { 464 struct sc_info *sc = oidp->oid_arg1; 465 int error; 466 unsigned int period; 467 468 period = sc->force_period; 469 470 /* Process sysctl (unsigned) integer request. */ 471 error = sysctl_handle_int(oidp, &period, 0, req); 472 if (error != 0 || req->newptr == NULL) 473 return (error); 474 475 /* Period is from 2^5 to 2^14, 0 falls back to pcm latency settings. */ 476 sc->force_period = 0; 477 if (period > 0) { 478 sc->force_period = 32; 479 while (sc->force_period < period && sc->force_period < 4096) 480 sc->force_period <<= 1; 481 } 482 483 return (0); 484 } 485 486 static uint32_t 487 hdsp_control_clock_preference(enum hdsp_clock_type type) 488 { 489 switch (type) { 490 case HDSP_CLOCK_INTERNAL: 491 return (HDSP_CONTROL_MASTER); 492 case HDSP_CLOCK_ADAT1: 493 return (HDSP_CONTROL_CLOCK(0)); 494 case HDSP_CLOCK_ADAT2: 495 return (HDSP_CONTROL_CLOCK(1)); 496 case HDSP_CLOCK_ADAT3: 497 return (HDSP_CONTROL_CLOCK(2)); 498 case HDSP_CLOCK_SPDIF: 499 return (HDSP_CONTROL_CLOCK(3)); 500 case HDSP_CLOCK_WORD: 501 return (HDSP_CONTROL_CLOCK(4)); 502 case HDSP_CLOCK_ADAT_SYNC: 503 return (HDSP_CONTROL_CLOCK(5)); 504 default: 505 return (HDSP_CONTROL_MASTER); 506 } 507 } 508 509 static int 510 hdsp_sysctl_clock_preference(SYSCTL_HANDLER_ARGS) 511 { 512 struct sc_info *sc; 513 struct hdsp_clock_source *clock_table, *clock; 514 char buf[16] = "invalid"; 515 int error; 516 uint32_t control; 517 518 sc = oidp->oid_arg1; 519 520 /* Select sync ports table for device type. */ 521 if (sc->type == HDSP_9632) 522 clock_table = hdsp_clock_source_table_9632; 523 else if (sc->type == HDSP_9652) 524 clock_table = hdsp_clock_source_table_9652; 525 else 526 return (ENXIO); 527 528 /* Extract preferred clock source from control register. */ 529 control = sc->ctrl_register & HDSP_CONTROL_CLOCK_MASK; 530 for (clock = clock_table; clock->name != NULL; ++clock) { 531 if (hdsp_control_clock_preference(clock->type) == control) 532 break; 533 } 534 if (clock->name != NULL) 535 strlcpy(buf, clock->name, sizeof(buf)); 536 537 /* Process sysctl string request. */ 538 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 539 if (error != 0 || req->newptr == NULL) 540 return (error); 541 542 /* Find clock source matching the sysctl string. */ 543 for (clock = clock_table; clock->name != NULL; ++clock) { 544 if (strncasecmp(buf, clock->name, sizeof(buf)) == 0) 545 break; 546 } 547 548 /* Set preferred clock source in control register. */ 549 if (clock->name != NULL) { 550 control = hdsp_control_clock_preference(clock->type); 551 control &= HDSP_CONTROL_CLOCK_MASK; 552 snd_mtxlock(sc->lock); 553 sc->ctrl_register &= ~HDSP_CONTROL_CLOCK_MASK; 554 sc->ctrl_register |= control; 555 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); 556 snd_mtxunlock(sc->lock); 557 } 558 return (0); 559 } 560 561 static uint32_t 562 hdsp_status2_clock_source(enum hdsp_clock_type type) 563 { 564 switch (type) { 565 case HDSP_CLOCK_INTERNAL: 566 return (0); 567 case HDSP_CLOCK_ADAT1: 568 return (HDSP_STATUS2_CLOCK(0)); 569 case HDSP_CLOCK_ADAT2: 570 return (HDSP_STATUS2_CLOCK(1)); 571 case HDSP_CLOCK_ADAT3: 572 return (HDSP_STATUS2_CLOCK(2)); 573 case HDSP_CLOCK_SPDIF: 574 return (HDSP_STATUS2_CLOCK(3)); 575 case HDSP_CLOCK_WORD: 576 return (HDSP_STATUS2_CLOCK(4)); 577 case HDSP_CLOCK_ADAT_SYNC: 578 return (HDSP_STATUS2_CLOCK(5)); 579 default: 580 return (0); 581 } 582 } 583 584 static int 585 hdsp_sysctl_clock_source(SYSCTL_HANDLER_ARGS) 586 { 587 struct sc_info *sc; 588 struct hdsp_clock_source *clock_table, *clock; 589 char buf[16] = "invalid"; 590 uint32_t status2; 591 592 sc = oidp->oid_arg1; 593 594 /* Select sync ports table for device type. */ 595 if (sc->type == HDSP_9632) 596 clock_table = hdsp_clock_source_table_9632; 597 else if (sc->type == HDSP_9652) 598 clock_table = hdsp_clock_source_table_9652; 599 else 600 return (ENXIO); 601 602 /* Read current (autosync) clock source from status2 register. */ 603 snd_mtxlock(sc->lock); 604 status2 = hdsp_read_4(sc, HDSP_STATUS2_REG); 605 status2 &= HDSP_STATUS2_CLOCK_MASK; 606 snd_mtxunlock(sc->lock); 607 608 /* Translate status2 register value to clock source. */ 609 for (clock = clock_table; clock->name != NULL; ++clock) { 610 /* In clock master mode, override with internal clock source. */ 611 if (sc->ctrl_register & HDSP_CONTROL_MASTER) { 612 if (clock->type == HDSP_CLOCK_INTERNAL) 613 break; 614 } else if (hdsp_status2_clock_source(clock->type) == status2) 615 break; 616 } 617 618 /* Process sysctl string request. */ 619 if (clock->name != NULL) 620 strlcpy(buf, clock->name, sizeof(buf)); 621 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 622 } 623 624 static int 625 hdsp_sysctl_clock_list(SYSCTL_HANDLER_ARGS) 626 { 627 struct sc_info *sc; 628 struct hdsp_clock_source *clock_table, *clock; 629 char buf[256]; 630 int n; 631 632 sc = oidp->oid_arg1; 633 n = 0; 634 635 /* Select clock source table for device type. */ 636 if (sc->type == HDSP_9632) 637 clock_table = hdsp_clock_source_table_9632; 638 else if (sc->type == HDSP_9652) 639 clock_table = hdsp_clock_source_table_9652; 640 else 641 return (ENXIO); 642 643 /* List available clock sources. */ 644 buf[0] = 0; 645 for (clock = clock_table; clock->name != NULL; ++clock) { 646 if (n > 0) 647 n += strlcpy(buf + n, ",", sizeof(buf) - n); 648 n += strlcpy(buf + n, clock->name, sizeof(buf) - n); 649 } 650 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 651 } 652 653 static bool 654 hdsp_clock_source_locked(enum hdsp_clock_type type, uint32_t status, 655 uint32_t status2) 656 { 657 switch (type) { 658 case HDSP_CLOCK_INTERNAL: 659 return (true); 660 case HDSP_CLOCK_ADAT1: 661 return ((status >> 3) & 0x01); 662 case HDSP_CLOCK_ADAT2: 663 return ((status >> 2) & 0x01); 664 case HDSP_CLOCK_ADAT3: 665 return ((status >> 1) & 0x01); 666 case HDSP_CLOCK_SPDIF: 667 return (!((status >> 25) & 0x01)); 668 case HDSP_CLOCK_WORD: 669 return ((status2 >> 3) & 0x01); 670 case HDSP_CLOCK_ADAT_SYNC: 671 return ((status >> 5) & 0x01); 672 default: 673 return (false); 674 } 675 } 676 677 static bool 678 hdsp_clock_source_synced(enum hdsp_clock_type type, uint32_t status, 679 uint32_t status2) 680 { 681 switch (type) { 682 case HDSP_CLOCK_INTERNAL: 683 return (true); 684 case HDSP_CLOCK_ADAT1: 685 return ((status >> 18) & 0x01); 686 case HDSP_CLOCK_ADAT2: 687 return ((status >> 17) & 0x01); 688 case HDSP_CLOCK_ADAT3: 689 return ((status >> 16) & 0x01); 690 case HDSP_CLOCK_SPDIF: 691 return (((status >> 4) & 0x01) && !((status >> 25) & 0x01)); 692 case HDSP_CLOCK_WORD: 693 return ((status2 >> 4) & 0x01); 694 case HDSP_CLOCK_ADAT_SYNC: 695 return ((status >> 27) & 0x01); 696 default: 697 return (false); 698 } 699 } 700 701 static int 702 hdsp_sysctl_sync_status(SYSCTL_HANDLER_ARGS) 703 { 704 struct sc_info *sc; 705 struct hdsp_clock_source *clock_table, *clock; 706 char buf[256]; 707 char *state; 708 int n; 709 uint32_t status, status2; 710 711 sc = oidp->oid_arg1; 712 n = 0; 713 714 /* Select sync ports table for device type. */ 715 if (sc->type == HDSP_9632) 716 clock_table = hdsp_clock_source_table_9632; 717 else if (sc->type == HDSP_9652) 718 clock_table = hdsp_clock_source_table_9652; 719 else 720 return (ENXIO); 721 722 /* Read current lock and sync bits from status registers. */ 723 snd_mtxlock(sc->lock); 724 status = hdsp_read_4(sc, HDSP_STATUS_REG); 725 status2 = hdsp_read_4(sc, HDSP_STATUS2_REG); 726 snd_mtxunlock(sc->lock); 727 728 /* List clock sources with lock and sync state. */ 729 for (clock = clock_table; clock->name != NULL; ++clock) { 730 if (clock->type == HDSP_CLOCK_INTERNAL) 731 continue; 732 if (n > 0) 733 n += strlcpy(buf + n, ",", sizeof(buf) - n); 734 state = "none"; 735 if (hdsp_clock_source_locked(clock->type, status, status2)) { 736 if (hdsp_clock_source_synced(clock->type, status, 737 status2)) 738 state = "sync"; 739 else 740 state = "lock"; 741 } 742 n += snprintf(buf + n, sizeof(buf) - n, "%s(%s)", 743 clock->name, state); 744 } 745 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 746 } 747 748 static int 749 hdsp_probe(device_t dev) 750 { 751 uint32_t rev; 752 753 if (pci_get_vendor(dev) == PCI_VENDOR_XILINX && 754 pci_get_device(dev) == PCI_DEVICE_XILINX_HDSP) { 755 rev = pci_get_revid(dev); 756 switch (rev) { 757 case PCI_REVISION_9632: 758 device_set_desc(dev, "RME HDSP 9632"); 759 return (0); 760 case PCI_REVISION_9652: 761 device_set_desc(dev, "RME HDSP 9652"); 762 return (0); 763 } 764 } 765 766 return (ENXIO); 767 } 768 769 static int 770 hdsp_init(struct sc_info *sc) 771 { 772 unsigned mixer_controls; 773 774 /* Set latency. */ 775 sc->period = 256; 776 /* 777 * The pcm channel latency settings propagate unreliable blocksizes, 778 * different for recording and playback, and skewed due to rounding 779 * and total buffer size limits. 780 * Force period to a consistent default until these issues are fixed. 781 */ 782 sc->force_period = 256; 783 sc->ctrl_register = hdsp_encode_latency(2); 784 785 /* Set rate. */ 786 sc->speed = HDSP_SPEED_DEFAULT; 787 sc->force_speed = 0; 788 sc->ctrl_register &= ~HDSP_FREQ_MASK; 789 sc->ctrl_register |= HDSP_FREQ_MASK_DEFAULT; 790 791 /* Set internal clock source (master). */ 792 sc->ctrl_register &= ~HDSP_CONTROL_CLOCK_MASK; 793 sc->ctrl_register |= HDSP_CONTROL_MASTER; 794 795 /* SPDIF from coax in, line out. */ 796 sc->ctrl_register &= ~HDSP_CONTROL_SPDIF_COAX; 797 sc->ctrl_register |= HDSP_CONTROL_SPDIF_COAX; 798 sc->ctrl_register &= ~HDSP_CONTROL_LINE_OUT; 799 sc->ctrl_register |= HDSP_CONTROL_LINE_OUT; 800 801 /* Default gain levels. */ 802 sc->ctrl_register &= ~HDSP_INPUT_LEVEL_MASK; 803 sc->ctrl_register |= HDSP_INPUT_LEVEL_LOWGAIN; 804 sc->ctrl_register &= ~HDSP_OUTPUT_LEVEL_MASK; 805 sc->ctrl_register |= HDSP_OUTPUT_LEVEL_MINUS10DBV; 806 sc->ctrl_register &= ~HDSP_PHONES_LEVEL_MASK; 807 sc->ctrl_register |= HDSP_PHONES_LEVEL_MINUS12DB; 808 809 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); 810 811 if (sc->type == HDSP_9652) 812 hdsp_write_4(sc, HDSP_CONTROL2_REG, HDSP_CONTROL2_9652_MIXER); 813 else 814 hdsp_write_4(sc, HDSP_CONTROL2_REG, 0); 815 816 switch (sc->type) { 817 case HDSP_9632: 818 /* Mixer matrix is 2 source rows (input, playback) per output. */ 819 mixer_controls = 2 * HDSP_MIX_SLOTS_9632 * HDSP_MIX_SLOTS_9632; 820 break; 821 case HDSP_9652: 822 /* Mixer matrix is 2 source rows (input, playback) per output. */ 823 mixer_controls = 2 * HDSP_MIX_SLOTS_9652 * HDSP_MIX_SLOTS_9652; 824 break; 825 default: 826 return (ENXIO); 827 } 828 829 /* Initialize mixer matrix by silencing all controls. */ 830 for (unsigned offset = 0; offset < mixer_controls * 2; offset += 4) { 831 /* Only accepts 4 byte values, pairs of 16 bit volume controls. */ 832 hdsp_write_4(sc, HDSP_MIXER_BASE + offset, 833 (HDSP_MIN_GAIN << 16) | HDSP_MIN_GAIN); 834 } 835 836 /* Reset pointer, rewrite frequency (same register) for 9632. */ 837 hdsp_write_4(sc, HDSP_RESET_POINTER, 0); 838 if (sc->type == HDSP_9632) { 839 /* Set DDS value. */ 840 hdsp_write_4(sc, HDSP_FREQ_REG, hdsp_freq_reg_value(sc->speed)); 841 } 842 843 return (0); 844 } 845 846 static int 847 hdsp_attach(device_t dev) 848 { 849 struct hdsp_channel *chan_map; 850 struct sc_pcminfo *scp; 851 struct sc_info *sc; 852 uint32_t rev; 853 int i, err; 854 855 #if 0 856 device_printf(dev, "hdsp_attach()\n"); 857 #endif 858 859 sc = device_get_softc(dev); 860 sc->lock = snd_mtxcreate(device_get_nameunit(dev), 861 "snd_hdsp softc"); 862 sc->dev = dev; 863 864 pci_enable_busmaster(dev); 865 rev = pci_get_revid(dev); 866 switch (rev) { 867 case PCI_REVISION_9632: 868 sc->type = HDSP_9632; 869 chan_map = hdsp_unified_pcm ? chan_map_9632_uni : chan_map_9632; 870 break; 871 case PCI_REVISION_9652: 872 sc->type = HDSP_9652; 873 chan_map = hdsp_unified_pcm ? chan_map_9652_uni : chan_map_9652; 874 break; 875 default: 876 return (ENXIO); 877 } 878 879 /* Allocate resources. */ 880 err = hdsp_alloc_resources(sc); 881 if (err) { 882 device_printf(dev, "Unable to allocate system resources.\n"); 883 return (ENXIO); 884 } 885 886 if (hdsp_init(sc) != 0) 887 return (ENXIO); 888 889 for (i = 0; i < HDSP_MAX_CHANS && chan_map[i].descr != NULL; i++) { 890 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_WAITOK | M_ZERO); 891 scp->hc = &chan_map[i]; 892 scp->sc = sc; 893 scp->dev = device_add_child(dev, "pcm", -1); 894 device_set_ivars(scp->dev, scp); 895 } 896 897 hdsp_map_dmabuf(sc); 898 899 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 900 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 901 "sync_status", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 902 sc, 0, hdsp_sysctl_sync_status, "A", 903 "List clock source signal lock and sync status"); 904 905 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 906 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 907 "clock_source", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 908 sc, 0, hdsp_sysctl_clock_source, "A", 909 "Currently effective clock source"); 910 911 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 912 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 913 "clock_preference", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 914 sc, 0, hdsp_sysctl_clock_preference, "A", 915 "Set 'internal' (master) or preferred autosync clock source"); 916 917 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 918 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 919 "clock_list", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 920 sc, 0, hdsp_sysctl_clock_list, "A", 921 "List of supported clock sources"); 922 923 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 924 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 925 "period", CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, 926 sc, 0, hdsp_sysctl_period, "A", 927 "Force period of samples per interrupt (32, 64, ... 4096)"); 928 929 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 930 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 931 "sample_rate", CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, 932 sc, 0, hdsp_sysctl_sample_rate, "A", 933 "Force sample rate (32000, 44100, 48000, ... 192000)"); 934 935 if (sc->type == HDSP_9632) { 936 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 937 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 938 "phones_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 939 sc, 0, hdsp_sysctl_phones_level, "A", 940 "Phones output level ('0dB', '-6dB', '-12dB')"); 941 942 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 943 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 944 "output_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 945 sc, 0, hdsp_sysctl_output_level, "A", 946 "Analog output level ('HighGain', '+4dBU', '-10dBV')"); 947 948 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 949 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 950 "input_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 951 sc, 0, hdsp_sysctl_input_level, "A", 952 "Analog input level ('LowGain', '+4dBU', '-10dBV')"); 953 } 954 955 return (bus_generic_attach(dev)); 956 } 957 958 static void 959 hdsp_child_deleted(device_t dev, device_t child) 960 { 961 free(device_get_ivars(child), M_DEVBUF); 962 } 963 964 static void 965 hdsp_dmafree(struct sc_info *sc) 966 { 967 968 bus_dmamap_unload(sc->dmat, sc->rmap); 969 bus_dmamap_unload(sc->dmat, sc->pmap); 970 bus_dmamem_free(sc->dmat, sc->rbuf, sc->rmap); 971 bus_dmamem_free(sc->dmat, sc->pbuf, sc->pmap); 972 sc->rbuf = sc->pbuf = NULL; 973 } 974 975 static int 976 hdsp_detach(device_t dev) 977 { 978 struct sc_info *sc; 979 int err; 980 981 sc = device_get_softc(dev); 982 if (sc == NULL) { 983 device_printf(dev,"Can't detach: softc is null.\n"); 984 return (0); 985 } 986 987 err = device_delete_children(dev); 988 if (err) 989 return (err); 990 991 hdsp_dmafree(sc); 992 993 if (sc->ih) 994 bus_teardown_intr(dev, sc->irq, sc->ih); 995 if (sc->dmat) 996 bus_dma_tag_destroy(sc->dmat); 997 if (sc->irq) 998 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 999 if (sc->cs) 1000 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->cs); 1001 if (sc->lock) 1002 snd_mtxfree(sc->lock); 1003 1004 return (0); 1005 } 1006 1007 static device_method_t hdsp_methods[] = { 1008 DEVMETHOD(device_probe, hdsp_probe), 1009 DEVMETHOD(device_attach, hdsp_attach), 1010 DEVMETHOD(device_detach, hdsp_detach), 1011 DEVMETHOD(bus_child_deleted, hdsp_child_deleted), 1012 { 0, 0 } 1013 }; 1014 1015 static driver_t hdsp_driver = { 1016 "hdsp", 1017 hdsp_methods, 1018 PCM_SOFTC_SIZE, 1019 }; 1020 1021 DRIVER_MODULE(snd_hdsp, pci, hdsp_driver, 0, 0); 1022