1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 5 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Intel High Definition Audio (Controller) driver for FreeBSD. 33 */ 34 35 #ifdef HAVE_KERNEL_OPTION_HEADERS 36 #include "opt_snd.h" 37 #endif 38 39 #include <dev/sound/pcm/sound.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 43 #include <sys/ctype.h> 44 #include <sys/endian.h> 45 #include <sys/taskqueue.h> 46 47 #include <dev/sound/pci/hda/hdac_private.h> 48 #include <dev/sound/pci/hda/hdac_reg.h> 49 #include <dev/sound/pci/hda/hda_reg.h> 50 #include <dev/sound/pci/hda/hdac.h> 51 52 #define HDA_DRV_TEST_REV "20120126_0002" 53 54 SND_DECLARE_FILE("$FreeBSD$"); 55 56 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 57 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 58 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 59 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 60 61 #define HDAC_QUIRK_64BIT (1 << 0) 62 #define HDAC_QUIRK_DMAPOS (1 << 1) 63 #define HDAC_QUIRK_MSI (1 << 2) 64 65 static const struct { 66 const char *key; 67 uint32_t value; 68 } hdac_quirks_tab[] = { 69 { "64bit", HDAC_QUIRK_DMAPOS }, 70 { "dmapos", HDAC_QUIRK_DMAPOS }, 71 { "msi", HDAC_QUIRK_MSI }, 72 }; 73 74 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 75 76 static const struct { 77 uint32_t model; 78 const char *desc; 79 char quirks_on; 80 char quirks_off; 81 } hdac_devices[] = { 82 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 }, 83 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 }, 84 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 }, 85 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 }, 86 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 }, 87 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 }, 88 { HDA_INTEL_BDW2, "Intel Broadwell", 0, 0 }, 89 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 90 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 91 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 92 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 }, 93 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 }, 94 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 }, 95 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 }, 96 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 }, 97 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 }, 98 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 }, 99 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 }, 100 { HDA_INTEL_KBLKLP, "Intel Kaby Lake-LP", 0, 0 }, 101 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 }, 102 { HDA_INTEL_KBLK, "Intel Kaby Lake", 0, 0 }, 103 { HDA_INTEL_KBLKH, "Intel Kaby Lake-H", 0, 0 }, 104 { HDA_INTEL_CFLK, "Intel Coffee Lake", 0, 0 }, 105 { HDA_INTEL_CNLK, "Intel Cannon Lake", 0, 0 }, 106 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 107 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 108 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 109 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 110 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 111 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 112 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 113 { HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 }, 114 { HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 }, 115 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 116 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 117 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 118 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 119 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 120 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 121 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 122 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 123 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 124 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 125 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 126 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 127 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 128 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 129 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 130 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 131 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 132 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 133 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 134 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 135 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 136 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 137 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 138 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 139 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 140 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 141 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 142 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 143 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 144 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 145 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 146 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 147 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 148 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 149 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 150 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 151 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 152 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 153 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 154 { HDA_ATI_R600, "ATI R600", 0, 0 }, 155 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 156 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 157 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 158 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 159 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 160 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 161 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 162 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 163 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 164 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 165 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 166 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 167 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 168 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 169 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 170 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 171 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 172 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 }, 173 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 174 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 175 { HDA_SIS_966, "SiS 966/968", 0, 0 }, 176 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 177 /* Unknown */ 178 { HDA_INTEL_ALL, "Intel", 0, 0 }, 179 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 180 { HDA_ATI_ALL, "ATI", 0, 0 }, 181 { HDA_AMD_ALL, "AMD", 0, 0 }, 182 { HDA_CREATIVE_ALL, "Creative", 0, 0 }, 183 { HDA_VIA_ALL, "VIA", 0, 0 }, 184 { HDA_SIS_ALL, "SiS", 0, 0 }, 185 { HDA_ULI_ALL, "ULI", 0, 0 }, 186 }; 187 188 static const struct { 189 uint16_t vendor; 190 uint8_t reg; 191 uint8_t mask; 192 uint8_t enable; 193 } hdac_pcie_snoop[] = { 194 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 195 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 196 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 197 }; 198 199 /**************************************************************************** 200 * Function prototypes 201 ****************************************************************************/ 202 static void hdac_intr_handler(void *); 203 static int hdac_reset(struct hdac_softc *, int); 204 static int hdac_get_capabilities(struct hdac_softc *); 205 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 206 static int hdac_dma_alloc(struct hdac_softc *, 207 struct hdac_dma *, bus_size_t); 208 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 209 static int hdac_mem_alloc(struct hdac_softc *); 210 static void hdac_mem_free(struct hdac_softc *); 211 static int hdac_irq_alloc(struct hdac_softc *); 212 static void hdac_irq_free(struct hdac_softc *); 213 static void hdac_corb_init(struct hdac_softc *); 214 static void hdac_rirb_init(struct hdac_softc *); 215 static void hdac_corb_start(struct hdac_softc *); 216 static void hdac_rirb_start(struct hdac_softc *); 217 218 static void hdac_attach2(void *); 219 220 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 221 222 static int hdac_probe(device_t); 223 static int hdac_attach(device_t); 224 static int hdac_detach(device_t); 225 static int hdac_suspend(device_t); 226 static int hdac_resume(device_t); 227 228 static int hdac_rirb_flush(struct hdac_softc *sc); 229 static int hdac_unsolq_flush(struct hdac_softc *sc); 230 231 #define hdac_command(a1, a2, a3) \ 232 hdac_send_command(a1, a3, a2) 233 234 /* This function surely going to make its way into upper level someday. */ 235 static void 236 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 237 { 238 const char *res = NULL; 239 int i = 0, j, k, len, inv; 240 241 if (resource_string_value(device_get_name(sc->dev), 242 device_get_unit(sc->dev), "config", &res) != 0) 243 return; 244 if (!(res != NULL && strlen(res) > 0)) 245 return; 246 HDA_BOOTVERBOSE( 247 device_printf(sc->dev, "Config options:"); 248 ); 249 for (;;) { 250 while (res[i] != '\0' && 251 (res[i] == ',' || isspace(res[i]) != 0)) 252 i++; 253 if (res[i] == '\0') { 254 HDA_BOOTVERBOSE( 255 printf("\n"); 256 ); 257 return; 258 } 259 j = i; 260 while (res[j] != '\0' && 261 !(res[j] == ',' || isspace(res[j]) != 0)) 262 j++; 263 len = j - i; 264 if (len > 2 && strncmp(res + i, "no", 2) == 0) 265 inv = 2; 266 else 267 inv = 0; 268 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) { 269 if (strncmp(res + i + inv, 270 hdac_quirks_tab[k].key, len - inv) != 0) 271 continue; 272 if (len - inv != strlen(hdac_quirks_tab[k].key)) 273 continue; 274 HDA_BOOTVERBOSE( 275 printf(" %s%s", (inv != 0) ? "no" : "", 276 hdac_quirks_tab[k].key); 277 ); 278 if (inv == 0) { 279 *on |= hdac_quirks_tab[k].value; 280 *on &= ~hdac_quirks_tab[k].value; 281 } else if (inv != 0) { 282 *off |= hdac_quirks_tab[k].value; 283 *off &= ~hdac_quirks_tab[k].value; 284 } 285 break; 286 } 287 i = j; 288 } 289 } 290 291 /**************************************************************************** 292 * void hdac_intr_handler(void *) 293 * 294 * Interrupt handler. Processes interrupts received from the hdac. 295 ****************************************************************************/ 296 static void 297 hdac_intr_handler(void *context) 298 { 299 struct hdac_softc *sc; 300 device_t dev; 301 uint32_t intsts; 302 uint8_t rirbsts; 303 int i; 304 305 sc = (struct hdac_softc *)context; 306 hdac_lock(sc); 307 308 /* Do we have anything to do? */ 309 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 310 if ((intsts & HDAC_INTSTS_GIS) == 0) { 311 hdac_unlock(sc); 312 return; 313 } 314 315 /* Was this a controller interrupt? */ 316 if (intsts & HDAC_INTSTS_CIS) { 317 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 318 /* Get as many responses that we can */ 319 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 320 HDAC_WRITE_1(&sc->mem, 321 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 322 hdac_rirb_flush(sc); 323 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 324 } 325 if (sc->unsolq_rp != sc->unsolq_wp) 326 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 327 } 328 329 if (intsts & HDAC_INTSTS_SIS_MASK) { 330 for (i = 0; i < sc->num_ss; i++) { 331 if ((intsts & (1 << i)) == 0) 332 continue; 333 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 334 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 335 if ((dev = sc->streams[i].dev) != NULL) { 336 HDAC_STREAM_INTR(dev, 337 sc->streams[i].dir, sc->streams[i].stream); 338 } 339 } 340 } 341 342 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 343 hdac_unlock(sc); 344 } 345 346 static void 347 hdac_poll_callback(void *arg) 348 { 349 struct hdac_softc *sc = arg; 350 351 if (sc == NULL) 352 return; 353 354 hdac_lock(sc); 355 if (sc->polling == 0) { 356 hdac_unlock(sc); 357 return; 358 } 359 callout_reset(&sc->poll_callout, sc->poll_ival, 360 hdac_poll_callback, sc); 361 hdac_unlock(sc); 362 363 hdac_intr_handler(sc); 364 } 365 366 /**************************************************************************** 367 * int hdac_reset(hdac_softc *, int) 368 * 369 * Reset the hdac to a quiescent and known state. 370 ****************************************************************************/ 371 static int 372 hdac_reset(struct hdac_softc *sc, int wakeup) 373 { 374 uint32_t gctl; 375 int count, i; 376 377 /* 378 * Stop all Streams DMA engine 379 */ 380 for (i = 0; i < sc->num_iss; i++) 381 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 382 for (i = 0; i < sc->num_oss; i++) 383 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 384 for (i = 0; i < sc->num_bss; i++) 385 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 386 387 /* 388 * Stop Control DMA engines. 389 */ 390 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 391 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 392 393 /* 394 * Reset DMA position buffer. 395 */ 396 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 397 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 398 399 /* 400 * Reset the controller. The reset must remain asserted for 401 * a minimum of 100us. 402 */ 403 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 404 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 405 count = 10000; 406 do { 407 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 408 if (!(gctl & HDAC_GCTL_CRST)) 409 break; 410 DELAY(10); 411 } while (--count); 412 if (gctl & HDAC_GCTL_CRST) { 413 device_printf(sc->dev, "Unable to put hdac in reset\n"); 414 return (ENXIO); 415 } 416 417 /* If wakeup is not requested - leave the controller in reset state. */ 418 if (!wakeup) 419 return (0); 420 421 DELAY(100); 422 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 423 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 424 count = 10000; 425 do { 426 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 427 if (gctl & HDAC_GCTL_CRST) 428 break; 429 DELAY(10); 430 } while (--count); 431 if (!(gctl & HDAC_GCTL_CRST)) { 432 device_printf(sc->dev, "Device stuck in reset\n"); 433 return (ENXIO); 434 } 435 436 /* 437 * Wait for codecs to finish their own reset sequence. The delay here 438 * should be of 250us but for some reasons, it's not enough on my 439 * computer. Let's use twice as much as necessary to make sure that 440 * it's reset properly. 441 */ 442 DELAY(1000); 443 444 return (0); 445 } 446 447 448 /**************************************************************************** 449 * int hdac_get_capabilities(struct hdac_softc *); 450 * 451 * Retreive the general capabilities of the hdac; 452 * Number of Input Streams 453 * Number of Output Streams 454 * Number of bidirectional Streams 455 * 64bit ready 456 * CORB and RIRB sizes 457 ****************************************************************************/ 458 static int 459 hdac_get_capabilities(struct hdac_softc *sc) 460 { 461 uint16_t gcap; 462 uint8_t corbsize, rirbsize; 463 464 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 465 sc->num_iss = HDAC_GCAP_ISS(gcap); 466 sc->num_oss = HDAC_GCAP_OSS(gcap); 467 sc->num_bss = HDAC_GCAP_BSS(gcap); 468 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 469 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 470 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 471 if (sc->quirks_on & HDAC_QUIRK_64BIT) 472 sc->support_64bit = 1; 473 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 474 sc->support_64bit = 0; 475 476 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 477 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 478 HDAC_CORBSIZE_CORBSZCAP_256) 479 sc->corb_size = 256; 480 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 481 HDAC_CORBSIZE_CORBSZCAP_16) 482 sc->corb_size = 16; 483 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 484 HDAC_CORBSIZE_CORBSZCAP_2) 485 sc->corb_size = 2; 486 else { 487 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 488 __func__, corbsize); 489 return (ENXIO); 490 } 491 492 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 493 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 494 HDAC_RIRBSIZE_RIRBSZCAP_256) 495 sc->rirb_size = 256; 496 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 497 HDAC_RIRBSIZE_RIRBSZCAP_16) 498 sc->rirb_size = 16; 499 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 500 HDAC_RIRBSIZE_RIRBSZCAP_2) 501 sc->rirb_size = 2; 502 else { 503 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 504 __func__, rirbsize); 505 return (ENXIO); 506 } 507 508 HDA_BOOTVERBOSE( 509 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 510 "NSDO %d%s, CORB %d, RIRB %d\n", 511 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 512 sc->support_64bit ? ", 64bit" : "", 513 sc->corb_size, sc->rirb_size); 514 ); 515 516 return (0); 517 } 518 519 520 /**************************************************************************** 521 * void hdac_dma_cb 522 * 523 * This function is called by bus_dmamap_load when the mapping has been 524 * established. We just record the physical address of the mapping into 525 * the struct hdac_dma passed in. 526 ****************************************************************************/ 527 static void 528 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 529 { 530 struct hdac_dma *dma; 531 532 if (error == 0) { 533 dma = (struct hdac_dma *)callback_arg; 534 dma->dma_paddr = segs[0].ds_addr; 535 } 536 } 537 538 539 /**************************************************************************** 540 * int hdac_dma_alloc 541 * 542 * This function allocate and setup a dma region (struct hdac_dma). 543 * It must be freed by a corresponding hdac_dma_free. 544 ****************************************************************************/ 545 static int 546 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 547 { 548 bus_size_t roundsz; 549 int result; 550 551 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 552 bzero(dma, sizeof(*dma)); 553 554 /* 555 * Create a DMA tag 556 */ 557 result = bus_dma_tag_create( 558 bus_get_dma_tag(sc->dev), /* parent */ 559 HDA_DMA_ALIGNMENT, /* alignment */ 560 0, /* boundary */ 561 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 562 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 563 BUS_SPACE_MAXADDR, /* highaddr */ 564 NULL, /* filtfunc */ 565 NULL, /* fistfuncarg */ 566 roundsz, /* maxsize */ 567 1, /* nsegments */ 568 roundsz, /* maxsegsz */ 569 0, /* flags */ 570 NULL, /* lockfunc */ 571 NULL, /* lockfuncarg */ 572 &dma->dma_tag); /* dmat */ 573 if (result != 0) { 574 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%d)\n", 575 __func__, result); 576 goto hdac_dma_alloc_fail; 577 } 578 579 /* 580 * Allocate DMA memory 581 */ 582 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 583 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 584 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 585 BUS_DMA_COHERENT), 586 &dma->dma_map); 587 if (result != 0) { 588 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%d)\n", 589 __func__, result); 590 goto hdac_dma_alloc_fail; 591 } 592 593 dma->dma_size = roundsz; 594 595 /* 596 * Map the memory 597 */ 598 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 599 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 600 if (result != 0 || dma->dma_paddr == 0) { 601 if (result == 0) 602 result = ENOMEM; 603 device_printf(sc->dev, "%s: bus_dmamem_load failed (%d)\n", 604 __func__, result); 605 goto hdac_dma_alloc_fail; 606 } 607 608 HDA_BOOTHVERBOSE( 609 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 610 __func__, (uintmax_t)size, (uintmax_t)roundsz); 611 ); 612 613 return (0); 614 615 hdac_dma_alloc_fail: 616 hdac_dma_free(sc, dma); 617 618 return (result); 619 } 620 621 622 /**************************************************************************** 623 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 624 * 625 * Free a struct dhac_dma that has been previously allocated via the 626 * hdac_dma_alloc function. 627 ****************************************************************************/ 628 static void 629 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 630 { 631 if (dma->dma_paddr != 0) { 632 /* Flush caches */ 633 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 634 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 635 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 636 dma->dma_paddr = 0; 637 } 638 if (dma->dma_vaddr != NULL) { 639 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 640 dma->dma_vaddr = NULL; 641 } 642 if (dma->dma_tag != NULL) { 643 bus_dma_tag_destroy(dma->dma_tag); 644 dma->dma_tag = NULL; 645 } 646 dma->dma_size = 0; 647 } 648 649 /**************************************************************************** 650 * int hdac_mem_alloc(struct hdac_softc *) 651 * 652 * Allocate all the bus resources necessary to speak with the physical 653 * controller. 654 ****************************************************************************/ 655 static int 656 hdac_mem_alloc(struct hdac_softc *sc) 657 { 658 struct hdac_mem *mem; 659 660 mem = &sc->mem; 661 mem->mem_rid = PCIR_BAR(0); 662 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 663 &mem->mem_rid, RF_ACTIVE); 664 if (mem->mem_res == NULL) { 665 device_printf(sc->dev, 666 "%s: Unable to allocate memory resource\n", __func__); 667 return (ENOMEM); 668 } 669 mem->mem_tag = rman_get_bustag(mem->mem_res); 670 mem->mem_handle = rman_get_bushandle(mem->mem_res); 671 672 return (0); 673 } 674 675 /**************************************************************************** 676 * void hdac_mem_free(struct hdac_softc *) 677 * 678 * Free up resources previously allocated by hdac_mem_alloc. 679 ****************************************************************************/ 680 static void 681 hdac_mem_free(struct hdac_softc *sc) 682 { 683 struct hdac_mem *mem; 684 685 mem = &sc->mem; 686 if (mem->mem_res != NULL) 687 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 688 mem->mem_res); 689 mem->mem_res = NULL; 690 } 691 692 /**************************************************************************** 693 * int hdac_irq_alloc(struct hdac_softc *) 694 * 695 * Allocate and setup the resources necessary for interrupt handling. 696 ****************************************************************************/ 697 static int 698 hdac_irq_alloc(struct hdac_softc *sc) 699 { 700 struct hdac_irq *irq; 701 int result; 702 703 irq = &sc->irq; 704 irq->irq_rid = 0x0; 705 706 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 707 (result = pci_msi_count(sc->dev)) == 1 && 708 pci_alloc_msi(sc->dev, &result) == 0) 709 irq->irq_rid = 0x1; 710 711 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 712 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 713 if (irq->irq_res == NULL) { 714 device_printf(sc->dev, "%s: Unable to allocate irq\n", 715 __func__); 716 goto hdac_irq_alloc_fail; 717 } 718 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 719 NULL, hdac_intr_handler, sc, &irq->irq_handle); 720 if (result != 0) { 721 device_printf(sc->dev, 722 "%s: Unable to setup interrupt handler (%d)\n", 723 __func__, result); 724 goto hdac_irq_alloc_fail; 725 } 726 727 return (0); 728 729 hdac_irq_alloc_fail: 730 hdac_irq_free(sc); 731 732 return (ENXIO); 733 } 734 735 /**************************************************************************** 736 * void hdac_irq_free(struct hdac_softc *) 737 * 738 * Free up resources previously allocated by hdac_irq_alloc. 739 ****************************************************************************/ 740 static void 741 hdac_irq_free(struct hdac_softc *sc) 742 { 743 struct hdac_irq *irq; 744 745 irq = &sc->irq; 746 if (irq->irq_res != NULL && irq->irq_handle != NULL) 747 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 748 if (irq->irq_res != NULL) 749 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 750 irq->irq_res); 751 if (irq->irq_rid == 0x1) 752 pci_release_msi(sc->dev); 753 irq->irq_handle = NULL; 754 irq->irq_res = NULL; 755 irq->irq_rid = 0x0; 756 } 757 758 /**************************************************************************** 759 * void hdac_corb_init(struct hdac_softc *) 760 * 761 * Initialize the corb registers for operations but do not start it up yet. 762 * The CORB engine must not be running when this function is called. 763 ****************************************************************************/ 764 static void 765 hdac_corb_init(struct hdac_softc *sc) 766 { 767 uint8_t corbsize; 768 uint64_t corbpaddr; 769 770 /* Setup the CORB size. */ 771 switch (sc->corb_size) { 772 case 256: 773 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 774 break; 775 case 16: 776 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 777 break; 778 case 2: 779 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 780 break; 781 default: 782 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 783 } 784 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 785 786 /* Setup the CORB Address in the hdac */ 787 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 788 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 789 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 790 791 /* Set the WP and RP */ 792 sc->corb_wp = 0; 793 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 794 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 795 /* 796 * The HDA specification indicates that the CORBRPRST bit will always 797 * read as zero. Unfortunately, it seems that at least the 82801G 798 * doesn't reset the bit to zero, which stalls the corb engine. 799 * manually reset the bit to zero before continuing. 800 */ 801 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 802 803 /* Enable CORB error reporting */ 804 #if 0 805 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 806 #endif 807 } 808 809 /**************************************************************************** 810 * void hdac_rirb_init(struct hdac_softc *) 811 * 812 * Initialize the rirb registers for operations but do not start it up yet. 813 * The RIRB engine must not be running when this function is called. 814 ****************************************************************************/ 815 static void 816 hdac_rirb_init(struct hdac_softc *sc) 817 { 818 uint8_t rirbsize; 819 uint64_t rirbpaddr; 820 821 /* Setup the RIRB size. */ 822 switch (sc->rirb_size) { 823 case 256: 824 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 825 break; 826 case 16: 827 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 828 break; 829 case 2: 830 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 831 break; 832 default: 833 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 834 } 835 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 836 837 /* Setup the RIRB Address in the hdac */ 838 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 839 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 840 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 841 842 /* Setup the WP and RP */ 843 sc->rirb_rp = 0; 844 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 845 846 /* Setup the interrupt threshold */ 847 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 848 849 /* Enable Overrun and response received reporting */ 850 #if 0 851 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 852 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 853 #else 854 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 855 #endif 856 857 /* 858 * Make sure that the Host CPU cache doesn't contain any dirty 859 * cache lines that falls in the rirb. If I understood correctly, it 860 * should be sufficient to do this only once as the rirb is purely 861 * read-only from now on. 862 */ 863 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 864 BUS_DMASYNC_PREREAD); 865 } 866 867 /**************************************************************************** 868 * void hdac_corb_start(hdac_softc *) 869 * 870 * Startup the corb DMA engine 871 ****************************************************************************/ 872 static void 873 hdac_corb_start(struct hdac_softc *sc) 874 { 875 uint32_t corbctl; 876 877 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 878 corbctl |= HDAC_CORBCTL_CORBRUN; 879 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 880 } 881 882 /**************************************************************************** 883 * void hdac_rirb_start(hdac_softc *) 884 * 885 * Startup the rirb DMA engine 886 ****************************************************************************/ 887 static void 888 hdac_rirb_start(struct hdac_softc *sc) 889 { 890 uint32_t rirbctl; 891 892 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 893 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 894 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 895 } 896 897 static int 898 hdac_rirb_flush(struct hdac_softc *sc) 899 { 900 struct hdac_rirb *rirb_base, *rirb; 901 nid_t cad; 902 uint32_t resp, resp_ex; 903 uint8_t rirbwp; 904 int ret; 905 906 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 907 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 908 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 909 BUS_DMASYNC_POSTREAD); 910 911 ret = 0; 912 while (sc->rirb_rp != rirbwp) { 913 sc->rirb_rp++; 914 sc->rirb_rp %= sc->rirb_size; 915 rirb = &rirb_base[sc->rirb_rp]; 916 resp = le32toh(rirb->response); 917 resp_ex = le32toh(rirb->response_ex); 918 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(resp_ex); 919 if (resp_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 920 sc->unsolq[sc->unsolq_wp++] = resp; 921 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 922 sc->unsolq[sc->unsolq_wp++] = cad; 923 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 924 } else if (sc->codecs[cad].pending <= 0) { 925 device_printf(sc->dev, "Unexpected unsolicited " 926 "response from address %d: %08x\n", cad, resp); 927 } else { 928 sc->codecs[cad].response = resp; 929 sc->codecs[cad].pending--; 930 } 931 ret++; 932 } 933 934 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 935 BUS_DMASYNC_PREREAD); 936 return (ret); 937 } 938 939 static int 940 hdac_unsolq_flush(struct hdac_softc *sc) 941 { 942 device_t child; 943 nid_t cad; 944 uint32_t resp; 945 int ret = 0; 946 947 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 948 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 949 while (sc->unsolq_rp != sc->unsolq_wp) { 950 resp = sc->unsolq[sc->unsolq_rp++]; 951 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 952 cad = sc->unsolq[sc->unsolq_rp++]; 953 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 954 if ((child = sc->codecs[cad].dev) != NULL) 955 HDAC_UNSOL_INTR(child, resp); 956 ret++; 957 } 958 sc->unsolq_st = HDAC_UNSOLQ_READY; 959 } 960 961 return (ret); 962 } 963 964 /**************************************************************************** 965 * uint32_t hdac_command_sendone_internal 966 * 967 * Wrapper function that sends only one command to a given codec 968 ****************************************************************************/ 969 static uint32_t 970 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 971 { 972 int timeout; 973 uint32_t *corb; 974 975 if (!hdac_lockowned(sc)) 976 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 977 verb &= ~HDA_CMD_CAD_MASK; 978 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 979 sc->codecs[cad].response = HDA_INVALID; 980 981 sc->codecs[cad].pending++; 982 sc->corb_wp++; 983 sc->corb_wp %= sc->corb_size; 984 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 985 bus_dmamap_sync(sc->corb_dma.dma_tag, 986 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 987 corb[sc->corb_wp] = htole32(verb); 988 bus_dmamap_sync(sc->corb_dma.dma_tag, 989 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 990 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 991 992 timeout = 10000; 993 do { 994 if (hdac_rirb_flush(sc) == 0) 995 DELAY(10); 996 } while (sc->codecs[cad].pending != 0 && --timeout); 997 998 if (sc->codecs[cad].pending != 0) { 999 device_printf(sc->dev, "Command timeout on address %d\n", cad); 1000 sc->codecs[cad].pending = 0; 1001 } 1002 1003 if (sc->unsolq_rp != sc->unsolq_wp) 1004 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1005 return (sc->codecs[cad].response); 1006 } 1007 1008 /**************************************************************************** 1009 * Device Methods 1010 ****************************************************************************/ 1011 1012 /**************************************************************************** 1013 * int hdac_probe(device_t) 1014 * 1015 * Probe for the presence of an hdac. If none is found, check for a generic 1016 * match using the subclass of the device. 1017 ****************************************************************************/ 1018 static int 1019 hdac_probe(device_t dev) 1020 { 1021 int i, result; 1022 uint32_t model; 1023 uint16_t class, subclass; 1024 char desc[64]; 1025 1026 model = (uint32_t)pci_get_device(dev) << 16; 1027 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1028 class = pci_get_class(dev); 1029 subclass = pci_get_subclass(dev); 1030 1031 bzero(desc, sizeof(desc)); 1032 result = ENXIO; 1033 for (i = 0; i < nitems(hdac_devices); i++) { 1034 if (hdac_devices[i].model == model) { 1035 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1036 result = BUS_PROBE_DEFAULT; 1037 break; 1038 } 1039 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1040 class == PCIC_MULTIMEDIA && 1041 subclass == PCIS_MULTIMEDIA_HDA) { 1042 snprintf(desc, sizeof(desc), 1043 "%s (0x%04x)", 1044 hdac_devices[i].desc, pci_get_device(dev)); 1045 result = BUS_PROBE_GENERIC; 1046 break; 1047 } 1048 } 1049 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1050 subclass == PCIS_MULTIMEDIA_HDA) { 1051 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1052 result = BUS_PROBE_GENERIC; 1053 } 1054 if (result != ENXIO) { 1055 strlcat(desc, " HDA Controller", sizeof(desc)); 1056 device_set_desc_copy(dev, desc); 1057 } 1058 1059 return (result); 1060 } 1061 1062 static void 1063 hdac_unsolq_task(void *context, int pending) 1064 { 1065 struct hdac_softc *sc; 1066 1067 sc = (struct hdac_softc *)context; 1068 1069 hdac_lock(sc); 1070 hdac_unsolq_flush(sc); 1071 hdac_unlock(sc); 1072 } 1073 1074 /**************************************************************************** 1075 * int hdac_attach(device_t) 1076 * 1077 * Attach the device into the kernel. Interrupts usually won't be enabled 1078 * when this function is called. Setup everything that doesn't require 1079 * interrupts and defer probing of codecs until interrupts are enabled. 1080 ****************************************************************************/ 1081 static int 1082 hdac_attach(device_t dev) 1083 { 1084 struct hdac_softc *sc; 1085 int result; 1086 int i, devid = -1; 1087 uint32_t model; 1088 uint16_t class, subclass; 1089 uint16_t vendor; 1090 uint8_t v; 1091 1092 sc = device_get_softc(dev); 1093 HDA_BOOTVERBOSE( 1094 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n", 1095 pci_get_subvendor(dev), pci_get_subdevice(dev)); 1096 device_printf(dev, "HDA Driver Revision: %s\n", 1097 HDA_DRV_TEST_REV); 1098 ); 1099 1100 model = (uint32_t)pci_get_device(dev) << 16; 1101 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1102 class = pci_get_class(dev); 1103 subclass = pci_get_subclass(dev); 1104 1105 for (i = 0; i < nitems(hdac_devices); i++) { 1106 if (hdac_devices[i].model == model) { 1107 devid = i; 1108 break; 1109 } 1110 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1111 class == PCIC_MULTIMEDIA && 1112 subclass == PCIS_MULTIMEDIA_HDA) { 1113 devid = i; 1114 break; 1115 } 1116 } 1117 1118 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1119 sc->dev = dev; 1120 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1121 callout_init(&sc->poll_callout, 1); 1122 for (i = 0; i < HDAC_CODEC_MAX; i++) 1123 sc->codecs[i].dev = NULL; 1124 if (devid >= 0) { 1125 sc->quirks_on = hdac_devices[devid].quirks_on; 1126 sc->quirks_off = hdac_devices[devid].quirks_off; 1127 } else { 1128 sc->quirks_on = 0; 1129 sc->quirks_off = 0; 1130 } 1131 if (resource_int_value(device_get_name(dev), 1132 device_get_unit(dev), "msi", &i) == 0) { 1133 if (i == 0) 1134 sc->quirks_off |= HDAC_QUIRK_MSI; 1135 else { 1136 sc->quirks_on |= HDAC_QUIRK_MSI; 1137 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1138 } 1139 } 1140 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1141 HDA_BOOTVERBOSE( 1142 device_printf(sc->dev, 1143 "Config options: on=0x%08x off=0x%08x\n", 1144 sc->quirks_on, sc->quirks_off); 1145 ); 1146 sc->poll_ival = hz; 1147 if (resource_int_value(device_get_name(dev), 1148 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1149 sc->polling = 1; 1150 else 1151 sc->polling = 0; 1152 1153 pci_enable_busmaster(dev); 1154 1155 vendor = pci_get_vendor(dev); 1156 if (vendor == INTEL_VENDORID) { 1157 /* TCSEL -> TC0 */ 1158 v = pci_read_config(dev, 0x44, 1); 1159 pci_write_config(dev, 0x44, v & 0xf8, 1); 1160 HDA_BOOTHVERBOSE( 1161 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1162 pci_read_config(dev, 0x44, 1)); 1163 ); 1164 } 1165 1166 #if defined(__i386__) || defined(__amd64__) 1167 sc->flags |= HDAC_F_DMA_NOCACHE; 1168 1169 if (resource_int_value(device_get_name(dev), 1170 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 1171 #else 1172 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1173 #endif 1174 /* 1175 * Try to enable PCIe snoop to avoid messing around with 1176 * uncacheable DMA attribute. Since PCIe snoop register 1177 * config is pretty much vendor specific, there are no 1178 * general solutions on how to enable it, forcing us (even 1179 * Microsoft) to enable uncacheable or write combined DMA 1180 * by default. 1181 * 1182 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 1183 */ 1184 for (i = 0; i < nitems(hdac_pcie_snoop); i++) { 1185 if (hdac_pcie_snoop[i].vendor != vendor) 1186 continue; 1187 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1188 if (hdac_pcie_snoop[i].reg == 0x00) 1189 break; 1190 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1191 if ((v & hdac_pcie_snoop[i].enable) == 1192 hdac_pcie_snoop[i].enable) 1193 break; 1194 v &= hdac_pcie_snoop[i].mask; 1195 v |= hdac_pcie_snoop[i].enable; 1196 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 1197 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1198 if ((v & hdac_pcie_snoop[i].enable) != 1199 hdac_pcie_snoop[i].enable) { 1200 HDA_BOOTVERBOSE( 1201 device_printf(dev, 1202 "WARNING: Failed to enable PCIe " 1203 "snoop!\n"); 1204 ); 1205 #if defined(__i386__) || defined(__amd64__) 1206 sc->flags |= HDAC_F_DMA_NOCACHE; 1207 #endif 1208 } 1209 break; 1210 } 1211 #if defined(__i386__) || defined(__amd64__) 1212 } 1213 #endif 1214 1215 HDA_BOOTHVERBOSE( 1216 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1217 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1218 "Uncacheable" : "PCIe snoop", vendor); 1219 ); 1220 1221 /* Allocate resources */ 1222 result = hdac_mem_alloc(sc); 1223 if (result != 0) 1224 goto hdac_attach_fail; 1225 result = hdac_irq_alloc(sc); 1226 if (result != 0) 1227 goto hdac_attach_fail; 1228 1229 /* Get Capabilities */ 1230 result = hdac_get_capabilities(sc); 1231 if (result != 0) 1232 goto hdac_attach_fail; 1233 1234 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1235 result = hdac_dma_alloc(sc, &sc->corb_dma, 1236 sc->corb_size * sizeof(uint32_t)); 1237 if (result != 0) 1238 goto hdac_attach_fail; 1239 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1240 sc->rirb_size * sizeof(struct hdac_rirb)); 1241 if (result != 0) 1242 goto hdac_attach_fail; 1243 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, 1244 M_HDAC, M_ZERO | M_WAITOK); 1245 for (i = 0; i < sc->num_ss; i++) { 1246 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1247 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1248 if (result != 0) 1249 goto hdac_attach_fail; 1250 } 1251 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1252 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1253 HDA_BOOTVERBOSE( 1254 device_printf(dev, "Failed to " 1255 "allocate DMA pos buffer " 1256 "(non-fatal)\n"); 1257 ); 1258 } else { 1259 uint64_t addr = sc->pos_dma.dma_paddr; 1260 1261 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1262 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1263 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1264 HDAC_DPLBASE_DPLBASE_DMAPBE); 1265 } 1266 } 1267 1268 result = bus_dma_tag_create( 1269 bus_get_dma_tag(sc->dev), /* parent */ 1270 HDA_DMA_ALIGNMENT, /* alignment */ 1271 0, /* boundary */ 1272 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1273 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1274 BUS_SPACE_MAXADDR, /* highaddr */ 1275 NULL, /* filtfunc */ 1276 NULL, /* fistfuncarg */ 1277 HDA_BUFSZ_MAX, /* maxsize */ 1278 1, /* nsegments */ 1279 HDA_BUFSZ_MAX, /* maxsegsz */ 1280 0, /* flags */ 1281 NULL, /* lockfunc */ 1282 NULL, /* lockfuncarg */ 1283 &sc->chan_dmat); /* dmat */ 1284 if (result != 0) { 1285 device_printf(dev, "%s: bus_dma_tag_create failed (%d)\n", 1286 __func__, result); 1287 goto hdac_attach_fail; 1288 } 1289 1290 /* Quiesce everything */ 1291 HDA_BOOTHVERBOSE( 1292 device_printf(dev, "Reset controller...\n"); 1293 ); 1294 hdac_reset(sc, 1); 1295 1296 /* Initialize the CORB and RIRB */ 1297 hdac_corb_init(sc); 1298 hdac_rirb_init(sc); 1299 1300 /* Defer remaining of initialization until interrupts are enabled */ 1301 sc->intrhook.ich_func = hdac_attach2; 1302 sc->intrhook.ich_arg = (void *)sc; 1303 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1304 sc->intrhook.ich_func = NULL; 1305 hdac_attach2((void *)sc); 1306 } 1307 1308 return (0); 1309 1310 hdac_attach_fail: 1311 hdac_irq_free(sc); 1312 if (sc->streams != NULL) 1313 for (i = 0; i < sc->num_ss; i++) 1314 hdac_dma_free(sc, &sc->streams[i].bdl); 1315 free(sc->streams, M_HDAC); 1316 hdac_dma_free(sc, &sc->rirb_dma); 1317 hdac_dma_free(sc, &sc->corb_dma); 1318 hdac_mem_free(sc); 1319 snd_mtxfree(sc->lock); 1320 1321 return (ENXIO); 1322 } 1323 1324 static int 1325 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1326 { 1327 struct hdac_softc *sc; 1328 device_t *devlist; 1329 device_t dev; 1330 int devcount, i, err, val; 1331 1332 dev = oidp->oid_arg1; 1333 sc = device_get_softc(dev); 1334 if (sc == NULL) 1335 return (EINVAL); 1336 val = 0; 1337 err = sysctl_handle_int(oidp, &val, 0, req); 1338 if (err != 0 || req->newptr == NULL || val == 0) 1339 return (err); 1340 1341 /* XXX: Temporary. For debugging. */ 1342 if (val == 100) { 1343 hdac_suspend(dev); 1344 return (0); 1345 } else if (val == 101) { 1346 hdac_resume(dev); 1347 return (0); 1348 } 1349 1350 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1351 return (err); 1352 hdac_lock(sc); 1353 for (i = 0; i < devcount; i++) 1354 HDAC_PINDUMP(devlist[i]); 1355 hdac_unlock(sc); 1356 free(devlist, M_TEMP); 1357 return (0); 1358 } 1359 1360 static int 1361 hdac_mdata_rate(uint16_t fmt) 1362 { 1363 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1364 int rate, bits; 1365 1366 if (fmt & (1 << 14)) 1367 rate = 44100; 1368 else 1369 rate = 48000; 1370 rate *= ((fmt >> 11) & 0x07) + 1; 1371 rate /= ((fmt >> 8) & 0x07) + 1; 1372 bits = mbits[(fmt >> 4) & 0x03]; 1373 bits *= (fmt & 0x0f) + 1; 1374 return (rate * bits); 1375 } 1376 1377 static int 1378 hdac_bdata_rate(uint16_t fmt, int output) 1379 { 1380 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1381 int rate, bits; 1382 1383 rate = 48000; 1384 rate *= ((fmt >> 11) & 0x07) + 1; 1385 bits = bbits[(fmt >> 4) & 0x03]; 1386 bits *= (fmt & 0x0f) + 1; 1387 if (!output) 1388 bits = ((bits + 7) & ~0x07) + 10; 1389 return (rate * bits); 1390 } 1391 1392 static void 1393 hdac_poll_reinit(struct hdac_softc *sc) 1394 { 1395 int i, pollticks, min = 1000000; 1396 struct hdac_stream *s; 1397 1398 if (sc->polling == 0) 1399 return; 1400 if (sc->unsol_registered > 0) 1401 min = hz / 2; 1402 for (i = 0; i < sc->num_ss; i++) { 1403 s = &sc->streams[i]; 1404 if (s->running == 0) 1405 continue; 1406 pollticks = ((uint64_t)hz * s->blksz) / 1407 (hdac_mdata_rate(s->format) / 8); 1408 pollticks >>= 1; 1409 if (pollticks > hz) 1410 pollticks = hz; 1411 if (pollticks < 1) { 1412 HDA_BOOTVERBOSE( 1413 device_printf(sc->dev, 1414 "poll interval < 1 tick !\n"); 1415 ); 1416 pollticks = 1; 1417 } 1418 if (min > pollticks) 1419 min = pollticks; 1420 } 1421 HDA_BOOTVERBOSE( 1422 device_printf(sc->dev, 1423 "poll interval %d -> %d ticks\n", 1424 sc->poll_ival, min); 1425 ); 1426 sc->poll_ival = min; 1427 if (min == 1000000) 1428 callout_stop(&sc->poll_callout); 1429 else 1430 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1431 } 1432 1433 static int 1434 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1435 { 1436 struct hdac_softc *sc; 1437 device_t dev; 1438 uint32_t ctl; 1439 int err, val; 1440 1441 dev = oidp->oid_arg1; 1442 sc = device_get_softc(dev); 1443 if (sc == NULL) 1444 return (EINVAL); 1445 hdac_lock(sc); 1446 val = sc->polling; 1447 hdac_unlock(sc); 1448 err = sysctl_handle_int(oidp, &val, 0, req); 1449 1450 if (err != 0 || req->newptr == NULL) 1451 return (err); 1452 if (val < 0 || val > 1) 1453 return (EINVAL); 1454 1455 hdac_lock(sc); 1456 if (val != sc->polling) { 1457 if (val == 0) { 1458 callout_stop(&sc->poll_callout); 1459 hdac_unlock(sc); 1460 callout_drain(&sc->poll_callout); 1461 hdac_lock(sc); 1462 sc->polling = 0; 1463 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1464 ctl |= HDAC_INTCTL_GIE; 1465 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1466 } else { 1467 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1468 ctl &= ~HDAC_INTCTL_GIE; 1469 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1470 sc->polling = 1; 1471 hdac_poll_reinit(sc); 1472 } 1473 } 1474 hdac_unlock(sc); 1475 1476 return (err); 1477 } 1478 1479 static void 1480 hdac_attach2(void *arg) 1481 { 1482 struct hdac_softc *sc; 1483 device_t child; 1484 uint32_t vendorid, revisionid; 1485 int i; 1486 uint16_t statests; 1487 1488 sc = (struct hdac_softc *)arg; 1489 1490 hdac_lock(sc); 1491 1492 /* Remove ourselves from the config hooks */ 1493 if (sc->intrhook.ich_func != NULL) { 1494 config_intrhook_disestablish(&sc->intrhook); 1495 sc->intrhook.ich_func = NULL; 1496 } 1497 1498 HDA_BOOTHVERBOSE( 1499 device_printf(sc->dev, "Starting CORB Engine...\n"); 1500 ); 1501 hdac_corb_start(sc); 1502 HDA_BOOTHVERBOSE( 1503 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1504 ); 1505 hdac_rirb_start(sc); 1506 HDA_BOOTHVERBOSE( 1507 device_printf(sc->dev, 1508 "Enabling controller interrupt...\n"); 1509 ); 1510 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1511 HDAC_GCTL_UNSOL); 1512 if (sc->polling == 0) { 1513 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1514 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1515 } 1516 DELAY(1000); 1517 1518 HDA_BOOTHVERBOSE( 1519 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1520 ); 1521 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1522 hdac_unlock(sc); 1523 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1524 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1525 HDA_BOOTHVERBOSE( 1526 device_printf(sc->dev, 1527 "Found CODEC at address %d\n", i); 1528 ); 1529 hdac_lock(sc); 1530 vendorid = hdac_send_command(sc, i, 1531 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1532 revisionid = hdac_send_command(sc, i, 1533 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1534 hdac_unlock(sc); 1535 if (vendorid == HDA_INVALID && 1536 revisionid == HDA_INVALID) { 1537 device_printf(sc->dev, 1538 "CODEC is not responding!\n"); 1539 continue; 1540 } 1541 sc->codecs[i].vendor_id = 1542 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1543 sc->codecs[i].device_id = 1544 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1545 sc->codecs[i].revision_id = 1546 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1547 sc->codecs[i].stepping_id = 1548 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1549 child = device_add_child(sc->dev, "hdacc", -1); 1550 if (child == NULL) { 1551 device_printf(sc->dev, 1552 "Failed to add CODEC device\n"); 1553 continue; 1554 } 1555 device_set_ivars(child, (void *)(intptr_t)i); 1556 sc->codecs[i].dev = child; 1557 } 1558 } 1559 bus_generic_attach(sc->dev); 1560 1561 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1562 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1563 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1564 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1565 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1566 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1567 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1568 sysctl_hdac_polling, "I", "Enable polling mode"); 1569 } 1570 1571 /**************************************************************************** 1572 * int hdac_suspend(device_t) 1573 * 1574 * Suspend and power down HDA bus and codecs. 1575 ****************************************************************************/ 1576 static int 1577 hdac_suspend(device_t dev) 1578 { 1579 struct hdac_softc *sc = device_get_softc(dev); 1580 1581 HDA_BOOTHVERBOSE( 1582 device_printf(dev, "Suspend...\n"); 1583 ); 1584 bus_generic_suspend(dev); 1585 1586 hdac_lock(sc); 1587 HDA_BOOTHVERBOSE( 1588 device_printf(dev, "Reset controller...\n"); 1589 ); 1590 callout_stop(&sc->poll_callout); 1591 hdac_reset(sc, 0); 1592 hdac_unlock(sc); 1593 callout_drain(&sc->poll_callout); 1594 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1595 HDA_BOOTHVERBOSE( 1596 device_printf(dev, "Suspend done\n"); 1597 ); 1598 return (0); 1599 } 1600 1601 /**************************************************************************** 1602 * int hdac_resume(device_t) 1603 * 1604 * Powerup and restore HDA bus and codecs state. 1605 ****************************************************************************/ 1606 static int 1607 hdac_resume(device_t dev) 1608 { 1609 struct hdac_softc *sc = device_get_softc(dev); 1610 int error; 1611 1612 HDA_BOOTHVERBOSE( 1613 device_printf(dev, "Resume...\n"); 1614 ); 1615 hdac_lock(sc); 1616 1617 /* Quiesce everything */ 1618 HDA_BOOTHVERBOSE( 1619 device_printf(dev, "Reset controller...\n"); 1620 ); 1621 hdac_reset(sc, 1); 1622 1623 /* Initialize the CORB and RIRB */ 1624 hdac_corb_init(sc); 1625 hdac_rirb_init(sc); 1626 1627 HDA_BOOTHVERBOSE( 1628 device_printf(dev, "Starting CORB Engine...\n"); 1629 ); 1630 hdac_corb_start(sc); 1631 HDA_BOOTHVERBOSE( 1632 device_printf(dev, "Starting RIRB Engine...\n"); 1633 ); 1634 hdac_rirb_start(sc); 1635 HDA_BOOTHVERBOSE( 1636 device_printf(dev, "Enabling controller interrupt...\n"); 1637 ); 1638 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1639 HDAC_GCTL_UNSOL); 1640 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1641 DELAY(1000); 1642 hdac_poll_reinit(sc); 1643 hdac_unlock(sc); 1644 1645 error = bus_generic_resume(dev); 1646 HDA_BOOTHVERBOSE( 1647 device_printf(dev, "Resume done\n"); 1648 ); 1649 return (error); 1650 } 1651 1652 /**************************************************************************** 1653 * int hdac_detach(device_t) 1654 * 1655 * Detach and free up resources utilized by the hdac device. 1656 ****************************************************************************/ 1657 static int 1658 hdac_detach(device_t dev) 1659 { 1660 struct hdac_softc *sc = device_get_softc(dev); 1661 device_t *devlist; 1662 int cad, i, devcount, error; 1663 1664 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1665 return (error); 1666 for (i = 0; i < devcount; i++) { 1667 cad = (intptr_t)device_get_ivars(devlist[i]); 1668 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1669 free(devlist, M_TEMP); 1670 return (error); 1671 } 1672 sc->codecs[cad].dev = NULL; 1673 } 1674 free(devlist, M_TEMP); 1675 1676 hdac_lock(sc); 1677 hdac_reset(sc, 0); 1678 hdac_unlock(sc); 1679 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1680 hdac_irq_free(sc); 1681 1682 for (i = 0; i < sc->num_ss; i++) 1683 hdac_dma_free(sc, &sc->streams[i].bdl); 1684 free(sc->streams, M_HDAC); 1685 hdac_dma_free(sc, &sc->pos_dma); 1686 hdac_dma_free(sc, &sc->rirb_dma); 1687 hdac_dma_free(sc, &sc->corb_dma); 1688 if (sc->chan_dmat != NULL) { 1689 bus_dma_tag_destroy(sc->chan_dmat); 1690 sc->chan_dmat = NULL; 1691 } 1692 hdac_mem_free(sc); 1693 snd_mtxfree(sc->lock); 1694 return (0); 1695 } 1696 1697 static bus_dma_tag_t 1698 hdac_get_dma_tag(device_t dev, device_t child) 1699 { 1700 struct hdac_softc *sc = device_get_softc(dev); 1701 1702 return (sc->chan_dmat); 1703 } 1704 1705 static int 1706 hdac_print_child(device_t dev, device_t child) 1707 { 1708 int retval; 1709 1710 retval = bus_print_child_header(dev, child); 1711 retval += printf(" at cad %d", 1712 (int)(intptr_t)device_get_ivars(child)); 1713 retval += bus_print_child_footer(dev, child); 1714 1715 return (retval); 1716 } 1717 1718 static int 1719 hdac_child_location_str(device_t dev, device_t child, char *buf, 1720 size_t buflen) 1721 { 1722 1723 snprintf(buf, buflen, "cad=%d", 1724 (int)(intptr_t)device_get_ivars(child)); 1725 return (0); 1726 } 1727 1728 static int 1729 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1730 size_t buflen) 1731 { 1732 struct hdac_softc *sc = device_get_softc(dev); 1733 nid_t cad = (uintptr_t)device_get_ivars(child); 1734 1735 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1736 "stepping=0x%02x", 1737 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1738 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1739 return (0); 1740 } 1741 1742 static int 1743 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1744 { 1745 struct hdac_softc *sc = device_get_softc(dev); 1746 nid_t cad = (uintptr_t)device_get_ivars(child); 1747 1748 switch (which) { 1749 case HDA_IVAR_CODEC_ID: 1750 *result = cad; 1751 break; 1752 case HDA_IVAR_VENDOR_ID: 1753 *result = sc->codecs[cad].vendor_id; 1754 break; 1755 case HDA_IVAR_DEVICE_ID: 1756 *result = sc->codecs[cad].device_id; 1757 break; 1758 case HDA_IVAR_REVISION_ID: 1759 *result = sc->codecs[cad].revision_id; 1760 break; 1761 case HDA_IVAR_STEPPING_ID: 1762 *result = sc->codecs[cad].stepping_id; 1763 break; 1764 case HDA_IVAR_SUBVENDOR_ID: 1765 *result = pci_get_subvendor(dev); 1766 break; 1767 case HDA_IVAR_SUBDEVICE_ID: 1768 *result = pci_get_subdevice(dev); 1769 break; 1770 case HDA_IVAR_DMA_NOCACHE: 1771 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1772 break; 1773 case HDA_IVAR_STRIPES_MASK: 1774 *result = (1 << (1 << sc->num_sdo)) - 1; 1775 break; 1776 default: 1777 return (ENOENT); 1778 } 1779 return (0); 1780 } 1781 1782 static struct mtx * 1783 hdac_get_mtx(device_t dev, device_t child) 1784 { 1785 struct hdac_softc *sc = device_get_softc(dev); 1786 1787 return (sc->lock); 1788 } 1789 1790 static uint32_t 1791 hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1792 { 1793 1794 return (hdac_send_command(device_get_softc(dev), 1795 (intptr_t)device_get_ivars(child), verb)); 1796 } 1797 1798 static int 1799 hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1800 { 1801 int i, ss; 1802 1803 ss = -1; 1804 /* Allocate ISS/OSS first. */ 1805 if (dir == 0) { 1806 for (i = 0; i < sc->num_iss; i++) { 1807 if (sc->streams[i].stream == stream) { 1808 ss = i; 1809 break; 1810 } 1811 } 1812 } else { 1813 for (i = 0; i < sc->num_oss; i++) { 1814 if (sc->streams[i + sc->num_iss].stream == stream) { 1815 ss = i + sc->num_iss; 1816 break; 1817 } 1818 } 1819 } 1820 /* Fallback to BSS. */ 1821 if (ss == -1) { 1822 for (i = 0; i < sc->num_bss; i++) { 1823 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1824 == stream) { 1825 ss = i + sc->num_iss + sc->num_oss; 1826 break; 1827 } 1828 } 1829 } 1830 return (ss); 1831 } 1832 1833 static int 1834 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1835 uint32_t **dmapos) 1836 { 1837 struct hdac_softc *sc = device_get_softc(dev); 1838 nid_t cad = (uintptr_t)device_get_ivars(child); 1839 int stream, ss, bw, maxbw, prevbw; 1840 1841 /* Look for empty stream. */ 1842 ss = hdac_find_stream(sc, dir, 0); 1843 1844 /* Return if found nothing. */ 1845 if (ss < 0) 1846 return (0); 1847 1848 /* Check bus bandwidth. */ 1849 bw = hdac_bdata_rate(format, dir); 1850 if (dir == 1) { 1851 bw *= 1 << (sc->num_sdo - stripe); 1852 prevbw = sc->sdo_bw_used; 1853 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1854 } else { 1855 prevbw = sc->codecs[cad].sdi_bw_used; 1856 maxbw = 48000 * 464; 1857 } 1858 HDA_BOOTHVERBOSE( 1859 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1860 (bw + prevbw) / 1000, maxbw / 1000, 1861 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1862 ); 1863 if (bw + prevbw > maxbw) 1864 return (0); 1865 if (dir == 1) 1866 sc->sdo_bw_used += bw; 1867 else 1868 sc->codecs[cad].sdi_bw_used += bw; 1869 1870 /* Allocate stream number */ 1871 if (ss >= sc->num_iss + sc->num_oss) 1872 stream = 15 - (ss - sc->num_iss - sc->num_oss); 1873 else if (ss >= sc->num_iss) 1874 stream = ss - sc->num_iss + 1; 1875 else 1876 stream = ss + 1; 1877 1878 sc->streams[ss].dev = child; 1879 sc->streams[ss].dir = dir; 1880 sc->streams[ss].stream = stream; 1881 sc->streams[ss].bw = bw; 1882 sc->streams[ss].format = format; 1883 sc->streams[ss].stripe = stripe; 1884 if (dmapos != NULL) { 1885 if (sc->pos_dma.dma_vaddr != NULL) 1886 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1887 else 1888 *dmapos = NULL; 1889 } 1890 return (stream); 1891 } 1892 1893 static void 1894 hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1895 { 1896 struct hdac_softc *sc = device_get_softc(dev); 1897 nid_t cad = (uintptr_t)device_get_ivars(child); 1898 int ss; 1899 1900 ss = hdac_find_stream(sc, dir, stream); 1901 KASSERT(ss >= 0, 1902 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1903 if (dir == 1) 1904 sc->sdo_bw_used -= sc->streams[ss].bw; 1905 else 1906 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1907 sc->streams[ss].stream = 0; 1908 sc->streams[ss].dev = NULL; 1909 } 1910 1911 static int 1912 hdac_stream_start(device_t dev, device_t child, 1913 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1914 { 1915 struct hdac_softc *sc = device_get_softc(dev); 1916 struct hdac_bdle *bdle; 1917 uint64_t addr; 1918 int i, ss, off; 1919 uint32_t ctl; 1920 1921 ss = hdac_find_stream(sc, dir, stream); 1922 KASSERT(ss >= 0, 1923 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1924 1925 addr = (uint64_t)buf; 1926 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1927 for (i = 0; i < blkcnt; i++, bdle++) { 1928 bdle->addrl = htole32((uint32_t)addr); 1929 bdle->addrh = htole32((uint32_t)(addr >> 32)); 1930 bdle->len = htole32(blksz); 1931 bdle->ioc = htole32(1); 1932 addr += blksz; 1933 } 1934 1935 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag, 1936 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_PREWRITE); 1937 1938 off = ss << 5; 1939 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1940 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1941 addr = sc->streams[ss].bdl.dma_paddr; 1942 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1943 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1944 1945 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1946 if (dir) 1947 ctl |= HDAC_SDCTL2_DIR; 1948 else 1949 ctl &= ~HDAC_SDCTL2_DIR; 1950 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1951 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1952 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1953 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1954 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1955 1956 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1957 1958 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1959 ctl |= 1 << ss; 1960 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1961 1962 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 1963 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 1964 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1965 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1966 HDAC_SDCTL_RUN; 1967 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1968 1969 sc->streams[ss].blksz = blksz; 1970 sc->streams[ss].running = 1; 1971 hdac_poll_reinit(sc); 1972 return (0); 1973 } 1974 1975 static void 1976 hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1977 { 1978 struct hdac_softc *sc = device_get_softc(dev); 1979 int ss, off; 1980 uint32_t ctl; 1981 1982 ss = hdac_find_stream(sc, dir, stream); 1983 KASSERT(ss >= 0, 1984 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1985 1986 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag, 1987 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_POSTWRITE); 1988 1989 off = ss << 5; 1990 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1991 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1992 HDAC_SDCTL_RUN); 1993 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1994 1995 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1996 ctl &= ~(1 << ss); 1997 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1998 1999 sc->streams[ss].running = 0; 2000 hdac_poll_reinit(sc); 2001 } 2002 2003 static void 2004 hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 2005 { 2006 struct hdac_softc *sc = device_get_softc(dev); 2007 int timeout = 1000; 2008 int to = timeout; 2009 int ss, off; 2010 uint32_t ctl; 2011 2012 ss = hdac_find_stream(sc, dir, stream); 2013 KASSERT(ss >= 0, 2014 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2015 2016 off = ss << 5; 2017 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2018 ctl |= HDAC_SDCTL_SRST; 2019 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2020 do { 2021 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2022 if (ctl & HDAC_SDCTL_SRST) 2023 break; 2024 DELAY(10); 2025 } while (--to); 2026 if (!(ctl & HDAC_SDCTL_SRST)) 2027 device_printf(dev, "Reset setting timeout\n"); 2028 ctl &= ~HDAC_SDCTL_SRST; 2029 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2030 to = timeout; 2031 do { 2032 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2033 if (!(ctl & HDAC_SDCTL_SRST)) 2034 break; 2035 DELAY(10); 2036 } while (--to); 2037 if (ctl & HDAC_SDCTL_SRST) 2038 device_printf(dev, "Reset timeout!\n"); 2039 } 2040 2041 static uint32_t 2042 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2043 { 2044 struct hdac_softc *sc = device_get_softc(dev); 2045 int ss, off; 2046 2047 ss = hdac_find_stream(sc, dir, stream); 2048 KASSERT(ss >= 0, 2049 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2050 2051 off = ss << 5; 2052 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2053 } 2054 2055 static int 2056 hdac_unsol_alloc(device_t dev, device_t child, int tag) 2057 { 2058 struct hdac_softc *sc = device_get_softc(dev); 2059 2060 sc->unsol_registered++; 2061 hdac_poll_reinit(sc); 2062 return (tag); 2063 } 2064 2065 static void 2066 hdac_unsol_free(device_t dev, device_t child, int tag) 2067 { 2068 struct hdac_softc *sc = device_get_softc(dev); 2069 2070 sc->unsol_registered--; 2071 hdac_poll_reinit(sc); 2072 } 2073 2074 static device_method_t hdac_methods[] = { 2075 /* device interface */ 2076 DEVMETHOD(device_probe, hdac_probe), 2077 DEVMETHOD(device_attach, hdac_attach), 2078 DEVMETHOD(device_detach, hdac_detach), 2079 DEVMETHOD(device_suspend, hdac_suspend), 2080 DEVMETHOD(device_resume, hdac_resume), 2081 /* Bus interface */ 2082 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2083 DEVMETHOD(bus_print_child, hdac_print_child), 2084 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2085 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2086 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2087 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2088 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2089 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2090 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2091 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2092 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2093 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2094 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2095 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2096 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2097 DEVMETHOD_END 2098 }; 2099 2100 static driver_t hdac_driver = { 2101 "hdac", 2102 hdac_methods, 2103 sizeof(struct hdac_softc), 2104 }; 2105 2106 static devclass_t hdac_devclass; 2107 2108 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL); 2109