1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 5 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Intel High Definition Audio (Controller) driver for FreeBSD. 33 */ 34 35 #ifdef HAVE_KERNEL_OPTION_HEADERS 36 #include "opt_snd.h" 37 #endif 38 39 #include <dev/sound/pcm/sound.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 43 #include <sys/ctype.h> 44 #include <sys/endian.h> 45 #include <sys/taskqueue.h> 46 47 #include <dev/sound/pci/hda/hdac_private.h> 48 #include <dev/sound/pci/hda/hdac_reg.h> 49 #include <dev/sound/pci/hda/hda_reg.h> 50 #include <dev/sound/pci/hda/hdac.h> 51 52 #define HDA_DRV_TEST_REV "20120126_0002" 53 54 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 55 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 56 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 57 58 #define HDAC_QUIRK_64BIT (1 << 0) 59 #define HDAC_QUIRK_DMAPOS (1 << 1) 60 #define HDAC_QUIRK_MSI (1 << 2) 61 62 static const struct { 63 const char *key; 64 uint32_t value; 65 } hdac_quirks_tab[] = { 66 { "64bit", HDAC_QUIRK_64BIT }, 67 { "dmapos", HDAC_QUIRK_DMAPOS }, 68 { "msi", HDAC_QUIRK_MSI }, 69 }; 70 71 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 72 73 static const struct { 74 uint32_t model; 75 const char *desc; 76 char quirks_on; 77 char quirks_off; 78 } hdac_devices[] = { 79 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 }, 80 { HDA_INTEL_CMLKLP, "Intel Comet Lake-LP", 0, 0 }, 81 { HDA_INTEL_CMLKH, "Intel Comet Lake-H", 0, 0 }, 82 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 }, 83 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 }, 84 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 }, 85 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 }, 86 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 }, 87 { HDA_INTEL_BDW2, "Intel Broadwell", 0, 0 }, 88 { HDA_INTEL_BXTNT, "Intel Broxton-T", 0, 0 }, 89 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 90 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 91 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 92 { HDA_INTEL_BR, "Intel Braswell", 0, 0 }, 93 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 }, 94 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 }, 95 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 }, 96 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 }, 97 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 }, 98 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 }, 99 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 }, 100 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 }, 101 { HDA_INTEL_KBLKLP, "Intel Kaby Lake-LP", 0, 0 }, 102 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 }, 103 { HDA_INTEL_KBLK, "Intel Kaby Lake", 0, 0 }, 104 { HDA_INTEL_KBLKH, "Intel Kaby Lake-H", 0, 0 }, 105 { HDA_INTEL_CFLK, "Intel Coffee Lake", 0, 0 }, 106 { HDA_INTEL_CMLKS, "Intel Comet Lake-S", 0, 0 }, 107 { HDA_INTEL_CNLK, "Intel Cannon Lake", 0, 0 }, 108 { HDA_INTEL_ICLK, "Intel Ice Lake", 0, 0 }, 109 { HDA_INTEL_TGLK, "Intel Tiger Lake", 0, 0 }, 110 { HDA_INTEL_TGLKH, "Intel Tiger Lake-H", 0, 0 }, 111 { HDA_INTEL_GMLK, "Intel Gemini Lake", 0, 0 }, 112 { HDA_INTEL_ALLK, "Intel Alder Lake", 0, 0 }, 113 { HDA_INTEL_ALLKM, "Intel Alder Lake-M", 0, 0 }, 114 { HDA_INTEL_ALLKN, "Intel Alder Lake-N", 0, 0 }, 115 { HDA_INTEL_ALLKP1, "Intel Alder Lake-P", 0, 0 }, 116 { HDA_INTEL_ALLKP2, "Intel Alder Lake-P", 0, 0 }, 117 { HDA_INTEL_ALLKPS, "Intel Alder Lake-PS", 0, 0 }, 118 { HDA_INTEL_RPTLK1, "Intel Raptor Lake-P", 0, 0 }, 119 { HDA_INTEL_RPTLK2, "Intel Raptor Lake-P", 0, 0 }, 120 { HDA_INTEL_RPTLK3, "Intel Raptor Lake-S", 0, 0 }, 121 { HDA_INTEL_MTL, "Intel Meteor Lake-P", 0, 0 }, 122 { HDA_INTEL_ARLS, "Intel Arrow Lake-S", 0, 0 }, 123 { HDA_INTEL_ARL, "Intel Arrow Lake", 0, 0 }, 124 { HDA_INTEL_LNLP, "Intel Lunar Lake-P", 0, 0 }, 125 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 126 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 127 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 128 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 129 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 130 { HDA_INTEL_JLK, "Intel Jasper Lake", 0, 0 }, 131 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 132 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 133 { HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 }, 134 { HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 }, 135 { HDA_INTEL_ELLK, "Intel Elkhart Lake", 0, 0 }, 136 { HDA_INTEL_ELLK2, "Intel Elkhart Lake", 0, 0 }, 137 { HDA_INTEL_JLK2, "Intel Jasper Lake", 0, 0 }, 138 { HDA_INTEL_BXTNP, "Intel Broxton-P", 0, 0 }, 139 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 140 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 141 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 142 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 143 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 144 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 145 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 146 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 147 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 148 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 149 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 150 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 151 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 152 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 153 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 154 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 155 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 156 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 157 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 158 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 159 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 160 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 161 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 162 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 163 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 164 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 165 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 166 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 167 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 168 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 169 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 170 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 171 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 172 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 173 { HDA_ATI_RAVEN, "ATI Raven", 0, 0 }, 174 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 175 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 176 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 177 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 178 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 179 { HDA_ATI_RS880, "ATI RS880", 0, 0 }, 180 { HDA_ATI_R600, "ATI R600", 0, 0 }, 181 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 182 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 183 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 184 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 185 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 186 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 187 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 188 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 189 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 190 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 191 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 192 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 193 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 194 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 195 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 196 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 197 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 198 { HDA_ATI_OLAND, "ATI Oland", 0, 0 }, 199 { HDA_ATI_KABINI, "ATI Kabini", 0, 0 }, 200 { HDA_ATI_TRINITY, "ATI Trinity", 0, 0 }, 201 { HDA_AMD_X370, "AMD X370", 0, 0 }, 202 { HDA_AMD_X570, "AMD X570", 0, 0 }, 203 { HDA_AMD_STONEY, "AMD Stoney", 0, 0 }, 204 { HDA_AMD_RAVEN, "AMD Raven", 0, 0 }, 205 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 }, 206 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 207 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 208 { HDA_VMWARE, "VMware", 0, 0 }, 209 { HDA_SIS_966, "SiS 966/968", 0, 0 }, 210 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 211 { HDA_CREATIVE_SB1570, "Creative SB Audigy FX", 0, HDAC_QUIRK_64BIT }, 212 /* Unknown */ 213 { HDA_INTEL_ALL, "Intel", 0, 0 }, 214 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 215 { HDA_ATI_ALL, "ATI", 0, 0 }, 216 { HDA_AMD_ALL, "AMD", 0, 0 }, 217 { HDA_CREATIVE_ALL, "Creative", 0, 0 }, 218 { HDA_VIA_ALL, "VIA", 0, 0 }, 219 { HDA_VMWARE_ALL, "VMware", 0, 0 }, 220 { HDA_SIS_ALL, "SiS", 0, 0 }, 221 { HDA_ULI_ALL, "ULI", 0, 0 }, 222 }; 223 224 static const struct { 225 uint16_t vendor; 226 uint8_t reg; 227 uint8_t mask; 228 uint8_t enable; 229 } hdac_pcie_snoop[] = { 230 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 231 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 232 { AMD_VENDORID, 0x42, 0xf8, 0x02 }, 233 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 234 }; 235 236 /**************************************************************************** 237 * Function prototypes 238 ****************************************************************************/ 239 static void hdac_intr_handler(void *); 240 static int hdac_reset(struct hdac_softc *, bool); 241 static int hdac_get_capabilities(struct hdac_softc *); 242 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 243 static int hdac_dma_alloc(struct hdac_softc *, 244 struct hdac_dma *, bus_size_t); 245 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 246 static int hdac_mem_alloc(struct hdac_softc *); 247 static void hdac_mem_free(struct hdac_softc *); 248 static int hdac_irq_alloc(struct hdac_softc *); 249 static void hdac_irq_free(struct hdac_softc *); 250 static void hdac_corb_init(struct hdac_softc *); 251 static void hdac_rirb_init(struct hdac_softc *); 252 static void hdac_corb_start(struct hdac_softc *); 253 static void hdac_rirb_start(struct hdac_softc *); 254 255 static void hdac_attach2(void *); 256 257 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 258 259 static int hdac_probe(device_t); 260 static int hdac_attach(device_t); 261 static int hdac_detach(device_t); 262 static int hdac_suspend(device_t); 263 static int hdac_resume(device_t); 264 265 static int hdac_rirb_flush(struct hdac_softc *sc); 266 static int hdac_unsolq_flush(struct hdac_softc *sc); 267 268 /* This function surely going to make its way into upper level someday. */ 269 static void 270 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 271 { 272 const char *res = NULL; 273 int i = 0, j, k, len, inv; 274 275 if (resource_string_value(device_get_name(sc->dev), 276 device_get_unit(sc->dev), "config", &res) != 0) 277 return; 278 if (!(res != NULL && strlen(res) > 0)) 279 return; 280 HDA_BOOTVERBOSE( 281 device_printf(sc->dev, "Config options:"); 282 ); 283 for (;;) { 284 while (res[i] != '\0' && 285 (res[i] == ',' || isspace(res[i]) != 0)) 286 i++; 287 if (res[i] == '\0') { 288 HDA_BOOTVERBOSE( 289 printf("\n"); 290 ); 291 return; 292 } 293 j = i; 294 while (res[j] != '\0' && 295 !(res[j] == ',' || isspace(res[j]) != 0)) 296 j++; 297 len = j - i; 298 if (len > 2 && strncmp(res + i, "no", 2) == 0) 299 inv = 2; 300 else 301 inv = 0; 302 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) { 303 if (strncmp(res + i + inv, 304 hdac_quirks_tab[k].key, len - inv) != 0) 305 continue; 306 if (len - inv != strlen(hdac_quirks_tab[k].key)) 307 continue; 308 HDA_BOOTVERBOSE( 309 printf(" %s%s", (inv != 0) ? "no" : "", 310 hdac_quirks_tab[k].key); 311 ); 312 if (inv == 0) { 313 *on |= hdac_quirks_tab[k].value; 314 *off &= ~hdac_quirks_tab[k].value; 315 } else if (inv != 0) { 316 *off |= hdac_quirks_tab[k].value; 317 *on &= ~hdac_quirks_tab[k].value; 318 } 319 break; 320 } 321 i = j; 322 } 323 } 324 325 static void 326 hdac_one_intr(struct hdac_softc *sc, uint32_t intsts) 327 { 328 device_t dev; 329 uint8_t rirbsts; 330 int i; 331 332 /* Was this a controller interrupt? */ 333 if (intsts & HDAC_INTSTS_CIS) { 334 /* 335 * Placeholder: if we ever enable any bits in HDAC_WAKEEN, then 336 * we will need to check and clear HDAC_STATESTS. 337 * That event is used to report codec status changes such as 338 * a reset or a wake-up event. 339 */ 340 /* 341 * Placeholder: if we ever enable HDAC_CORBCTL_CMEIE, then we 342 * will need to check and clear HDAC_CORBSTS_CMEI in 343 * HDAC_CORBSTS. 344 * That event is used to report CORB memory errors. 345 */ 346 /* 347 * Placeholder: if we ever enable HDAC_RIRBCTL_RIRBOIC, then we 348 * will need to check and clear HDAC_RIRBSTS_RIRBOIS in 349 * HDAC_RIRBSTS. 350 * That event is used to report response FIFO overruns. 351 */ 352 353 /* Get as many responses that we can */ 354 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 355 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 356 HDAC_WRITE_1(&sc->mem, 357 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 358 hdac_rirb_flush(sc); 359 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 360 } 361 if (sc->unsolq_rp != sc->unsolq_wp) 362 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 363 } 364 365 if (intsts & HDAC_INTSTS_SIS_MASK) { 366 for (i = 0; i < sc->num_ss; i++) { 367 if ((intsts & (1 << i)) == 0) 368 continue; 369 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 370 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 371 if ((dev = sc->streams[i].dev) != NULL) { 372 HDAC_STREAM_INTR(dev, 373 sc->streams[i].dir, sc->streams[i].stream); 374 } 375 } 376 } 377 } 378 379 /**************************************************************************** 380 * void hdac_intr_handler(void *) 381 * 382 * Interrupt handler. Processes interrupts received from the hdac. 383 ****************************************************************************/ 384 static void 385 hdac_intr_handler(void *context) 386 { 387 struct hdac_softc *sc; 388 uint32_t intsts; 389 390 sc = (struct hdac_softc *)context; 391 392 /* 393 * Loop until HDAC_INTSTS_GIS gets clear. 394 * It is plausible that hardware interrupts a host only when GIS goes 395 * from zero to one. GIS is formed by OR-ing multiple hardware 396 * statuses, so it's possible that a previously cleared status gets set 397 * again while another status has not been cleared yet. Thus, there 398 * will be no new interrupt as GIS always stayed set. If we don't 399 * re-examine GIS then we can leave it set and never get an interrupt 400 * again. 401 */ 402 hdac_lock(sc); 403 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 404 while (intsts != 0xffffffff && (intsts & HDAC_INTSTS_GIS) != 0) { 405 hdac_one_intr(sc, intsts); 406 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 407 } 408 hdac_unlock(sc); 409 } 410 411 static void 412 hdac_poll_callback(void *arg) 413 { 414 struct hdac_softc *sc = arg; 415 416 if (sc == NULL) 417 return; 418 419 hdac_lock(sc); 420 if (sc->polling == 0) { 421 hdac_unlock(sc); 422 return; 423 } 424 callout_reset(&sc->poll_callout, sc->poll_ival, hdac_poll_callback, sc); 425 hdac_unlock(sc); 426 427 hdac_intr_handler(sc); 428 } 429 430 /**************************************************************************** 431 * int hdac_reset(hdac_softc *, bool) 432 * 433 * Reset the hdac to a quiescent and known state. 434 ****************************************************************************/ 435 static int 436 hdac_reset(struct hdac_softc *sc, bool wakeup) 437 { 438 uint32_t gctl; 439 int count, i; 440 441 /* 442 * Stop all Streams DMA engine 443 */ 444 for (i = 0; i < sc->num_iss; i++) 445 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 446 for (i = 0; i < sc->num_oss; i++) 447 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 448 for (i = 0; i < sc->num_bss; i++) 449 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 450 451 /* 452 * Stop Control DMA engines. 453 */ 454 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 455 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 456 457 /* 458 * Reset DMA position buffer. 459 */ 460 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 461 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 462 463 /* 464 * Reset the controller. The reset must remain asserted for 465 * a minimum of 100us. 466 */ 467 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 468 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 469 count = 10000; 470 do { 471 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 472 if (!(gctl & HDAC_GCTL_CRST)) 473 break; 474 DELAY(10); 475 } while (--count); 476 if (gctl & HDAC_GCTL_CRST) { 477 device_printf(sc->dev, "Unable to put hdac in reset\n"); 478 return (ENXIO); 479 } 480 481 /* If wakeup is not requested - leave the controller in reset state. */ 482 if (!wakeup) 483 return (0); 484 485 DELAY(100); 486 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 487 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 488 count = 10000; 489 do { 490 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 491 if (gctl & HDAC_GCTL_CRST) 492 break; 493 DELAY(10); 494 } while (--count); 495 if (!(gctl & HDAC_GCTL_CRST)) { 496 device_printf(sc->dev, "Device stuck in reset\n"); 497 return (ENXIO); 498 } 499 500 /* 501 * Wait for codecs to finish their own reset sequence. The delay here 502 * must be at least 521us (HDA 1.0a section 4.3 Codec Discovery). 503 */ 504 DELAY(1000); 505 506 return (0); 507 } 508 509 /**************************************************************************** 510 * int hdac_get_capabilities(struct hdac_softc *); 511 * 512 * Retreive the general capabilities of the hdac; 513 * Number of Input Streams 514 * Number of Output Streams 515 * Number of bidirectional Streams 516 * 64bit ready 517 * CORB and RIRB sizes 518 ****************************************************************************/ 519 static int 520 hdac_get_capabilities(struct hdac_softc *sc) 521 { 522 uint16_t gcap; 523 uint8_t corbsize, rirbsize; 524 525 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 526 sc->num_iss = HDAC_GCAP_ISS(gcap); 527 sc->num_oss = HDAC_GCAP_OSS(gcap); 528 sc->num_bss = HDAC_GCAP_BSS(gcap); 529 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 530 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 531 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 532 if (sc->quirks_on & HDAC_QUIRK_64BIT) 533 sc->support_64bit = 1; 534 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 535 sc->support_64bit = 0; 536 537 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 538 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 539 HDAC_CORBSIZE_CORBSZCAP_256) 540 sc->corb_size = 256; 541 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 542 HDAC_CORBSIZE_CORBSZCAP_16) 543 sc->corb_size = 16; 544 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 545 HDAC_CORBSIZE_CORBSZCAP_2) 546 sc->corb_size = 2; 547 else { 548 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 549 __func__, corbsize); 550 return (ENXIO); 551 } 552 553 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 554 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 555 HDAC_RIRBSIZE_RIRBSZCAP_256) 556 sc->rirb_size = 256; 557 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 558 HDAC_RIRBSIZE_RIRBSZCAP_16) 559 sc->rirb_size = 16; 560 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 561 HDAC_RIRBSIZE_RIRBSZCAP_2) 562 sc->rirb_size = 2; 563 else { 564 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 565 __func__, rirbsize); 566 return (ENXIO); 567 } 568 569 HDA_BOOTVERBOSE( 570 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 571 "NSDO %d%s, CORB %d, RIRB %d\n", 572 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 573 sc->support_64bit ? ", 64bit" : "", 574 sc->corb_size, sc->rirb_size); 575 ); 576 577 return (0); 578 } 579 580 /**************************************************************************** 581 * void hdac_dma_cb 582 * 583 * This function is called by bus_dmamap_load when the mapping has been 584 * established. We just record the physical address of the mapping into 585 * the struct hdac_dma passed in. 586 ****************************************************************************/ 587 static void 588 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 589 { 590 struct hdac_dma *dma; 591 592 if (error == 0) { 593 dma = (struct hdac_dma *)callback_arg; 594 dma->dma_paddr = segs[0].ds_addr; 595 } 596 } 597 598 /**************************************************************************** 599 * int hdac_dma_alloc 600 * 601 * This function allocate and setup a dma region (struct hdac_dma). 602 * It must be freed by a corresponding hdac_dma_free. 603 ****************************************************************************/ 604 static int 605 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 606 { 607 bus_size_t roundsz; 608 int result; 609 610 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 611 bzero(dma, sizeof(*dma)); 612 613 /* 614 * Create a DMA tag 615 */ 616 result = bus_dma_tag_create( 617 bus_get_dma_tag(sc->dev), /* parent */ 618 HDA_DMA_ALIGNMENT, /* alignment */ 619 0, /* boundary */ 620 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 621 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 622 BUS_SPACE_MAXADDR, /* highaddr */ 623 NULL, /* filtfunc */ 624 NULL, /* fistfuncarg */ 625 roundsz, /* maxsize */ 626 1, /* nsegments */ 627 roundsz, /* maxsegsz */ 628 0, /* flags */ 629 NULL, /* lockfunc */ 630 NULL, /* lockfuncarg */ 631 &dma->dma_tag); /* dmat */ 632 if (result != 0) { 633 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%d)\n", 634 __func__, result); 635 goto hdac_dma_alloc_fail; 636 } 637 638 /* 639 * Allocate DMA memory 640 */ 641 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 642 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 643 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 644 BUS_DMA_COHERENT), 645 &dma->dma_map); 646 if (result != 0) { 647 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%d)\n", 648 __func__, result); 649 goto hdac_dma_alloc_fail; 650 } 651 652 dma->dma_size = roundsz; 653 654 /* 655 * Map the memory 656 */ 657 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 658 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 659 if (result != 0 || dma->dma_paddr == 0) { 660 if (result == 0) 661 result = ENOMEM; 662 device_printf(sc->dev, "%s: bus_dmamem_load failed (%d)\n", 663 __func__, result); 664 goto hdac_dma_alloc_fail; 665 } 666 667 HDA_BOOTHVERBOSE( 668 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 669 __func__, (uintmax_t)size, (uintmax_t)roundsz); 670 ); 671 672 return (0); 673 674 hdac_dma_alloc_fail: 675 hdac_dma_free(sc, dma); 676 677 return (result); 678 } 679 680 /**************************************************************************** 681 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 682 * 683 * Free a struct hdac_dma that has been previously allocated via the 684 * hdac_dma_alloc function. 685 ****************************************************************************/ 686 static void 687 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 688 { 689 if (dma->dma_paddr != 0) { 690 /* Flush caches */ 691 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 692 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 693 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 694 dma->dma_paddr = 0; 695 } 696 if (dma->dma_vaddr != NULL) { 697 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 698 dma->dma_vaddr = NULL; 699 } 700 if (dma->dma_tag != NULL) { 701 bus_dma_tag_destroy(dma->dma_tag); 702 dma->dma_tag = NULL; 703 } 704 dma->dma_size = 0; 705 } 706 707 /**************************************************************************** 708 * int hdac_mem_alloc(struct hdac_softc *) 709 * 710 * Allocate all the bus resources necessary to speak with the physical 711 * controller. 712 ****************************************************************************/ 713 static int 714 hdac_mem_alloc(struct hdac_softc *sc) 715 { 716 struct hdac_mem *mem; 717 718 mem = &sc->mem; 719 mem->mem_rid = PCIR_BAR(0); 720 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 721 &mem->mem_rid, RF_ACTIVE); 722 if (mem->mem_res == NULL) { 723 device_printf(sc->dev, 724 "%s: Unable to allocate memory resource\n", __func__); 725 return (ENOMEM); 726 } 727 mem->mem_tag = rman_get_bustag(mem->mem_res); 728 mem->mem_handle = rman_get_bushandle(mem->mem_res); 729 730 return (0); 731 } 732 733 /**************************************************************************** 734 * void hdac_mem_free(struct hdac_softc *) 735 * 736 * Free up resources previously allocated by hdac_mem_alloc. 737 ****************************************************************************/ 738 static void 739 hdac_mem_free(struct hdac_softc *sc) 740 { 741 struct hdac_mem *mem; 742 743 mem = &sc->mem; 744 if (mem->mem_res != NULL) 745 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 746 mem->mem_res); 747 mem->mem_res = NULL; 748 } 749 750 /**************************************************************************** 751 * int hdac_irq_alloc(struct hdac_softc *) 752 * 753 * Allocate and setup the resources necessary for interrupt handling. 754 ****************************************************************************/ 755 static int 756 hdac_irq_alloc(struct hdac_softc *sc) 757 { 758 struct hdac_irq *irq; 759 int result; 760 761 irq = &sc->irq; 762 irq->irq_rid = 0x0; 763 764 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 765 (result = pci_msi_count(sc->dev)) == 1 && 766 pci_alloc_msi(sc->dev, &result) == 0) 767 irq->irq_rid = 0x1; 768 769 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 770 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 771 if (irq->irq_res == NULL) { 772 device_printf(sc->dev, "%s: Unable to allocate irq\n", 773 __func__); 774 goto hdac_irq_alloc_fail; 775 } 776 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 777 NULL, hdac_intr_handler, sc, &irq->irq_handle); 778 if (result != 0) { 779 device_printf(sc->dev, 780 "%s: Unable to setup interrupt handler (%d)\n", 781 __func__, result); 782 goto hdac_irq_alloc_fail; 783 } 784 785 return (0); 786 787 hdac_irq_alloc_fail: 788 hdac_irq_free(sc); 789 790 return (ENXIO); 791 } 792 793 /**************************************************************************** 794 * void hdac_irq_free(struct hdac_softc *) 795 * 796 * Free up resources previously allocated by hdac_irq_alloc. 797 ****************************************************************************/ 798 static void 799 hdac_irq_free(struct hdac_softc *sc) 800 { 801 struct hdac_irq *irq; 802 803 irq = &sc->irq; 804 if (irq->irq_res != NULL && irq->irq_handle != NULL) 805 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 806 if (irq->irq_res != NULL) 807 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 808 irq->irq_res); 809 if (irq->irq_rid == 0x1) 810 pci_release_msi(sc->dev); 811 irq->irq_handle = NULL; 812 irq->irq_res = NULL; 813 irq->irq_rid = 0x0; 814 } 815 816 /**************************************************************************** 817 * void hdac_corb_init(struct hdac_softc *) 818 * 819 * Initialize the corb registers for operations but do not start it up yet. 820 * The CORB engine must not be running when this function is called. 821 ****************************************************************************/ 822 static void 823 hdac_corb_init(struct hdac_softc *sc) 824 { 825 uint8_t corbsize; 826 uint64_t corbpaddr; 827 828 /* Setup the CORB size. */ 829 switch (sc->corb_size) { 830 case 256: 831 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 832 break; 833 case 16: 834 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 835 break; 836 case 2: 837 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 838 break; 839 default: 840 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 841 } 842 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 843 844 /* Setup the CORB Address in the hdac */ 845 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 846 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 847 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 848 849 /* Set the WP and RP */ 850 sc->corb_wp = 0; 851 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 852 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 853 /* 854 * The HDA specification indicates that the CORBRPRST bit will always 855 * read as zero. Unfortunately, it seems that at least the 82801G 856 * doesn't reset the bit to zero, which stalls the corb engine. 857 * manually reset the bit to zero before continuing. 858 */ 859 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 860 861 /* Enable CORB error reporting */ 862 #if 0 863 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 864 #endif 865 } 866 867 /**************************************************************************** 868 * void hdac_rirb_init(struct hdac_softc *) 869 * 870 * Initialize the rirb registers for operations but do not start it up yet. 871 * The RIRB engine must not be running when this function is called. 872 ****************************************************************************/ 873 static void 874 hdac_rirb_init(struct hdac_softc *sc) 875 { 876 uint8_t rirbsize; 877 uint64_t rirbpaddr; 878 879 /* Setup the RIRB size. */ 880 switch (sc->rirb_size) { 881 case 256: 882 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 883 break; 884 case 16: 885 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 886 break; 887 case 2: 888 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 889 break; 890 default: 891 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 892 } 893 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 894 895 /* Setup the RIRB Address in the hdac */ 896 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 897 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 898 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 899 900 /* Setup the WP and RP */ 901 sc->rirb_rp = 0; 902 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 903 904 /* Setup the interrupt threshold */ 905 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 906 907 /* Enable Overrun and response received reporting */ 908 #if 0 909 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 910 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 911 #else 912 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 913 #endif 914 915 /* 916 * Make sure that the Host CPU cache doesn't contain any dirty 917 * cache lines that falls in the rirb. If I understood correctly, it 918 * should be sufficient to do this only once as the rirb is purely 919 * read-only from now on. 920 */ 921 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 922 BUS_DMASYNC_PREREAD); 923 } 924 925 /**************************************************************************** 926 * void hdac_corb_start(hdac_softc *) 927 * 928 * Startup the corb DMA engine 929 ****************************************************************************/ 930 static void 931 hdac_corb_start(struct hdac_softc *sc) 932 { 933 uint32_t corbctl; 934 935 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 936 corbctl |= HDAC_CORBCTL_CORBRUN; 937 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 938 } 939 940 /**************************************************************************** 941 * void hdac_rirb_start(hdac_softc *) 942 * 943 * Startup the rirb DMA engine 944 ****************************************************************************/ 945 static void 946 hdac_rirb_start(struct hdac_softc *sc) 947 { 948 uint32_t rirbctl; 949 950 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 951 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 952 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 953 } 954 955 static int 956 hdac_rirb_flush(struct hdac_softc *sc) 957 { 958 struct hdac_rirb *rirb_base, *rirb; 959 nid_t cad; 960 uint32_t resp, resp_ex; 961 uint8_t rirbwp; 962 int ret; 963 964 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 965 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 966 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 967 BUS_DMASYNC_POSTREAD); 968 969 ret = 0; 970 while (sc->rirb_rp != rirbwp) { 971 sc->rirb_rp++; 972 sc->rirb_rp %= sc->rirb_size; 973 rirb = &rirb_base[sc->rirb_rp]; 974 resp = le32toh(rirb->response); 975 resp_ex = le32toh(rirb->response_ex); 976 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(resp_ex); 977 if (resp_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 978 sc->unsolq[sc->unsolq_wp++] = resp; 979 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 980 sc->unsolq[sc->unsolq_wp++] = cad; 981 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 982 } else if (sc->codecs[cad].pending <= 0) { 983 device_printf(sc->dev, "Unexpected unsolicited " 984 "response from address %d: %08x\n", cad, resp); 985 } else { 986 sc->codecs[cad].response = resp; 987 sc->codecs[cad].pending--; 988 } 989 ret++; 990 } 991 992 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 993 BUS_DMASYNC_PREREAD); 994 return (ret); 995 } 996 997 static int 998 hdac_unsolq_flush(struct hdac_softc *sc) 999 { 1000 device_t child; 1001 nid_t cad; 1002 uint32_t resp; 1003 int ret = 0; 1004 1005 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 1006 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 1007 while (sc->unsolq_rp != sc->unsolq_wp) { 1008 resp = sc->unsolq[sc->unsolq_rp++]; 1009 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 1010 cad = sc->unsolq[sc->unsolq_rp++]; 1011 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 1012 if ((child = sc->codecs[cad].dev) != NULL && 1013 device_is_attached(child)) 1014 HDAC_UNSOL_INTR(child, resp); 1015 ret++; 1016 } 1017 sc->unsolq_st = HDAC_UNSOLQ_READY; 1018 } 1019 1020 return (ret); 1021 } 1022 1023 /**************************************************************************** 1024 * uint32_t hdac_send_command 1025 * 1026 * Wrapper function that sends only one command to a given codec 1027 ****************************************************************************/ 1028 static uint32_t 1029 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 1030 { 1031 int timeout; 1032 uint32_t *corb; 1033 1034 hdac_lockassert(sc); 1035 verb &= ~HDA_CMD_CAD_MASK; 1036 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 1037 sc->codecs[cad].response = HDA_INVALID; 1038 1039 sc->codecs[cad].pending++; 1040 sc->corb_wp++; 1041 sc->corb_wp %= sc->corb_size; 1042 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 1043 bus_dmamap_sync(sc->corb_dma.dma_tag, 1044 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 1045 corb[sc->corb_wp] = htole32(verb); 1046 bus_dmamap_sync(sc->corb_dma.dma_tag, 1047 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 1048 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1049 1050 timeout = 10000; 1051 do { 1052 if (hdac_rirb_flush(sc) == 0) 1053 DELAY(10); 1054 } while (sc->codecs[cad].pending != 0 && --timeout); 1055 1056 if (sc->codecs[cad].pending != 0) { 1057 device_printf(sc->dev, "Command 0x%08x timeout on address %d\n", 1058 verb, cad); 1059 sc->codecs[cad].pending = 0; 1060 } 1061 1062 if (sc->unsolq_rp != sc->unsolq_wp) 1063 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1064 return (sc->codecs[cad].response); 1065 } 1066 1067 /**************************************************************************** 1068 * Device Methods 1069 ****************************************************************************/ 1070 1071 /**************************************************************************** 1072 * int hdac_probe(device_t) 1073 * 1074 * Probe for the presence of an hdac. If none is found, check for a generic 1075 * match using the subclass of the device. 1076 ****************************************************************************/ 1077 static int 1078 hdac_probe(device_t dev) 1079 { 1080 int i, result; 1081 uint32_t model; 1082 uint16_t class, subclass; 1083 char desc[64]; 1084 1085 model = (uint32_t)pci_get_device(dev) << 16; 1086 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1087 class = pci_get_class(dev); 1088 subclass = pci_get_subclass(dev); 1089 1090 bzero(desc, sizeof(desc)); 1091 result = ENXIO; 1092 for (i = 0; i < nitems(hdac_devices); i++) { 1093 if (hdac_devices[i].model == model) { 1094 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1095 result = BUS_PROBE_DEFAULT; 1096 break; 1097 } 1098 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1099 class == PCIC_MULTIMEDIA && 1100 subclass == PCIS_MULTIMEDIA_HDA) { 1101 snprintf(desc, sizeof(desc), "%s (0x%04x)", 1102 hdac_devices[i].desc, pci_get_device(dev)); 1103 result = BUS_PROBE_GENERIC; 1104 break; 1105 } 1106 } 1107 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1108 subclass == PCIS_MULTIMEDIA_HDA) { 1109 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1110 result = BUS_PROBE_GENERIC; 1111 } 1112 if (result != ENXIO) 1113 device_set_descf(dev, "%s HDA Controller", desc); 1114 1115 return (result); 1116 } 1117 1118 static void 1119 hdac_unsolq_task(void *context, int pending) 1120 { 1121 struct hdac_softc *sc; 1122 1123 sc = (struct hdac_softc *)context; 1124 1125 hdac_lock(sc); 1126 hdac_unsolq_flush(sc); 1127 hdac_unlock(sc); 1128 } 1129 1130 /**************************************************************************** 1131 * int hdac_attach(device_t) 1132 * 1133 * Attach the device into the kernel. Interrupts usually won't be enabled 1134 * when this function is called. Setup everything that doesn't require 1135 * interrupts and defer probing of codecs until interrupts are enabled. 1136 ****************************************************************************/ 1137 static int 1138 hdac_attach(device_t dev) 1139 { 1140 struct hdac_softc *sc; 1141 int result; 1142 int i, devid = -1; 1143 uint32_t model; 1144 uint16_t class, subclass; 1145 uint16_t vendor; 1146 uint8_t v; 1147 1148 sc = device_get_softc(dev); 1149 HDA_BOOTVERBOSE( 1150 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n", 1151 pci_get_subvendor(dev), pci_get_subdevice(dev)); 1152 device_printf(dev, "HDA Driver Revision: %s\n", 1153 HDA_DRV_TEST_REV); 1154 ); 1155 1156 model = (uint32_t)pci_get_device(dev) << 16; 1157 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1158 class = pci_get_class(dev); 1159 subclass = pci_get_subclass(dev); 1160 1161 for (i = 0; i < nitems(hdac_devices); i++) { 1162 if (hdac_devices[i].model == model) { 1163 devid = i; 1164 break; 1165 } 1166 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1167 class == PCIC_MULTIMEDIA && 1168 subclass == PCIS_MULTIMEDIA_HDA) { 1169 devid = i; 1170 break; 1171 } 1172 } 1173 1174 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1175 sc->dev = dev; 1176 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1177 callout_init(&sc->poll_callout, 1); 1178 for (i = 0; i < HDAC_CODEC_MAX; i++) 1179 sc->codecs[i].dev = NULL; 1180 if (devid >= 0) { 1181 sc->quirks_on = hdac_devices[devid].quirks_on; 1182 sc->quirks_off = hdac_devices[devid].quirks_off; 1183 } else { 1184 sc->quirks_on = 0; 1185 sc->quirks_off = 0; 1186 } 1187 if (resource_int_value(device_get_name(dev), 1188 device_get_unit(dev), "msi", &i) == 0) { 1189 if (i == 0) 1190 sc->quirks_off |= HDAC_QUIRK_MSI; 1191 else { 1192 sc->quirks_on |= HDAC_QUIRK_MSI; 1193 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1194 } 1195 } 1196 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1197 HDA_BOOTVERBOSE( 1198 device_printf(sc->dev, 1199 "Config options: on=0x%08x off=0x%08x\n", 1200 sc->quirks_on, sc->quirks_off); 1201 ); 1202 sc->poll_ival = hz; 1203 if (resource_int_value(device_get_name(dev), 1204 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1205 sc->polling = 1; 1206 else 1207 sc->polling = 0; 1208 1209 pci_enable_busmaster(dev); 1210 1211 vendor = pci_get_vendor(dev); 1212 if (vendor == INTEL_VENDORID) { 1213 /* TCSEL -> TC0 */ 1214 v = pci_read_config(dev, 0x44, 1); 1215 pci_write_config(dev, 0x44, v & 0xf8, 1); 1216 HDA_BOOTHVERBOSE( 1217 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1218 pci_read_config(dev, 0x44, 1)); 1219 ); 1220 } 1221 1222 #if defined(__i386__) || defined(__amd64__) 1223 sc->flags |= HDAC_F_DMA_NOCACHE; 1224 1225 if (resource_int_value(device_get_name(dev), 1226 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 1227 #else 1228 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1229 #endif 1230 /* 1231 * Try to enable PCIe snoop to avoid messing around with 1232 * uncacheable DMA attribute. Since PCIe snoop register 1233 * config is pretty much vendor specific, there are no 1234 * general solutions on how to enable it, forcing us (even 1235 * Microsoft) to enable uncacheable or write combined DMA 1236 * by default. 1237 * 1238 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 1239 */ 1240 for (i = 0; i < nitems(hdac_pcie_snoop); i++) { 1241 if (hdac_pcie_snoop[i].vendor != vendor) 1242 continue; 1243 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1244 if (hdac_pcie_snoop[i].reg == 0x00) 1245 break; 1246 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1247 if ((v & hdac_pcie_snoop[i].enable) == 1248 hdac_pcie_snoop[i].enable) 1249 break; 1250 v &= hdac_pcie_snoop[i].mask; 1251 v |= hdac_pcie_snoop[i].enable; 1252 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 1253 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1254 if ((v & hdac_pcie_snoop[i].enable) != 1255 hdac_pcie_snoop[i].enable) { 1256 HDA_BOOTVERBOSE( 1257 device_printf(dev, 1258 "WARNING: Failed to enable PCIe " 1259 "snoop!\n"); 1260 ); 1261 #if defined(__i386__) || defined(__amd64__) 1262 sc->flags |= HDAC_F_DMA_NOCACHE; 1263 #endif 1264 } 1265 break; 1266 } 1267 #if defined(__i386__) || defined(__amd64__) 1268 } 1269 #endif 1270 1271 HDA_BOOTHVERBOSE( 1272 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1273 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1274 "Uncacheable" : "PCIe snoop", vendor); 1275 ); 1276 1277 /* Allocate resources */ 1278 result = hdac_mem_alloc(sc); 1279 if (result != 0) 1280 goto hdac_attach_fail; 1281 1282 /* Get Capabilities */ 1283 hdac_reset(sc, 1); 1284 result = hdac_get_capabilities(sc); 1285 if (result != 0) 1286 goto hdac_attach_fail; 1287 1288 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1289 result = hdac_dma_alloc(sc, &sc->corb_dma, 1290 sc->corb_size * sizeof(uint32_t)); 1291 if (result != 0) 1292 goto hdac_attach_fail; 1293 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1294 sc->rirb_size * sizeof(struct hdac_rirb)); 1295 if (result != 0) 1296 goto hdac_attach_fail; 1297 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, 1298 M_HDAC, M_ZERO | M_WAITOK); 1299 for (i = 0; i < sc->num_ss; i++) { 1300 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1301 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1302 if (result != 0) 1303 goto hdac_attach_fail; 1304 } 1305 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1306 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1307 HDA_BOOTVERBOSE( 1308 device_printf(dev, "Failed to " 1309 "allocate DMA pos buffer " 1310 "(non-fatal)\n"); 1311 ); 1312 } else { 1313 uint64_t addr = sc->pos_dma.dma_paddr; 1314 1315 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1316 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1317 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1318 HDAC_DPLBASE_DPLBASE_DMAPBE); 1319 } 1320 } 1321 1322 result = bus_dma_tag_create( 1323 bus_get_dma_tag(sc->dev), /* parent */ 1324 HDA_DMA_ALIGNMENT, /* alignment */ 1325 0, /* boundary */ 1326 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1327 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1328 BUS_SPACE_MAXADDR, /* highaddr */ 1329 NULL, /* filtfunc */ 1330 NULL, /* fistfuncarg */ 1331 HDA_BUFSZ_MAX, /* maxsize */ 1332 1, /* nsegments */ 1333 HDA_BUFSZ_MAX, /* maxsegsz */ 1334 0, /* flags */ 1335 NULL, /* lockfunc */ 1336 NULL, /* lockfuncarg */ 1337 &sc->chan_dmat); /* dmat */ 1338 if (result != 0) { 1339 device_printf(dev, "%s: bus_dma_tag_create failed (%d)\n", 1340 __func__, result); 1341 goto hdac_attach_fail; 1342 } 1343 1344 /* Quiesce everything */ 1345 HDA_BOOTHVERBOSE( 1346 device_printf(dev, "Reset controller...\n"); 1347 ); 1348 hdac_reset(sc, true); 1349 1350 /* Initialize the CORB and RIRB */ 1351 hdac_corb_init(sc); 1352 hdac_rirb_init(sc); 1353 1354 result = hdac_irq_alloc(sc); 1355 if (result != 0) 1356 goto hdac_attach_fail; 1357 1358 /* Defer remaining of initialization until interrupts are enabled */ 1359 sc->intrhook.ich_func = hdac_attach2; 1360 sc->intrhook.ich_arg = (void *)sc; 1361 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1362 sc->intrhook.ich_func = NULL; 1363 hdac_attach2((void *)sc); 1364 } 1365 1366 return (0); 1367 1368 hdac_attach_fail: 1369 hdac_irq_free(sc); 1370 if (sc->streams != NULL) 1371 for (i = 0; i < sc->num_ss; i++) 1372 hdac_dma_free(sc, &sc->streams[i].bdl); 1373 free(sc->streams, M_HDAC); 1374 hdac_dma_free(sc, &sc->rirb_dma); 1375 hdac_dma_free(sc, &sc->corb_dma); 1376 hdac_mem_free(sc); 1377 snd_mtxfree(sc->lock); 1378 1379 return (ENXIO); 1380 } 1381 1382 static int 1383 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1384 { 1385 struct hdac_softc *sc; 1386 device_t *devlist; 1387 device_t dev; 1388 int devcount, i, err, val; 1389 1390 dev = oidp->oid_arg1; 1391 sc = device_get_softc(dev); 1392 if (sc == NULL) 1393 return (EINVAL); 1394 val = 0; 1395 err = sysctl_handle_int(oidp, &val, 0, req); 1396 if (err != 0 || req->newptr == NULL || val == 0) 1397 return (err); 1398 1399 /* XXX: Temporary. For debugging. */ 1400 if (val == 100) { 1401 hdac_suspend(dev); 1402 return (0); 1403 } else if (val == 101) { 1404 hdac_resume(dev); 1405 return (0); 1406 } 1407 1408 bus_topo_lock(); 1409 1410 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) { 1411 bus_topo_unlock(); 1412 return (err); 1413 } 1414 1415 hdac_lock(sc); 1416 for (i = 0; i < devcount; i++) 1417 HDAC_PINDUMP(devlist[i]); 1418 hdac_unlock(sc); 1419 1420 bus_topo_unlock(); 1421 1422 free(devlist, M_TEMP); 1423 return (0); 1424 } 1425 1426 static int 1427 hdac_mdata_rate(uint16_t fmt) 1428 { 1429 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1430 int rate, bits; 1431 1432 if (fmt & (1 << 14)) 1433 rate = 44100; 1434 else 1435 rate = 48000; 1436 rate *= ((fmt >> 11) & 0x07) + 1; 1437 rate /= ((fmt >> 8) & 0x07) + 1; 1438 bits = mbits[(fmt >> 4) & 0x03]; 1439 bits *= (fmt & 0x0f) + 1; 1440 return (rate * bits); 1441 } 1442 1443 static int 1444 hdac_bdata_rate(uint16_t fmt, int output) 1445 { 1446 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1447 int rate, bits; 1448 1449 rate = 48000; 1450 rate *= ((fmt >> 11) & 0x07) + 1; 1451 bits = bbits[(fmt >> 4) & 0x03]; 1452 bits *= (fmt & 0x0f) + 1; 1453 if (!output) 1454 bits = ((bits + 7) & ~0x07) + 10; 1455 return (rate * bits); 1456 } 1457 1458 static void 1459 hdac_poll_reinit(struct hdac_softc *sc) 1460 { 1461 int i, pollticks, min = 1000000; 1462 struct hdac_stream *s; 1463 1464 if (sc->polling == 0) 1465 return; 1466 if (sc->unsol_registered > 0) 1467 min = hz / 2; 1468 for (i = 0; i < sc->num_ss; i++) { 1469 s = &sc->streams[i]; 1470 if (s->running == 0) 1471 continue; 1472 pollticks = ((uint64_t)hz * s->blksz) / 1473 (hdac_mdata_rate(s->format) / 8); 1474 pollticks >>= 1; 1475 if (pollticks > hz) 1476 pollticks = hz; 1477 if (pollticks < 1) 1478 pollticks = 1; 1479 if (min > pollticks) 1480 min = pollticks; 1481 } 1482 sc->poll_ival = min; 1483 if (min == 1000000) 1484 callout_stop(&sc->poll_callout); 1485 else 1486 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1487 } 1488 1489 static int 1490 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1491 { 1492 struct hdac_softc *sc; 1493 device_t dev; 1494 uint32_t ctl; 1495 int err, val; 1496 1497 dev = oidp->oid_arg1; 1498 sc = device_get_softc(dev); 1499 if (sc == NULL) 1500 return (EINVAL); 1501 hdac_lock(sc); 1502 val = sc->polling; 1503 hdac_unlock(sc); 1504 err = sysctl_handle_int(oidp, &val, 0, req); 1505 1506 if (err != 0 || req->newptr == NULL) 1507 return (err); 1508 if (val < 0 || val > 1) 1509 return (EINVAL); 1510 1511 hdac_lock(sc); 1512 if (val != sc->polling) { 1513 if (val == 0) { 1514 callout_stop(&sc->poll_callout); 1515 hdac_unlock(sc); 1516 callout_drain(&sc->poll_callout); 1517 hdac_lock(sc); 1518 sc->polling = 0; 1519 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1520 ctl |= HDAC_INTCTL_GIE; 1521 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1522 } else { 1523 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1524 ctl &= ~HDAC_INTCTL_GIE; 1525 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1526 sc->polling = 1; 1527 hdac_poll_reinit(sc); 1528 } 1529 } 1530 hdac_unlock(sc); 1531 1532 return (err); 1533 } 1534 1535 static void 1536 hdac_attach2(void *arg) 1537 { 1538 struct hdac_softc *sc; 1539 device_t child; 1540 uint32_t vendorid, revisionid; 1541 int i; 1542 uint16_t statests; 1543 1544 sc = (struct hdac_softc *)arg; 1545 1546 hdac_lock(sc); 1547 1548 /* Remove ourselves from the config hooks */ 1549 if (sc->intrhook.ich_func != NULL) { 1550 config_intrhook_disestablish(&sc->intrhook); 1551 sc->intrhook.ich_func = NULL; 1552 } 1553 1554 HDA_BOOTHVERBOSE( 1555 device_printf(sc->dev, "Starting CORB Engine...\n"); 1556 ); 1557 hdac_corb_start(sc); 1558 HDA_BOOTHVERBOSE( 1559 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1560 ); 1561 hdac_rirb_start(sc); 1562 1563 /* 1564 * Clear HDAC_WAKEEN as at present we have no use for SDI wake 1565 * (status change) interrupts. The documentation says that we 1566 * should not make any assumptions about the state of this register 1567 * and set it explicitly. 1568 * NB: this needs to be done before the interrupt is enabled as 1569 * the handler does not expect this interrupt source. 1570 */ 1571 HDAC_WRITE_2(&sc->mem, HDAC_WAKEEN, 0); 1572 1573 /* 1574 * Read and clear post-reset SDI wake status. 1575 * Each set bit corresponds to a codec that came out of reset. 1576 */ 1577 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1578 HDAC_WRITE_2(&sc->mem, HDAC_STATESTS, statests); 1579 1580 HDA_BOOTHVERBOSE( 1581 device_printf(sc->dev, 1582 "Enabling controller interrupt...\n"); 1583 ); 1584 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1585 HDAC_GCTL_UNSOL); 1586 if (sc->polling == 0) { 1587 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1588 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1589 } 1590 DELAY(1000); 1591 1592 HDA_BOOTHVERBOSE( 1593 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1594 ); 1595 hdac_unlock(sc); 1596 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1597 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1598 HDA_BOOTHVERBOSE( 1599 device_printf(sc->dev, 1600 "Found CODEC at address %d\n", i); 1601 ); 1602 hdac_lock(sc); 1603 vendorid = hdac_send_command(sc, i, 1604 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1605 revisionid = hdac_send_command(sc, i, 1606 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1607 hdac_unlock(sc); 1608 if (vendorid == HDA_INVALID && 1609 revisionid == HDA_INVALID) { 1610 device_printf(sc->dev, 1611 "CODEC at address %d not responding!\n", i); 1612 continue; 1613 } 1614 sc->codecs[i].vendor_id = 1615 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1616 sc->codecs[i].device_id = 1617 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1618 sc->codecs[i].revision_id = 1619 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1620 sc->codecs[i].stepping_id = 1621 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1622 child = device_add_child(sc->dev, "hdacc", DEVICE_UNIT_ANY); 1623 if (child == NULL) { 1624 device_printf(sc->dev, 1625 "Failed to add CODEC device\n"); 1626 continue; 1627 } 1628 device_set_ivars(child, (void *)(intptr_t)i); 1629 sc->codecs[i].dev = child; 1630 } 1631 } 1632 bus_attach_children(sc->dev); 1633 1634 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1635 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1636 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 1637 sizeof(sc->dev), sysctl_hdac_pindump, "I", "Dump pin states/data"); 1638 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1639 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1640 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 1641 sizeof(sc->dev), sysctl_hdac_polling, "I", "Enable polling mode"); 1642 } 1643 1644 /**************************************************************************** 1645 * int hdac_shutdown(device_t) 1646 * 1647 * Power down HDA bus and codecs. 1648 ****************************************************************************/ 1649 static int 1650 hdac_shutdown(device_t dev) 1651 { 1652 struct hdac_softc *sc = device_get_softc(dev); 1653 1654 HDA_BOOTHVERBOSE( 1655 device_printf(dev, "Shutdown...\n"); 1656 ); 1657 callout_drain(&sc->poll_callout); 1658 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1659 bus_generic_shutdown(dev); 1660 1661 hdac_lock(sc); 1662 HDA_BOOTHVERBOSE( 1663 device_printf(dev, "Reset controller...\n"); 1664 ); 1665 hdac_reset(sc, false); 1666 hdac_unlock(sc); 1667 HDA_BOOTHVERBOSE( 1668 device_printf(dev, "Shutdown done\n"); 1669 ); 1670 return (0); 1671 } 1672 1673 /**************************************************************************** 1674 * int hdac_suspend(device_t) 1675 * 1676 * Suspend and power down HDA bus and codecs. 1677 ****************************************************************************/ 1678 static int 1679 hdac_suspend(device_t dev) 1680 { 1681 struct hdac_softc *sc = device_get_softc(dev); 1682 1683 HDA_BOOTHVERBOSE( 1684 device_printf(dev, "Suspend...\n"); 1685 ); 1686 bus_generic_suspend(dev); 1687 1688 hdac_lock(sc); 1689 HDA_BOOTHVERBOSE( 1690 device_printf(dev, "Reset controller...\n"); 1691 ); 1692 callout_stop(&sc->poll_callout); 1693 hdac_reset(sc, false); 1694 hdac_unlock(sc); 1695 callout_drain(&sc->poll_callout); 1696 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1697 HDA_BOOTHVERBOSE( 1698 device_printf(dev, "Suspend done\n"); 1699 ); 1700 return (0); 1701 } 1702 1703 /**************************************************************************** 1704 * int hdac_resume(device_t) 1705 * 1706 * Powerup and restore HDA bus and codecs state. 1707 ****************************************************************************/ 1708 static int 1709 hdac_resume(device_t dev) 1710 { 1711 struct hdac_softc *sc = device_get_softc(dev); 1712 int error; 1713 1714 HDA_BOOTHVERBOSE( 1715 device_printf(dev, "Resume...\n"); 1716 ); 1717 hdac_lock(sc); 1718 1719 /* Quiesce everything */ 1720 HDA_BOOTHVERBOSE( 1721 device_printf(dev, "Reset controller...\n"); 1722 ); 1723 hdac_reset(sc, true); 1724 1725 /* Initialize the CORB and RIRB */ 1726 hdac_corb_init(sc); 1727 hdac_rirb_init(sc); 1728 1729 HDA_BOOTHVERBOSE( 1730 device_printf(dev, "Starting CORB Engine...\n"); 1731 ); 1732 hdac_corb_start(sc); 1733 HDA_BOOTHVERBOSE( 1734 device_printf(dev, "Starting RIRB Engine...\n"); 1735 ); 1736 hdac_rirb_start(sc); 1737 1738 /* 1739 * Clear HDAC_WAKEEN as at present we have no use for SDI wake 1740 * (status change) events. The documentation says that we should 1741 * not make any assumptions about the state of this register and 1742 * set it explicitly. 1743 * Also, clear HDAC_STATESTS. 1744 * NB: this needs to be done before the interrupt is enabled as 1745 * the handler does not expect this interrupt source. 1746 */ 1747 HDAC_WRITE_2(&sc->mem, HDAC_WAKEEN, 0); 1748 HDAC_WRITE_2(&sc->mem, HDAC_STATESTS, HDAC_STATESTS_SDIWAKE_MASK); 1749 1750 HDA_BOOTHVERBOSE( 1751 device_printf(dev, "Enabling controller interrupt...\n"); 1752 ); 1753 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1754 HDAC_GCTL_UNSOL); 1755 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1756 DELAY(1000); 1757 hdac_poll_reinit(sc); 1758 hdac_unlock(sc); 1759 1760 error = bus_generic_resume(dev); 1761 HDA_BOOTHVERBOSE( 1762 device_printf(dev, "Resume done\n"); 1763 ); 1764 return (error); 1765 } 1766 1767 /**************************************************************************** 1768 * int hdac_detach(device_t) 1769 * 1770 * Detach and free up resources utilized by the hdac device. 1771 ****************************************************************************/ 1772 static int 1773 hdac_detach(device_t dev) 1774 { 1775 struct hdac_softc *sc = device_get_softc(dev); 1776 int i, error; 1777 1778 callout_drain(&sc->poll_callout); 1779 hdac_irq_free(sc); 1780 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1781 1782 error = bus_generic_detach(dev); 1783 if (error != 0) 1784 return (error); 1785 1786 hdac_lock(sc); 1787 hdac_reset(sc, false); 1788 hdac_unlock(sc); 1789 1790 for (i = 0; i < sc->num_ss; i++) 1791 hdac_dma_free(sc, &sc->streams[i].bdl); 1792 free(sc->streams, M_HDAC); 1793 hdac_dma_free(sc, &sc->pos_dma); 1794 hdac_dma_free(sc, &sc->rirb_dma); 1795 hdac_dma_free(sc, &sc->corb_dma); 1796 if (sc->chan_dmat != NULL) { 1797 bus_dma_tag_destroy(sc->chan_dmat); 1798 sc->chan_dmat = NULL; 1799 } 1800 hdac_mem_free(sc); 1801 snd_mtxfree(sc->lock); 1802 return (0); 1803 } 1804 1805 static bus_dma_tag_t 1806 hdac_get_dma_tag(device_t dev, device_t child) 1807 { 1808 struct hdac_softc *sc = device_get_softc(dev); 1809 1810 return (sc->chan_dmat); 1811 } 1812 1813 static int 1814 hdac_print_child(device_t dev, device_t child) 1815 { 1816 int retval; 1817 1818 retval = bus_print_child_header(dev, child); 1819 retval += printf(" at cad %d", (int)(intptr_t)device_get_ivars(child)); 1820 retval += bus_print_child_footer(dev, child); 1821 1822 return (retval); 1823 } 1824 1825 static int 1826 hdac_child_location(device_t dev, device_t child, struct sbuf *sb) 1827 { 1828 1829 sbuf_printf(sb, "cad=%d", (int)(intptr_t)device_get_ivars(child)); 1830 return (0); 1831 } 1832 1833 static int 1834 hdac_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 1835 { 1836 struct hdac_softc *sc = device_get_softc(dev); 1837 nid_t cad = (uintptr_t)device_get_ivars(child); 1838 1839 sbuf_printf(sb, 1840 "vendor=0x%04x device=0x%04x revision=0x%02x stepping=0x%02x", 1841 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1842 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1843 return (0); 1844 } 1845 1846 static int 1847 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1848 { 1849 struct hdac_softc *sc = device_get_softc(dev); 1850 nid_t cad = (uintptr_t)device_get_ivars(child); 1851 1852 switch (which) { 1853 case HDA_IVAR_CODEC_ID: 1854 *result = cad; 1855 break; 1856 case HDA_IVAR_VENDOR_ID: 1857 *result = sc->codecs[cad].vendor_id; 1858 break; 1859 case HDA_IVAR_DEVICE_ID: 1860 *result = sc->codecs[cad].device_id; 1861 break; 1862 case HDA_IVAR_REVISION_ID: 1863 *result = sc->codecs[cad].revision_id; 1864 break; 1865 case HDA_IVAR_STEPPING_ID: 1866 *result = sc->codecs[cad].stepping_id; 1867 break; 1868 case HDA_IVAR_SUBVENDOR_ID: 1869 *result = pci_get_subvendor(dev); 1870 break; 1871 case HDA_IVAR_SUBDEVICE_ID: 1872 *result = pci_get_subdevice(dev); 1873 break; 1874 case HDA_IVAR_DMA_NOCACHE: 1875 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1876 break; 1877 case HDA_IVAR_STRIPES_MASK: 1878 *result = (1 << (1 << sc->num_sdo)) - 1; 1879 break; 1880 default: 1881 return (ENOENT); 1882 } 1883 return (0); 1884 } 1885 1886 static struct mtx * 1887 hdac_get_mtx(device_t dev, device_t child) 1888 { 1889 struct hdac_softc *sc = device_get_softc(dev); 1890 1891 return (sc->lock); 1892 } 1893 1894 static uint32_t 1895 hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1896 { 1897 1898 return (hdac_send_command(device_get_softc(dev), 1899 (intptr_t)device_get_ivars(child), verb)); 1900 } 1901 1902 static int 1903 hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1904 { 1905 int i, ss; 1906 1907 ss = -1; 1908 /* Allocate ISS/OSS first. */ 1909 if (dir == 0) { 1910 for (i = 0; i < sc->num_iss; i++) { 1911 if (sc->streams[i].stream == stream) { 1912 ss = i; 1913 break; 1914 } 1915 } 1916 } else { 1917 for (i = 0; i < sc->num_oss; i++) { 1918 if (sc->streams[i + sc->num_iss].stream == stream) { 1919 ss = i + sc->num_iss; 1920 break; 1921 } 1922 } 1923 } 1924 /* Fallback to BSS. */ 1925 if (ss == -1) { 1926 for (i = 0; i < sc->num_bss; i++) { 1927 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1928 == stream) { 1929 ss = i + sc->num_iss + sc->num_oss; 1930 break; 1931 } 1932 } 1933 } 1934 return (ss); 1935 } 1936 1937 static int 1938 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1939 uint32_t **dmapos) 1940 { 1941 struct hdac_softc *sc = device_get_softc(dev); 1942 nid_t cad = (uintptr_t)device_get_ivars(child); 1943 int stream, ss, bw, maxbw, prevbw; 1944 1945 /* Look for empty stream. */ 1946 ss = hdac_find_stream(sc, dir, 0); 1947 1948 /* Return if found nothing. */ 1949 if (ss < 0) 1950 return (0); 1951 1952 /* Check bus bandwidth. */ 1953 bw = hdac_bdata_rate(format, dir); 1954 if (dir == 1) { 1955 bw *= 1 << (sc->num_sdo - stripe); 1956 prevbw = sc->sdo_bw_used; 1957 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1958 } else { 1959 prevbw = sc->codecs[cad].sdi_bw_used; 1960 maxbw = 48000 * 464; 1961 } 1962 HDA_BOOTHVERBOSE( 1963 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1964 (bw + prevbw) / 1000, maxbw / 1000, 1965 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1966 ); 1967 if (bw + prevbw > maxbw) 1968 return (0); 1969 if (dir == 1) 1970 sc->sdo_bw_used += bw; 1971 else 1972 sc->codecs[cad].sdi_bw_used += bw; 1973 1974 /* Allocate stream number */ 1975 if (ss >= sc->num_iss + sc->num_oss) 1976 stream = 15 - (ss - sc->num_iss - sc->num_oss); 1977 else if (ss >= sc->num_iss) 1978 stream = ss - sc->num_iss + 1; 1979 else 1980 stream = ss + 1; 1981 1982 sc->streams[ss].dev = child; 1983 sc->streams[ss].dir = dir; 1984 sc->streams[ss].stream = stream; 1985 sc->streams[ss].bw = bw; 1986 sc->streams[ss].format = format; 1987 sc->streams[ss].stripe = stripe; 1988 if (dmapos != NULL) { 1989 if (sc->pos_dma.dma_vaddr != NULL) 1990 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1991 else 1992 *dmapos = NULL; 1993 } 1994 return (stream); 1995 } 1996 1997 static void 1998 hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1999 { 2000 struct hdac_softc *sc = device_get_softc(dev); 2001 nid_t cad = (uintptr_t)device_get_ivars(child); 2002 int ss; 2003 2004 ss = hdac_find_stream(sc, dir, stream); 2005 KASSERT(ss >= 0, 2006 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 2007 if (dir == 1) 2008 sc->sdo_bw_used -= sc->streams[ss].bw; 2009 else 2010 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 2011 sc->streams[ss].stream = 0; 2012 sc->streams[ss].dev = NULL; 2013 } 2014 2015 static int 2016 hdac_stream_start(device_t dev, device_t child, int dir, int stream, 2017 bus_addr_t buf, int blksz, int blkcnt) 2018 { 2019 struct hdac_softc *sc = device_get_softc(dev); 2020 struct hdac_bdle *bdle; 2021 uint64_t addr; 2022 int i, ss, off; 2023 uint32_t ctl; 2024 2025 ss = hdac_find_stream(sc, dir, stream); 2026 KASSERT(ss >= 0, 2027 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 2028 2029 addr = (uint64_t)buf; 2030 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 2031 for (i = 0; i < blkcnt; i++, bdle++) { 2032 bdle->addrl = htole32((uint32_t)addr); 2033 bdle->addrh = htole32((uint32_t)(addr >> 32)); 2034 bdle->len = htole32(blksz); 2035 bdle->ioc = htole32(1); 2036 addr += blksz; 2037 } 2038 2039 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag, 2040 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_PREWRITE); 2041 2042 off = ss << 5; 2043 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 2044 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 2045 addr = sc->streams[ss].bdl.dma_paddr; 2046 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 2047 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2048 2049 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 2050 if (dir) 2051 ctl |= HDAC_SDCTL2_DIR; 2052 else 2053 ctl &= ~HDAC_SDCTL2_DIR; 2054 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2055 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 2056 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 2057 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 2058 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 2059 2060 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 2061 2062 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2063 ctl |= 1 << ss; 2064 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2065 2066 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 2067 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 2068 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2069 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2070 HDAC_SDCTL_RUN; 2071 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2072 2073 sc->streams[ss].blksz = blksz; 2074 sc->streams[ss].running = 1; 2075 hdac_poll_reinit(sc); 2076 return (0); 2077 } 2078 2079 static void 2080 hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 2081 { 2082 struct hdac_softc *sc = device_get_softc(dev); 2083 int ss, off; 2084 uint32_t ctl; 2085 2086 ss = hdac_find_stream(sc, dir, stream); 2087 KASSERT(ss >= 0, 2088 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 2089 2090 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag, 2091 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_POSTWRITE); 2092 2093 off = ss << 5; 2094 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2095 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2096 HDAC_SDCTL_RUN); 2097 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2098 2099 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2100 ctl &= ~(1 << ss); 2101 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2102 2103 sc->streams[ss].running = 0; 2104 hdac_poll_reinit(sc); 2105 } 2106 2107 static void 2108 hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 2109 { 2110 struct hdac_softc *sc = device_get_softc(dev); 2111 int timeout = 1000; 2112 int to = timeout; 2113 int ss, off; 2114 uint32_t ctl; 2115 2116 ss = hdac_find_stream(sc, dir, stream); 2117 KASSERT(ss >= 0, 2118 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2119 2120 off = ss << 5; 2121 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2122 ctl |= HDAC_SDCTL_SRST; 2123 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2124 do { 2125 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2126 if (ctl & HDAC_SDCTL_SRST) 2127 break; 2128 DELAY(10); 2129 } while (--to); 2130 if (!(ctl & HDAC_SDCTL_SRST)) 2131 device_printf(dev, "Reset setting timeout\n"); 2132 ctl &= ~HDAC_SDCTL_SRST; 2133 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2134 to = timeout; 2135 do { 2136 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2137 if (!(ctl & HDAC_SDCTL_SRST)) 2138 break; 2139 DELAY(10); 2140 } while (--to); 2141 if (ctl & HDAC_SDCTL_SRST) 2142 device_printf(dev, "Reset timeout!\n"); 2143 } 2144 2145 static uint32_t 2146 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2147 { 2148 struct hdac_softc *sc = device_get_softc(dev); 2149 int ss, off; 2150 2151 ss = hdac_find_stream(sc, dir, stream); 2152 KASSERT(ss >= 0, 2153 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2154 2155 off = ss << 5; 2156 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2157 } 2158 2159 static int 2160 hdac_unsol_alloc(device_t dev, device_t child, int tag) 2161 { 2162 struct hdac_softc *sc = device_get_softc(dev); 2163 2164 sc->unsol_registered++; 2165 hdac_poll_reinit(sc); 2166 return (tag); 2167 } 2168 2169 static void 2170 hdac_unsol_free(device_t dev, device_t child, int tag) 2171 { 2172 struct hdac_softc *sc = device_get_softc(dev); 2173 2174 sc->unsol_registered--; 2175 hdac_poll_reinit(sc); 2176 } 2177 2178 static device_method_t hdac_methods[] = { 2179 /* device interface */ 2180 DEVMETHOD(device_probe, hdac_probe), 2181 DEVMETHOD(device_attach, hdac_attach), 2182 DEVMETHOD(device_detach, hdac_detach), 2183 DEVMETHOD(device_shutdown, hdac_shutdown), 2184 DEVMETHOD(device_suspend, hdac_suspend), 2185 DEVMETHOD(device_resume, hdac_resume), 2186 /* Bus interface */ 2187 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2188 DEVMETHOD(bus_print_child, hdac_print_child), 2189 DEVMETHOD(bus_child_location, hdac_child_location), 2190 DEVMETHOD(bus_child_pnpinfo, hdac_child_pnpinfo_method), 2191 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2192 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2193 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2194 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2195 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2196 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2197 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2198 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2199 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2200 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2201 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2202 DEVMETHOD_END 2203 }; 2204 2205 static driver_t hdac_driver = { 2206 "hdac", 2207 hdac_methods, 2208 sizeof(struct hdac_softc), 2209 }; 2210 2211 DRIVER_MODULE_ORDERED(snd_hda, pci, hdac_driver, NULL, NULL, SI_ORDER_ANY); 2212