1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. 31 */ 32 33 #ifdef HAVE_KERNEL_OPTION_HEADERS 34 #include "opt_snd.h" 35 #endif 36 37 #include <dev/sound/pcm/sound.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <sys/ctype.h> 42 #include <sys/taskqueue.h> 43 44 #include <dev/sound/pci/hda/hdac_private.h> 45 #include <dev/sound/pci/hda/hdac_reg.h> 46 #include <dev/sound/pci/hda/hda_reg.h> 47 #include <dev/sound/pci/hda/hdac.h> 48 49 #define HDA_DRV_TEST_REV "20120126_0002" 50 51 SND_DECLARE_FILE("$FreeBSD$"); 52 53 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 54 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 55 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 56 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 57 58 #define HDAC_QUIRK_64BIT (1 << 0) 59 #define HDAC_QUIRK_DMAPOS (1 << 1) 60 #define HDAC_QUIRK_MSI (1 << 2) 61 62 static const struct { 63 char *key; 64 uint32_t value; 65 } hdac_quirks_tab[] = { 66 { "64bit", HDAC_QUIRK_DMAPOS }, 67 { "dmapos", HDAC_QUIRK_DMAPOS }, 68 { "msi", HDAC_QUIRK_MSI }, 69 }; 70 #define HDAC_QUIRKS_TAB_LEN \ 71 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 72 73 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 74 75 static const struct { 76 uint32_t model; 77 char *desc; 78 char quirks_on; 79 char quirks_off; 80 } hdac_devices[] = { 81 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 82 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 83 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 84 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 85 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 86 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 87 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 88 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 89 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 90 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 91 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0, 0 }, 92 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0, 0 }, 93 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 94 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 95 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 96 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 97 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 98 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 99 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 100 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 101 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 102 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 103 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 104 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 105 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 106 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 107 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 108 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 109 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 110 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 111 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 112 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 113 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 114 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 115 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 116 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 117 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 118 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 119 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 120 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 121 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 122 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 123 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 124 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 125 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 126 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 127 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 128 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 129 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 130 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 131 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 132 { HDA_ATI_R600, "ATI R600", 0, 0 }, 133 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 134 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 135 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 136 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 137 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 138 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 139 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 140 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 141 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 142 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 143 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 144 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 145 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 146 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 147 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 148 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 149 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 150 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 151 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 152 { HDA_SIS_966, "SiS 966", 0, 0 }, 153 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 154 /* Unknown */ 155 { HDA_INTEL_ALL, "Intel", 0, 0 }, 156 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 157 { HDA_ATI_ALL, "ATI", 0, 0 }, 158 { HDA_VIA_ALL, "VIA", 0, 0 }, 159 { HDA_SIS_ALL, "SiS", 0, 0 }, 160 { HDA_ULI_ALL, "ULI", 0, 0 }, 161 }; 162 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 163 164 static const struct { 165 uint16_t vendor; 166 uint8_t reg; 167 uint8_t mask; 168 uint8_t enable; 169 } hdac_pcie_snoop[] = { 170 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 171 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 172 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 173 }; 174 #define HDAC_PCIESNOOP_LEN \ 175 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 176 177 /**************************************************************************** 178 * Function prototypes 179 ****************************************************************************/ 180 static void hdac_intr_handler(void *); 181 static int hdac_reset(struct hdac_softc *, int); 182 static int hdac_get_capabilities(struct hdac_softc *); 183 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 184 static int hdac_dma_alloc(struct hdac_softc *, 185 struct hdac_dma *, bus_size_t); 186 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 187 static int hdac_mem_alloc(struct hdac_softc *); 188 static void hdac_mem_free(struct hdac_softc *); 189 static int hdac_irq_alloc(struct hdac_softc *); 190 static void hdac_irq_free(struct hdac_softc *); 191 static void hdac_corb_init(struct hdac_softc *); 192 static void hdac_rirb_init(struct hdac_softc *); 193 static void hdac_corb_start(struct hdac_softc *); 194 static void hdac_rirb_start(struct hdac_softc *); 195 196 static void hdac_attach2(void *); 197 198 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 199 200 static int hdac_probe(device_t); 201 static int hdac_attach(device_t); 202 static int hdac_detach(device_t); 203 static int hdac_suspend(device_t); 204 static int hdac_resume(device_t); 205 206 static int hdac_rirb_flush(struct hdac_softc *sc); 207 static int hdac_unsolq_flush(struct hdac_softc *sc); 208 209 #define hdac_command(a1, a2, a3) \ 210 hdac_send_command(a1, a3, a2) 211 212 /* This function surely going to make its way into upper level someday. */ 213 static void 214 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 215 { 216 const char *res = NULL; 217 int i = 0, j, k, len, inv; 218 219 if (resource_string_value(device_get_name(sc->dev), 220 device_get_unit(sc->dev), "config", &res) != 0) 221 return; 222 if (!(res != NULL && strlen(res) > 0)) 223 return; 224 HDA_BOOTVERBOSE( 225 device_printf(sc->dev, "Config options:"); 226 ); 227 for (;;) { 228 while (res[i] != '\0' && 229 (res[i] == ',' || isspace(res[i]) != 0)) 230 i++; 231 if (res[i] == '\0') { 232 HDA_BOOTVERBOSE( 233 printf("\n"); 234 ); 235 return; 236 } 237 j = i; 238 while (res[j] != '\0' && 239 !(res[j] == ',' || isspace(res[j]) != 0)) 240 j++; 241 len = j - i; 242 if (len > 2 && strncmp(res + i, "no", 2) == 0) 243 inv = 2; 244 else 245 inv = 0; 246 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 247 if (strncmp(res + i + inv, 248 hdac_quirks_tab[k].key, len - inv) != 0) 249 continue; 250 if (len - inv != strlen(hdac_quirks_tab[k].key)) 251 continue; 252 HDA_BOOTVERBOSE( 253 printf(" %s%s", (inv != 0) ? "no" : "", 254 hdac_quirks_tab[k].key); 255 ); 256 if (inv == 0) { 257 *on |= hdac_quirks_tab[k].value; 258 *on &= ~hdac_quirks_tab[k].value; 259 } else if (inv != 0) { 260 *off |= hdac_quirks_tab[k].value; 261 *off &= ~hdac_quirks_tab[k].value; 262 } 263 break; 264 } 265 i = j; 266 } 267 } 268 269 /**************************************************************************** 270 * void hdac_intr_handler(void *) 271 * 272 * Interrupt handler. Processes interrupts received from the hdac. 273 ****************************************************************************/ 274 static void 275 hdac_intr_handler(void *context) 276 { 277 struct hdac_softc *sc; 278 device_t dev; 279 uint32_t intsts; 280 uint8_t rirbsts; 281 int i; 282 283 sc = (struct hdac_softc *)context; 284 hdac_lock(sc); 285 286 /* Do we have anything to do? */ 287 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 288 if ((intsts & HDAC_INTSTS_GIS) == 0) { 289 hdac_unlock(sc); 290 return; 291 } 292 293 /* Was this a controller interrupt? */ 294 if (intsts & HDAC_INTSTS_CIS) { 295 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 296 /* Get as many responses that we can */ 297 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 298 HDAC_WRITE_1(&sc->mem, 299 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 300 hdac_rirb_flush(sc); 301 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 302 } 303 if (sc->unsolq_rp != sc->unsolq_wp) 304 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 305 } 306 307 if (intsts & HDAC_INTSTS_SIS_MASK) { 308 for (i = 0; i < sc->num_ss; i++) { 309 if ((intsts & (1 << i)) == 0) 310 continue; 311 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 312 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 313 if ((dev = sc->streams[i].dev) != NULL) { 314 HDAC_STREAM_INTR(dev, 315 sc->streams[i].dir, sc->streams[i].stream); 316 } 317 } 318 } 319 320 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 321 hdac_unlock(sc); 322 } 323 324 static void 325 hdac_poll_callback(void *arg) 326 { 327 struct hdac_softc *sc = arg; 328 329 if (sc == NULL) 330 return; 331 332 hdac_lock(sc); 333 if (sc->polling == 0) { 334 hdac_unlock(sc); 335 return; 336 } 337 callout_reset(&sc->poll_callout, sc->poll_ival, 338 hdac_poll_callback, sc); 339 hdac_unlock(sc); 340 341 hdac_intr_handler(sc); 342 } 343 344 /**************************************************************************** 345 * int hdac_reset(hdac_softc *, int) 346 * 347 * Reset the hdac to a quiescent and known state. 348 ****************************************************************************/ 349 static int 350 hdac_reset(struct hdac_softc *sc, int wakeup) 351 { 352 uint32_t gctl; 353 int count, i; 354 355 /* 356 * Stop all Streams DMA engine 357 */ 358 for (i = 0; i < sc->num_iss; i++) 359 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 360 for (i = 0; i < sc->num_oss; i++) 361 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 362 for (i = 0; i < sc->num_bss; i++) 363 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 364 365 /* 366 * Stop Control DMA engines. 367 */ 368 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 369 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 370 371 /* 372 * Reset DMA position buffer. 373 */ 374 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 375 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 376 377 /* 378 * Reset the controller. The reset must remain asserted for 379 * a minimum of 100us. 380 */ 381 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 382 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 383 count = 10000; 384 do { 385 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 386 if (!(gctl & HDAC_GCTL_CRST)) 387 break; 388 DELAY(10); 389 } while (--count); 390 if (gctl & HDAC_GCTL_CRST) { 391 device_printf(sc->dev, "Unable to put hdac in reset\n"); 392 return (ENXIO); 393 } 394 395 /* If wakeup is not requested - leave the controller in reset state. */ 396 if (!wakeup) 397 return (0); 398 399 DELAY(100); 400 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 401 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 402 count = 10000; 403 do { 404 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 405 if (gctl & HDAC_GCTL_CRST) 406 break; 407 DELAY(10); 408 } while (--count); 409 if (!(gctl & HDAC_GCTL_CRST)) { 410 device_printf(sc->dev, "Device stuck in reset\n"); 411 return (ENXIO); 412 } 413 414 /* 415 * Wait for codecs to finish their own reset sequence. The delay here 416 * should be of 250us but for some reasons, on it's not enough on my 417 * computer. Let's use twice as much as necessary to make sure that 418 * it's reset properly. 419 */ 420 DELAY(1000); 421 422 return (0); 423 } 424 425 426 /**************************************************************************** 427 * int hdac_get_capabilities(struct hdac_softc *); 428 * 429 * Retreive the general capabilities of the hdac; 430 * Number of Input Streams 431 * Number of Output Streams 432 * Number of bidirectional Streams 433 * 64bit ready 434 * CORB and RIRB sizes 435 ****************************************************************************/ 436 static int 437 hdac_get_capabilities(struct hdac_softc *sc) 438 { 439 uint16_t gcap; 440 uint8_t corbsize, rirbsize; 441 442 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 443 sc->num_iss = HDAC_GCAP_ISS(gcap); 444 sc->num_oss = HDAC_GCAP_OSS(gcap); 445 sc->num_bss = HDAC_GCAP_BSS(gcap); 446 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 447 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 448 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 449 if (sc->quirks_on & HDAC_QUIRK_64BIT) 450 sc->support_64bit = 1; 451 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 452 sc->support_64bit = 0; 453 454 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 455 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 456 HDAC_CORBSIZE_CORBSZCAP_256) 457 sc->corb_size = 256; 458 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 459 HDAC_CORBSIZE_CORBSZCAP_16) 460 sc->corb_size = 16; 461 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 462 HDAC_CORBSIZE_CORBSZCAP_2) 463 sc->corb_size = 2; 464 else { 465 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 466 __func__, corbsize); 467 return (ENXIO); 468 } 469 470 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 471 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 472 HDAC_RIRBSIZE_RIRBSZCAP_256) 473 sc->rirb_size = 256; 474 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 475 HDAC_RIRBSIZE_RIRBSZCAP_16) 476 sc->rirb_size = 16; 477 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 478 HDAC_RIRBSIZE_RIRBSZCAP_2) 479 sc->rirb_size = 2; 480 else { 481 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 482 __func__, rirbsize); 483 return (ENXIO); 484 } 485 486 HDA_BOOTVERBOSE( 487 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 488 "NSDO %d%s, CORB %d, RIRB %d\n", 489 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 490 sc->support_64bit ? ", 64bit" : "", 491 sc->corb_size, sc->rirb_size); 492 ); 493 494 return (0); 495 } 496 497 498 /**************************************************************************** 499 * void hdac_dma_cb 500 * 501 * This function is called by bus_dmamap_load when the mapping has been 502 * established. We just record the physical address of the mapping into 503 * the struct hdac_dma passed in. 504 ****************************************************************************/ 505 static void 506 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 507 { 508 struct hdac_dma *dma; 509 510 if (error == 0) { 511 dma = (struct hdac_dma *)callback_arg; 512 dma->dma_paddr = segs[0].ds_addr; 513 } 514 } 515 516 517 /**************************************************************************** 518 * int hdac_dma_alloc 519 * 520 * This function allocate and setup a dma region (struct hdac_dma). 521 * It must be freed by a corresponding hdac_dma_free. 522 ****************************************************************************/ 523 static int 524 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 525 { 526 bus_size_t roundsz; 527 int result; 528 529 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 530 bzero(dma, sizeof(*dma)); 531 532 /* 533 * Create a DMA tag 534 */ 535 result = bus_dma_tag_create( 536 bus_get_dma_tag(sc->dev), /* parent */ 537 HDA_DMA_ALIGNMENT, /* alignment */ 538 0, /* boundary */ 539 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 540 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 541 BUS_SPACE_MAXADDR, /* highaddr */ 542 NULL, /* filtfunc */ 543 NULL, /* fistfuncarg */ 544 roundsz, /* maxsize */ 545 1, /* nsegments */ 546 roundsz, /* maxsegsz */ 547 0, /* flags */ 548 NULL, /* lockfunc */ 549 NULL, /* lockfuncarg */ 550 &dma->dma_tag); /* dmat */ 551 if (result != 0) { 552 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 553 __func__, result); 554 goto hdac_dma_alloc_fail; 555 } 556 557 /* 558 * Allocate DMA memory 559 */ 560 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 561 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 562 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 563 &dma->dma_map); 564 if (result != 0) { 565 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 566 __func__, result); 567 goto hdac_dma_alloc_fail; 568 } 569 570 dma->dma_size = roundsz; 571 572 /* 573 * Map the memory 574 */ 575 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 576 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 577 if (result != 0 || dma->dma_paddr == 0) { 578 if (result == 0) 579 result = ENOMEM; 580 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 581 __func__, result); 582 goto hdac_dma_alloc_fail; 583 } 584 585 HDA_BOOTHVERBOSE( 586 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 587 __func__, (uintmax_t)size, (uintmax_t)roundsz); 588 ); 589 590 return (0); 591 592 hdac_dma_alloc_fail: 593 hdac_dma_free(sc, dma); 594 595 return (result); 596 } 597 598 599 /**************************************************************************** 600 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 601 * 602 * Free a struct dhac_dma that has been previously allocated via the 603 * hdac_dma_alloc function. 604 ****************************************************************************/ 605 static void 606 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 607 { 608 if (dma->dma_map != NULL) { 609 #if 0 610 /* Flush caches */ 611 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 612 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 613 #endif 614 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 615 } 616 if (dma->dma_vaddr != NULL) { 617 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 618 dma->dma_vaddr = NULL; 619 } 620 dma->dma_map = NULL; 621 if (dma->dma_tag != NULL) { 622 bus_dma_tag_destroy(dma->dma_tag); 623 dma->dma_tag = NULL; 624 } 625 dma->dma_size = 0; 626 } 627 628 /**************************************************************************** 629 * int hdac_mem_alloc(struct hdac_softc *) 630 * 631 * Allocate all the bus resources necessary to speak with the physical 632 * controller. 633 ****************************************************************************/ 634 static int 635 hdac_mem_alloc(struct hdac_softc *sc) 636 { 637 struct hdac_mem *mem; 638 639 mem = &sc->mem; 640 mem->mem_rid = PCIR_BAR(0); 641 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 642 &mem->mem_rid, RF_ACTIVE); 643 if (mem->mem_res == NULL) { 644 device_printf(sc->dev, 645 "%s: Unable to allocate memory resource\n", __func__); 646 return (ENOMEM); 647 } 648 mem->mem_tag = rman_get_bustag(mem->mem_res); 649 mem->mem_handle = rman_get_bushandle(mem->mem_res); 650 651 return (0); 652 } 653 654 /**************************************************************************** 655 * void hdac_mem_free(struct hdac_softc *) 656 * 657 * Free up resources previously allocated by hdac_mem_alloc. 658 ****************************************************************************/ 659 static void 660 hdac_mem_free(struct hdac_softc *sc) 661 { 662 struct hdac_mem *mem; 663 664 mem = &sc->mem; 665 if (mem->mem_res != NULL) 666 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 667 mem->mem_res); 668 mem->mem_res = NULL; 669 } 670 671 /**************************************************************************** 672 * int hdac_irq_alloc(struct hdac_softc *) 673 * 674 * Allocate and setup the resources necessary for interrupt handling. 675 ****************************************************************************/ 676 static int 677 hdac_irq_alloc(struct hdac_softc *sc) 678 { 679 struct hdac_irq *irq; 680 int result; 681 682 irq = &sc->irq; 683 irq->irq_rid = 0x0; 684 685 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 686 (result = pci_msi_count(sc->dev)) == 1 && 687 pci_alloc_msi(sc->dev, &result) == 0) 688 irq->irq_rid = 0x1; 689 690 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 691 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 692 if (irq->irq_res == NULL) { 693 device_printf(sc->dev, "%s: Unable to allocate irq\n", 694 __func__); 695 goto hdac_irq_alloc_fail; 696 } 697 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 698 NULL, hdac_intr_handler, sc, &irq->irq_handle); 699 if (result != 0) { 700 device_printf(sc->dev, 701 "%s: Unable to setup interrupt handler (%x)\n", 702 __func__, result); 703 goto hdac_irq_alloc_fail; 704 } 705 706 return (0); 707 708 hdac_irq_alloc_fail: 709 hdac_irq_free(sc); 710 711 return (ENXIO); 712 } 713 714 /**************************************************************************** 715 * void hdac_irq_free(struct hdac_softc *) 716 * 717 * Free up resources previously allocated by hdac_irq_alloc. 718 ****************************************************************************/ 719 static void 720 hdac_irq_free(struct hdac_softc *sc) 721 { 722 struct hdac_irq *irq; 723 724 irq = &sc->irq; 725 if (irq->irq_res != NULL && irq->irq_handle != NULL) 726 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 727 if (irq->irq_res != NULL) 728 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 729 irq->irq_res); 730 if (irq->irq_rid == 0x1) 731 pci_release_msi(sc->dev); 732 irq->irq_handle = NULL; 733 irq->irq_res = NULL; 734 irq->irq_rid = 0x0; 735 } 736 737 /**************************************************************************** 738 * void hdac_corb_init(struct hdac_softc *) 739 * 740 * Initialize the corb registers for operations but do not start it up yet. 741 * The CORB engine must not be running when this function is called. 742 ****************************************************************************/ 743 static void 744 hdac_corb_init(struct hdac_softc *sc) 745 { 746 uint8_t corbsize; 747 uint64_t corbpaddr; 748 749 /* Setup the CORB size. */ 750 switch (sc->corb_size) { 751 case 256: 752 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 753 break; 754 case 16: 755 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 756 break; 757 case 2: 758 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 759 break; 760 default: 761 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 762 } 763 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 764 765 /* Setup the CORB Address in the hdac */ 766 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 767 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 768 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 769 770 /* Set the WP and RP */ 771 sc->corb_wp = 0; 772 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 773 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 774 /* 775 * The HDA specification indicates that the CORBRPRST bit will always 776 * read as zero. Unfortunately, it seems that at least the 82801G 777 * doesn't reset the bit to zero, which stalls the corb engine. 778 * manually reset the bit to zero before continuing. 779 */ 780 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 781 782 /* Enable CORB error reporting */ 783 #if 0 784 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 785 #endif 786 } 787 788 /**************************************************************************** 789 * void hdac_rirb_init(struct hdac_softc *) 790 * 791 * Initialize the rirb registers for operations but do not start it up yet. 792 * The RIRB engine must not be running when this function is called. 793 ****************************************************************************/ 794 static void 795 hdac_rirb_init(struct hdac_softc *sc) 796 { 797 uint8_t rirbsize; 798 uint64_t rirbpaddr; 799 800 /* Setup the RIRB size. */ 801 switch (sc->rirb_size) { 802 case 256: 803 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 804 break; 805 case 16: 806 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 807 break; 808 case 2: 809 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 810 break; 811 default: 812 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 813 } 814 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 815 816 /* Setup the RIRB Address in the hdac */ 817 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 818 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 819 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 820 821 /* Setup the WP and RP */ 822 sc->rirb_rp = 0; 823 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 824 825 /* Setup the interrupt threshold */ 826 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 827 828 /* Enable Overrun and response received reporting */ 829 #if 0 830 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 831 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 832 #else 833 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 834 #endif 835 836 #if 0 837 /* 838 * Make sure that the Host CPU cache doesn't contain any dirty 839 * cache lines that falls in the rirb. If I understood correctly, it 840 * should be sufficient to do this only once as the rirb is purely 841 * read-only from now on. 842 */ 843 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 844 BUS_DMASYNC_PREREAD); 845 #endif 846 } 847 848 /**************************************************************************** 849 * void hdac_corb_start(hdac_softc *) 850 * 851 * Startup the corb DMA engine 852 ****************************************************************************/ 853 static void 854 hdac_corb_start(struct hdac_softc *sc) 855 { 856 uint32_t corbctl; 857 858 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 859 corbctl |= HDAC_CORBCTL_CORBRUN; 860 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 861 } 862 863 /**************************************************************************** 864 * void hdac_rirb_start(hdac_softc *) 865 * 866 * Startup the rirb DMA engine 867 ****************************************************************************/ 868 static void 869 hdac_rirb_start(struct hdac_softc *sc) 870 { 871 uint32_t rirbctl; 872 873 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 874 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 875 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 876 } 877 878 static int 879 hdac_rirb_flush(struct hdac_softc *sc) 880 { 881 struct hdac_rirb *rirb_base, *rirb; 882 nid_t cad; 883 uint32_t resp; 884 uint8_t rirbwp; 885 int ret; 886 887 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 888 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 889 #if 0 890 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 891 BUS_DMASYNC_POSTREAD); 892 #endif 893 894 ret = 0; 895 while (sc->rirb_rp != rirbwp) { 896 sc->rirb_rp++; 897 sc->rirb_rp %= sc->rirb_size; 898 rirb = &rirb_base[sc->rirb_rp]; 899 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 900 resp = rirb->response; 901 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 902 sc->unsolq[sc->unsolq_wp++] = resp; 903 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 904 sc->unsolq[sc->unsolq_wp++] = cad; 905 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 906 } else if (sc->codecs[cad].pending <= 0) { 907 device_printf(sc->dev, "Unexpected unsolicited " 908 "response from address %d: %08x\n", cad, resp); 909 } else { 910 sc->codecs[cad].response = resp; 911 sc->codecs[cad].pending--; 912 } 913 ret++; 914 } 915 return (ret); 916 } 917 918 static int 919 hdac_unsolq_flush(struct hdac_softc *sc) 920 { 921 device_t child; 922 nid_t cad; 923 uint32_t resp; 924 int ret = 0; 925 926 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 927 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 928 while (sc->unsolq_rp != sc->unsolq_wp) { 929 resp = sc->unsolq[sc->unsolq_rp++]; 930 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 931 cad = sc->unsolq[sc->unsolq_rp++]; 932 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 933 if ((child = sc->codecs[cad].dev) != NULL) 934 HDAC_UNSOL_INTR(child, resp); 935 ret++; 936 } 937 sc->unsolq_st = HDAC_UNSOLQ_READY; 938 } 939 940 return (ret); 941 } 942 943 /**************************************************************************** 944 * uint32_t hdac_command_sendone_internal 945 * 946 * Wrapper function that sends only one command to a given codec 947 ****************************************************************************/ 948 static uint32_t 949 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 950 { 951 int timeout; 952 uint32_t *corb; 953 954 if (!hdac_lockowned(sc)) 955 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 956 verb &= ~HDA_CMD_CAD_MASK; 957 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 958 sc->codecs[cad].response = HDA_INVALID; 959 960 sc->codecs[cad].pending++; 961 sc->corb_wp++; 962 sc->corb_wp %= sc->corb_size; 963 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 964 #if 0 965 bus_dmamap_sync(sc->corb_dma.dma_tag, 966 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 967 #endif 968 corb[sc->corb_wp] = verb; 969 #if 0 970 bus_dmamap_sync(sc->corb_dma.dma_tag, 971 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 972 #endif 973 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 974 975 timeout = 10000; 976 do { 977 if (hdac_rirb_flush(sc) == 0) 978 DELAY(10); 979 } while (sc->codecs[cad].pending != 0 && --timeout); 980 981 if (sc->codecs[cad].pending != 0) { 982 device_printf(sc->dev, "Command timeout on address %d\n", cad); 983 sc->codecs[cad].pending = 0; 984 } 985 986 if (sc->unsolq_rp != sc->unsolq_wp) 987 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 988 return (sc->codecs[cad].response); 989 } 990 991 /**************************************************************************** 992 * Device Methods 993 ****************************************************************************/ 994 995 /**************************************************************************** 996 * int hdac_probe(device_t) 997 * 998 * Probe for the presence of an hdac. If none is found, check for a generic 999 * match using the subclass of the device. 1000 ****************************************************************************/ 1001 static int 1002 hdac_probe(device_t dev) 1003 { 1004 int i, result; 1005 uint32_t model; 1006 uint16_t class, subclass; 1007 char desc[64]; 1008 1009 model = (uint32_t)pci_get_device(dev) << 16; 1010 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1011 class = pci_get_class(dev); 1012 subclass = pci_get_subclass(dev); 1013 1014 bzero(desc, sizeof(desc)); 1015 result = ENXIO; 1016 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 1017 if (hdac_devices[i].model == model) { 1018 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1019 result = BUS_PROBE_DEFAULT; 1020 break; 1021 } 1022 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1023 class == PCIC_MULTIMEDIA && 1024 subclass == PCIS_MULTIMEDIA_HDA) { 1025 snprintf(desc, sizeof(desc), 1026 "%s (0x%04x)", 1027 hdac_devices[i].desc, pci_get_device(dev)); 1028 result = BUS_PROBE_GENERIC; 1029 break; 1030 } 1031 } 1032 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1033 subclass == PCIS_MULTIMEDIA_HDA) { 1034 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1035 result = BUS_PROBE_GENERIC; 1036 } 1037 if (result != ENXIO) { 1038 strlcat(desc, " HDA Controller", sizeof(desc)); 1039 device_set_desc_copy(dev, desc); 1040 } 1041 1042 return (result); 1043 } 1044 1045 static void 1046 hdac_unsolq_task(void *context, int pending) 1047 { 1048 struct hdac_softc *sc; 1049 1050 sc = (struct hdac_softc *)context; 1051 1052 hdac_lock(sc); 1053 hdac_unsolq_flush(sc); 1054 hdac_unlock(sc); 1055 } 1056 1057 /**************************************************************************** 1058 * int hdac_attach(device_t) 1059 * 1060 * Attach the device into the kernel. Interrupts usually won't be enabled 1061 * when this function is called. Setup everything that doesn't require 1062 * interrupts and defer probing of codecs until interrupts are enabled. 1063 ****************************************************************************/ 1064 static int 1065 hdac_attach(device_t dev) 1066 { 1067 struct hdac_softc *sc; 1068 int result; 1069 int i, devid = -1; 1070 uint32_t model; 1071 uint16_t class, subclass; 1072 uint16_t vendor; 1073 uint8_t v; 1074 1075 sc = device_get_softc(dev); 1076 HDA_BOOTVERBOSE( 1077 device_printf(dev, "HDA Driver Revision: %s\n", 1078 HDA_DRV_TEST_REV); 1079 ); 1080 1081 model = (uint32_t)pci_get_device(dev) << 16; 1082 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1083 class = pci_get_class(dev); 1084 subclass = pci_get_subclass(dev); 1085 1086 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 1087 if (hdac_devices[i].model == model) { 1088 devid = i; 1089 break; 1090 } 1091 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1092 class == PCIC_MULTIMEDIA && 1093 subclass == PCIS_MULTIMEDIA_HDA) { 1094 devid = i; 1095 break; 1096 } 1097 } 1098 1099 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1100 sc->dev = dev; 1101 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1102 callout_init(&sc->poll_callout, CALLOUT_MPSAFE); 1103 for (i = 0; i < HDAC_CODEC_MAX; i++) 1104 sc->codecs[i].dev = NULL; 1105 if (devid >= 0) { 1106 sc->quirks_on = hdac_devices[devid].quirks_on; 1107 sc->quirks_off = hdac_devices[devid].quirks_off; 1108 } else { 1109 sc->quirks_on = 0; 1110 sc->quirks_off = 0; 1111 } 1112 if (resource_int_value(device_get_name(dev), 1113 device_get_unit(dev), "msi", &i) == 0) { 1114 if (i == 0) 1115 sc->quirks_off |= HDAC_QUIRK_MSI; 1116 else { 1117 sc->quirks_on |= HDAC_QUIRK_MSI; 1118 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1119 } 1120 } 1121 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1122 HDA_BOOTVERBOSE( 1123 device_printf(sc->dev, 1124 "Config options: on=0x%08x off=0x%08x\n", 1125 sc->quirks_on, sc->quirks_off); 1126 ); 1127 sc->poll_ival = hz; 1128 if (resource_int_value(device_get_name(dev), 1129 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1130 sc->polling = 1; 1131 else 1132 sc->polling = 0; 1133 1134 pci_enable_busmaster(dev); 1135 1136 vendor = pci_get_vendor(dev); 1137 if (vendor == INTEL_VENDORID) { 1138 /* TCSEL -> TC0 */ 1139 v = pci_read_config(dev, 0x44, 1); 1140 pci_write_config(dev, 0x44, v & 0xf8, 1); 1141 HDA_BOOTHVERBOSE( 1142 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1143 pci_read_config(dev, 0x44, 1)); 1144 ); 1145 } 1146 1147 #if defined(__i386__) || defined(__amd64__) 1148 sc->flags |= HDAC_F_DMA_NOCACHE; 1149 1150 if (resource_int_value(device_get_name(dev), 1151 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 1152 #else 1153 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1154 #endif 1155 /* 1156 * Try to enable PCIe snoop to avoid messing around with 1157 * uncacheable DMA attribute. Since PCIe snoop register 1158 * config is pretty much vendor specific, there are no 1159 * general solutions on how to enable it, forcing us (even 1160 * Microsoft) to enable uncacheable or write combined DMA 1161 * by default. 1162 * 1163 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 1164 */ 1165 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 1166 if (hdac_pcie_snoop[i].vendor != vendor) 1167 continue; 1168 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1169 if (hdac_pcie_snoop[i].reg == 0x00) 1170 break; 1171 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1172 if ((v & hdac_pcie_snoop[i].enable) == 1173 hdac_pcie_snoop[i].enable) 1174 break; 1175 v &= hdac_pcie_snoop[i].mask; 1176 v |= hdac_pcie_snoop[i].enable; 1177 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 1178 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1179 if ((v & hdac_pcie_snoop[i].enable) != 1180 hdac_pcie_snoop[i].enable) { 1181 HDA_BOOTVERBOSE( 1182 device_printf(dev, 1183 "WARNING: Failed to enable PCIe " 1184 "snoop!\n"); 1185 ); 1186 #if defined(__i386__) || defined(__amd64__) 1187 sc->flags |= HDAC_F_DMA_NOCACHE; 1188 #endif 1189 } 1190 break; 1191 } 1192 #if defined(__i386__) || defined(__amd64__) 1193 } 1194 #endif 1195 1196 HDA_BOOTHVERBOSE( 1197 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1198 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1199 "Uncacheable" : "PCIe snoop", vendor); 1200 ); 1201 1202 /* Allocate resources */ 1203 result = hdac_mem_alloc(sc); 1204 if (result != 0) 1205 goto hdac_attach_fail; 1206 result = hdac_irq_alloc(sc); 1207 if (result != 0) 1208 goto hdac_attach_fail; 1209 1210 /* Get Capabilities */ 1211 result = hdac_get_capabilities(sc); 1212 if (result != 0) 1213 goto hdac_attach_fail; 1214 1215 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1216 result = hdac_dma_alloc(sc, &sc->corb_dma, 1217 sc->corb_size * sizeof(uint32_t)); 1218 if (result != 0) 1219 goto hdac_attach_fail; 1220 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1221 sc->rirb_size * sizeof(struct hdac_rirb)); 1222 if (result != 0) 1223 goto hdac_attach_fail; 1224 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, 1225 M_HDAC, M_ZERO | M_WAITOK); 1226 for (i = 0; i < sc->num_ss; i++) { 1227 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1228 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1229 if (result != 0) 1230 goto hdac_attach_fail; 1231 } 1232 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1233 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1234 HDA_BOOTVERBOSE( 1235 device_printf(dev, "Failed to " 1236 "allocate DMA pos buffer " 1237 "(non-fatal)\n"); 1238 ); 1239 } else { 1240 uint64_t addr = sc->pos_dma.dma_paddr; 1241 1242 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1243 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1244 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1245 HDAC_DPLBASE_DPLBASE_DMAPBE); 1246 } 1247 } 1248 1249 result = bus_dma_tag_create( 1250 bus_get_dma_tag(sc->dev), /* parent */ 1251 HDA_DMA_ALIGNMENT, /* alignment */ 1252 0, /* boundary */ 1253 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1254 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1255 BUS_SPACE_MAXADDR, /* highaddr */ 1256 NULL, /* filtfunc */ 1257 NULL, /* fistfuncarg */ 1258 HDA_BUFSZ_MAX, /* maxsize */ 1259 1, /* nsegments */ 1260 HDA_BUFSZ_MAX, /* maxsegsz */ 1261 0, /* flags */ 1262 NULL, /* lockfunc */ 1263 NULL, /* lockfuncarg */ 1264 &sc->chan_dmat); /* dmat */ 1265 if (result != 0) { 1266 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 1267 __func__, result); 1268 goto hdac_attach_fail; 1269 } 1270 1271 /* Quiesce everything */ 1272 HDA_BOOTHVERBOSE( 1273 device_printf(dev, "Reset controller...\n"); 1274 ); 1275 hdac_reset(sc, 1); 1276 1277 /* Initialize the CORB and RIRB */ 1278 hdac_corb_init(sc); 1279 hdac_rirb_init(sc); 1280 1281 /* Defer remaining of initialization until interrupts are enabled */ 1282 sc->intrhook.ich_func = hdac_attach2; 1283 sc->intrhook.ich_arg = (void *)sc; 1284 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1285 sc->intrhook.ich_func = NULL; 1286 hdac_attach2((void *)sc); 1287 } 1288 1289 return (0); 1290 1291 hdac_attach_fail: 1292 hdac_irq_free(sc); 1293 for (i = 0; i < sc->num_ss; i++) 1294 hdac_dma_free(sc, &sc->streams[i].bdl); 1295 free(sc->streams, M_HDAC); 1296 hdac_dma_free(sc, &sc->rirb_dma); 1297 hdac_dma_free(sc, &sc->corb_dma); 1298 hdac_mem_free(sc); 1299 snd_mtxfree(sc->lock); 1300 1301 return (ENXIO); 1302 } 1303 1304 static int 1305 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1306 { 1307 struct hdac_softc *sc; 1308 device_t *devlist; 1309 device_t dev; 1310 int devcount, i, err, val; 1311 1312 dev = oidp->oid_arg1; 1313 sc = device_get_softc(dev); 1314 if (sc == NULL) 1315 return (EINVAL); 1316 val = 0; 1317 err = sysctl_handle_int(oidp, &val, 0, req); 1318 if (err != 0 || req->newptr == NULL || val == 0) 1319 return (err); 1320 1321 /* XXX: Temporary. For debugging. */ 1322 if (val == 100) { 1323 hdac_suspend(dev); 1324 return (0); 1325 } else if (val == 101) { 1326 hdac_resume(dev); 1327 return (0); 1328 } 1329 1330 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1331 return (err); 1332 hdac_lock(sc); 1333 for (i = 0; i < devcount; i++) 1334 HDAC_PINDUMP(devlist[i]); 1335 hdac_unlock(sc); 1336 free(devlist, M_TEMP); 1337 return (0); 1338 } 1339 1340 static int 1341 hdac_mdata_rate(uint16_t fmt) 1342 { 1343 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1344 int rate, bits; 1345 1346 if (fmt & (1 << 14)) 1347 rate = 44100; 1348 else 1349 rate = 48000; 1350 rate *= ((fmt >> 11) & 0x07) + 1; 1351 rate /= ((fmt >> 8) & 0x07) + 1; 1352 bits = mbits[(fmt >> 4) & 0x03]; 1353 bits *= (fmt & 0x0f) + 1; 1354 return (rate * bits); 1355 } 1356 1357 static int 1358 hdac_bdata_rate(uint16_t fmt, int output) 1359 { 1360 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1361 int rate, bits; 1362 1363 rate = 48000; 1364 rate *= ((fmt >> 11) & 0x07) + 1; 1365 bits = bbits[(fmt >> 4) & 0x03]; 1366 bits *= (fmt & 0x0f) + 1; 1367 if (!output) 1368 bits = ((bits + 7) & ~0x07) + 10; 1369 return (rate * bits); 1370 } 1371 1372 static void 1373 hdac_poll_reinit(struct hdac_softc *sc) 1374 { 1375 int i, pollticks, min = 1000000; 1376 struct hdac_stream *s; 1377 1378 if (sc->polling == 0) 1379 return; 1380 if (sc->unsol_registered > 0) 1381 min = hz / 2; 1382 for (i = 0; i < sc->num_ss; i++) { 1383 s = &sc->streams[i]; 1384 if (s->running == 0) 1385 continue; 1386 pollticks = ((uint64_t)hz * s->blksz) / 1387 (hdac_mdata_rate(s->format) / 8); 1388 pollticks >>= 1; 1389 if (pollticks > hz) 1390 pollticks = hz; 1391 if (pollticks < 1) { 1392 HDA_BOOTVERBOSE( 1393 device_printf(sc->dev, 1394 "poll interval < 1 tick !\n"); 1395 ); 1396 pollticks = 1; 1397 } 1398 if (min > pollticks) 1399 min = pollticks; 1400 } 1401 HDA_BOOTVERBOSE( 1402 device_printf(sc->dev, 1403 "poll interval %d -> %d ticks\n", 1404 sc->poll_ival, min); 1405 ); 1406 sc->poll_ival = min; 1407 if (min == 1000000) 1408 callout_stop(&sc->poll_callout); 1409 else 1410 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1411 } 1412 1413 static int 1414 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1415 { 1416 struct hdac_softc *sc; 1417 device_t dev; 1418 uint32_t ctl; 1419 int err, val; 1420 1421 dev = oidp->oid_arg1; 1422 sc = device_get_softc(dev); 1423 if (sc == NULL) 1424 return (EINVAL); 1425 hdac_lock(sc); 1426 val = sc->polling; 1427 hdac_unlock(sc); 1428 err = sysctl_handle_int(oidp, &val, 0, req); 1429 1430 if (err != 0 || req->newptr == NULL) 1431 return (err); 1432 if (val < 0 || val > 1) 1433 return (EINVAL); 1434 1435 hdac_lock(sc); 1436 if (val != sc->polling) { 1437 if (val == 0) { 1438 callout_stop(&sc->poll_callout); 1439 hdac_unlock(sc); 1440 callout_drain(&sc->poll_callout); 1441 hdac_lock(sc); 1442 sc->polling = 0; 1443 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1444 ctl |= HDAC_INTCTL_GIE; 1445 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1446 } else { 1447 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1448 ctl &= ~HDAC_INTCTL_GIE; 1449 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1450 sc->polling = 1; 1451 hdac_poll_reinit(sc); 1452 } 1453 } 1454 hdac_unlock(sc); 1455 1456 return (err); 1457 } 1458 1459 static void 1460 hdac_attach2(void *arg) 1461 { 1462 struct hdac_softc *sc; 1463 device_t child; 1464 uint32_t vendorid, revisionid; 1465 int i; 1466 uint16_t statests; 1467 1468 sc = (struct hdac_softc *)arg; 1469 1470 hdac_lock(sc); 1471 1472 /* Remove ourselves from the config hooks */ 1473 if (sc->intrhook.ich_func != NULL) { 1474 config_intrhook_disestablish(&sc->intrhook); 1475 sc->intrhook.ich_func = NULL; 1476 } 1477 1478 HDA_BOOTHVERBOSE( 1479 device_printf(sc->dev, "Starting CORB Engine...\n"); 1480 ); 1481 hdac_corb_start(sc); 1482 HDA_BOOTHVERBOSE( 1483 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1484 ); 1485 hdac_rirb_start(sc); 1486 HDA_BOOTHVERBOSE( 1487 device_printf(sc->dev, 1488 "Enabling controller interrupt...\n"); 1489 ); 1490 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1491 HDAC_GCTL_UNSOL); 1492 if (sc->polling == 0) { 1493 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1494 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1495 } 1496 DELAY(1000); 1497 1498 HDA_BOOTHVERBOSE( 1499 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1500 ); 1501 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1502 hdac_unlock(sc); 1503 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1504 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1505 HDA_BOOTHVERBOSE( 1506 device_printf(sc->dev, 1507 "Found CODEC at address %d\n", i); 1508 ); 1509 hdac_lock(sc); 1510 vendorid = hdac_send_command(sc, i, 1511 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1512 revisionid = hdac_send_command(sc, i, 1513 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1514 hdac_unlock(sc); 1515 if (vendorid == HDA_INVALID && 1516 revisionid == HDA_INVALID) { 1517 device_printf(sc->dev, 1518 "CODEC is not responding!\n"); 1519 continue; 1520 } 1521 sc->codecs[i].vendor_id = 1522 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1523 sc->codecs[i].device_id = 1524 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1525 sc->codecs[i].revision_id = 1526 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1527 sc->codecs[i].stepping_id = 1528 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1529 child = device_add_child(sc->dev, "hdacc", -1); 1530 if (child == NULL) { 1531 device_printf(sc->dev, 1532 "Failed to add CODEC device\n"); 1533 continue; 1534 } 1535 device_set_ivars(child, (void *)(intptr_t)i); 1536 sc->codecs[i].dev = child; 1537 } 1538 } 1539 bus_generic_attach(sc->dev); 1540 1541 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1542 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1543 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1544 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1545 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1546 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1547 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1548 sysctl_hdac_polling, "I", "Enable polling mode"); 1549 } 1550 1551 /**************************************************************************** 1552 * int hdac_suspend(device_t) 1553 * 1554 * Suspend and power down HDA bus and codecs. 1555 ****************************************************************************/ 1556 static int 1557 hdac_suspend(device_t dev) 1558 { 1559 struct hdac_softc *sc = device_get_softc(dev); 1560 1561 HDA_BOOTHVERBOSE( 1562 device_printf(dev, "Suspend...\n"); 1563 ); 1564 bus_generic_suspend(dev); 1565 1566 hdac_lock(sc); 1567 HDA_BOOTHVERBOSE( 1568 device_printf(dev, "Reset controller...\n"); 1569 ); 1570 callout_stop(&sc->poll_callout); 1571 hdac_reset(sc, 0); 1572 hdac_unlock(sc); 1573 callout_drain(&sc->poll_callout); 1574 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1575 HDA_BOOTHVERBOSE( 1576 device_printf(dev, "Suspend done\n"); 1577 ); 1578 return (0); 1579 } 1580 1581 /**************************************************************************** 1582 * int hdac_resume(device_t) 1583 * 1584 * Powerup and restore HDA bus and codecs state. 1585 ****************************************************************************/ 1586 static int 1587 hdac_resume(device_t dev) 1588 { 1589 struct hdac_softc *sc = device_get_softc(dev); 1590 int error; 1591 1592 HDA_BOOTHVERBOSE( 1593 device_printf(dev, "Resume...\n"); 1594 ); 1595 hdac_lock(sc); 1596 1597 /* Quiesce everything */ 1598 HDA_BOOTHVERBOSE( 1599 device_printf(dev, "Reset controller...\n"); 1600 ); 1601 hdac_reset(sc, 1); 1602 1603 /* Initialize the CORB and RIRB */ 1604 hdac_corb_init(sc); 1605 hdac_rirb_init(sc); 1606 1607 HDA_BOOTHVERBOSE( 1608 device_printf(dev, "Starting CORB Engine...\n"); 1609 ); 1610 hdac_corb_start(sc); 1611 HDA_BOOTHVERBOSE( 1612 device_printf(dev, "Starting RIRB Engine...\n"); 1613 ); 1614 hdac_rirb_start(sc); 1615 HDA_BOOTHVERBOSE( 1616 device_printf(dev, "Enabling controller interrupt...\n"); 1617 ); 1618 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1619 HDAC_GCTL_UNSOL); 1620 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1621 DELAY(1000); 1622 hdac_poll_reinit(sc); 1623 hdac_unlock(sc); 1624 1625 error = bus_generic_resume(dev); 1626 HDA_BOOTHVERBOSE( 1627 device_printf(dev, "Resume done\n"); 1628 ); 1629 return (error); 1630 } 1631 1632 /**************************************************************************** 1633 * int hdac_detach(device_t) 1634 * 1635 * Detach and free up resources utilized by the hdac device. 1636 ****************************************************************************/ 1637 static int 1638 hdac_detach(device_t dev) 1639 { 1640 struct hdac_softc *sc = device_get_softc(dev); 1641 device_t *devlist; 1642 int cad, i, devcount, error; 1643 1644 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1645 return (error); 1646 for (i = 0; i < devcount; i++) { 1647 cad = (intptr_t)device_get_ivars(devlist[i]); 1648 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1649 free(devlist, M_TEMP); 1650 return (error); 1651 } 1652 sc->codecs[cad].dev = NULL; 1653 } 1654 free(devlist, M_TEMP); 1655 1656 hdac_lock(sc); 1657 hdac_reset(sc, 0); 1658 hdac_unlock(sc); 1659 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1660 hdac_irq_free(sc); 1661 1662 for (i = 0; i < sc->num_ss; i++) 1663 hdac_dma_free(sc, &sc->streams[i].bdl); 1664 free(sc->streams, M_HDAC); 1665 hdac_dma_free(sc, &sc->pos_dma); 1666 hdac_dma_free(sc, &sc->rirb_dma); 1667 hdac_dma_free(sc, &sc->corb_dma); 1668 if (sc->chan_dmat != NULL) { 1669 bus_dma_tag_destroy(sc->chan_dmat); 1670 sc->chan_dmat = NULL; 1671 } 1672 hdac_mem_free(sc); 1673 snd_mtxfree(sc->lock); 1674 return (0); 1675 } 1676 1677 static bus_dma_tag_t 1678 hdac_get_dma_tag(device_t dev, device_t child) 1679 { 1680 struct hdac_softc *sc = device_get_softc(dev); 1681 1682 return (sc->chan_dmat); 1683 } 1684 1685 static int 1686 hdac_print_child(device_t dev, device_t child) 1687 { 1688 int retval; 1689 1690 retval = bus_print_child_header(dev, child); 1691 retval += printf(" at cad %d", 1692 (int)(intptr_t)device_get_ivars(child)); 1693 retval += bus_print_child_footer(dev, child); 1694 1695 return (retval); 1696 } 1697 1698 static int 1699 hdac_child_location_str(device_t dev, device_t child, char *buf, 1700 size_t buflen) 1701 { 1702 1703 snprintf(buf, buflen, "cad=%d", 1704 (int)(intptr_t)device_get_ivars(child)); 1705 return (0); 1706 } 1707 1708 static int 1709 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1710 size_t buflen) 1711 { 1712 struct hdac_softc *sc = device_get_softc(dev); 1713 nid_t cad = (uintptr_t)device_get_ivars(child); 1714 1715 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1716 "stepping=0x%02x", 1717 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1718 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1719 return (0); 1720 } 1721 1722 static int 1723 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1724 { 1725 struct hdac_softc *sc = device_get_softc(dev); 1726 nid_t cad = (uintptr_t)device_get_ivars(child); 1727 1728 switch (which) { 1729 case HDA_IVAR_CODEC_ID: 1730 *result = cad; 1731 break; 1732 case HDA_IVAR_VENDOR_ID: 1733 *result = sc->codecs[cad].vendor_id; 1734 break; 1735 case HDA_IVAR_DEVICE_ID: 1736 *result = sc->codecs[cad].device_id; 1737 break; 1738 case HDA_IVAR_REVISION_ID: 1739 *result = sc->codecs[cad].revision_id; 1740 break; 1741 case HDA_IVAR_STEPPING_ID: 1742 *result = sc->codecs[cad].stepping_id; 1743 break; 1744 case HDA_IVAR_SUBVENDOR_ID: 1745 *result = pci_get_subvendor(dev); 1746 break; 1747 case HDA_IVAR_SUBDEVICE_ID: 1748 *result = pci_get_subdevice(dev); 1749 break; 1750 case HDA_IVAR_DMA_NOCACHE: 1751 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1752 break; 1753 default: 1754 return (ENOENT); 1755 } 1756 return (0); 1757 } 1758 1759 static struct mtx * 1760 hdac_get_mtx(device_t dev, device_t child) 1761 { 1762 struct hdac_softc *sc = device_get_softc(dev); 1763 1764 return (sc->lock); 1765 } 1766 1767 static uint32_t 1768 hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1769 { 1770 1771 return (hdac_send_command(device_get_softc(dev), 1772 (intptr_t)device_get_ivars(child), verb)); 1773 } 1774 1775 static int 1776 hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1777 { 1778 int i, ss; 1779 1780 ss = -1; 1781 /* Allocate ISS/BSS first. */ 1782 if (dir == 0) { 1783 for (i = 0; i < sc->num_iss; i++) { 1784 if (sc->streams[i].stream == stream) { 1785 ss = i; 1786 break; 1787 } 1788 } 1789 } else { 1790 for (i = 0; i < sc->num_oss; i++) { 1791 if (sc->streams[i + sc->num_iss].stream == stream) { 1792 ss = i + sc->num_iss; 1793 break; 1794 } 1795 } 1796 } 1797 /* Fallback to BSS. */ 1798 if (ss == -1) { 1799 for (i = 0; i < sc->num_bss; i++) { 1800 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1801 == stream) { 1802 ss = i + sc->num_iss + sc->num_oss; 1803 break; 1804 } 1805 } 1806 } 1807 return (ss); 1808 } 1809 1810 static int 1811 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1812 uint32_t **dmapos) 1813 { 1814 struct hdac_softc *sc = device_get_softc(dev); 1815 nid_t cad = (uintptr_t)device_get_ivars(child); 1816 int stream, ss, bw, maxbw, prevbw; 1817 1818 /* Look for empty stream. */ 1819 ss = hdac_find_stream(sc, dir, 0); 1820 1821 /* Return if found nothing. */ 1822 if (ss < 0) 1823 return (0); 1824 1825 /* Check bus bandwidth. */ 1826 bw = hdac_bdata_rate(format, dir); 1827 if (dir == 1) { 1828 bw *= 1 << (sc->num_sdo - stripe); 1829 prevbw = sc->sdo_bw_used; 1830 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1831 } else { 1832 prevbw = sc->codecs[cad].sdi_bw_used; 1833 maxbw = 48000 * 464; 1834 } 1835 HDA_BOOTHVERBOSE( 1836 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1837 (bw + prevbw) / 1000, maxbw / 1000, 1838 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1839 ); 1840 if (bw + prevbw > maxbw) 1841 return (0); 1842 if (dir == 1) 1843 sc->sdo_bw_used += bw; 1844 else 1845 sc->codecs[cad].sdi_bw_used += bw; 1846 1847 /* Allocate stream number */ 1848 if (ss >= sc->num_iss + sc->num_oss) 1849 stream = 15 - (ss - sc->num_iss + sc->num_oss); 1850 else if (ss >= sc->num_iss) 1851 stream = ss - sc->num_iss + 1; 1852 else 1853 stream = ss + 1; 1854 1855 sc->streams[ss].dev = child; 1856 sc->streams[ss].dir = dir; 1857 sc->streams[ss].stream = stream; 1858 sc->streams[ss].bw = bw; 1859 sc->streams[ss].format = format; 1860 sc->streams[ss].stripe = stripe; 1861 if (dmapos != NULL) { 1862 if (sc->pos_dma.dma_vaddr != NULL) 1863 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1864 else 1865 *dmapos = NULL; 1866 } 1867 return (stream); 1868 } 1869 1870 static void 1871 hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1872 { 1873 struct hdac_softc *sc = device_get_softc(dev); 1874 nid_t cad = (uintptr_t)device_get_ivars(child); 1875 int ss; 1876 1877 ss = hdac_find_stream(sc, dir, stream); 1878 KASSERT(ss >= 0, 1879 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1880 if (dir == 1) 1881 sc->sdo_bw_used -= sc->streams[ss].bw; 1882 else 1883 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1884 sc->streams[ss].stream = 0; 1885 sc->streams[ss].dev = NULL; 1886 } 1887 1888 static int 1889 hdac_stream_start(device_t dev, device_t child, 1890 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1891 { 1892 struct hdac_softc *sc = device_get_softc(dev); 1893 struct hdac_bdle *bdle; 1894 uint64_t addr; 1895 int i, ss, off; 1896 uint32_t ctl; 1897 1898 ss = hdac_find_stream(sc, dir, stream); 1899 KASSERT(ss >= 0, 1900 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1901 1902 addr = (uint64_t)buf; 1903 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1904 for (i = 0; i < blkcnt; i++, bdle++) { 1905 bdle->addrl = (uint32_t)addr; 1906 bdle->addrh = (uint32_t)(addr >> 32); 1907 bdle->len = blksz; 1908 bdle->ioc = 1; 1909 addr += blksz; 1910 } 1911 1912 off = ss << 5; 1913 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1914 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1915 addr = sc->streams[ss].bdl.dma_paddr; 1916 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1917 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1918 1919 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1920 if (dir) 1921 ctl |= HDAC_SDCTL2_DIR; 1922 else 1923 ctl &= ~HDAC_SDCTL2_DIR; 1924 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1925 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1926 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1927 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1928 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1929 1930 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1931 1932 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1933 ctl |= 1 << ss; 1934 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1935 1936 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 1937 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 1938 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1939 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1940 HDAC_SDCTL_RUN; 1941 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1942 1943 sc->streams[ss].blksz = blksz; 1944 sc->streams[ss].running = 1; 1945 hdac_poll_reinit(sc); 1946 return (0); 1947 } 1948 1949 static void 1950 hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1951 { 1952 struct hdac_softc *sc = device_get_softc(dev); 1953 int ss, off; 1954 uint32_t ctl; 1955 1956 ss = hdac_find_stream(sc, dir, stream); 1957 KASSERT(ss >= 0, 1958 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1959 1960 off = ss << 5; 1961 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1962 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1963 HDAC_SDCTL_RUN); 1964 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1965 1966 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1967 ctl &= ~(1 << ss); 1968 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1969 1970 sc->streams[ss].running = 0; 1971 hdac_poll_reinit(sc); 1972 } 1973 1974 static void 1975 hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 1976 { 1977 struct hdac_softc *sc = device_get_softc(dev); 1978 int timeout = 1000; 1979 int to = timeout; 1980 int ss, off; 1981 uint32_t ctl; 1982 1983 ss = hdac_find_stream(sc, dir, stream); 1984 KASSERT(ss >= 0, 1985 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 1986 1987 off = ss << 5; 1988 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1989 ctl |= HDAC_SDCTL_SRST; 1990 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1991 do { 1992 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1993 if (ctl & HDAC_SDCTL_SRST) 1994 break; 1995 DELAY(10); 1996 } while (--to); 1997 if (!(ctl & HDAC_SDCTL_SRST)) 1998 device_printf(dev, "Reset setting timeout\n"); 1999 ctl &= ~HDAC_SDCTL_SRST; 2000 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2001 to = timeout; 2002 do { 2003 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2004 if (!(ctl & HDAC_SDCTL_SRST)) 2005 break; 2006 DELAY(10); 2007 } while (--to); 2008 if (ctl & HDAC_SDCTL_SRST) 2009 device_printf(dev, "Reset timeout!\n"); 2010 } 2011 2012 static uint32_t 2013 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2014 { 2015 struct hdac_softc *sc = device_get_softc(dev); 2016 int ss, off; 2017 2018 ss = hdac_find_stream(sc, dir, stream); 2019 KASSERT(ss >= 0, 2020 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2021 2022 off = ss << 5; 2023 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2024 } 2025 2026 static int 2027 hdac_unsol_alloc(device_t dev, device_t child, int tag) 2028 { 2029 struct hdac_softc *sc = device_get_softc(dev); 2030 2031 sc->unsol_registered++; 2032 hdac_poll_reinit(sc); 2033 return (tag); 2034 } 2035 2036 static void 2037 hdac_unsol_free(device_t dev, device_t child, int tag) 2038 { 2039 struct hdac_softc *sc = device_get_softc(dev); 2040 2041 sc->unsol_registered--; 2042 hdac_poll_reinit(sc); 2043 } 2044 2045 static device_method_t hdac_methods[] = { 2046 /* device interface */ 2047 DEVMETHOD(device_probe, hdac_probe), 2048 DEVMETHOD(device_attach, hdac_attach), 2049 DEVMETHOD(device_detach, hdac_detach), 2050 DEVMETHOD(device_suspend, hdac_suspend), 2051 DEVMETHOD(device_resume, hdac_resume), 2052 /* Bus interface */ 2053 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2054 DEVMETHOD(bus_print_child, hdac_print_child), 2055 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2056 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2057 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2058 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2059 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2060 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2061 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2062 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2063 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2064 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2065 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2066 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2067 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2068 { 0, 0 } 2069 }; 2070 2071 static driver_t hdac_driver = { 2072 "hdac", 2073 hdac_methods, 2074 sizeof(struct hdac_softc), 2075 }; 2076 2077 static devclass_t hdac_devclass; 2078 2079 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 2080