1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70 #include <sys/ctype.h> 71 72 #include <dev/sound/pcm/sound.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 76 #include <dev/sound/pci/hda/hdac_private.h> 77 #include <dev/sound/pci/hda/hdac_reg.h> 78 #include <dev/sound/pci/hda/hda_reg.h> 79 #include <dev/sound/pci/hda/hdac.h> 80 81 #include "mixer_if.h" 82 83 /* 84 * XXX PAT superhero, until we have true support for BUS_DMA_NOCACHE. 85 * Blindly assume that pmap_change_attr() exist if PAT_UNCACHEABLE 86 * is defined. If not, fetch it from our cute little-pmap. 87 */ 88 #if defined(__i386__) || defined(__amd64__) 89 #include <machine/specialreg.h> 90 #ifndef PAT_UNCACHEABLE 91 #include <dev/sound/pci/hda/lpmap.c> 92 #endif 93 #endif 94 95 #define HDAC_DMA_UNCACHEABLE 0 96 #define HDAC_DMA_WRITEBACK 1 97 98 #define HDA_DRV_TEST_REV "20070320_0043" 99 #define HDA_WIDGET_PARSER_REV 1 100 101 SND_DECLARE_FILE("$FreeBSD$"); 102 103 #undef HDA_DEBUG_ENABLED 104 #define HDA_DEBUG_ENABLED 1 105 106 #ifdef HDA_DEBUG_ENABLED 107 #define HDA_DEBUG(stmt) do { \ 108 stmt \ 109 } while(0) 110 #else 111 #define HDA_DEBUG(stmt) 112 #endif 113 114 #define HDA_BOOTVERBOSE(stmt) do { \ 115 if (bootverbose) { \ 116 stmt \ 117 } \ 118 } while(0) 119 120 #if 1 121 #undef HDAC_INTR_EXTRA 122 #define HDAC_INTR_EXTRA 1 123 #endif 124 125 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 126 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 127 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 128 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 129 130 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 131 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 132 (fl) == 0xffffffff || \ 133 (((fl) & 0xffff0000) == 0xffff0000 && \ 134 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 135 (((fl) & 0x0000ffff) == 0x0000ffff && \ 136 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 137 #define HDA_MATCH_ALL 0xffffffff 138 #define HDAC_INVALID 0xffffffff 139 140 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 141 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 142 143 /* Controller models */ 144 145 /* Intel */ 146 #define INTEL_VENDORID 0x8086 147 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 148 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 151 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 152 153 /* Nvidia */ 154 #define NVIDIA_VENDORID 0x10de 155 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 156 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 157 #define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 158 #define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 159 #define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 160 #define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 161 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 162 163 /* ATI */ 164 #define ATI_VENDORID 0x1002 165 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 166 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 167 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 168 169 /* VIA */ 170 #define VIA_VENDORID 0x1106 171 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 172 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 173 174 /* SiS */ 175 #define SIS_VENDORID 0x1039 176 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 177 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 178 179 /* OEM/subvendors */ 180 181 /* Intel */ 182 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 183 184 /* HP/Compaq */ 185 #define HP_VENDORID 0x103c 186 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 187 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 188 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 189 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 190 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 191 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 192 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 193 #define HP_NX6325_SUBVENDORX 0x103c30b0 194 195 /* Dell */ 196 #define DELL_VENDORID 0x1028 197 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 198 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 199 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 200 201 /* Clevo */ 202 #define CLEVO_VENDORID 0x1558 203 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 204 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 205 206 /* Acer */ 207 #define ACER_VENDORID 0x1025 208 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 209 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 210 211 /* Asus */ 212 #define ASUS_VENDORID 0x1043 213 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 214 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 215 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 216 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 217 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 218 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 219 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 220 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 221 222 /* IBM / Lenovo */ 223 #define IBM_VENDORID 0x1014 224 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 225 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 226 227 /* Lenovo */ 228 #define LENOVO_VENDORID 0x17aa 229 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 230 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 231 232 /* Samsung */ 233 #define SAMSUNG_VENDORID 0x144d 234 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 235 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 236 237 /* Medion ? */ 238 #define MEDION_VENDORID 0x161f 239 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 240 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 241 242 /* 243 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 244 * instead of their own, which is beyond my comprehension 245 * (see HDA_CODEC_STAC9221 below). 246 */ 247 #define APPLE_INTEL_MAC 0x76808384 248 249 /* LG Electronics */ 250 #define LG_VENDORID 0x1854 251 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 252 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 253 254 /* Fujitsu Siemens */ 255 #define FS_VENDORID 0x1734 256 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 257 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 258 259 /* Toshiba */ 260 #define TOSHIBA_VENDORID 0x1179 261 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 262 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 263 264 /* Micro-Star International (MSI) */ 265 #define MSI_VENDORID 0x1462 266 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 267 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 268 269 /* Misc constants.. */ 270 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 271 #define HDA_AMP_MUTE_NONE (0) 272 #define HDA_AMP_MUTE_LEFT (1 << 0) 273 #define HDA_AMP_MUTE_RIGHT (1 << 1) 274 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 275 276 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 277 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 278 279 #define HDA_DAC_PATH (1 << 0) 280 #define HDA_ADC_PATH (1 << 1) 281 #define HDA_ADC_RECSEL (1 << 2) 282 283 #define HDA_CTL_OUT (1 << 0) 284 #define HDA_CTL_IN (1 << 1) 285 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 286 287 #define HDA_GPIO_MAX 15 288 /* 0 - 14 = GPIO */ 289 #define HDA_QUIRK_GPIO0 (1 << 0) 290 #define HDA_QUIRK_GPIO1 (1 << 1) 291 #define HDA_QUIRK_GPIO2 (1 << 2) 292 #define HDA_QUIRK_GPIOFLUSH (1 << 15) 293 #define HDA_QUIRK_SOFTPCMVOL (1 << 16) 294 #define HDA_QUIRK_FIXEDRATE (1 << 17) 295 #define HDA_QUIRK_FORCESTEREO (1 << 18) 296 #define HDA_QUIRK_EAPDINV (1 << 19) 297 #define HDA_QUIRK_VREF (1 << 20) 298 299 static const struct { 300 char *key; 301 uint32_t value; 302 } hdac_quirks_tab[] = { 303 { "gpio0", HDA_QUIRK_GPIO0 }, 304 { "gpio1", HDA_QUIRK_GPIO1 }, 305 { "gpio2", HDA_QUIRK_GPIO2 }, 306 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 307 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 308 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 309 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 310 { "eapdinv", HDA_QUIRK_EAPDINV }, 311 { "vref", HDA_QUIRK_VREF }, 312 }; 313 #define HDAC_QUIRKS_TAB_LEN \ 314 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 315 316 #define HDA_BDL_MIN 2 317 #define HDA_BDL_MAX 256 318 #define HDA_BDL_DEFAULT HDA_BDL_MIN 319 320 #define HDA_BLK_MIN 128 321 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 322 323 #define HDA_BUFSZ_MIN 4096 324 #define HDA_BUFSZ_MAX 65536 325 #define HDA_BUFSZ_DEFAULT 16384 326 327 #define HDA_PARSE_MAXDEPTH 10 328 329 #define HDAC_UNSOLTAG_EVENT_HP 0x00 330 331 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 332 333 enum { 334 HDA_PARSE_MIXER, 335 HDA_PARSE_DIRECT 336 }; 337 338 /* Default */ 339 static uint32_t hdac_fmt[] = { 340 AFMT_STEREO | AFMT_S16_LE, 341 0 342 }; 343 344 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 345 346 static const struct { 347 uint32_t model; 348 char *desc; 349 } hdac_devices[] = { 350 { HDA_INTEL_82801F, "Intel 82801F" }, 351 { HDA_INTEL_82801G, "Intel 82801G" }, 352 { HDA_INTEL_82801H, "Intel 82801H" }, 353 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 354 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 355 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 356 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 357 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 358 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 359 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 360 { HDA_ATI_SB450, "ATI SB450" }, 361 { HDA_ATI_SB600, "ATI SB600" }, 362 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 363 { HDA_SIS_966, "SiS 966" }, 364 /* Unknown */ 365 { HDA_INTEL_ALL, "Intel (Unknown)" }, 366 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 367 { HDA_ATI_ALL, "ATI (Unknown)" }, 368 { HDA_VIA_ALL, "VIA (Unknown)" }, 369 { HDA_SIS_ALL, "SiS (Unknown)" }, 370 }; 371 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 372 373 static const struct { 374 uint32_t rate; 375 int valid; 376 uint16_t base; 377 uint16_t mul; 378 uint16_t div; 379 } hda_rate_tab[] = { 380 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 381 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 382 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 383 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 384 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 385 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 386 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 387 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 388 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 389 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 390 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 391 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 392 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 393 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 394 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 395 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 396 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 397 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 398 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 399 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 400 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 401 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 402 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 403 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 404 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 405 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 406 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 407 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 408 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 409 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 410 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 411 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 412 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 413 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 414 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 415 }; 416 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 417 418 /* All codecs you can eat... */ 419 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 420 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 421 422 /* Realtek */ 423 #define REALTEK_VENDORID 0x10ec 424 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 425 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 426 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 427 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 428 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 429 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 430 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 431 432 /* Analog Device */ 433 #define ANALOGDEVICE_VENDORID 0x11d4 434 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 435 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 436 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 437 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 438 439 /* CMedia */ 440 #define CMEDIA_VENDORID 0x434d 441 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 442 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 443 444 /* Sigmatel */ 445 #define SIGMATEL_VENDORID 0x8384 446 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 447 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 448 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 449 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 450 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 451 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 452 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 453 454 /* 455 * Conexant 456 * 457 * Ok, the truth is, I don't have any idea at all whether 458 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 459 * place that tell me it is "Venice" is from its Windows driver INF. 460 * 461 * Venice - CX????? 462 * Waikiki - CX20551-22 463 */ 464 #define CONEXANT_VENDORID 0x14f1 465 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 466 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 467 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 468 469 470 /* Codecs */ 471 static const struct { 472 uint32_t id; 473 char *name; 474 } hdac_codecs[] = { 475 { HDA_CODEC_ALC260, "Realtek ALC260" }, 476 { HDA_CODEC_ALC861, "Realtek ALC861" }, 477 { HDA_CODEC_ALC880, "Realtek ALC880" }, 478 { HDA_CODEC_ALC882, "Realtek ALC882" }, 479 { HDA_CODEC_ALC883, "Realtek ALC883" }, 480 { HDA_CODEC_ALC888, "Realtek ALC888" }, 481 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 482 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 483 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 484 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 485 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 486 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 487 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 488 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 489 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 490 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 491 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 492 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 493 /* Unknown codec */ 494 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 495 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 496 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 497 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 498 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 499 }; 500 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 501 502 enum { 503 HDAC_HP_SWITCH_CTL, 504 HDAC_HP_SWITCH_CTRL 505 }; 506 507 static const struct { 508 uint32_t model; 509 uint32_t id; 510 int type; 511 int inverted; 512 nid_t hpnid; 513 nid_t spkrnid[8]; 514 nid_t eapdnid; 515 } hdac_hp_switch[] = { 516 /* Specific OEM models */ 517 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 518 17, { 16, -1 }, 16 }, 519 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 520 6, { 5, -1 }, 5 }, 521 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 522 6, { 5, -1 }, 5 }, 523 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 524 6, { 5, -1 }, 5 }, 525 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 526 6, { 5, -1 }, -1 }, 527 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 528 13, { 14, -1 }, -1 }, 529 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 530 13, { 14, -1 }, -1 }, 531 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 532 10, { 13, -1 }, -1 }, 533 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 534 26, { 27, -1 }, -1 }, 535 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 536 27, { 20, -1 }, -1 }, 537 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 538 20, { 21, -1 }, -1 }, 539 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 540 20, { 27, -1 }, -1 }, 541 /* 542 * All models that at least come from the same vendor with 543 * simmilar codec. 544 */ 545 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 546 17, { 16, -1 }, 16 }, 547 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 548 6, { 5, -1 }, 5 }, 549 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 550 6, { 5, -1 }, -1 }, 551 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 552 13, { 14, -1 }, -1 }, 553 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 554 26, { 27, -1 }, -1 }, 555 #if 0 556 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 557 20, { 21, -1 }, -1 }, 558 #endif 559 }; 560 #define HDAC_HP_SWITCH_LEN \ 561 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 562 563 static const struct { 564 uint32_t model; 565 uint32_t id; 566 nid_t eapdnid; 567 int hp_switch; 568 } hdac_eapd_switch[] = { 569 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 570 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 571 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 572 }; 573 #define HDAC_EAPD_SWITCH_LEN \ 574 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 575 576 /**************************************************************************** 577 * Function prototypes 578 ****************************************************************************/ 579 static void hdac_intr_handler(void *); 580 static int hdac_reset(struct hdac_softc *); 581 static int hdac_get_capabilities(struct hdac_softc *); 582 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 583 static int hdac_dma_alloc(struct hdac_softc *, 584 struct hdac_dma *, bus_size_t); 585 static void hdac_dma_free(struct hdac_dma *); 586 static int hdac_mem_alloc(struct hdac_softc *); 587 static void hdac_mem_free(struct hdac_softc *); 588 static int hdac_irq_alloc(struct hdac_softc *); 589 static void hdac_irq_free(struct hdac_softc *); 590 static void hdac_corb_init(struct hdac_softc *); 591 static void hdac_rirb_init(struct hdac_softc *); 592 static void hdac_corb_start(struct hdac_softc *); 593 static void hdac_rirb_start(struct hdac_softc *); 594 static void hdac_scan_codecs(struct hdac_softc *); 595 static int hdac_probe_codec(struct hdac_codec *); 596 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 597 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 598 599 static void hdac_attach2(void *); 600 601 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 602 uint32_t, int); 603 static void hdac_command_send_internal(struct hdac_softc *, 604 struct hdac_command_list *, int); 605 606 static int hdac_probe(device_t); 607 static int hdac_attach(device_t); 608 static int hdac_detach(device_t); 609 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 610 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 611 uint32_t, int, int); 612 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 613 nid_t, int, int); 614 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 615 nid_t, nid_t, int, int, int, int, int, int); 616 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 617 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 618 619 static int hdac_rirb_flush(struct hdac_softc *sc); 620 static int hdac_unsolq_flush(struct hdac_softc *sc); 621 622 #define hdac_command(a1, a2, a3) \ 623 hdac_command_sendone_internal(a1, a2, a3) 624 625 #define hdac_codec_id(d) \ 626 ((uint32_t)((d == NULL) ? 0x00000000 : \ 627 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 628 ((uint32_t)(d)->device_id & 0x0000ffff)))) 629 630 static char * 631 hdac_codec_name(struct hdac_devinfo *devinfo) 632 { 633 uint32_t id; 634 int i; 635 636 id = hdac_codec_id(devinfo); 637 638 for (i = 0; i < HDAC_CODECS_LEN; i++) { 639 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 640 return (hdac_codecs[i].name); 641 } 642 643 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 644 } 645 646 static char * 647 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 648 { 649 static char *ossname[] = SOUND_DEVICE_NAMES; 650 static char *unknown = "???"; 651 int i; 652 653 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 654 if (devmask & (1 << i)) 655 return (ossname[i]); 656 } 657 return (unknown); 658 } 659 660 static void 661 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 662 { 663 static char *ossname[] = SOUND_DEVICE_NAMES; 664 int i, first = 1; 665 666 bzero(buf, len); 667 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 668 if (mask & (1 << i)) { 669 if (first == 0) 670 strlcat(buf, ", ", len); 671 strlcat(buf, ossname[i], len); 672 first = 0; 673 } 674 } 675 } 676 677 static struct hdac_audio_ctl * 678 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 679 { 680 if (devinfo == NULL || 681 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 682 index == NULL || devinfo->function.audio.ctl == NULL || 683 devinfo->function.audio.ctlcnt < 1 || 684 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 685 return (NULL); 686 return (&devinfo->function.audio.ctl[(*index)++]); 687 } 688 689 static struct hdac_audio_ctl * 690 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 691 int index, int cnt) 692 { 693 struct hdac_audio_ctl *ctl, *retctl = NULL; 694 int i, at, atindex, found = 0; 695 696 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 697 return (NULL); 698 699 at = cnt; 700 if (at == 0) 701 at = 1; 702 else if (at < 0) 703 at = -1; 704 atindex = index; 705 if (atindex < 0) 706 atindex = -1; 707 708 i = 0; 709 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 710 if (ctl->enable == 0 || ctl->widget == NULL) 711 continue; 712 if (!(ctl->widget->nid == nid && (atindex == -1 || 713 ctl->index == atindex))) 714 continue; 715 found++; 716 if (found == cnt) 717 return (ctl); 718 retctl = ctl; 719 } 720 721 return ((at == -1) ? retctl : NULL); 722 } 723 724 static void 725 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 726 { 727 struct hdac_softc *sc; 728 struct hdac_widget *w; 729 struct hdac_audio_ctl *ctl; 730 uint32_t id, res; 731 int i = 0, j, forcemute; 732 nid_t cad; 733 734 if (devinfo == NULL || devinfo->codec == NULL || 735 devinfo->codec->sc == NULL) 736 return; 737 738 sc = devinfo->codec->sc; 739 cad = devinfo->codec->cad; 740 id = hdac_codec_id(devinfo); 741 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 742 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 743 sc->pci_subvendor) && 744 hdac_hp_switch[i].id == id) 745 break; 746 } 747 748 if (i >= HDAC_HP_SWITCH_LEN) 749 return; 750 751 forcemute = 0; 752 if (hdac_hp_switch[i].eapdnid != -1) { 753 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 754 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 755 forcemute = (w->param.eapdbtl & 756 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 757 } 758 759 res = hdac_command(sc, 760 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 761 HDA_BOOTVERBOSE( 762 device_printf(sc->dev, 763 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 764 hdac_hp_switch[i].hpnid, res); 765 ); 766 res >>= 31; 767 res ^= hdac_hp_switch[i].inverted; 768 769 switch (hdac_hp_switch[i].type) { 770 case HDAC_HP_SWITCH_CTL: 771 ctl = hdac_audio_ctl_amp_get(devinfo, 772 hdac_hp_switch[i].hpnid, 0, 1); 773 if (ctl != NULL) { 774 ctl->muted = (res != 0 && forcemute == 0) ? 775 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 776 hdac_audio_ctl_amp_set(ctl, 777 HDA_AMP_MUTE_DEFAULT, ctl->left, 778 ctl->right); 779 } 780 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 781 ctl = hdac_audio_ctl_amp_get(devinfo, 782 hdac_hp_switch[i].spkrnid[j], 0, 1); 783 if (ctl != NULL) { 784 ctl->muted = (res != 0 || forcemute == 1) ? 785 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 786 hdac_audio_ctl_amp_set(ctl, 787 HDA_AMP_MUTE_DEFAULT, ctl->left, 788 ctl->right); 789 } 790 } 791 break; 792 case HDAC_HP_SWITCH_CTRL: 793 if (res != 0) { 794 /* HP in */ 795 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 796 if (w != NULL && w->type == 797 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 798 if (forcemute == 0) 799 w->wclass.pin.ctrl |= 800 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 801 else 802 w->wclass.pin.ctrl &= 803 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 804 hdac_command(sc, 805 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 806 w->wclass.pin.ctrl), cad); 807 } 808 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 809 w = hdac_widget_get(devinfo, 810 hdac_hp_switch[i].spkrnid[j]); 811 if (w != NULL && w->type == 812 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 813 w->wclass.pin.ctrl &= 814 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 815 hdac_command(sc, 816 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 817 w->nid, 818 w->wclass.pin.ctrl), cad); 819 } 820 } 821 } else { 822 /* HP out */ 823 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 824 if (w != NULL && w->type == 825 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 826 w->wclass.pin.ctrl &= 827 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 828 hdac_command(sc, 829 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 830 w->wclass.pin.ctrl), cad); 831 } 832 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 833 w = hdac_widget_get(devinfo, 834 hdac_hp_switch[i].spkrnid[j]); 835 if (w != NULL && w->type == 836 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 837 if (forcemute == 0) 838 w->wclass.pin.ctrl |= 839 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 840 else 841 w->wclass.pin.ctrl &= 842 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 843 hdac_command(sc, 844 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 845 w->nid, 846 w->wclass.pin.ctrl), cad); 847 } 848 } 849 } 850 break; 851 default: 852 break; 853 } 854 } 855 856 static void 857 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 858 { 859 struct hdac_softc *sc; 860 struct hdac_devinfo *devinfo = NULL; 861 device_t *devlist = NULL; 862 int devcount, i; 863 864 if (codec == NULL || codec->sc == NULL) 865 return; 866 867 sc = codec->sc; 868 869 HDA_BOOTVERBOSE( 870 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 871 ); 872 873 device_get_children(sc->dev, &devlist, &devcount); 874 for (i = 0; devlist != NULL && i < devcount; i++) { 875 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 876 if (devinfo != NULL && devinfo->node_type == 877 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 878 devinfo->codec != NULL && 879 devinfo->codec->cad == codec->cad) { 880 break; 881 } else 882 devinfo = NULL; 883 } 884 if (devlist != NULL) 885 free(devlist, M_TEMP); 886 887 if (devinfo == NULL) 888 return; 889 890 switch (tag) { 891 case HDAC_UNSOLTAG_EVENT_HP: 892 hdac_hp_switch_handler(devinfo); 893 break; 894 default: 895 break; 896 } 897 } 898 899 static int 900 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 901 { 902 /* XXX to be removed */ 903 #ifdef HDAC_INTR_EXTRA 904 uint32_t res; 905 #endif 906 907 if (ch->blkcnt == 0) 908 return (0); 909 910 /* XXX to be removed */ 911 #ifdef HDAC_INTR_EXTRA 912 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 913 #endif 914 915 /* XXX to be removed */ 916 #ifdef HDAC_INTR_EXTRA 917 HDA_BOOTVERBOSE( 918 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 919 device_printf(sc->dev, 920 "PCMDIR_%s intr triggered beyond stream boundary:" 921 "%08x\n", 922 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 923 ); 924 #endif 925 926 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 927 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 928 929 /* XXX to be removed */ 930 #ifdef HDAC_INTR_EXTRA 931 if (res & HDAC_SDSTS_BCIS) { 932 #endif 933 return (1); 934 /* XXX to be removed */ 935 #ifdef HDAC_INTR_EXTRA 936 } 937 #endif 938 939 return (0); 940 } 941 942 /**************************************************************************** 943 * void hdac_intr_handler(void *) 944 * 945 * Interrupt handler. Processes interrupts received from the hdac. 946 ****************************************************************************/ 947 static void 948 hdac_intr_handler(void *context) 949 { 950 struct hdac_softc *sc; 951 uint32_t intsts; 952 uint8_t rirbsts; 953 struct hdac_rirb *rirb_base; 954 uint32_t trigger = 0; 955 956 sc = (struct hdac_softc *)context; 957 958 hdac_lock(sc); 959 if (sc->polling != 0) { 960 hdac_unlock(sc); 961 return; 962 } 963 /* Do we have anything to do? */ 964 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 965 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 966 hdac_unlock(sc); 967 return; 968 } 969 970 /* Was this a controller interrupt? */ 971 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 972 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 973 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 974 /* Get as many responses that we can */ 975 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 976 HDAC_WRITE_1(&sc->mem, 977 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 978 hdac_rirb_flush(sc); 979 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 980 } 981 /* XXX to be removed */ 982 /* Clear interrupt and exit */ 983 #ifdef HDAC_INTR_EXTRA 984 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 985 #endif 986 } 987 988 hdac_unsolq_flush(sc); 989 990 if (intsts & HDAC_INTSTS_SIS_MASK) { 991 if ((intsts & (1 << sc->num_iss)) && 992 hdac_stream_intr(sc, &sc->play) != 0) 993 trigger |= 1; 994 if ((intsts & (1 << 0)) && 995 hdac_stream_intr(sc, &sc->rec) != 0) 996 trigger |= 2; 997 /* XXX to be removed */ 998 #ifdef HDAC_INTR_EXTRA 999 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1000 HDAC_INTSTS_SIS_MASK); 1001 #endif 1002 } 1003 1004 hdac_unlock(sc); 1005 1006 if (trigger & 1) 1007 chn_intr(sc->play.c); 1008 if (trigger & 2) 1009 chn_intr(sc->rec.c); 1010 } 1011 1012 /**************************************************************************** 1013 * int hdac_reset(hdac_softc *) 1014 * 1015 * Reset the hdac to a quiescent and known state. 1016 ****************************************************************************/ 1017 static int 1018 hdac_reset(struct hdac_softc *sc) 1019 { 1020 uint32_t gctl; 1021 int count, i; 1022 1023 /* 1024 * Stop all Streams DMA engine 1025 */ 1026 for (i = 0; i < sc->num_iss; i++) 1027 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1028 for (i = 0; i < sc->num_oss; i++) 1029 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1030 for (i = 0; i < sc->num_bss; i++) 1031 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1032 1033 /* 1034 * Stop Control DMA engines 1035 */ 1036 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1037 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1038 1039 /* 1040 * Reset the controller. The reset must remain asserted for 1041 * a minimum of 100us. 1042 */ 1043 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1044 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1045 count = 10000; 1046 do { 1047 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1048 if (!(gctl & HDAC_GCTL_CRST)) 1049 break; 1050 DELAY(10); 1051 } while (--count); 1052 if (gctl & HDAC_GCTL_CRST) { 1053 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1054 return (ENXIO); 1055 } 1056 DELAY(100); 1057 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1058 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1059 count = 10000; 1060 do { 1061 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1062 if (gctl & HDAC_GCTL_CRST) 1063 break; 1064 DELAY(10); 1065 } while (--count); 1066 if (!(gctl & HDAC_GCTL_CRST)) { 1067 device_printf(sc->dev, "Device stuck in reset\n"); 1068 return (ENXIO); 1069 } 1070 1071 /* 1072 * Wait for codecs to finish their own reset sequence. The delay here 1073 * should be of 250us but for some reasons, on it's not enough on my 1074 * computer. Let's use twice as much as necessary to make sure that 1075 * it's reset properly. 1076 */ 1077 DELAY(1000); 1078 1079 return (0); 1080 } 1081 1082 1083 /**************************************************************************** 1084 * int hdac_get_capabilities(struct hdac_softc *); 1085 * 1086 * Retreive the general capabilities of the hdac; 1087 * Number of Input Streams 1088 * Number of Output Streams 1089 * Number of bidirectional Streams 1090 * 64bit ready 1091 * CORB and RIRB sizes 1092 ****************************************************************************/ 1093 static int 1094 hdac_get_capabilities(struct hdac_softc *sc) 1095 { 1096 uint16_t gcap; 1097 uint8_t corbsize, rirbsize; 1098 1099 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1100 sc->num_iss = HDAC_GCAP_ISS(gcap); 1101 sc->num_oss = HDAC_GCAP_OSS(gcap); 1102 sc->num_bss = HDAC_GCAP_BSS(gcap); 1103 1104 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1105 1106 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1107 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1108 HDAC_CORBSIZE_CORBSZCAP_256) 1109 sc->corb_size = 256; 1110 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1111 HDAC_CORBSIZE_CORBSZCAP_16) 1112 sc->corb_size = 16; 1113 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1114 HDAC_CORBSIZE_CORBSZCAP_2) 1115 sc->corb_size = 2; 1116 else { 1117 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1118 __func__, corbsize); 1119 return (ENXIO); 1120 } 1121 1122 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1123 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1124 HDAC_RIRBSIZE_RIRBSZCAP_256) 1125 sc->rirb_size = 256; 1126 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1127 HDAC_RIRBSIZE_RIRBSZCAP_16) 1128 sc->rirb_size = 16; 1129 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1130 HDAC_RIRBSIZE_RIRBSZCAP_2) 1131 sc->rirb_size = 2; 1132 else { 1133 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1134 __func__, rirbsize); 1135 return (ENXIO); 1136 } 1137 1138 return (0); 1139 } 1140 1141 1142 /**************************************************************************** 1143 * void hdac_dma_cb 1144 * 1145 * This function is called by bus_dmamap_load when the mapping has been 1146 * established. We just record the physical address of the mapping into 1147 * the struct hdac_dma passed in. 1148 ****************************************************************************/ 1149 static void 1150 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1151 { 1152 struct hdac_dma *dma; 1153 1154 if (error == 0) { 1155 dma = (struct hdac_dma *)callback_arg; 1156 dma->dma_paddr = segs[0].ds_addr; 1157 } 1158 } 1159 1160 static void 1161 hdac_dma_attr(vm_offset_t va, vm_size_t size, int mode) 1162 { 1163 #if defined(__i386__) || defined(__amd64__) 1164 switch (mode) { 1165 case HDAC_DMA_UNCACHEABLE: 1166 pmap_change_attr(va, size, PAT_UNCACHEABLE); 1167 break; 1168 case HDAC_DMA_WRITEBACK: 1169 pmap_change_attr(va, size, PAT_WRITE_BACK); 1170 break; 1171 default: 1172 break; 1173 } 1174 #endif 1175 } 1176 1177 /**************************************************************************** 1178 * int hdac_dma_alloc 1179 * 1180 * This function allocate and setup a dma region (struct hdac_dma). 1181 * It must be freed by a corresponding hdac_dma_free. 1182 ****************************************************************************/ 1183 static int 1184 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1185 { 1186 int result; 1187 int lowaddr; 1188 1189 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1190 BUS_SPACE_MAXADDR_32BIT; 1191 bzero(dma, sizeof(*dma)); 1192 1193 /* 1194 * Create a DMA tag 1195 */ 1196 result = bus_dma_tag_create(NULL, /* parent */ 1197 HDAC_DMA_ALIGNMENT, /* alignment */ 1198 0, /* boundary */ 1199 lowaddr, /* lowaddr */ 1200 BUS_SPACE_MAXADDR, /* highaddr */ 1201 NULL, /* filtfunc */ 1202 NULL, /* fistfuncarg */ 1203 size, /* maxsize */ 1204 1, /* nsegments */ 1205 size, /* maxsegsz */ 1206 0, /* flags */ 1207 NULL, /* lockfunc */ 1208 NULL, /* lockfuncarg */ 1209 &dma->dma_tag); /* dmat */ 1210 if (result != 0) { 1211 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1212 __func__, result); 1213 goto hdac_dma_alloc_fail; 1214 } 1215 1216 /* 1217 * Allocate DMA memory 1218 */ 1219 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1220 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map); 1221 if (result != 0) { 1222 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1223 __func__, result); 1224 goto hdac_dma_alloc_fail; 1225 } 1226 1227 /* 1228 * Map the memory 1229 */ 1230 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1231 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1232 BUS_DMA_NOWAIT); 1233 if (result != 0 || dma->dma_paddr == 0) { 1234 if (result == 0) 1235 result = ENOMEM; 1236 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1237 __func__, result); 1238 goto hdac_dma_alloc_fail; 1239 } 1240 hdac_dma_attr((vm_offset_t)dma->dma_vaddr, size, HDAC_DMA_UNCACHEABLE); 1241 dma->dma_size = size; 1242 1243 return (0); 1244 hdac_dma_alloc_fail: 1245 hdac_dma_free(dma); 1246 1247 return (result); 1248 } 1249 1250 1251 /**************************************************************************** 1252 * void hdac_dma_free(struct hdac_dma *) 1253 * 1254 * Free a struct dhac_dma that has been previously allocated via the 1255 * hdac_dma_alloc function. 1256 ****************************************************************************/ 1257 static void 1258 hdac_dma_free(struct hdac_dma *dma) 1259 { 1260 if (dma->dma_map != NULL) { 1261 /* Flush caches */ 1262 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1263 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1264 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1265 } 1266 if (dma->dma_vaddr != NULL) { 1267 if (dma->dma_size > 0) 1268 hdac_dma_attr((vm_offset_t)dma->dma_vaddr, 1269 dma->dma_size, HDAC_DMA_WRITEBACK); 1270 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1271 dma->dma_vaddr = NULL; 1272 } 1273 dma->dma_map = NULL; 1274 if (dma->dma_tag != NULL) { 1275 bus_dma_tag_destroy(dma->dma_tag); 1276 dma->dma_tag = NULL; 1277 } 1278 dma->dma_size = 0; 1279 } 1280 1281 /**************************************************************************** 1282 * int hdac_mem_alloc(struct hdac_softc *) 1283 * 1284 * Allocate all the bus resources necessary to speak with the physical 1285 * controller. 1286 ****************************************************************************/ 1287 static int 1288 hdac_mem_alloc(struct hdac_softc *sc) 1289 { 1290 struct hdac_mem *mem; 1291 1292 mem = &sc->mem; 1293 mem->mem_rid = PCIR_BAR(0); 1294 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1295 &mem->mem_rid, RF_ACTIVE); 1296 if (mem->mem_res == NULL) { 1297 device_printf(sc->dev, 1298 "%s: Unable to allocate memory resource\n", __func__); 1299 return (ENOMEM); 1300 } 1301 mem->mem_tag = rman_get_bustag(mem->mem_res); 1302 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1303 1304 return (0); 1305 } 1306 1307 /**************************************************************************** 1308 * void hdac_mem_free(struct hdac_softc *) 1309 * 1310 * Free up resources previously allocated by hdac_mem_alloc. 1311 ****************************************************************************/ 1312 static void 1313 hdac_mem_free(struct hdac_softc *sc) 1314 { 1315 struct hdac_mem *mem; 1316 1317 mem = &sc->mem; 1318 if (mem->mem_res != NULL) 1319 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1320 mem->mem_res); 1321 mem->mem_res = NULL; 1322 } 1323 1324 /**************************************************************************** 1325 * int hdac_irq_alloc(struct hdac_softc *) 1326 * 1327 * Allocate and setup the resources necessary for interrupt handling. 1328 ****************************************************************************/ 1329 static int 1330 hdac_irq_alloc(struct hdac_softc *sc) 1331 { 1332 struct hdac_irq *irq; 1333 int result; 1334 1335 irq = &sc->irq; 1336 irq->irq_rid = 0x0; 1337 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1338 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1339 if (irq->irq_res == NULL) { 1340 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1341 __func__); 1342 goto hdac_irq_alloc_fail; 1343 } 1344 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1345 hdac_intr_handler, sc, &irq->irq_handle); 1346 if (result != 0) { 1347 device_printf(sc->dev, 1348 "%s: Unable to setup interrupt handler (%x)\n", 1349 __func__, result); 1350 goto hdac_irq_alloc_fail; 1351 } 1352 1353 return (0); 1354 1355 hdac_irq_alloc_fail: 1356 hdac_irq_free(sc); 1357 1358 return (ENXIO); 1359 } 1360 1361 /**************************************************************************** 1362 * void hdac_irq_free(struct hdac_softc *) 1363 * 1364 * Free up resources previously allocated by hdac_irq_alloc. 1365 ****************************************************************************/ 1366 static void 1367 hdac_irq_free(struct hdac_softc *sc) 1368 { 1369 struct hdac_irq *irq; 1370 1371 irq = &sc->irq; 1372 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1373 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1374 if (irq->irq_res != NULL) 1375 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1376 irq->irq_res); 1377 irq->irq_handle = NULL; 1378 irq->irq_res = NULL; 1379 } 1380 1381 /**************************************************************************** 1382 * void hdac_corb_init(struct hdac_softc *) 1383 * 1384 * Initialize the corb registers for operations but do not start it up yet. 1385 * The CORB engine must not be running when this function is called. 1386 ****************************************************************************/ 1387 static void 1388 hdac_corb_init(struct hdac_softc *sc) 1389 { 1390 uint8_t corbsize; 1391 uint64_t corbpaddr; 1392 1393 /* Setup the CORB size. */ 1394 switch (sc->corb_size) { 1395 case 256: 1396 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1397 break; 1398 case 16: 1399 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1400 break; 1401 case 2: 1402 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1403 break; 1404 default: 1405 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1406 } 1407 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1408 1409 /* Setup the CORB Address in the hdac */ 1410 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1411 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1412 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1413 1414 /* Set the WP and RP */ 1415 sc->corb_wp = 0; 1416 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1417 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1418 /* 1419 * The HDA specification indicates that the CORBRPRST bit will always 1420 * read as zero. Unfortunately, it seems that at least the 82801G 1421 * doesn't reset the bit to zero, which stalls the corb engine. 1422 * manually reset the bit to zero before continuing. 1423 */ 1424 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1425 1426 /* Enable CORB error reporting */ 1427 #if 0 1428 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1429 #endif 1430 } 1431 1432 /**************************************************************************** 1433 * void hdac_rirb_init(struct hdac_softc *) 1434 * 1435 * Initialize the rirb registers for operations but do not start it up yet. 1436 * The RIRB engine must not be running when this function is called. 1437 ****************************************************************************/ 1438 static void 1439 hdac_rirb_init(struct hdac_softc *sc) 1440 { 1441 uint8_t rirbsize; 1442 uint64_t rirbpaddr; 1443 1444 /* Setup the RIRB size. */ 1445 switch (sc->rirb_size) { 1446 case 256: 1447 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1448 break; 1449 case 16: 1450 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1451 break; 1452 case 2: 1453 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1454 break; 1455 default: 1456 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1457 } 1458 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1459 1460 /* Setup the RIRB Address in the hdac */ 1461 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1462 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1463 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1464 1465 /* Setup the WP and RP */ 1466 sc->rirb_rp = 0; 1467 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1468 1469 if (sc->polling == 0) { 1470 /* Setup the interrupt threshold */ 1471 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1472 1473 /* Enable Overrun and response received reporting */ 1474 #if 0 1475 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1476 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1477 #else 1478 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1479 #endif 1480 } 1481 1482 /* 1483 * Make sure that the Host CPU cache doesn't contain any dirty 1484 * cache lines that falls in the rirb. If I understood correctly, it 1485 * should be sufficient to do this only once as the rirb is purely 1486 * read-only from now on. 1487 */ 1488 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1489 BUS_DMASYNC_PREREAD); 1490 } 1491 1492 /**************************************************************************** 1493 * void hdac_corb_start(hdac_softc *) 1494 * 1495 * Startup the corb DMA engine 1496 ****************************************************************************/ 1497 static void 1498 hdac_corb_start(struct hdac_softc *sc) 1499 { 1500 uint32_t corbctl; 1501 1502 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1503 corbctl |= HDAC_CORBCTL_CORBRUN; 1504 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1505 } 1506 1507 /**************************************************************************** 1508 * void hdac_rirb_start(hdac_softc *) 1509 * 1510 * Startup the rirb DMA engine 1511 ****************************************************************************/ 1512 static void 1513 hdac_rirb_start(struct hdac_softc *sc) 1514 { 1515 uint32_t rirbctl; 1516 1517 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1518 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1519 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1520 } 1521 1522 1523 /**************************************************************************** 1524 * void hdac_scan_codecs(struct hdac_softc *) 1525 * 1526 * Scan the bus for available codecs. 1527 ****************************************************************************/ 1528 static void 1529 hdac_scan_codecs(struct hdac_softc *sc) 1530 { 1531 struct hdac_codec *codec; 1532 int i; 1533 uint16_t statests; 1534 1535 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1536 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1537 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1538 /* We have found a codec. */ 1539 hdac_unlock(sc); 1540 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1541 M_HDAC, M_ZERO | M_NOWAIT); 1542 hdac_lock(sc); 1543 if (codec == NULL) { 1544 device_printf(sc->dev, 1545 "Unable to allocate memory for codec\n"); 1546 continue; 1547 } 1548 codec->commands = NULL; 1549 codec->responses_received = 0; 1550 codec->verbs_sent = 0; 1551 codec->sc = sc; 1552 codec->cad = i; 1553 sc->codecs[i] = codec; 1554 if (hdac_probe_codec(codec) != 0) 1555 break; 1556 } 1557 } 1558 /* All codecs have been probed, now try to attach drivers to them */ 1559 /* bus_generic_attach(sc->dev); */ 1560 } 1561 1562 /**************************************************************************** 1563 * void hdac_probe_codec(struct hdac_softc *, int) 1564 * 1565 * Probe a the given codec_id for available function groups. 1566 ****************************************************************************/ 1567 static int 1568 hdac_probe_codec(struct hdac_codec *codec) 1569 { 1570 struct hdac_softc *sc = codec->sc; 1571 struct hdac_devinfo *devinfo; 1572 uint32_t vendorid, revisionid, subnode; 1573 int startnode; 1574 int endnode; 1575 int i; 1576 nid_t cad = codec->cad; 1577 1578 HDA_BOOTVERBOSE( 1579 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1580 ); 1581 vendorid = hdac_command(sc, 1582 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1583 cad); 1584 revisionid = hdac_command(sc, 1585 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1586 cad); 1587 subnode = hdac_command(sc, 1588 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1589 cad); 1590 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1591 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1592 1593 HDA_BOOTVERBOSE( 1594 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1595 startnode, endnode); 1596 ); 1597 for (i = startnode; i < endnode; i++) { 1598 devinfo = hdac_probe_function(codec, i); 1599 if (devinfo != NULL) { 1600 /* XXX Ignore other FG. */ 1601 devinfo->vendor_id = 1602 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1603 devinfo->device_id = 1604 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1605 devinfo->revision_id = 1606 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1607 devinfo->stepping_id = 1608 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1609 HDA_BOOTVERBOSE( 1610 device_printf(sc->dev, 1611 "HDA_DEBUG: \tFound AFG nid=%d " 1612 "[startnode=%d endnode=%d]\n", 1613 devinfo->nid, startnode, endnode); 1614 ); 1615 return (1); 1616 } 1617 } 1618 1619 HDA_BOOTVERBOSE( 1620 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1621 ); 1622 return (0); 1623 } 1624 1625 static struct hdac_devinfo * 1626 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1627 { 1628 struct hdac_softc *sc = codec->sc; 1629 struct hdac_devinfo *devinfo; 1630 uint32_t fctgrptype; 1631 nid_t cad = codec->cad; 1632 1633 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1634 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1635 1636 /* XXX For now, ignore other FG. */ 1637 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1638 return (NULL); 1639 1640 hdac_unlock(sc); 1641 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1642 M_NOWAIT | M_ZERO); 1643 hdac_lock(sc); 1644 if (devinfo == NULL) { 1645 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1646 __func__); 1647 return (NULL); 1648 } 1649 1650 devinfo->nid = nid; 1651 devinfo->node_type = fctgrptype; 1652 devinfo->codec = codec; 1653 1654 hdac_add_child(sc, devinfo); 1655 1656 return (devinfo); 1657 } 1658 1659 static void 1660 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1661 { 1662 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1663 device_set_ivars(devinfo->dev, (void *)devinfo); 1664 /* XXX - Print more information when booting verbose??? */ 1665 } 1666 1667 static void 1668 hdac_widget_connection_parse(struct hdac_widget *w) 1669 { 1670 struct hdac_softc *sc = w->devinfo->codec->sc; 1671 uint32_t res; 1672 int i, j, max, found, entnum, cnid; 1673 nid_t cad = w->devinfo->codec->cad; 1674 nid_t nid = w->nid; 1675 1676 res = hdac_command(sc, 1677 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1678 1679 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1680 1681 if (w->nconns < 1) 1682 return; 1683 1684 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1685 res = 0; 1686 i = 0; 1687 found = 0; 1688 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1689 1690 while (i < w->nconns) { 1691 res = hdac_command(sc, 1692 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1693 for (j = 0; j < entnum; j++) { 1694 cnid = res; 1695 cnid >>= (32 / entnum) * j; 1696 cnid &= (1 << (32 / entnum)) - 1; 1697 if (cnid == 0) 1698 continue; 1699 if (found > max) { 1700 device_printf(sc->dev, 1701 "node %d: Adding %d: " 1702 "Max connection reached!\n", 1703 nid, cnid); 1704 continue; 1705 } 1706 w->conns[found++] = cnid; 1707 } 1708 i += entnum; 1709 } 1710 1711 HDA_BOOTVERBOSE( 1712 if (w->nconns != found) { 1713 device_printf(sc->dev, 1714 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1715 "length=%d != found=%d\n", 1716 nid, w->nconns, found); 1717 } 1718 ); 1719 } 1720 1721 static uint32_t 1722 hdac_widget_pin_getconfig(struct hdac_widget *w) 1723 { 1724 struct hdac_softc *sc; 1725 uint32_t config, orig, id; 1726 nid_t cad, nid; 1727 1728 sc = w->devinfo->codec->sc; 1729 cad = w->devinfo->codec->cad; 1730 nid = w->nid; 1731 id = hdac_codec_id(w->devinfo); 1732 1733 config = hdac_command(sc, 1734 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1735 cad); 1736 orig = config; 1737 1738 /* 1739 * XXX REWRITE!!!! Don't argue! 1740 */ 1741 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1742 switch (nid) { 1743 case 26: 1744 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1745 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1746 break; 1747 case 27: 1748 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1749 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1750 break; 1751 default: 1752 break; 1753 } 1754 } else if (id == HDA_CODEC_ALC880 && 1755 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1756 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1757 /* 1758 * Super broken BIOS 1759 */ 1760 switch (nid) { 1761 case 20: 1762 break; 1763 case 21: 1764 break; 1765 case 22: 1766 break; 1767 case 23: 1768 break; 1769 case 24: /* MIC1 */ 1770 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1771 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1772 break; 1773 case 25: /* XXX MIC2 */ 1774 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1775 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1776 break; 1777 case 26: /* LINE1 */ 1778 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1779 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1780 break; 1781 case 27: /* XXX LINE2 */ 1782 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1783 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1784 break; 1785 case 28: /* CD */ 1786 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1787 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1788 break; 1789 case 30: 1790 break; 1791 case 31: 1792 break; 1793 default: 1794 break; 1795 } 1796 } else if (id == HDA_CODEC_ALC883 && 1797 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 1798 switch (nid) { 1799 case 25: 1800 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1801 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1802 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1803 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1804 break; 1805 default: 1806 break; 1807 } 1808 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 1809 HP_V3000_SUBVENDOR) { 1810 switch (nid) { 1811 case 18: 1812 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 1813 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 1814 break; 1815 case 20: 1816 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1817 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1818 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1819 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1820 break; 1821 case 21: 1822 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1823 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1824 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 1825 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1826 break; 1827 default: 1828 break; 1829 } 1830 } 1831 1832 HDA_BOOTVERBOSE( 1833 if (config != orig) 1834 device_printf(sc->dev, 1835 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 1836 nid, orig, config); 1837 ); 1838 1839 return (config); 1840 } 1841 1842 static uint32_t 1843 hdac_widget_pin_getcaps(struct hdac_widget *w) 1844 { 1845 struct hdac_softc *sc; 1846 uint32_t caps, orig, id; 1847 nid_t cad, nid; 1848 1849 sc = w->devinfo->codec->sc; 1850 cad = w->devinfo->codec->cad; 1851 nid = w->nid; 1852 id = hdac_codec_id(w->devinfo); 1853 1854 caps = hdac_command(sc, 1855 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1856 orig = caps; 1857 1858 HDA_BOOTVERBOSE( 1859 if (caps != orig) 1860 device_printf(sc->dev, 1861 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 1862 nid, orig, caps); 1863 ); 1864 1865 return (caps); 1866 } 1867 1868 static void 1869 hdac_widget_pin_parse(struct hdac_widget *w) 1870 { 1871 struct hdac_softc *sc = w->devinfo->codec->sc; 1872 uint32_t config, pincap; 1873 char *devstr, *connstr; 1874 nid_t cad = w->devinfo->codec->cad; 1875 nid_t nid = w->nid; 1876 1877 config = hdac_widget_pin_getconfig(w); 1878 w->wclass.pin.config = config; 1879 1880 pincap = hdac_widget_pin_getcaps(w); 1881 w->wclass.pin.cap = pincap; 1882 1883 w->wclass.pin.ctrl = hdac_command(sc, 1884 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1885 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1886 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1887 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1888 1889 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1890 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1891 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1892 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1893 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1894 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1895 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1896 w->param.eapdbtl = hdac_command(sc, 1897 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1898 w->param.eapdbtl &= 0x7; 1899 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1900 } else 1901 w->param.eapdbtl = HDAC_INVALID; 1902 1903 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1904 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1905 devstr = "line out"; 1906 break; 1907 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1908 devstr = "speaker"; 1909 break; 1910 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1911 devstr = "headphones out"; 1912 break; 1913 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1914 devstr = "CD"; 1915 break; 1916 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1917 devstr = "SPDIF out"; 1918 break; 1919 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1920 devstr = "digital (other) out"; 1921 break; 1922 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1923 devstr = "modem, line side"; 1924 break; 1925 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1926 devstr = "modem, handset side"; 1927 break; 1928 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1929 devstr = "line in"; 1930 break; 1931 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1932 devstr = "AUX"; 1933 break; 1934 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1935 devstr = "Mic in"; 1936 break; 1937 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1938 devstr = "telephony"; 1939 break; 1940 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1941 devstr = "SPDIF in"; 1942 break; 1943 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1944 devstr = "digital (other) in"; 1945 break; 1946 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1947 devstr = "other"; 1948 break; 1949 default: 1950 devstr = "unknown"; 1951 break; 1952 } 1953 1954 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1955 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1956 connstr = "jack"; 1957 break; 1958 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1959 connstr = "none"; 1960 break; 1961 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1962 connstr = "fixed"; 1963 break; 1964 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1965 connstr = "jack / fixed"; 1966 break; 1967 default: 1968 connstr = "unknown"; 1969 break; 1970 } 1971 1972 strlcat(w->name, ": ", sizeof(w->name)); 1973 strlcat(w->name, devstr, sizeof(w->name)); 1974 strlcat(w->name, " (", sizeof(w->name)); 1975 strlcat(w->name, connstr, sizeof(w->name)); 1976 strlcat(w->name, ")", sizeof(w->name)); 1977 } 1978 1979 static void 1980 hdac_widget_parse(struct hdac_widget *w) 1981 { 1982 struct hdac_softc *sc = w->devinfo->codec->sc; 1983 uint32_t wcap, cap; 1984 char *typestr; 1985 nid_t cad = w->devinfo->codec->cad; 1986 nid_t nid = w->nid; 1987 1988 wcap = hdac_command(sc, 1989 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1990 cad); 1991 w->param.widget_cap = wcap; 1992 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1993 1994 switch (w->type) { 1995 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1996 typestr = "audio output"; 1997 break; 1998 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1999 typestr = "audio input"; 2000 break; 2001 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2002 typestr = "audio mixer"; 2003 break; 2004 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2005 typestr = "audio selector"; 2006 break; 2007 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2008 typestr = "pin"; 2009 break; 2010 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2011 typestr = "power widget"; 2012 break; 2013 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2014 typestr = "volume widget"; 2015 break; 2016 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2017 typestr = "beep widget"; 2018 break; 2019 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2020 typestr = "vendor widget"; 2021 break; 2022 default: 2023 typestr = "unknown type"; 2024 break; 2025 } 2026 2027 strlcpy(w->name, typestr, sizeof(w->name)); 2028 2029 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2030 hdac_command(sc, 2031 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2032 cad); 2033 DELAY(1000); 2034 } 2035 2036 hdac_widget_connection_parse(w); 2037 2038 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2039 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2040 w->param.outamp_cap = 2041 hdac_command(sc, 2042 HDA_CMD_GET_PARAMETER(cad, nid, 2043 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2044 else 2045 w->param.outamp_cap = 2046 w->devinfo->function.audio.outamp_cap; 2047 } else 2048 w->param.outamp_cap = 0; 2049 2050 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2051 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2052 w->param.inamp_cap = 2053 hdac_command(sc, 2054 HDA_CMD_GET_PARAMETER(cad, nid, 2055 HDA_PARAM_INPUT_AMP_CAP), cad); 2056 else 2057 w->param.inamp_cap = 2058 w->devinfo->function.audio.inamp_cap; 2059 } else 2060 w->param.inamp_cap = 0; 2061 2062 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2063 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2064 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2065 cap = hdac_command(sc, 2066 HDA_CMD_GET_PARAMETER(cad, nid, 2067 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2068 w->param.supp_stream_formats = (cap != 0) ? cap : 2069 w->devinfo->function.audio.supp_stream_formats; 2070 cap = hdac_command(sc, 2071 HDA_CMD_GET_PARAMETER(cad, nid, 2072 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2073 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2074 w->devinfo->function.audio.supp_pcm_size_rate; 2075 } else { 2076 w->param.supp_stream_formats = 2077 w->devinfo->function.audio.supp_stream_formats; 2078 w->param.supp_pcm_size_rate = 2079 w->devinfo->function.audio.supp_pcm_size_rate; 2080 } 2081 } else { 2082 w->param.supp_stream_formats = 0; 2083 w->param.supp_pcm_size_rate = 0; 2084 } 2085 2086 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2087 hdac_widget_pin_parse(w); 2088 } 2089 2090 static struct hdac_widget * 2091 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2092 { 2093 if (devinfo == NULL || devinfo->widget == NULL || 2094 nid < devinfo->startnode || nid >= devinfo->endnode) 2095 return (NULL); 2096 return (&devinfo->widget[nid - devinfo->startnode]); 2097 } 2098 2099 static __inline int 2100 hda_poll_channel(struct hdac_chan *ch) 2101 { 2102 uint32_t sz, delta; 2103 volatile uint32_t ptr; 2104 2105 if (ch->active == 0) 2106 return (0); 2107 2108 sz = ch->blksz * ch->blkcnt; 2109 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 2110 ch->ptr = ptr; 2111 ptr %= sz; 2112 ptr &= ~(ch->blksz - 1); 2113 delta = (sz + ptr - ch->prevptr) % sz; 2114 2115 if (delta < ch->blksz) 2116 return (0); 2117 2118 ch->prevptr = ptr; 2119 2120 return (1); 2121 } 2122 2123 #define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2124 2125 static void 2126 hda_poll_callback(void *arg) 2127 { 2128 struct hdac_softc *sc = arg; 2129 uint32_t trigger = 0; 2130 2131 if (sc == NULL) 2132 return; 2133 2134 hdac_lock(sc); 2135 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2136 hdac_unlock(sc); 2137 return; 2138 } 2139 2140 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2141 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2142 2143 /* XXX */ 2144 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2145 hda_poll_callback, sc); 2146 2147 hdac_unlock(sc); 2148 2149 if (trigger & 1) 2150 chn_intr(sc->play.c); 2151 if (trigger & 2) 2152 chn_intr(sc->rec.c); 2153 } 2154 2155 static int 2156 hdac_rirb_flush(struct hdac_softc *sc) 2157 { 2158 struct hdac_rirb *rirb_base, *rirb; 2159 struct hdac_codec *codec; 2160 struct hdac_command_list *commands; 2161 nid_t cad; 2162 uint32_t resp; 2163 uint8_t rirbwp; 2164 int ret = 0; 2165 2166 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2167 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2168 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2169 BUS_DMASYNC_POSTREAD); 2170 2171 while (sc->rirb_rp != rirbwp) { 2172 sc->rirb_rp++; 2173 sc->rirb_rp %= sc->rirb_size; 2174 rirb = &rirb_base[sc->rirb_rp]; 2175 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2176 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2177 sc->codecs[cad] == NULL) 2178 continue; 2179 resp = rirb->response; 2180 codec = sc->codecs[cad]; 2181 commands = codec->commands; 2182 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2183 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2184 ((resp >> 26) & 0xffff); 2185 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2186 } else if (commands != NULL && commands->num_commands > 0 && 2187 codec->responses_received < commands->num_commands) 2188 commands->responses[codec->responses_received++] = 2189 resp; 2190 ret++; 2191 } 2192 2193 return (ret); 2194 } 2195 2196 static int 2197 hdac_unsolq_flush(struct hdac_softc *sc) 2198 { 2199 nid_t cad; 2200 uint32_t tag; 2201 int ret = 0; 2202 2203 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2204 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2205 while (sc->unsolq_rp != sc->unsolq_wp) { 2206 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2207 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2208 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2209 hdac_unsolicited_handler(sc->codecs[cad], tag); 2210 ret++; 2211 } 2212 sc->unsolq_st = HDAC_UNSOLQ_READY; 2213 } 2214 2215 return (ret); 2216 } 2217 2218 static void 2219 hdac_poll_callback(void *arg) 2220 { 2221 struct hdac_softc *sc = arg; 2222 if (sc == NULL) 2223 return; 2224 2225 hdac_lock(sc); 2226 if (sc->polling == 0) { 2227 hdac_unlock(sc); 2228 return; 2229 } 2230 hdac_rirb_flush(sc); 2231 hdac_unsolq_flush(sc); 2232 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2233 hdac_poll_callback, sc); 2234 hdac_unlock(sc); 2235 } 2236 2237 static void 2238 hdac_stream_stop(struct hdac_chan *ch) 2239 { 2240 struct hdac_softc *sc = ch->devinfo->codec->sc; 2241 uint32_t ctl; 2242 2243 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2244 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2245 HDAC_SDCTL_RUN); 2246 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2247 2248 ch->active = 0; 2249 2250 if (sc->polling != 0) { 2251 int pollticks; 2252 2253 if (hda_chan_active(sc) == 0) { 2254 callout_stop(&sc->poll_hda); 2255 sc->poll_ticks = 1; 2256 } else { 2257 if (sc->play.active != 0) 2258 ch = &sc->play; 2259 else 2260 ch = &sc->rec; 2261 pollticks = ((uint64_t)hz * ch->blksz) / 2262 ((uint64_t)sndbuf_getbps(ch->b) * 2263 sndbuf_getspd(ch->b)); 2264 pollticks >>= 2; 2265 if (pollticks > hz) 2266 pollticks = hz; 2267 if (pollticks < 1) { 2268 HDA_BOOTVERBOSE( 2269 device_printf(sc->dev, 2270 "%s: pollticks=%d < 1 !\n", 2271 __func__, pollticks); 2272 ); 2273 pollticks = 1; 2274 } 2275 if (pollticks > sc->poll_ticks) { 2276 HDA_BOOTVERBOSE( 2277 device_printf(sc->dev, 2278 "%s: pollticks %d -> %d\n", 2279 __func__, sc->poll_ticks, 2280 pollticks); 2281 ); 2282 sc->poll_ticks = pollticks; 2283 callout_reset(&sc->poll_hda, 1, 2284 hda_poll_callback, sc); 2285 } 2286 } 2287 } else { 2288 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2289 ctl &= ~(1 << (ch->off >> 5)); 2290 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2291 } 2292 } 2293 2294 static void 2295 hdac_stream_start(struct hdac_chan *ch) 2296 { 2297 struct hdac_softc *sc = ch->devinfo->codec->sc; 2298 uint32_t ctl; 2299 2300 if (sc->polling != 0) { 2301 int pollticks; 2302 2303 pollticks = ((uint64_t)hz * ch->blksz) / 2304 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2305 pollticks >>= 2; 2306 if (pollticks > hz) 2307 pollticks = hz; 2308 if (pollticks < 1) { 2309 HDA_BOOTVERBOSE( 2310 device_printf(sc->dev, 2311 "%s: pollticks=%d < 1 !\n", 2312 __func__, pollticks); 2313 ); 2314 pollticks = 1; 2315 } 2316 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2317 HDA_BOOTVERBOSE( 2318 if (hda_chan_active(sc) == 0) { 2319 device_printf(sc->dev, 2320 "%s: pollticks=%d\n", 2321 __func__, pollticks); 2322 } else { 2323 device_printf(sc->dev, 2324 "%s: pollticks %d -> %d\n", 2325 __func__, sc->poll_ticks, 2326 pollticks); 2327 } 2328 ); 2329 sc->poll_ticks = pollticks; 2330 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2331 sc); 2332 } 2333 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2334 ctl |= HDAC_SDCTL_RUN; 2335 } else { 2336 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2337 ctl |= 1 << (ch->off >> 5); 2338 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2339 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2340 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2341 HDAC_SDCTL_RUN; 2342 } 2343 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2344 2345 ch->active = 1; 2346 } 2347 2348 static void 2349 hdac_stream_reset(struct hdac_chan *ch) 2350 { 2351 struct hdac_softc *sc = ch->devinfo->codec->sc; 2352 int timeout = 1000; 2353 int to = timeout; 2354 uint32_t ctl; 2355 2356 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2357 ctl |= HDAC_SDCTL_SRST; 2358 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2359 do { 2360 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2361 if (ctl & HDAC_SDCTL_SRST) 2362 break; 2363 DELAY(10); 2364 } while (--to); 2365 if (!(ctl & HDAC_SDCTL_SRST)) { 2366 device_printf(sc->dev, "timeout in reset\n"); 2367 } 2368 ctl &= ~HDAC_SDCTL_SRST; 2369 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2370 to = timeout; 2371 do { 2372 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2373 if (!(ctl & HDAC_SDCTL_SRST)) 2374 break; 2375 DELAY(10); 2376 } while (--to); 2377 if (ctl & HDAC_SDCTL_SRST) 2378 device_printf(sc->dev, "can't reset!\n"); 2379 } 2380 2381 static void 2382 hdac_stream_setid(struct hdac_chan *ch) 2383 { 2384 struct hdac_softc *sc = ch->devinfo->codec->sc; 2385 uint32_t ctl; 2386 2387 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2388 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2389 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2390 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2391 } 2392 2393 static void 2394 hdac_bdl_setup(struct hdac_chan *ch) 2395 { 2396 struct hdac_softc *sc = ch->devinfo->codec->sc; 2397 struct hdac_bdle *bdle; 2398 uint64_t addr; 2399 uint32_t blksz, blkcnt; 2400 int i; 2401 2402 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2403 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2404 2405 if (sc->polling != 0) { 2406 blksz = ch->blksz * ch->blkcnt; 2407 blkcnt = 1; 2408 } else { 2409 blksz = ch->blksz; 2410 blkcnt = ch->blkcnt; 2411 } 2412 2413 for (i = 0; i < blkcnt; i++, bdle++) { 2414 bdle->addrl = (uint32_t)addr; 2415 bdle->addrh = (uint32_t)(addr >> 32); 2416 bdle->len = blksz; 2417 bdle->ioc = 1 ^ sc->polling; 2418 addr += blksz; 2419 } 2420 2421 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2422 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2423 addr = ch->bdl_dma.dma_paddr; 2424 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2425 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2426 } 2427 2428 static int 2429 hdac_bdl_alloc(struct hdac_chan *ch) 2430 { 2431 struct hdac_softc *sc = ch->devinfo->codec->sc; 2432 int rc; 2433 2434 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2435 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2436 if (rc) { 2437 device_printf(sc->dev, "can't alloc bdl\n"); 2438 return (rc); 2439 } 2440 2441 return (0); 2442 } 2443 2444 static void 2445 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2446 int index, int lmute, int rmute, 2447 int left, int right, int dir) 2448 { 2449 uint16_t v = 0; 2450 2451 if (sc == NULL) 2452 return; 2453 2454 if (left != right || lmute != rmute) { 2455 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2456 (lmute << 7) | left; 2457 hdac_command(sc, 2458 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2459 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2460 (rmute << 7) | right; 2461 } else 2462 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2463 (lmute << 7) | left; 2464 2465 hdac_command(sc, 2466 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2467 } 2468 2469 static void 2470 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2471 int left, int right) 2472 { 2473 struct hdac_softc *sc; 2474 nid_t nid, cad; 2475 int lmute, rmute; 2476 2477 if (ctl == NULL || ctl->widget == NULL || 2478 ctl->widget->devinfo == NULL || 2479 ctl->widget->devinfo->codec == NULL || 2480 ctl->widget->devinfo->codec->sc == NULL) 2481 return; 2482 2483 sc = ctl->widget->devinfo->codec->sc; 2484 cad = ctl->widget->devinfo->codec->cad; 2485 nid = ctl->widget->nid; 2486 2487 if (mute == HDA_AMP_MUTE_DEFAULT) { 2488 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2489 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2490 } else { 2491 lmute = HDA_AMP_LEFT_MUTED(mute); 2492 rmute = HDA_AMP_RIGHT_MUTED(mute); 2493 } 2494 2495 if (ctl->dir & HDA_CTL_OUT) 2496 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2497 lmute, rmute, left, right, 0); 2498 if (ctl->dir & HDA_CTL_IN) 2499 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2500 lmute, rmute, left, right, 1); 2501 ctl->left = left; 2502 ctl->right = right; 2503 } 2504 2505 static void 2506 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2507 { 2508 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2509 return; 2510 hdac_command(w->devinfo->codec->sc, 2511 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2512 w->nid, index), w->devinfo->codec->cad); 2513 w->selconn = index; 2514 } 2515 2516 2517 /**************************************************************************** 2518 * uint32_t hdac_command_sendone_internal 2519 * 2520 * Wrapper function that sends only one command to a given codec 2521 ****************************************************************************/ 2522 static uint32_t 2523 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2524 { 2525 struct hdac_command_list cl; 2526 uint32_t response = HDAC_INVALID; 2527 2528 if (!hdac_lockowned(sc)) 2529 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2530 cl.num_commands = 1; 2531 cl.verbs = &verb; 2532 cl.responses = &response; 2533 2534 hdac_command_send_internal(sc, &cl, cad); 2535 2536 return (response); 2537 } 2538 2539 /**************************************************************************** 2540 * hdac_command_send_internal 2541 * 2542 * Send a command list to the codec via the corb. We queue as much verbs as 2543 * we can and msleep on the codec. When the interrupt get the responses 2544 * back from the rirb, it will wake us up so we can queue the remaining verbs 2545 * if any. 2546 ****************************************************************************/ 2547 static void 2548 hdac_command_send_internal(struct hdac_softc *sc, 2549 struct hdac_command_list *commands, nid_t cad) 2550 { 2551 struct hdac_codec *codec; 2552 int corbrp; 2553 uint32_t *corb; 2554 int timeout; 2555 int retry = 10; 2556 struct hdac_rirb *rirb_base; 2557 2558 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2559 commands->num_commands < 1) 2560 return; 2561 2562 codec = sc->codecs[cad]; 2563 codec->commands = commands; 2564 codec->responses_received = 0; 2565 codec->verbs_sent = 0; 2566 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2567 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2568 2569 do { 2570 if (codec->verbs_sent != commands->num_commands) { 2571 /* Queue as many verbs as possible */ 2572 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2573 bus_dmamap_sync(sc->corb_dma.dma_tag, 2574 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2575 while (codec->verbs_sent != commands->num_commands && 2576 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2577 sc->corb_wp++; 2578 sc->corb_wp %= sc->corb_size; 2579 corb[sc->corb_wp] = 2580 commands->verbs[codec->verbs_sent++]; 2581 } 2582 2583 /* Send the verbs to the codecs */ 2584 bus_dmamap_sync(sc->corb_dma.dma_tag, 2585 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2586 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2587 } 2588 2589 timeout = 1000; 2590 while (hdac_rirb_flush(sc) == 0 && --timeout) 2591 DELAY(10); 2592 } while ((codec->verbs_sent != commands->num_commands || 2593 codec->responses_received != commands->num_commands) && --retry); 2594 2595 if (retry == 0) 2596 device_printf(sc->dev, 2597 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2598 __func__, commands->num_commands, codec->verbs_sent, 2599 codec->responses_received); 2600 2601 codec->commands = NULL; 2602 codec->responses_received = 0; 2603 codec->verbs_sent = 0; 2604 2605 hdac_unsolq_flush(sc); 2606 } 2607 2608 2609 /**************************************************************************** 2610 * Device Methods 2611 ****************************************************************************/ 2612 2613 /**************************************************************************** 2614 * int hdac_probe(device_t) 2615 * 2616 * Probe for the presence of an hdac. If none is found, check for a generic 2617 * match using the subclass of the device. 2618 ****************************************************************************/ 2619 static int 2620 hdac_probe(device_t dev) 2621 { 2622 int i, result; 2623 uint32_t model; 2624 uint16_t class, subclass; 2625 char desc[64]; 2626 2627 model = (uint32_t)pci_get_device(dev) << 16; 2628 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2629 class = pci_get_class(dev); 2630 subclass = pci_get_subclass(dev); 2631 2632 bzero(desc, sizeof(desc)); 2633 result = ENXIO; 2634 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2635 if (hdac_devices[i].model == model) { 2636 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2637 result = BUS_PROBE_DEFAULT; 2638 break; 2639 } 2640 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2641 class == PCIC_MULTIMEDIA && 2642 subclass == PCIS_MULTIMEDIA_HDA) { 2643 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2644 result = BUS_PROBE_GENERIC; 2645 break; 2646 } 2647 } 2648 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2649 subclass == PCIS_MULTIMEDIA_HDA) { 2650 strlcpy(desc, "Generic", sizeof(desc)); 2651 result = BUS_PROBE_GENERIC; 2652 } 2653 if (result != ENXIO) { 2654 strlcat(desc, " High Definition Audio Controller", 2655 sizeof(desc)); 2656 device_set_desc_copy(dev, desc); 2657 } 2658 2659 return (result); 2660 } 2661 2662 static int 2663 hdac_channel_free(kobj_t obj, void *data) 2664 { 2665 struct hdac_chan *ch = data; 2666 2667 if (ch != NULL && ch->b != NULL && ch->b->buf != NULL) 2668 hdac_dma_attr((vm_offset_t)ch->b->buf, sndbuf_getmaxsize(ch->b), 2669 HDAC_DMA_WRITEBACK); 2670 2671 return (1); 2672 } 2673 2674 static void * 2675 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2676 struct pcm_channel *c, int dir) 2677 { 2678 struct hdac_devinfo *devinfo = data; 2679 struct hdac_softc *sc = devinfo->codec->sc; 2680 struct hdac_chan *ch; 2681 2682 hdac_lock(sc); 2683 if (dir == PCMDIR_PLAY) { 2684 ch = &sc->play; 2685 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2686 ch->dir = PCMDIR_PLAY; 2687 ch->sid = ++sc->streamcnt; 2688 devinfo->function.audio.playcnt++; 2689 } else { 2690 ch = &sc->rec; 2691 ch->off = devinfo->function.audio.reccnt << 5; 2692 ch->dir = PCMDIR_REC; 2693 ch->sid = ++sc->streamcnt; 2694 devinfo->function.audio.reccnt++; 2695 } 2696 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2697 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2698 ch->pcmrates[0] = 48000; 2699 ch->pcmrates[1] = 0; 2700 } 2701 ch->b = b; 2702 ch->c = c; 2703 ch->devinfo = devinfo; 2704 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2705 ch->blkcnt = sc->chan_blkcnt; 2706 hdac_unlock(sc); 2707 2708 if (hdac_bdl_alloc(ch) != 0) { 2709 ch->blkcnt = 0; 2710 return (NULL); 2711 } 2712 2713 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2714 return (NULL); 2715 2716 hdac_dma_attr((vm_offset_t)ch->b->buf, sndbuf_getmaxsize(ch->b), 2717 HDAC_DMA_UNCACHEABLE); 2718 2719 return (ch); 2720 } 2721 2722 static int 2723 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2724 { 2725 struct hdac_chan *ch = data; 2726 int i; 2727 2728 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2729 if (format == ch->caps.fmtlist[i]) { 2730 ch->fmt = format; 2731 return (0); 2732 } 2733 } 2734 2735 return (EINVAL); 2736 } 2737 2738 static int 2739 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2740 { 2741 struct hdac_chan *ch = data; 2742 uint32_t spd = 0, threshold; 2743 int i; 2744 2745 for (i = 0; ch->pcmrates[i] != 0; i++) { 2746 spd = ch->pcmrates[i]; 2747 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2748 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2749 if (speed < threshold) 2750 break; 2751 } 2752 2753 if (spd == 0) /* impossible */ 2754 ch->spd = 48000; 2755 else 2756 ch->spd = spd; 2757 2758 return (ch->spd); 2759 } 2760 2761 static void 2762 hdac_stream_setup(struct hdac_chan *ch) 2763 { 2764 struct hdac_softc *sc = ch->devinfo->codec->sc; 2765 int i; 2766 nid_t cad = ch->devinfo->codec->cad; 2767 uint16_t fmt; 2768 2769 fmt = 0; 2770 if (ch->fmt & AFMT_S16_LE) 2771 fmt |= ch->bit16 << 4; 2772 else if (ch->fmt & AFMT_S32_LE) 2773 fmt |= ch->bit32 << 4; 2774 else 2775 fmt |= 1 << 4; 2776 2777 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2778 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2779 fmt |= hda_rate_tab[i].base; 2780 fmt |= hda_rate_tab[i].mul; 2781 fmt |= hda_rate_tab[i].div; 2782 break; 2783 } 2784 } 2785 2786 if (ch->fmt & AFMT_STEREO) 2787 fmt |= 1; 2788 2789 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2790 2791 for (i = 0; ch->io[i] != -1; i++) { 2792 HDA_BOOTVERBOSE( 2793 device_printf(sc->dev, 2794 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2795 "fmt=0x%08x\n", 2796 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2797 ch->io[i], fmt); 2798 ); 2799 hdac_command(sc, 2800 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2801 hdac_command(sc, 2802 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2803 ch->sid << 4), cad); 2804 } 2805 } 2806 2807 static int 2808 hdac_channel_setfragments(kobj_t obj, void *data, 2809 uint32_t blksz, uint32_t blkcnt) 2810 { 2811 struct hdac_chan *ch = data; 2812 struct hdac_softc *sc = ch->devinfo->codec->sc; 2813 2814 blksz &= HDA_BLK_ALIGN; 2815 2816 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 2817 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 2818 if (blksz < HDA_BLK_MIN) 2819 blksz = HDA_BLK_MIN; 2820 if (blkcnt > HDA_BDL_MAX) 2821 blkcnt = HDA_BDL_MAX; 2822 if (blkcnt < HDA_BDL_MIN) 2823 blkcnt = HDA_BDL_MIN; 2824 2825 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 2826 if ((blkcnt >> 1) >= HDA_BDL_MIN) 2827 blkcnt >>= 1; 2828 else if ((blksz >> 1) >= HDA_BLK_MIN) 2829 blksz >>= 1; 2830 else 2831 break; 2832 } 2833 2834 if ((sndbuf_getblksz(ch->b) != blksz || 2835 sndbuf_getblkcnt(ch->b) != blkcnt) && 2836 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 2837 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2838 __func__, blksz, blkcnt); 2839 2840 ch->blksz = sndbuf_getblksz(ch->b); 2841 ch->blkcnt = sndbuf_getblkcnt(ch->b); 2842 2843 return (1); 2844 } 2845 2846 static int 2847 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2848 { 2849 struct hdac_chan *ch = data; 2850 struct hdac_softc *sc = ch->devinfo->codec->sc; 2851 2852 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 2853 2854 return (ch->blksz); 2855 } 2856 2857 static void 2858 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2859 { 2860 struct hdac_devinfo *devinfo = ch->devinfo; 2861 nid_t cad = devinfo->codec->cad; 2862 int i; 2863 2864 hdac_stream_stop(ch); 2865 2866 for (i = 0; ch->io[i] != -1; i++) { 2867 hdac_command(sc, 2868 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2869 0), cad); 2870 } 2871 } 2872 2873 static void 2874 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2875 { 2876 ch->ptr = 0; 2877 ch->prevptr = 0; 2878 hdac_stream_stop(ch); 2879 hdac_stream_reset(ch); 2880 hdac_bdl_setup(ch); 2881 hdac_stream_setid(ch); 2882 hdac_stream_setup(ch); 2883 hdac_stream_start(ch); 2884 } 2885 2886 static int 2887 hdac_channel_trigger(kobj_t obj, void *data, int go) 2888 { 2889 struct hdac_chan *ch = data; 2890 struct hdac_softc *sc = ch->devinfo->codec->sc; 2891 2892 hdac_lock(sc); 2893 switch (go) { 2894 case PCMTRIG_START: 2895 hdac_channel_start(sc, ch); 2896 break; 2897 case PCMTRIG_STOP: 2898 case PCMTRIG_ABORT: 2899 hdac_channel_stop(sc, ch); 2900 break; 2901 default: 2902 break; 2903 } 2904 hdac_unlock(sc); 2905 2906 return (0); 2907 } 2908 2909 static int 2910 hdac_channel_getptr(kobj_t obj, void *data) 2911 { 2912 struct hdac_chan *ch = data; 2913 struct hdac_softc *sc = ch->devinfo->codec->sc; 2914 uint32_t ptr; 2915 2916 hdac_lock(sc); 2917 if (sc->polling != 0) 2918 ptr = ch->ptr; 2919 else 2920 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2921 hdac_unlock(sc); 2922 2923 /* 2924 * Round to available space and force 128 bytes aligment. 2925 */ 2926 ptr %= ch->blksz * ch->blkcnt; 2927 ptr &= HDA_BLK_ALIGN; 2928 2929 return (ptr); 2930 } 2931 2932 static struct pcmchan_caps * 2933 hdac_channel_getcaps(kobj_t obj, void *data) 2934 { 2935 return (&((struct hdac_chan *)data)->caps); 2936 } 2937 2938 static kobj_method_t hdac_channel_methods[] = { 2939 KOBJMETHOD(channel_init, hdac_channel_init), 2940 KOBJMETHOD(channel_free, hdac_channel_free), 2941 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2942 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2943 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2944 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 2945 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2946 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2947 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2948 { 0, 0 } 2949 }; 2950 CHANNEL_DECLARE(hdac_channel); 2951 2952 static int 2953 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2954 { 2955 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2956 struct hdac_softc *sc = devinfo->codec->sc; 2957 struct hdac_widget *w, *cw; 2958 struct hdac_audio_ctl *ctl; 2959 uint32_t mask, recmask, id; 2960 int i, j, softpcmvol; 2961 nid_t cad; 2962 2963 hdac_lock(sc); 2964 2965 mask = 0; 2966 recmask = 0; 2967 2968 id = hdac_codec_id(devinfo); 2969 cad = devinfo->codec->cad; 2970 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2971 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2972 sc->pci_subvendor) && 2973 hdac_hp_switch[i].id == id)) 2974 continue; 2975 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2976 if (w != NULL && w->enable != 0 2977 && w->type == 2978 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2979 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2980 hdac_command(sc, 2981 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2982 w->nid, 2983 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2984 HDAC_UNSOLTAG_EVENT_HP), cad); 2985 hdac_hp_switch_handler(devinfo); 2986 HDA_BOOTVERBOSE( 2987 device_printf(sc->dev, 2988 "HDA_DEBUG: Enabling headphone/speaker " 2989 "audio routing switching:\n"); 2990 device_printf(sc->dev, 2991 "HDA_DEBUG: \tindex=%d nid=%d " 2992 "pci_subvendor=0x%08x " 2993 "codec=0x%08x\n", 2994 i, w->nid, sc->pci_subvendor, id); 2995 ); 2996 } 2997 break; 2998 } 2999 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3000 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3001 sc->pci_subvendor) && 3002 hdac_eapd_switch[i].id == id)) 3003 continue; 3004 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3005 if (w == NULL || w->enable == 0) 3006 break; 3007 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3008 w->param.eapdbtl == HDAC_INVALID) 3009 break; 3010 mask |= SOUND_MASK_OGAIN; 3011 break; 3012 } 3013 3014 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3015 w = hdac_widget_get(devinfo, i); 3016 if (w == NULL || w->enable == 0) 3017 continue; 3018 mask |= w->ctlflags; 3019 if (!(w->pflags & HDA_ADC_RECSEL)) 3020 continue; 3021 for (j = 0; j < w->nconns; j++) { 3022 cw = hdac_widget_get(devinfo, w->conns[j]); 3023 if (cw == NULL || cw->enable == 0) 3024 continue; 3025 recmask |= cw->ctlflags; 3026 } 3027 } 3028 3029 if (!(mask & SOUND_MASK_PCM)) { 3030 softpcmvol = 1; 3031 mask |= SOUND_MASK_PCM; 3032 } else 3033 softpcmvol = (devinfo->function.audio.quirks & 3034 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3035 3036 i = 0; 3037 ctl = NULL; 3038 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3039 if (ctl->widget == NULL || ctl->enable == 0) 3040 continue; 3041 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3042 continue; 3043 if (ctl->step > 0) 3044 break; 3045 } 3046 3047 if (softpcmvol == 1 || ctl == NULL) { 3048 struct snddev_info *d = NULL; 3049 d = device_get_softc(sc->dev); 3050 if (d != NULL) { 3051 d->flags |= SD_F_SOFTPCMVOL; 3052 HDA_BOOTVERBOSE( 3053 device_printf(sc->dev, 3054 "HDA_DEBUG: %s Soft PCM volume\n", 3055 (softpcmvol == 1) ? 3056 "Forcing" : "Enabling"); 3057 ); 3058 } 3059 i = 0; 3060 /* 3061 * XXX Temporary quirk for STAC9220, until the parser 3062 * become smarter. 3063 */ 3064 if (id == HDA_CODEC_STAC9220) { 3065 mask |= SOUND_MASK_VOLUME; 3066 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3067 NULL) { 3068 if (ctl->widget == NULL || ctl->enable == 0) 3069 continue; 3070 if (ctl->widget->nid == 11 && ctl->index == 0) { 3071 ctl->ossmask = SOUND_MASK_VOLUME; 3072 ctl->ossval = 100 | (100 << 8); 3073 } else 3074 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3075 } 3076 } else if (id == HDA_CODEC_STAC9221) { 3077 mask |= SOUND_MASK_VOLUME; 3078 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3079 NULL) { 3080 if (ctl->widget == NULL) 3081 continue; 3082 if (ctl->widget->nid == 2 && ctl->index == 0) { 3083 ctl->enable = 1; 3084 ctl->ossmask = SOUND_MASK_VOLUME; 3085 ctl->ossval = 100 | (100 << 8); 3086 } else if (ctl->enable == 0) 3087 continue; 3088 else 3089 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3090 } 3091 } else { 3092 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3093 SOUND_MASK_PCM); 3094 if (!(mask & SOUND_MASK_VOLUME)) 3095 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3096 SOUND_MIXER_NONE); 3097 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3098 NULL) { 3099 if (ctl->widget == NULL || ctl->enable == 0) 3100 continue; 3101 if (!HDA_FLAG_MATCH(ctl->ossmask, 3102 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3103 continue; 3104 if (!(ctl->mute == 1 && ctl->step == 0)) 3105 ctl->enable = 0; 3106 } 3107 } 3108 } 3109 3110 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 3111 3112 mix_setrecdevs(m, recmask); 3113 mix_setdevs(m, mask); 3114 3115 hdac_unlock(sc); 3116 3117 return (0); 3118 } 3119 3120 static int 3121 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3122 unsigned left, unsigned right) 3123 { 3124 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3125 struct hdac_softc *sc = devinfo->codec->sc; 3126 struct hdac_widget *w; 3127 struct hdac_audio_ctl *ctl; 3128 uint32_t id, mute; 3129 int lvol, rvol, mlvol, mrvol; 3130 int i = 0; 3131 3132 hdac_lock(sc); 3133 if (dev == SOUND_MIXER_OGAIN) { 3134 uint32_t orig; 3135 /*if (left != right || !(left == 0 || left == 1)) { 3136 hdac_unlock(sc); 3137 return (-1); 3138 }*/ 3139 id = hdac_codec_id(devinfo); 3140 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3141 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3142 sc->pci_subvendor) && 3143 hdac_eapd_switch[i].id == id) 3144 break; 3145 } 3146 if (i >= HDAC_EAPD_SWITCH_LEN) { 3147 hdac_unlock(sc); 3148 return (-1); 3149 } 3150 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3151 if (w == NULL || 3152 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3153 w->param.eapdbtl == HDAC_INVALID) { 3154 hdac_unlock(sc); 3155 return (-1); 3156 } 3157 orig = w->param.eapdbtl; 3158 if (left == 0) 3159 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3160 else 3161 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3162 if (orig != w->param.eapdbtl) { 3163 uint32_t val; 3164 3165 if (hdac_eapd_switch[i].hp_switch != 0) 3166 hdac_hp_switch_handler(devinfo); 3167 val = w->param.eapdbtl; 3168 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3169 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3170 hdac_command(sc, 3171 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3172 w->nid, val), devinfo->codec->cad); 3173 } 3174 hdac_unlock(sc); 3175 return (left | (left << 8)); 3176 } 3177 if (dev == SOUND_MIXER_VOLUME) 3178 devinfo->function.audio.mvol = left | (right << 8); 3179 3180 mlvol = devinfo->function.audio.mvol & 0x7f; 3181 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3182 lvol = 0; 3183 rvol = 0; 3184 3185 i = 0; 3186 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3187 if (ctl->widget == NULL || ctl->enable == 0 || 3188 !(ctl->ossmask & (1 << dev))) 3189 continue; 3190 switch (dev) { 3191 case SOUND_MIXER_VOLUME: 3192 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3193 lvol = (lvol * ctl->step) / 100; 3194 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3195 rvol = (rvol * ctl->step) / 100; 3196 break; 3197 default: 3198 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3199 lvol = (left * mlvol) / 100; 3200 lvol = (lvol * ctl->step) / 100; 3201 rvol = (right * mrvol) / 100; 3202 rvol = (rvol * ctl->step) / 100; 3203 } else { 3204 lvol = (left * ctl->step) / 100; 3205 rvol = (right * ctl->step) / 100; 3206 } 3207 ctl->ossval = left | (right << 8); 3208 break; 3209 } 3210 mute = 0; 3211 if (ctl->step < 1) { 3212 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3213 (ctl->muted & HDA_AMP_MUTE_LEFT); 3214 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3215 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3216 } else { 3217 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3218 (ctl->muted & HDA_AMP_MUTE_LEFT); 3219 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3220 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3221 } 3222 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3223 } 3224 hdac_unlock(sc); 3225 3226 return (left | (right << 8)); 3227 } 3228 3229 static int 3230 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3231 { 3232 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3233 struct hdac_widget *w, *cw; 3234 struct hdac_softc *sc = devinfo->codec->sc; 3235 uint32_t ret = src, target; 3236 int i, j; 3237 3238 target = 0; 3239 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3240 if (src & (1 << i)) { 3241 target = 1 << i; 3242 break; 3243 } 3244 } 3245 3246 hdac_lock(sc); 3247 3248 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3249 w = hdac_widget_get(devinfo, i); 3250 if (w == NULL || w->enable == 0) 3251 continue; 3252 if (!(w->pflags & HDA_ADC_RECSEL)) 3253 continue; 3254 for (j = 0; j < w->nconns; j++) { 3255 cw = hdac_widget_get(devinfo, w->conns[j]); 3256 if (cw == NULL || cw->enable == 0) 3257 continue; 3258 if ((target == SOUND_MASK_VOLUME && 3259 cw->type != 3260 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3261 (target != SOUND_MASK_VOLUME && 3262 cw->type == 3263 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3264 continue; 3265 if (cw->ctlflags & target) { 3266 hdac_widget_connection_select(w, j); 3267 ret = target; 3268 j += w->nconns; 3269 } 3270 } 3271 } 3272 3273 hdac_unlock(sc); 3274 3275 return (ret); 3276 } 3277 3278 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3279 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3280 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3281 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3282 { 0, 0 } 3283 }; 3284 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3285 3286 /**************************************************************************** 3287 * int hdac_attach(device_t) 3288 * 3289 * Attach the device into the kernel. Interrupts usually won't be enabled 3290 * when this function is called. Setup everything that doesn't require 3291 * interrupts and defer probing of codecs until interrupts are enabled. 3292 ****************************************************************************/ 3293 static int 3294 hdac_attach(device_t dev) 3295 { 3296 struct hdac_softc *sc; 3297 int result; 3298 int i = 0; 3299 3300 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3301 if (sc == NULL) { 3302 device_printf(dev, "cannot allocate softc\n"); 3303 return (ENOMEM); 3304 } 3305 3306 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3307 sc->dev = dev; 3308 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3309 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3310 3311 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3312 /* Screw nx6325 - subdevice/subvendor swapped */ 3313 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3314 } 3315 3316 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3317 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3318 3319 sc->poll_ticks = 1; 3320 if (resource_int_value(device_get_name(sc->dev), 3321 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3322 sc->polling = 1; 3323 else 3324 sc->polling = 0; 3325 3326 sc->chan_size = pcm_getbuffersize(dev, 3327 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3328 3329 if (resource_int_value(device_get_name(sc->dev), 3330 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3331 i &= HDA_BLK_ALIGN; 3332 if (i < HDA_BLK_MIN) 3333 i = HDA_BLK_MIN; 3334 sc->chan_blkcnt = sc->chan_size / i; 3335 i = 0; 3336 while (sc->chan_blkcnt >> i) 3337 i++; 3338 sc->chan_blkcnt = 1 << (i - 1); 3339 if (sc->chan_blkcnt < HDA_BDL_MIN) 3340 sc->chan_blkcnt = HDA_BDL_MIN; 3341 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3342 sc->chan_blkcnt = HDA_BDL_MAX; 3343 } else 3344 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3345 3346 result = bus_dma_tag_create(NULL, /* parent */ 3347 HDAC_DMA_ALIGNMENT, /* alignment */ 3348 0, /* boundary */ 3349 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3350 BUS_SPACE_MAXADDR, /* highaddr */ 3351 NULL, /* filtfunc */ 3352 NULL, /* fistfuncarg */ 3353 sc->chan_size, /* maxsize */ 3354 1, /* nsegments */ 3355 sc->chan_size, /* maxsegsz */ 3356 0, /* flags */ 3357 NULL, /* lockfunc */ 3358 NULL, /* lockfuncarg */ 3359 &sc->chan_dmat); /* dmat */ 3360 if (result != 0) { 3361 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3362 __func__, result); 3363 snd_mtxfree(sc->lock); 3364 free(sc, M_DEVBUF); 3365 return (ENXIO); 3366 } 3367 3368 3369 sc->hdabus = NULL; 3370 for (i = 0; i < HDAC_CODEC_MAX; i++) 3371 sc->codecs[i] = NULL; 3372 3373 pci_enable_busmaster(dev); 3374 3375 /* Allocate resources */ 3376 result = hdac_mem_alloc(sc); 3377 if (result != 0) 3378 goto hdac_attach_fail; 3379 result = hdac_irq_alloc(sc); 3380 if (result != 0) 3381 goto hdac_attach_fail; 3382 3383 /* Get Capabilities */ 3384 result = hdac_get_capabilities(sc); 3385 if (result != 0) 3386 goto hdac_attach_fail; 3387 3388 /* Allocate CORB and RIRB dma memory */ 3389 result = hdac_dma_alloc(sc, &sc->corb_dma, 3390 sc->corb_size * sizeof(uint32_t)); 3391 if (result != 0) 3392 goto hdac_attach_fail; 3393 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3394 sc->rirb_size * sizeof(struct hdac_rirb)); 3395 if (result != 0) 3396 goto hdac_attach_fail; 3397 3398 /* Quiesce everything */ 3399 hdac_reset(sc); 3400 3401 /* Disable PCI-Express QOS */ 3402 pci_write_config(sc->dev, 0x44, 3403 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3404 3405 /* Initialize the CORB and RIRB */ 3406 hdac_corb_init(sc); 3407 hdac_rirb_init(sc); 3408 3409 /* Defer remaining of initialization until interrupts are enabled */ 3410 sc->intrhook.ich_func = hdac_attach2; 3411 sc->intrhook.ich_arg = (void *)sc; 3412 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3413 sc->intrhook.ich_func = NULL; 3414 hdac_attach2((void *)sc); 3415 } 3416 3417 return (0); 3418 3419 hdac_attach_fail: 3420 hdac_dma_free(&sc->rirb_dma); 3421 hdac_dma_free(&sc->corb_dma); 3422 hdac_irq_free(sc); 3423 hdac_mem_free(sc); 3424 snd_mtxfree(sc->lock); 3425 free(sc, M_DEVBUF); 3426 3427 return (ENXIO); 3428 } 3429 3430 static void 3431 hdac_audio_parse(struct hdac_devinfo *devinfo) 3432 { 3433 struct hdac_softc *sc = devinfo->codec->sc; 3434 struct hdac_widget *w; 3435 uint32_t res; 3436 int i; 3437 nid_t cad, nid; 3438 3439 cad = devinfo->codec->cad; 3440 nid = devinfo->nid; 3441 3442 hdac_command(sc, 3443 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3444 3445 DELAY(100); 3446 3447 res = hdac_command(sc, 3448 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3449 3450 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3451 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3452 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3453 3454 HDA_BOOTVERBOSE( 3455 device_printf(sc->dev, " Vendor: 0x%08x\n", 3456 devinfo->vendor_id); 3457 device_printf(sc->dev, " Device: 0x%08x\n", 3458 devinfo->device_id); 3459 device_printf(sc->dev, " Revision: 0x%08x\n", 3460 devinfo->revision_id); 3461 device_printf(sc->dev, " Stepping: 0x%08x\n", 3462 devinfo->stepping_id); 3463 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3464 sc->pci_subvendor); 3465 device_printf(sc->dev, " Nodes: start=%d " 3466 "endnode=%d total=%d\n", 3467 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3468 ); 3469 3470 res = hdac_command(sc, 3471 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3472 cad); 3473 devinfo->function.audio.supp_stream_formats = res; 3474 3475 res = hdac_command(sc, 3476 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3477 cad); 3478 devinfo->function.audio.supp_pcm_size_rate = res; 3479 3480 res = hdac_command(sc, 3481 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3482 cad); 3483 devinfo->function.audio.outamp_cap = res; 3484 3485 res = hdac_command(sc, 3486 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3487 cad); 3488 devinfo->function.audio.inamp_cap = res; 3489 3490 if (devinfo->nodecnt > 0) { 3491 hdac_unlock(sc); 3492 devinfo->widget = (struct hdac_widget *)malloc( 3493 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3494 M_NOWAIT | M_ZERO); 3495 hdac_lock(sc); 3496 } else 3497 devinfo->widget = NULL; 3498 3499 if (devinfo->widget == NULL) { 3500 device_printf(sc->dev, "unable to allocate widgets!\n"); 3501 devinfo->endnode = devinfo->startnode; 3502 devinfo->nodecnt = 0; 3503 return; 3504 } 3505 3506 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3507 w = hdac_widget_get(devinfo, i); 3508 if (w == NULL) 3509 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3510 else { 3511 w->devinfo = devinfo; 3512 w->nid = i; 3513 w->enable = 1; 3514 w->selconn = -1; 3515 w->pflags = 0; 3516 w->ctlflags = 0; 3517 w->param.eapdbtl = HDAC_INVALID; 3518 hdac_widget_parse(w); 3519 } 3520 } 3521 } 3522 3523 static void 3524 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3525 { 3526 struct hdac_softc *sc = devinfo->codec->sc; 3527 struct hdac_audio_ctl *ctls; 3528 struct hdac_widget *w, *cw; 3529 int i, j, cnt, max, ocap, icap; 3530 int mute, offset, step, size; 3531 3532 /* XXX This is redundant */ 3533 max = 0; 3534 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3535 w = hdac_widget_get(devinfo, i); 3536 if (w == NULL || w->enable == 0) 3537 continue; 3538 if (w->param.outamp_cap != 0) 3539 max++; 3540 if (w->param.inamp_cap != 0) { 3541 switch (w->type) { 3542 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3543 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3544 for (j = 0; j < w->nconns; j++) { 3545 cw = hdac_widget_get(devinfo, 3546 w->conns[j]); 3547 if (cw == NULL || cw->enable == 0) 3548 continue; 3549 max++; 3550 } 3551 break; 3552 default: 3553 max++; 3554 break; 3555 } 3556 } 3557 } 3558 3559 devinfo->function.audio.ctlcnt = max; 3560 3561 if (max < 1) 3562 return; 3563 3564 hdac_unlock(sc); 3565 ctls = (struct hdac_audio_ctl *)malloc( 3566 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3567 hdac_lock(sc); 3568 3569 if (ctls == NULL) { 3570 /* Blekh! */ 3571 device_printf(sc->dev, "unable to allocate ctls!\n"); 3572 devinfo->function.audio.ctlcnt = 0; 3573 return; 3574 } 3575 3576 cnt = 0; 3577 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3578 if (cnt >= max) { 3579 device_printf(sc->dev, "%s: Ctl overflow!\n", 3580 __func__); 3581 break; 3582 } 3583 w = hdac_widget_get(devinfo, i); 3584 if (w == NULL || w->enable == 0) 3585 continue; 3586 ocap = w->param.outamp_cap; 3587 icap = w->param.inamp_cap; 3588 if (ocap != 0) { 3589 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3590 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3591 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3592 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3593 /*if (offset > step) { 3594 HDA_BOOTVERBOSE( 3595 device_printf(sc->dev, 3596 "HDA_DEBUG: BUGGY outamp: nid=%d " 3597 "[offset=%d > step=%d]\n", 3598 w->nid, offset, step); 3599 ); 3600 offset = step; 3601 }*/ 3602 ctls[cnt].enable = 1; 3603 ctls[cnt].widget = w; 3604 ctls[cnt].mute = mute; 3605 ctls[cnt].step = step; 3606 ctls[cnt].size = size; 3607 ctls[cnt].offset = offset; 3608 ctls[cnt].left = offset; 3609 ctls[cnt].right = offset; 3610 ctls[cnt++].dir = HDA_CTL_OUT; 3611 } 3612 3613 if (icap != 0) { 3614 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3615 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3616 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3617 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3618 /*if (offset > step) { 3619 HDA_BOOTVERBOSE( 3620 device_printf(sc->dev, 3621 "HDA_DEBUG: BUGGY inamp: nid=%d " 3622 "[offset=%d > step=%d]\n", 3623 w->nid, offset, step); 3624 ); 3625 offset = step; 3626 }*/ 3627 switch (w->type) { 3628 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3629 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3630 for (j = 0; j < w->nconns; j++) { 3631 if (cnt >= max) { 3632 device_printf(sc->dev, 3633 "%s: Ctl overflow!\n", 3634 __func__); 3635 break; 3636 } 3637 cw = hdac_widget_get(devinfo, 3638 w->conns[j]); 3639 if (cw == NULL || cw->enable == 0) 3640 continue; 3641 ctls[cnt].enable = 1; 3642 ctls[cnt].widget = w; 3643 ctls[cnt].childwidget = cw; 3644 ctls[cnt].index = j; 3645 ctls[cnt].mute = mute; 3646 ctls[cnt].step = step; 3647 ctls[cnt].size = size; 3648 ctls[cnt].offset = offset; 3649 ctls[cnt].left = offset; 3650 ctls[cnt].right = offset; 3651 ctls[cnt++].dir = HDA_CTL_IN; 3652 } 3653 break; 3654 default: 3655 if (cnt >= max) { 3656 device_printf(sc->dev, 3657 "%s: Ctl overflow!\n", 3658 __func__); 3659 break; 3660 } 3661 ctls[cnt].enable = 1; 3662 ctls[cnt].widget = w; 3663 ctls[cnt].mute = mute; 3664 ctls[cnt].step = step; 3665 ctls[cnt].size = size; 3666 ctls[cnt].offset = offset; 3667 ctls[cnt].left = offset; 3668 ctls[cnt].right = offset; 3669 ctls[cnt++].dir = HDA_CTL_IN; 3670 break; 3671 } 3672 } 3673 } 3674 3675 devinfo->function.audio.ctl = ctls; 3676 } 3677 3678 static const struct { 3679 uint32_t model; 3680 uint32_t id; 3681 uint32_t set, unset; 3682 } hdac_quirks[] = { 3683 /* 3684 * XXX Force stereo quirk. Monoural recording / playback 3685 * on few codecs (especially ALC880) seems broken or 3686 * perhaps unsupported. 3687 */ 3688 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3689 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3690 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3691 HDA_QUIRK_GPIO0, 0 }, 3692 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3693 HDA_QUIRK_GPIO0, 0 }, 3694 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3695 HDA_QUIRK_GPIO0, 0 }, 3696 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 3697 HDA_QUIRK_GPIO0, 0 }, 3698 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3699 HDA_QUIRK_EAPDINV, 0 }, 3700 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3701 HDA_QUIRK_EAPDINV, 0 }, 3702 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3703 HDA_QUIRK_GPIO1, 0 }, 3704 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3705 HDA_QUIRK_EAPDINV, 0 }, 3706 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3707 HDA_QUIRK_EAPDINV, 0 }, 3708 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3709 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3710 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3711 0, HDA_QUIRK_FORCESTEREO }, 3712 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3713 HDA_QUIRK_SOFTPCMVOL, 0 } 3714 }; 3715 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3716 3717 static void 3718 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3719 { 3720 struct hdac_widget *w; 3721 struct hdac_audio_ctl *ctl; 3722 uint32_t id, subvendor; 3723 int i; 3724 3725 id = hdac_codec_id(devinfo); 3726 subvendor = devinfo->codec->sc->pci_subvendor; 3727 3728 /* 3729 * Quirks 3730 */ 3731 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3732 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3733 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3734 continue; 3735 if (hdac_quirks[i].set != 0) 3736 devinfo->function.audio.quirks |= 3737 hdac_quirks[i].set; 3738 if (hdac_quirks[i].unset != 0) 3739 devinfo->function.audio.quirks &= 3740 ~(hdac_quirks[i].unset); 3741 } 3742 3743 switch (id) { 3744 case HDA_CODEC_ALC260: 3745 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3746 w = hdac_widget_get(devinfo, i); 3747 if (w == NULL || w->enable == 0) 3748 continue; 3749 if (w->type != 3750 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3751 continue; 3752 if (w->nid != 5) 3753 w->enable = 0; 3754 } 3755 if (subvendor == HP_XW4300_SUBVENDOR) { 3756 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 3757 if (ctl != NULL && ctl->widget != NULL) { 3758 ctl->ossmask = SOUND_MASK_SPEAKER; 3759 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3760 } 3761 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 3762 if (ctl != NULL && ctl->widget != NULL) { 3763 ctl->ossmask = SOUND_MASK_SPEAKER; 3764 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3765 } 3766 } 3767 break; 3768 case HDA_CODEC_ALC861: 3769 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3770 if (ctl != NULL) 3771 ctl->muted = HDA_AMP_MUTE_ALL; 3772 break; 3773 case HDA_CODEC_ALC880: 3774 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3775 w = hdac_widget_get(devinfo, i); 3776 if (w == NULL || w->enable == 0) 3777 continue; 3778 if (w->type == 3779 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3780 w->nid != 9 && w->nid != 29) { 3781 w->enable = 0; 3782 } else if (w->type != 3783 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3784 w->nid == 29) { 3785 w->type = 3786 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3787 w->param.widget_cap &= 3788 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3789 w->param.widget_cap |= 3790 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3791 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3792 strlcpy(w->name, "beep widget", sizeof(w->name)); 3793 } 3794 } 3795 break; 3796 case HDA_CODEC_ALC883: 3797 /* 3798 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 3799 * Clear vref cap for jack connectivity. 3800 */ 3801 w = hdac_widget_get(devinfo, 24); 3802 if (w != NULL && w->enable != 0 && w->type == 3803 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3804 (w->wclass.pin.config & 3805 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3806 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3807 w->wclass.pin.cap &= ~( 3808 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3809 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3810 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3811 w = hdac_widget_get(devinfo, 25); 3812 if (w != NULL && w->enable != 0 && w->type == 3813 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3814 (w->wclass.pin.config & 3815 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3816 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3817 w->wclass.pin.cap &= ~( 3818 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3819 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3820 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3821 /* 3822 * nid: 26 = Line-in, leave it alone. 3823 */ 3824 break; 3825 case HDA_CODEC_AD1981HD: 3826 w = hdac_widget_get(devinfo, 11); 3827 if (w != NULL && w->enable != 0 && w->nconns > 3) 3828 w->selconn = 3; 3829 if (subvendor == IBM_M52_SUBVENDOR) { 3830 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3831 if (ctl != NULL) 3832 ctl->ossmask = SOUND_MASK_SPEAKER; 3833 } 3834 break; 3835 case HDA_CODEC_AD1986A: 3836 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3837 w = hdac_widget_get(devinfo, i); 3838 if (w == NULL || w->enable == 0) 3839 continue; 3840 if (w->type != 3841 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3842 continue; 3843 if (w->nid != 3) 3844 w->enable = 0; 3845 } 3846 break; 3847 case HDA_CODEC_STAC9221: 3848 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3849 w = hdac_widget_get(devinfo, i); 3850 if (w == NULL || w->enable == 0) 3851 continue; 3852 if (w->type != 3853 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3854 continue; 3855 if (w->nid != 2) 3856 w->enable = 0; 3857 } 3858 break; 3859 case HDA_CODEC_STAC9221D: 3860 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3861 w = hdac_widget_get(devinfo, i); 3862 if (w == NULL || w->enable == 0) 3863 continue; 3864 if (w->type == 3865 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3866 w->nid != 6) 3867 w->enable = 0; 3868 3869 } 3870 break; 3871 default: 3872 break; 3873 } 3874 } 3875 3876 static int 3877 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3878 { 3879 int *dev = &devinfo->function.audio.ossidx; 3880 3881 while (*dev < SOUND_MIXER_NRDEVICES) { 3882 switch (*dev) { 3883 case SOUND_MIXER_VOLUME: 3884 case SOUND_MIXER_BASS: 3885 case SOUND_MIXER_TREBLE: 3886 case SOUND_MIXER_PCM: 3887 case SOUND_MIXER_SPEAKER: 3888 case SOUND_MIXER_LINE: 3889 case SOUND_MIXER_MIC: 3890 case SOUND_MIXER_CD: 3891 case SOUND_MIXER_RECLEV: 3892 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3893 (*dev)++; 3894 break; 3895 default: 3896 return (*dev)++; 3897 break; 3898 } 3899 } 3900 3901 return (-1); 3902 } 3903 3904 static int 3905 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3906 { 3907 struct hdac_widget *w; 3908 int i, ret = 0; 3909 3910 if (depth > HDA_PARSE_MAXDEPTH) 3911 return (0); 3912 w = hdac_widget_get(devinfo, nid); 3913 if (w == NULL || w->enable == 0) 3914 return (0); 3915 switch (w->type) { 3916 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3917 w->pflags |= HDA_DAC_PATH; 3918 ret = 1; 3919 break; 3920 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3921 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3922 for (i = 0; i < w->nconns; i++) { 3923 if (hdac_widget_find_dac_path(devinfo, 3924 w->conns[i], depth + 1) != 0) { 3925 if (w->selconn == -1) 3926 w->selconn = i; 3927 ret = 1; 3928 w->pflags |= HDA_DAC_PATH; 3929 } 3930 } 3931 break; 3932 default: 3933 break; 3934 } 3935 return (ret); 3936 } 3937 3938 static int 3939 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3940 { 3941 struct hdac_widget *w; 3942 int i, conndev, ret = 0; 3943 3944 if (depth > HDA_PARSE_MAXDEPTH) 3945 return (0); 3946 w = hdac_widget_get(devinfo, nid); 3947 if (w == NULL || w->enable == 0) 3948 return (0); 3949 switch (w->type) { 3950 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3951 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3952 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3953 for (i = 0; i < w->nconns; i++) { 3954 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3955 depth + 1) != 0) { 3956 if (w->selconn == -1) 3957 w->selconn = i; 3958 w->pflags |= HDA_ADC_PATH; 3959 ret = 1; 3960 } 3961 } 3962 break; 3963 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3964 conndev = w->wclass.pin.config & 3965 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3966 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3967 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3968 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3969 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3970 w->pflags |= HDA_ADC_PATH; 3971 ret = 1; 3972 } 3973 break; 3974 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3975 if (w->pflags & HDA_DAC_PATH) { 3976 w->pflags |= HDA_ADC_PATH; 3977 ret = 1; 3978 } 3979 break;*/ 3980 default: 3981 break; 3982 } 3983 return (ret); 3984 } 3985 3986 static uint32_t 3987 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3988 nid_t nid, nid_t pnid, int index, int depth) 3989 { 3990 struct hdac_widget *w, *pw; 3991 struct hdac_audio_ctl *ctl; 3992 uint32_t fl = 0; 3993 int i, ossdev, conndev, strategy; 3994 3995 if (depth > HDA_PARSE_MAXDEPTH) 3996 return (0); 3997 3998 w = hdac_widget_get(devinfo, nid); 3999 if (w == NULL || w->enable == 0) 4000 return (0); 4001 4002 pw = hdac_widget_get(devinfo, pnid); 4003 strategy = devinfo->function.audio.parsing_strategy; 4004 4005 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4006 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4007 for (i = 0; i < w->nconns; i++) { 4008 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4009 w->nid, i, depth + 1); 4010 } 4011 w->ctlflags |= fl; 4012 return (fl); 4013 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4014 (w->pflags & HDA_DAC_PATH)) { 4015 i = 0; 4016 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4017 if (ctl->enable == 0 || ctl->widget == NULL) 4018 continue; 4019 /* XXX This should be compressed! */ 4020 if ((ctl->widget->nid == w->nid) || 4021 (ctl->widget->nid == pnid && ctl->index == index && 4022 (ctl->dir & HDA_CTL_IN)) || 4023 (ctl->widget->nid == pnid && pw != NULL && 4024 pw->type == 4025 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4026 (pw->nconns < 2 || pw->selconn == index || 4027 pw->selconn == -1) && 4028 (ctl->dir & HDA_CTL_OUT)) || 4029 (strategy == HDA_PARSE_DIRECT && 4030 ctl->widget->nid == w->nid)) { 4031 /*if (pw != NULL && pw->selconn == -1) 4032 pw->selconn = index; 4033 fl |= SOUND_MASK_VOLUME; 4034 fl |= SOUND_MASK_PCM; 4035 ctl->ossmask |= SOUND_MASK_VOLUME; 4036 ctl->ossmask |= SOUND_MASK_PCM; 4037 ctl->ossdev = SOUND_MIXER_PCM;*/ 4038 if (!(w->ctlflags & SOUND_MASK_PCM) || 4039 (pw != NULL && 4040 !(pw->ctlflags & SOUND_MASK_PCM))) { 4041 fl |= SOUND_MASK_VOLUME; 4042 fl |= SOUND_MASK_PCM; 4043 ctl->ossmask |= SOUND_MASK_VOLUME; 4044 ctl->ossmask |= SOUND_MASK_PCM; 4045 ctl->ossdev = SOUND_MIXER_PCM; 4046 w->ctlflags |= SOUND_MASK_VOLUME; 4047 w->ctlflags |= SOUND_MASK_PCM; 4048 if (pw != NULL) { 4049 if (pw->selconn == -1) 4050 pw->selconn = index; 4051 pw->ctlflags |= 4052 SOUND_MASK_VOLUME; 4053 pw->ctlflags |= 4054 SOUND_MASK_PCM; 4055 } 4056 } 4057 } 4058 } 4059 w->ctlflags |= fl; 4060 return (fl); 4061 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4062 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4063 (w->pflags & HDA_ADC_PATH)) { 4064 conndev = w->wclass.pin.config & 4065 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4066 i = 0; 4067 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4068 if (ctl->enable == 0 || ctl->widget == NULL) 4069 continue; 4070 /* XXX This should be compressed! */ 4071 if (((ctl->widget->nid == pnid && ctl->index == index && 4072 (ctl->dir & HDA_CTL_IN)) || 4073 (ctl->widget->nid == pnid && pw != NULL && 4074 pw->type == 4075 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4076 (pw->nconns < 2 || pw->selconn == index || 4077 pw->selconn == -1) && 4078 (ctl->dir & HDA_CTL_OUT)) || 4079 (strategy == HDA_PARSE_DIRECT && 4080 ctl->widget->nid == w->nid)) && 4081 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4082 if (pw != NULL && pw->selconn == -1) 4083 pw->selconn = index; 4084 ossdev = 0; 4085 switch (conndev) { 4086 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4087 ossdev = SOUND_MIXER_MIC; 4088 break; 4089 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4090 ossdev = SOUND_MIXER_LINE; 4091 break; 4092 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4093 ossdev = SOUND_MIXER_CD; 4094 break; 4095 default: 4096 ossdev = 4097 hdac_audio_ctl_ossmixer_getnextdev( 4098 devinfo); 4099 if (ossdev < 0) 4100 ossdev = 0; 4101 break; 4102 } 4103 if (strategy == HDA_PARSE_MIXER) { 4104 fl |= SOUND_MASK_VOLUME; 4105 ctl->ossmask |= SOUND_MASK_VOLUME; 4106 } 4107 fl |= 1 << ossdev; 4108 ctl->ossmask |= 1 << ossdev; 4109 ctl->ossdev = ossdev; 4110 } 4111 } 4112 w->ctlflags |= fl; 4113 return (fl); 4114 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4115 i = 0; 4116 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4117 if (ctl->enable == 0 || ctl->widget == NULL) 4118 continue; 4119 /* XXX This should be compressed! */ 4120 if (((ctl->widget->nid == pnid && ctl->index == index && 4121 (ctl->dir & HDA_CTL_IN)) || 4122 (ctl->widget->nid == pnid && pw != NULL && 4123 pw->type == 4124 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4125 (pw->nconns < 2 || pw->selconn == index || 4126 pw->selconn == -1) && 4127 (ctl->dir & HDA_CTL_OUT)) || 4128 (strategy == HDA_PARSE_DIRECT && 4129 ctl->widget->nid == w->nid)) && 4130 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4131 if (pw != NULL && pw->selconn == -1) 4132 pw->selconn = index; 4133 fl |= SOUND_MASK_VOLUME; 4134 fl |= SOUND_MASK_SPEAKER; 4135 ctl->ossmask |= SOUND_MASK_VOLUME; 4136 ctl->ossmask |= SOUND_MASK_SPEAKER; 4137 ctl->ossdev = SOUND_MIXER_SPEAKER; 4138 } 4139 } 4140 w->ctlflags |= fl; 4141 return (fl); 4142 } 4143 return (0); 4144 } 4145 4146 static uint32_t 4147 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4148 { 4149 struct hdac_widget *w, *cw; 4150 struct hdac_audio_ctl *ctl; 4151 uint32_t fl; 4152 int i; 4153 4154 if (depth > HDA_PARSE_MAXDEPTH) 4155 return (0); 4156 4157 w = hdac_widget_get(devinfo, nid); 4158 if (w == NULL || w->enable == 0) 4159 return (0); 4160 /*if (!(w->pflags & HDA_ADC_PATH)) 4161 return (0); 4162 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4163 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4164 return (0);*/ 4165 i = 0; 4166 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4167 if (ctl->enable == 0 || ctl->widget == NULL) 4168 continue; 4169 if (ctl->widget->nid == nid) { 4170 ctl->ossmask |= SOUND_MASK_RECLEV; 4171 w->ctlflags |= SOUND_MASK_RECLEV; 4172 return (SOUND_MASK_RECLEV); 4173 } 4174 } 4175 for (i = 0; i < w->nconns; i++) { 4176 cw = hdac_widget_get(devinfo, w->conns[i]); 4177 if (cw == NULL || cw->enable == 0) 4178 continue; 4179 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4180 continue; 4181 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4182 if (fl != 0) { 4183 cw->ctlflags |= fl; 4184 w->ctlflags |= fl; 4185 return (fl); 4186 } 4187 } 4188 return (0); 4189 } 4190 4191 static int 4192 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4193 { 4194 struct hdac_widget *w, *cw; 4195 int i, child = 0; 4196 4197 if (depth > HDA_PARSE_MAXDEPTH) 4198 return (0); 4199 4200 w = hdac_widget_get(devinfo, nid); 4201 if (w == NULL || w->enable == 0) 4202 return (0); 4203 /*if (!(w->pflags & HDA_ADC_PATH)) 4204 return (0); 4205 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4206 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4207 return (0);*/ 4208 /* XXX weak! */ 4209 for (i = 0; i < w->nconns; i++) { 4210 cw = hdac_widget_get(devinfo, w->conns[i]); 4211 if (cw == NULL) 4212 continue; 4213 if (++child > 1) { 4214 w->pflags |= HDA_ADC_RECSEL; 4215 return (1); 4216 } 4217 } 4218 for (i = 0; i < w->nconns; i++) { 4219 if (hdac_audio_ctl_recsel_build(devinfo, 4220 w->conns[i], depth + 1) != 0) 4221 return (1); 4222 } 4223 return (0); 4224 } 4225 4226 static int 4227 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4228 { 4229 struct hdac_widget *w, *cw; 4230 int i, j, conndev, found_dac = 0; 4231 int strategy; 4232 4233 strategy = devinfo->function.audio.parsing_strategy; 4234 4235 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4236 w = hdac_widget_get(devinfo, i); 4237 if (w == NULL || w->enable == 0) 4238 continue; 4239 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4240 continue; 4241 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4242 continue; 4243 conndev = w->wclass.pin.config & 4244 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4245 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4246 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4247 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4248 continue; 4249 for (j = 0; j < w->nconns; j++) { 4250 cw = hdac_widget_get(devinfo, w->conns[j]); 4251 if (cw == NULL || cw->enable == 0) 4252 continue; 4253 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4254 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4255 cw->type == 4256 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4257 continue; 4258 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4259 != 0) { 4260 if (w->selconn == -1) 4261 w->selconn = j; 4262 w->pflags |= HDA_DAC_PATH; 4263 found_dac++; 4264 } 4265 } 4266 } 4267 4268 return (found_dac); 4269 } 4270 4271 static void 4272 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4273 { 4274 struct hdac_widget *w; 4275 struct hdac_audio_ctl *ctl; 4276 int i, j, dacs, strategy; 4277 4278 /* Construct DAC path */ 4279 strategy = HDA_PARSE_MIXER; 4280 devinfo->function.audio.parsing_strategy = strategy; 4281 HDA_BOOTVERBOSE( 4282 device_printf(devinfo->codec->sc->dev, 4283 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4284 HDA_WIDGET_PARSER_REV); 4285 ); 4286 dacs = hdac_audio_build_tree_strategy(devinfo); 4287 if (dacs == 0) { 4288 HDA_BOOTVERBOSE( 4289 device_printf(devinfo->codec->sc->dev, 4290 "HDA_DEBUG: HWiP: 0 DAC path found! " 4291 "Retrying parser " 4292 "using HDA_PARSE_DIRECT strategy.\n"); 4293 ); 4294 strategy = HDA_PARSE_DIRECT; 4295 devinfo->function.audio.parsing_strategy = strategy; 4296 dacs = hdac_audio_build_tree_strategy(devinfo); 4297 } 4298 4299 HDA_BOOTVERBOSE( 4300 device_printf(devinfo->codec->sc->dev, 4301 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4302 "strategy.\n", 4303 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4304 ); 4305 4306 /* Construct ADC path */ 4307 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4308 w = hdac_widget_get(devinfo, i); 4309 if (w == NULL || w->enable == 0) 4310 continue; 4311 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4312 continue; 4313 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4314 } 4315 4316 /* Output mixers */ 4317 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4318 w = hdac_widget_get(devinfo, i); 4319 if (w == NULL || w->enable == 0) 4320 continue; 4321 if ((strategy == HDA_PARSE_MIXER && 4322 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4323 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4324 && (w->pflags & HDA_DAC_PATH)) || 4325 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4326 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4327 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4328 w->nid, devinfo->startnode - 1, 0, 0); 4329 } else if (w->type == 4330 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4331 j = 0; 4332 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4333 NULL) { 4334 if (ctl->enable == 0 || ctl->widget == NULL) 4335 continue; 4336 if (ctl->widget->nid != w->nid) 4337 continue; 4338 ctl->ossmask |= SOUND_MASK_VOLUME; 4339 ctl->ossmask |= SOUND_MASK_SPEAKER; 4340 ctl->ossdev = SOUND_MIXER_SPEAKER; 4341 w->ctlflags |= SOUND_MASK_VOLUME; 4342 w->ctlflags |= SOUND_MASK_SPEAKER; 4343 } 4344 } 4345 } 4346 4347 /* Input mixers (rec) */ 4348 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4349 w = hdac_widget_get(devinfo, i); 4350 if (w == NULL || w->enable == 0) 4351 continue; 4352 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4353 w->pflags & HDA_ADC_PATH)) 4354 continue; 4355 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4356 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4357 } 4358 } 4359 4360 #define HDA_COMMIT_CONN (1 << 0) 4361 #define HDA_COMMIT_CTRL (1 << 1) 4362 #define HDA_COMMIT_EAPD (1 << 2) 4363 #define HDA_COMMIT_GPIO (1 << 3) 4364 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4365 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4366 4367 static void 4368 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4369 { 4370 struct hdac_softc *sc = devinfo->codec->sc; 4371 struct hdac_widget *w; 4372 nid_t cad; 4373 int i; 4374 4375 if (!(cfl & HDA_COMMIT_ALL)) 4376 return; 4377 4378 cad = devinfo->codec->cad; 4379 4380 if (cfl & HDA_COMMIT_GPIO) { 4381 uint32_t gdata, gmask, gdir; 4382 int commitgpio = 0; 4383 4384 gdata = 0; 4385 gmask = 0; 4386 gdir = 0; 4387 4388 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4389 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4390 0x7e7, 0), cad); 4391 4392 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4393 commitgpio = 1; 4394 else { 4395 for (i = 0; i < HDA_GPIO_MAX; i++) { 4396 if (!(devinfo->function.audio.quirks & 4397 (1 << i))) 4398 continue; 4399 if (commitgpio == 0) { 4400 commitgpio = 1; 4401 gdata = hdac_command(sc, 4402 HDA_CMD_GET_GPIO_DATA(cad, 4403 devinfo->nid), cad); 4404 gmask = hdac_command(sc, 4405 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4406 devinfo->nid), cad); 4407 gdir = hdac_command(sc, 4408 HDA_CMD_GET_GPIO_DIRECTION(cad, 4409 devinfo->nid), cad); 4410 HDA_BOOTVERBOSE( 4411 device_printf(sc->dev, 4412 "GPIO init: data=0x%08x " 4413 "mask=0x%08x dir=0x%08x\n", 4414 gdata, gmask, gdir); 4415 ); 4416 } 4417 gdata |= 1 << i; 4418 gmask |= 1 << i; 4419 gdir |= 1 << i; 4420 } 4421 } 4422 4423 if (commitgpio != 0) { 4424 HDA_BOOTVERBOSE( 4425 device_printf(sc->dev, 4426 "GPIO commit: data=0x%08x mask=0x%08x " 4427 "dir=0x%08x\n", 4428 gdata, gmask, gdir); 4429 ); 4430 hdac_command(sc, 4431 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4432 gmask), cad); 4433 hdac_command(sc, 4434 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4435 gdir), cad); 4436 hdac_command(sc, 4437 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4438 gdata), cad); 4439 } 4440 } 4441 4442 for (i = 0; i < devinfo->nodecnt; i++) { 4443 w = &devinfo->widget[i]; 4444 if (w == NULL || w->enable == 0) 4445 continue; 4446 if (cfl & HDA_COMMIT_CONN) { 4447 if (w->selconn == -1) 4448 w->selconn = 0; 4449 if (w->nconns > 0) 4450 hdac_widget_connection_select(w, w->selconn); 4451 } 4452 if ((cfl & HDA_COMMIT_CTRL) && 4453 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4454 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4455 (HDA_DAC_PATH | HDA_ADC_PATH)) 4456 device_printf(sc->dev, "WARNING: node %d " 4457 "participate both for DAC/ADC!\n", w->nid); 4458 if (w->pflags & HDA_DAC_PATH) { 4459 w->wclass.pin.ctrl &= 4460 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4461 if ((w->wclass.pin.config & 4462 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4463 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4464 w->wclass.pin.ctrl &= 4465 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4466 } else if (w->pflags & HDA_ADC_PATH) { 4467 w->wclass.pin.ctrl &= 4468 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4469 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4470 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4471 uint32_t pincap = w->wclass.pin.cap; 4472 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4473 w->wclass.pin.ctrl |= 4474 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4475 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4476 ); 4477 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4478 w->wclass.pin.ctrl |= 4479 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4480 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4481 ); 4482 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4483 w->wclass.pin.ctrl |= 4484 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4485 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4486 ); 4487 } 4488 } else 4489 w->wclass.pin.ctrl &= ~( 4490 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4491 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4492 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4493 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4494 hdac_command(sc, 4495 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4496 w->wclass.pin.ctrl), cad); 4497 } 4498 if ((cfl & HDA_COMMIT_EAPD) && 4499 w->param.eapdbtl != HDAC_INVALID) { 4500 uint32_t val; 4501 4502 val = w->param.eapdbtl; 4503 if (devinfo->function.audio.quirks & 4504 HDA_QUIRK_EAPDINV) 4505 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4506 hdac_command(sc, 4507 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4508 val), cad); 4509 4510 } 4511 DELAY(1000); 4512 } 4513 } 4514 4515 static void 4516 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4517 { 4518 struct hdac_softc *sc = devinfo->codec->sc; 4519 struct hdac_audio_ctl *ctl; 4520 int i; 4521 4522 devinfo->function.audio.mvol = 100 | (100 << 8); 4523 i = 0; 4524 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4525 if (ctl->enable == 0 || ctl->widget == NULL) { 4526 HDA_BOOTVERBOSE( 4527 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4528 i, (ctl->widget != NULL) ? 4529 ctl->widget->nid : -1); 4530 if (ctl->childwidget != NULL) 4531 printf(" childnid=%d", 4532 ctl->childwidget->nid); 4533 if (ctl->widget == NULL) 4534 printf(" NULL WIDGET!"); 4535 printf(" DISABLED\n"); 4536 ); 4537 continue; 4538 } 4539 HDA_BOOTVERBOSE( 4540 if (ctl->ossmask == 0) { 4541 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4542 i, ctl->widget->nid); 4543 if (ctl->childwidget != NULL) 4544 printf(" childnid=%d", 4545 ctl->childwidget->nid); 4546 printf(" Bind to NONE\n"); 4547 } 4548 ); 4549 if (ctl->step > 0) { 4550 ctl->ossval = (ctl->left * 100) / ctl->step; 4551 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4552 } else 4553 ctl->ossval = 0; 4554 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4555 ctl->left, ctl->right); 4556 } 4557 } 4558 4559 static int 4560 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4561 { 4562 struct hdac_chan *ch; 4563 struct hdac_widget *w; 4564 uint32_t cap, fmtcap, pcmcap, path; 4565 int i, type, ret, max; 4566 4567 if (dir == PCMDIR_PLAY) { 4568 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4569 ch = &devinfo->codec->sc->play; 4570 path = HDA_DAC_PATH; 4571 } else { 4572 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4573 ch = &devinfo->codec->sc->rec; 4574 path = HDA_ADC_PATH; 4575 } 4576 4577 ch->caps = hdac_caps; 4578 ch->caps.fmtlist = ch->fmtlist; 4579 ch->bit16 = 1; 4580 ch->bit32 = 0; 4581 ch->pcmrates[0] = 48000; 4582 ch->pcmrates[1] = 0; 4583 4584 ret = 0; 4585 fmtcap = devinfo->function.audio.supp_stream_formats; 4586 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4587 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4588 4589 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4590 w = hdac_widget_get(devinfo, i); 4591 if (w == NULL || w->enable == 0 || w->type != type || 4592 !(w->pflags & path)) 4593 continue; 4594 cap = w->param.widget_cap; 4595 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4596 continue;*/ 4597 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4598 continue; 4599 cap = w->param.supp_stream_formats; 4600 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4601 } 4602 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4603 }*/ 4604 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4605 continue; 4606 if (ret == 0) { 4607 fmtcap = w->param.supp_stream_formats; 4608 pcmcap = w->param.supp_pcm_size_rate; 4609 } else { 4610 fmtcap &= w->param.supp_stream_formats; 4611 pcmcap &= w->param.supp_pcm_size_rate; 4612 } 4613 ch->io[ret++] = i; 4614 } 4615 ch->io[ret] = -1; 4616 4617 ch->supp_stream_formats = fmtcap; 4618 ch->supp_pcm_size_rate = pcmcap; 4619 4620 /* 4621 * 8bit = 0 4622 * 16bit = 1 4623 * 20bit = 2 4624 * 24bit = 3 4625 * 32bit = 4 4626 */ 4627 if (ret > 0) { 4628 cap = pcmcap; 4629 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4630 ch->bit16 = 1; 4631 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4632 ch->bit16 = 0; 4633 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4634 ch->bit32 = 4; 4635 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4636 ch->bit32 = 3; 4637 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4638 ch->bit32 = 2; 4639 i = 0; 4640 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4641 ch->fmtlist[i++] = AFMT_S16_LE; 4642 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4643 if (ch->bit32 > 0) { 4644 if (!(devinfo->function.audio.quirks & 4645 HDA_QUIRK_FORCESTEREO)) 4646 ch->fmtlist[i++] = AFMT_S32_LE; 4647 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4648 } 4649 ch->fmtlist[i] = 0; 4650 i = 0; 4651 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4652 ch->pcmrates[i++] = 8000; 4653 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4654 ch->pcmrates[i++] = 11025; 4655 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4656 ch->pcmrates[i++] = 16000; 4657 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4658 ch->pcmrates[i++] = 22050; 4659 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4660 ch->pcmrates[i++] = 32000; 4661 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4662 ch->pcmrates[i++] = 44100; 4663 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4664 ch->pcmrates[i++] = 48000; 4665 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4666 ch->pcmrates[i++] = 88200; 4667 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4668 ch->pcmrates[i++] = 96000; 4669 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4670 ch->pcmrates[i++] = 176400; 4671 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4672 ch->pcmrates[i++] = 192000; 4673 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4674 ch->pcmrates[i] = 0; 4675 if (i > 0) { 4676 ch->caps.minspeed = ch->pcmrates[0]; 4677 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4678 } 4679 } 4680 4681 return (ret); 4682 } 4683 4684 static void 4685 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4686 { 4687 struct hdac_audio_ctl *ctl; 4688 struct hdac_softc *sc = devinfo->codec->sc; 4689 int i; 4690 uint32_t fl = 0; 4691 4692 4693 if (flag == 0) { 4694 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4695 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4696 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4697 } 4698 4699 i = 0; 4700 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4701 if (ctl->enable == 0 || ctl->widget == NULL || 4702 ctl->widget->enable == 0) 4703 continue; 4704 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4705 (flag != 0 && (ctl->ossmask & flag))) { 4706 if (banner != NULL) { 4707 device_printf(sc->dev, "\n"); 4708 device_printf(sc->dev, "%s\n", banner); 4709 } 4710 goto hdac_ctl_dump_it_all; 4711 } 4712 } 4713 4714 return; 4715 4716 hdac_ctl_dump_it_all: 4717 i = 0; 4718 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4719 if (ctl->enable == 0 || ctl->widget == NULL || 4720 ctl->widget->enable == 0) 4721 continue; 4722 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4723 (flag != 0 && (ctl->ossmask & flag)))) 4724 continue; 4725 if (flag == 0) { 4726 device_printf(sc->dev, "\n"); 4727 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4728 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4729 } 4730 device_printf(sc->dev, " |\n"); 4731 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4732 ctl->widget->nid, ctl->index); 4733 if (ctl->childwidget != NULL) 4734 printf("(nid: %2d) ", ctl->childwidget->nid); 4735 else 4736 printf(" "); 4737 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4738 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4739 ctl->ossmask); 4740 } 4741 } 4742 4743 static void 4744 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4745 { 4746 uint32_t cap; 4747 4748 cap = fcap; 4749 if (cap != 0) { 4750 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4751 device_printf(sc->dev, " Format:"); 4752 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4753 printf(" AC3"); 4754 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4755 printf(" FLOAT32"); 4756 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4757 printf(" PCM"); 4758 printf("\n"); 4759 } 4760 cap = pcmcap; 4761 if (cap != 0) { 4762 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4763 device_printf(sc->dev, " PCM size:"); 4764 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4765 printf(" 8"); 4766 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4767 printf(" 16"); 4768 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4769 printf(" 20"); 4770 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4771 printf(" 24"); 4772 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4773 printf(" 32"); 4774 printf("\n"); 4775 device_printf(sc->dev, " PCM rate:"); 4776 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4777 printf(" 8"); 4778 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4779 printf(" 11"); 4780 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4781 printf(" 16"); 4782 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4783 printf(" 22"); 4784 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4785 printf(" 32"); 4786 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4787 printf(" 44"); 4788 printf(" 48"); 4789 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4790 printf(" 88"); 4791 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4792 printf(" 96"); 4793 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4794 printf(" 176"); 4795 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4796 printf(" 192"); 4797 printf("\n"); 4798 } 4799 } 4800 4801 static void 4802 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4803 { 4804 uint32_t pincap, wcap; 4805 4806 pincap = w->wclass.pin.cap; 4807 wcap = w->param.widget_cap; 4808 4809 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4810 device_printf(sc->dev, " "); 4811 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4812 printf(" ISC"); 4813 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4814 printf(" TRQD"); 4815 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4816 printf(" PDC"); 4817 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4818 printf(" HP"); 4819 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4820 printf(" OUT"); 4821 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4822 printf(" IN"); 4823 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4824 printf(" BAL"); 4825 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4826 printf(" VREF["); 4827 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4828 printf(" 50"); 4829 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4830 printf(" 80"); 4831 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4832 printf(" 100"); 4833 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4834 printf(" GROUND"); 4835 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4836 printf(" HIZ"); 4837 printf(" ]"); 4838 } 4839 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4840 printf(" EAPD"); 4841 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4842 printf(" : UNSOL"); 4843 printf("\n"); 4844 device_printf(sc->dev, " Pin config: 0x%08x\n", 4845 w->wclass.pin.config); 4846 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4847 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4848 printf(" HP"); 4849 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4850 printf(" IN"); 4851 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4852 printf(" OUT"); 4853 printf("\n"); 4854 } 4855 4856 static void 4857 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4858 { 4859 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4860 device_printf(sc->dev, " " 4861 "mute=%d step=%d size=%d offset=%d\n", 4862 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4863 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4864 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4865 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4866 } 4867 4868 static void 4869 hdac_dump_nodes(struct hdac_devinfo *devinfo) 4870 { 4871 struct hdac_softc *sc = devinfo->codec->sc; 4872 struct hdac_widget *w, *cw; 4873 int i, j; 4874 4875 device_printf(sc->dev, "\n"); 4876 device_printf(sc->dev, "Default Parameter\n"); 4877 device_printf(sc->dev, "-----------------\n"); 4878 hdac_dump_audio_formats(sc, 4879 devinfo->function.audio.supp_stream_formats, 4880 devinfo->function.audio.supp_pcm_size_rate); 4881 device_printf(sc->dev, " IN amp: 0x%08x\n", 4882 devinfo->function.audio.inamp_cap); 4883 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4884 devinfo->function.audio.outamp_cap); 4885 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4886 w = hdac_widget_get(devinfo, i); 4887 if (w == NULL) { 4888 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4889 continue; 4890 } 4891 device_printf(sc->dev, "\n"); 4892 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4893 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4894 "DIGITAL" : "ANALOG", 4895 (w->enable == 0) ? " [DISABLED]" : ""); 4896 device_printf(sc->dev, " name: %s\n", w->name); 4897 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4898 w->param.widget_cap); 4899 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4900 w->pflags); 4901 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4902 w->ctlflags); 4903 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4904 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4905 hdac_dump_audio_formats(sc, 4906 w->param.supp_stream_formats, 4907 w->param.supp_pcm_size_rate); 4908 } else if (w->type == 4909 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4910 hdac_dump_pin(sc, w); 4911 if (w->param.eapdbtl != HDAC_INVALID) 4912 device_printf(sc->dev, " EAPD: 0x%08x\n", 4913 w->param.eapdbtl); 4914 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4915 w->param.outamp_cap != 0) 4916 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4917 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4918 w->param.inamp_cap != 0) 4919 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4920 device_printf(sc->dev, " connections: %d\n", w->nconns); 4921 for (j = 0; j < w->nconns; j++) { 4922 cw = hdac_widget_get(devinfo, w->conns[j]); 4923 device_printf(sc->dev, " |\n"); 4924 device_printf(sc->dev, " + <- nid=%d [%s]", 4925 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4926 if (cw == NULL) 4927 printf(" [UNKNOWN]"); 4928 else if (cw->enable == 0) 4929 printf(" [DISABLED]"); 4930 if (w->nconns > 1 && w->selconn == j && w->type != 4931 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4932 printf(" (selected)"); 4933 printf("\n"); 4934 } 4935 } 4936 4937 } 4938 4939 static int 4940 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4941 { 4942 struct hdac_widget *w, *cw; 4943 struct hdac_softc *sc = devinfo->codec->sc; 4944 int i; 4945 4946 if (depth > HDA_PARSE_MAXDEPTH) 4947 return (0); 4948 4949 w = hdac_widget_get(devinfo, nid); 4950 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4951 return (0); 4952 4953 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4954 device_printf(sc->dev, "\n"); 4955 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4956 device_printf(sc->dev, " ^\n"); 4957 device_printf(sc->dev, " |\n"); 4958 device_printf(sc->dev, " +-----<------+\n"); 4959 } else { 4960 device_printf(sc->dev, " ^\n"); 4961 device_printf(sc->dev, " |\n"); 4962 device_printf(sc->dev, " "); 4963 printf(" nid=%d [%s]\n", w->nid, w->name); 4964 } 4965 4966 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4967 return (1); 4968 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4969 for (i = 0; i < w->nconns; i++) { 4970 cw = hdac_widget_get(devinfo, w->conns[i]); 4971 if (cw == NULL || cw->enable == 0 || cw->type == 4972 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4973 continue; 4974 if (hdac_dump_dac_internal(devinfo, cw->nid, 4975 depth + 1) != 0) 4976 return (1); 4977 } 4978 } else if ((w->type == 4979 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4980 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4981 w->selconn > -1 && w->selconn < w->nconns) { 4982 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4983 depth + 1) != 0) 4984 return (1); 4985 } 4986 4987 return (0); 4988 } 4989 4990 static void 4991 hdac_dump_dac(struct hdac_devinfo *devinfo) 4992 { 4993 struct hdac_widget *w; 4994 struct hdac_softc *sc = devinfo->codec->sc; 4995 int i, printed = 0; 4996 4997 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4998 w = hdac_widget_get(devinfo, i); 4999 if (w == NULL || w->enable == 0) 5000 continue; 5001 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5002 !(w->pflags & HDA_DAC_PATH)) 5003 continue; 5004 if (printed == 0) { 5005 printed = 1; 5006 device_printf(sc->dev, "\n"); 5007 device_printf(sc->dev, "Playback path:\n"); 5008 } 5009 hdac_dump_dac_internal(devinfo, w->nid, 0); 5010 } 5011 } 5012 5013 static void 5014 hdac_dump_adc(struct hdac_devinfo *devinfo) 5015 { 5016 struct hdac_widget *w, *cw; 5017 struct hdac_softc *sc = devinfo->codec->sc; 5018 int i, j; 5019 int printed = 0; 5020 char ossdevs[256]; 5021 5022 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5023 w = hdac_widget_get(devinfo, i); 5024 if (w == NULL || w->enable == 0) 5025 continue; 5026 if (!(w->pflags & HDA_ADC_RECSEL)) 5027 continue; 5028 if (printed == 0) { 5029 printed = 1; 5030 device_printf(sc->dev, "\n"); 5031 device_printf(sc->dev, "Recording sources:\n"); 5032 } 5033 device_printf(sc->dev, "\n"); 5034 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5035 for (j = 0; j < w->nconns; j++) { 5036 cw = hdac_widget_get(devinfo, w->conns[j]); 5037 if (cw == NULL || cw->enable == 0) 5038 continue; 5039 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5040 ossdevs, sizeof(ossdevs)); 5041 device_printf(sc->dev, " |\n"); 5042 device_printf(sc->dev, " + <- nid=%d [%s]", 5043 cw->nid, cw->name); 5044 if (strlen(ossdevs) > 0) { 5045 printf(" [recsrc: %s]", ossdevs); 5046 } 5047 printf("\n"); 5048 } 5049 } 5050 } 5051 5052 static void 5053 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5054 { 5055 nid_t *nids; 5056 5057 if (pcnt > 0) { 5058 device_printf(sc->dev, "\n"); 5059 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5060 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5061 sc->play.supp_pcm_size_rate); 5062 device_printf(sc->dev, " DAC:"); 5063 for (nids = sc->play.io; *nids != -1; nids++) 5064 printf(" %d", *nids); 5065 printf("\n"); 5066 } 5067 5068 if (rcnt > 0) { 5069 device_printf(sc->dev, "\n"); 5070 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5071 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5072 sc->rec.supp_pcm_size_rate); 5073 device_printf(sc->dev, " ADC:"); 5074 for (nids = sc->rec.io; *nids != -1; nids++) 5075 printf(" %d", *nids); 5076 printf("\n"); 5077 } 5078 } 5079 5080 static void 5081 hdac_release_resources(struct hdac_softc *sc) 5082 { 5083 struct hdac_devinfo *devinfo = NULL; 5084 device_t *devlist = NULL; 5085 int i, devcount; 5086 5087 if (sc == NULL) 5088 return; 5089 5090 hdac_lock(sc); 5091 if (sc->polling != 0) 5092 callout_stop(&sc->poll_hdac); 5093 hdac_reset(sc); 5094 hdac_unlock(sc); 5095 snd_mtxfree(sc->lock); 5096 5097 device_get_children(sc->dev, &devlist, &devcount); 5098 for (i = 0; devlist != NULL && i < devcount; i++) { 5099 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5100 if (devinfo == NULL) 5101 continue; 5102 if (devinfo->widget != NULL) 5103 free(devinfo->widget, M_HDAC); 5104 if (devinfo->node_type == 5105 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5106 devinfo->function.audio.ctl != NULL) 5107 free(devinfo->function.audio.ctl, M_HDAC); 5108 free(devinfo, M_HDAC); 5109 device_delete_child(sc->dev, devlist[i]); 5110 } 5111 if (devlist != NULL) 5112 free(devlist, M_TEMP); 5113 5114 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5115 if (sc->codecs[i] != NULL) 5116 free(sc->codecs[i], M_HDAC); 5117 sc->codecs[i] = NULL; 5118 } 5119 5120 hdac_dma_free(&sc->rirb_dma); 5121 hdac_dma_free(&sc->corb_dma); 5122 if (sc->play.blkcnt > 0) 5123 hdac_dma_free(&sc->play.bdl_dma); 5124 if (sc->rec.blkcnt > 0) 5125 hdac_dma_free(&sc->rec.bdl_dma); 5126 if (sc->chan_dmat != NULL) { 5127 bus_dma_tag_destroy(sc->chan_dmat); 5128 sc->chan_dmat = NULL; 5129 } 5130 hdac_irq_free(sc); 5131 hdac_mem_free(sc); 5132 free(sc, M_DEVBUF); 5133 } 5134 5135 /* This function surely going to make its way into upper level someday. */ 5136 static void 5137 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5138 { 5139 const char *res = NULL; 5140 int i = 0, j, k, len, inv; 5141 5142 if (on != NULL) 5143 *on = 0; 5144 if (off != NULL) 5145 *off = 0; 5146 if (sc == NULL) 5147 return; 5148 if (resource_string_value(device_get_name(sc->dev), 5149 device_get_unit(sc->dev), "config", &res) != 0) 5150 return; 5151 if (!(res != NULL && strlen(res) > 0)) 5152 return; 5153 HDA_BOOTVERBOSE( 5154 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5155 ); 5156 for (;;) { 5157 while (res[i] != '\0' && 5158 (res[i] == ',' || isspace(res[i]) != 0)) 5159 i++; 5160 if (res[i] == '\0') { 5161 HDA_BOOTVERBOSE( 5162 printf("\n"); 5163 ); 5164 return; 5165 } 5166 j = i; 5167 while (res[j] != '\0' && 5168 !(res[j] == ',' || isspace(res[j]) != 0)) 5169 j++; 5170 len = j - i; 5171 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5172 inv = 2; 5173 else 5174 inv = 0; 5175 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5176 if (strncmp(res + i + inv, 5177 hdac_quirks_tab[k].key, len - inv) != 0) 5178 continue; 5179 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5180 break; 5181 HDA_BOOTVERBOSE( 5182 printf(" %s%s", (inv != 0) ? "no" : "", 5183 hdac_quirks_tab[k].key); 5184 ); 5185 if (inv == 0 && on != NULL) 5186 *on |= hdac_quirks_tab[k].value; 5187 else if (inv != 0 && off != NULL) 5188 *off |= hdac_quirks_tab[k].value; 5189 break; 5190 } 5191 i = j; 5192 } 5193 } 5194 5195 #ifdef SND_DYNSYSCTL 5196 static int 5197 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5198 { 5199 struct hdac_softc *sc; 5200 struct hdac_devinfo *devinfo; 5201 device_t dev; 5202 uint32_t ctl; 5203 int err, val; 5204 5205 dev = oidp->oid_arg1; 5206 devinfo = pcm_getdevinfo(dev); 5207 if (devinfo == NULL || devinfo->codec == NULL || 5208 devinfo->codec->sc == NULL) 5209 return (EINVAL); 5210 sc = devinfo->codec->sc; 5211 hdac_lock(sc); 5212 val = sc->polling; 5213 hdac_unlock(sc); 5214 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5215 5216 if (err || req->newptr == NULL) 5217 return (err); 5218 if (val < 0 || val > 1) 5219 return (EINVAL); 5220 5221 hdac_lock(sc); 5222 if (val != sc->polling) { 5223 if (hda_chan_active(sc) != 0) 5224 err = EBUSY; 5225 else if (val == 0) { 5226 callout_stop(&sc->poll_hdac); 5227 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5228 sc->rirb_size / 2); 5229 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5230 ctl |= HDAC_RIRBCTL_RINTCTL; 5231 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5232 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5233 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5234 sc->polling = 0; 5235 DELAY(1000); 5236 } else { 5237 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5238 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5239 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5240 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5241 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5242 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5243 sc); 5244 sc->polling = 1; 5245 DELAY(1000); 5246 } 5247 } 5248 hdac_unlock(sc); 5249 5250 return (err); 5251 } 5252 #endif 5253 5254 static void 5255 hdac_attach2(void *arg) 5256 { 5257 struct hdac_softc *sc; 5258 struct hdac_widget *w; 5259 struct hdac_audio_ctl *ctl; 5260 uint32_t quirks_on, quirks_off; 5261 int pcnt, rcnt; 5262 int i; 5263 char status[SND_STATUSLEN]; 5264 device_t *devlist = NULL; 5265 int devcount; 5266 struct hdac_devinfo *devinfo = NULL; 5267 5268 sc = (struct hdac_softc *)arg; 5269 5270 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5271 5272 HDA_BOOTVERBOSE( 5273 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5274 quirks_on, quirks_off); 5275 ); 5276 5277 hdac_lock(sc); 5278 5279 /* Remove ourselves from the config hooks */ 5280 if (sc->intrhook.ich_func != NULL) { 5281 config_intrhook_disestablish(&sc->intrhook); 5282 sc->intrhook.ich_func = NULL; 5283 } 5284 5285 /* Start the corb and rirb engines */ 5286 HDA_BOOTVERBOSE( 5287 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5288 ); 5289 hdac_corb_start(sc); 5290 HDA_BOOTVERBOSE( 5291 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5292 ); 5293 hdac_rirb_start(sc); 5294 5295 HDA_BOOTVERBOSE( 5296 device_printf(sc->dev, 5297 "HDA_DEBUG: Enabling controller interrupt...\n"); 5298 ); 5299 if (sc->polling == 0) 5300 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5301 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5302 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5303 HDAC_GCTL_UNSOL); 5304 5305 DELAY(1000); 5306 5307 HDA_BOOTVERBOSE( 5308 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5309 ); 5310 hdac_scan_codecs(sc); 5311 5312 device_get_children(sc->dev, &devlist, &devcount); 5313 for (i = 0; devlist != NULL && i < devcount; i++) { 5314 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5315 if (devinfo != NULL && devinfo->node_type == 5316 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5317 break; 5318 } else 5319 devinfo = NULL; 5320 } 5321 if (devlist != NULL) 5322 free(devlist, M_TEMP); 5323 5324 if (devinfo == NULL) { 5325 hdac_unlock(sc); 5326 device_printf(sc->dev, "Audio Function Group not found!\n"); 5327 hdac_release_resources(sc); 5328 return; 5329 } 5330 5331 HDA_BOOTVERBOSE( 5332 device_printf(sc->dev, 5333 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5334 devinfo->nid, devinfo->codec->cad); 5335 ); 5336 hdac_audio_parse(devinfo); 5337 HDA_BOOTVERBOSE( 5338 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5339 ); 5340 hdac_audio_ctl_parse(devinfo); 5341 HDA_BOOTVERBOSE( 5342 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5343 ); 5344 hdac_vendor_patch_parse(devinfo); 5345 if (quirks_on != 0) 5346 devinfo->function.audio.quirks |= quirks_on; 5347 if (quirks_off != 0) 5348 devinfo->function.audio.quirks &= ~quirks_off; 5349 5350 /* XXX Disable all DIGITAL path. */ 5351 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5352 w = hdac_widget_get(devinfo, i); 5353 if (w == NULL) 5354 continue; 5355 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5356 w->enable = 0; 5357 continue; 5358 } 5359 /* XXX Disable useless pin ? */ 5360 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5361 (w->wclass.pin.config & 5362 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5363 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5364 w->enable = 0; 5365 } 5366 i = 0; 5367 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5368 if (ctl->widget == NULL) 5369 continue; 5370 w = ctl->widget; 5371 if (w->enable == 0) 5372 ctl->enable = 0; 5373 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5374 ctl->enable = 0; 5375 w = ctl->childwidget; 5376 if (w == NULL) 5377 continue; 5378 if (w->enable == 0 || 5379 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5380 ctl->enable = 0; 5381 } 5382 5383 HDA_BOOTVERBOSE( 5384 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5385 ); 5386 hdac_audio_build_tree(devinfo); 5387 5388 HDA_BOOTVERBOSE( 5389 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5390 ); 5391 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5392 HDA_BOOTVERBOSE( 5393 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5394 ); 5395 hdac_audio_ctl_commit(devinfo); 5396 5397 HDA_BOOTVERBOSE( 5398 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5399 ); 5400 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5401 HDA_BOOTVERBOSE( 5402 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5403 ); 5404 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5405 5406 hdac_unlock(sc); 5407 HDA_BOOTVERBOSE( 5408 device_printf(sc->dev, 5409 "HDA_DEBUG: OSS mixer initialization...\n"); 5410 ); 5411 5412 /* 5413 * There is no point of return after this. If the driver failed, 5414 * so be it. Let the detach procedure do all the cleanup. 5415 */ 5416 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5417 device_printf(sc->dev, "Can't register mixer\n"); 5418 5419 if (pcnt > 0) 5420 pcnt = 1; 5421 if (rcnt > 0) 5422 rcnt = 1; 5423 5424 HDA_BOOTVERBOSE( 5425 device_printf(sc->dev, 5426 "HDA_DEBUG: Registering PCM channels...\n"); 5427 ); 5428 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5429 device_printf(sc->dev, "Can't register PCM\n"); 5430 5431 sc->registered++; 5432 5433 for (i = 0; i < pcnt; i++) 5434 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5435 for (i = 0; i < rcnt; i++) 5436 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5437 5438 #ifdef SND_DYNSYSCTL 5439 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5440 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5441 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5442 sysctl_hdac_polling, "I", "Enable polling mode"); 5443 #endif 5444 5445 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5446 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5447 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5448 pcm_setstatus(sc->dev, status); 5449 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5450 HDA_BOOTVERBOSE( 5451 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5452 hdac_codec_id(devinfo)); 5453 ); 5454 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5455 HDA_DRV_TEST_REV); 5456 5457 HDA_BOOTVERBOSE( 5458 if (devinfo->function.audio.quirks != 0) { 5459 device_printf(sc->dev, "\n"); 5460 device_printf(sc->dev, "HDA config/quirks:"); 5461 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5462 if (devinfo->function.audio.quirks & 5463 hdac_quirks_tab[i].value) 5464 printf(" %s", hdac_quirks_tab[i].key); 5465 } 5466 printf("\n"); 5467 } 5468 device_printf(sc->dev, "\n"); 5469 device_printf(sc->dev, "+-------------------+\n"); 5470 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5471 device_printf(sc->dev, "+-------------------+\n"); 5472 hdac_dump_nodes(devinfo); 5473 device_printf(sc->dev, "\n"); 5474 device_printf(sc->dev, "+------------------------+\n"); 5475 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5476 device_printf(sc->dev, "+------------------------+\n"); 5477 device_printf(sc->dev, "\n"); 5478 i = 0; 5479 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5480 device_printf(sc->dev, "%3d: nid=%d", i, 5481 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5482 if (ctl->childwidget != NULL) 5483 printf(" cnid=%d", ctl->childwidget->nid); 5484 printf(" dir=0x%x index=%d " 5485 "ossmask=0x%08x ossdev=%d%s\n", 5486 ctl->dir, ctl->index, 5487 ctl->ossmask, ctl->ossdev, 5488 (ctl->enable == 0) ? " [DISABLED]" : ""); 5489 } 5490 device_printf(sc->dev, "\n"); 5491 device_printf(sc->dev, "+-----------------------------------+\n"); 5492 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5493 device_printf(sc->dev, "+-----------------------------------+\n"); 5494 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5495 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5496 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5497 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5498 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5499 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5500 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5501 hdac_dump_ctls(devinfo, NULL, 0); 5502 hdac_dump_dac(devinfo); 5503 hdac_dump_adc(devinfo); 5504 device_printf(sc->dev, "\n"); 5505 device_printf(sc->dev, "+--------------------------------------+\n"); 5506 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5507 device_printf(sc->dev, "+--------------------------------------+\n"); 5508 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5509 ); 5510 5511 if (sc->polling != 0) { 5512 hdac_lock(sc); 5513 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5514 hdac_unlock(sc); 5515 } 5516 } 5517 5518 /**************************************************************************** 5519 * int hdac_detach(device_t) 5520 * 5521 * Detach and free up resources utilized by the hdac device. 5522 ****************************************************************************/ 5523 static int 5524 hdac_detach(device_t dev) 5525 { 5526 struct hdac_softc *sc = NULL; 5527 struct hdac_devinfo *devinfo = NULL; 5528 int err; 5529 5530 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5531 if (devinfo != NULL && devinfo->codec != NULL) 5532 sc = devinfo->codec->sc; 5533 if (sc == NULL) 5534 return (0); 5535 5536 if (sc->registered > 0) { 5537 err = pcm_unregister(dev); 5538 if (err != 0) 5539 return (err); 5540 } 5541 5542 hdac_release_resources(sc); 5543 5544 return (0); 5545 } 5546 5547 static device_method_t hdac_methods[] = { 5548 /* device interface */ 5549 DEVMETHOD(device_probe, hdac_probe), 5550 DEVMETHOD(device_attach, hdac_attach), 5551 DEVMETHOD(device_detach, hdac_detach), 5552 { 0, 0 } 5553 }; 5554 5555 static driver_t hdac_driver = { 5556 "pcm", 5557 hdac_methods, 5558 PCM_SOFTC_SIZE, 5559 }; 5560 5561 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5562 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5563 MODULE_VERSION(snd_hda, 1); 5564