1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71 #ifdef HAVE_KERNEL_OPTION_HEADERS 72 #include "opt_snd.h" 73 #endif 74 75 #include <dev/sound/pcm/sound.h> 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 79 #include <sys/ctype.h> 80 #include <sys/taskqueue.h> 81 82 #include <dev/sound/pci/hda/hdac_private.h> 83 #include <dev/sound/pci/hda/hdac_reg.h> 84 #include <dev/sound/pci/hda/hda_reg.h> 85 #include <dev/sound/pci/hda/hdac.h> 86 87 #include "mixer_if.h" 88 89 #define HDA_DRV_TEST_REV "20100226_0142" 90 91 SND_DECLARE_FILE("$FreeBSD$"); 92 93 #define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97 } while (0) 98 99 #define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103 } while (0) 104 105 #if 1 106 #undef HDAC_INTR_EXTRA 107 #define HDAC_INTR_EXTRA 1 108 #endif 109 110 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 111 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122 #define HDA_MATCH_ALL 0xffffffff 123 #define HDAC_INVALID 0xffffffff 124 125 /* Default controller / jack sense poll: 250ms */ 126 #define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128 /* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131 #define HDAC_TRIGGER_NONE 0x00000000 132 #define HDAC_TRIGGER_PLAY 0x00000fff 133 #define HDAC_TRIGGER_REC 0x00fff000 134 #define HDAC_TRIGGER_UNSOL 0x80000000 135 136 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139 /* Controller models */ 140 141 /* Intel */ 142 #define INTEL_VENDORID 0x8086 143 #define HDA_INTEL_CPT HDA_MODEL_CONSTRUCT(INTEL, 0x1c20) 144 #define HDA_INTEL_PATSBURG HDA_MODEL_CONSTRUCT(INTEL, 0x1d20) 145 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 146 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 147 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 148 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 149 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 150 #define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 151 #define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 152 #define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 153 #define HDA_INTEL_PCH2 HDA_MODEL_CONSTRUCT(INTEL, 0x3b57) 154 #define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 155 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 156 157 /* Nvidia */ 158 #define NVIDIA_VENDORID 0x10de 159 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 160 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 161 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 162 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 163 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 164 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 165 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 166 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 167 #define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 168 #define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 169 #define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 170 #define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 171 #define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 172 #define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 173 #define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 174 #define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 175 #define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 176 #define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 177 #define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 178 #define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 179 #define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 180 #define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 181 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 182 183 /* ATI */ 184 #define ATI_VENDORID 0x1002 185 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 186 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 187 #define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 188 #define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 189 #define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 190 #define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 191 #define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 192 #define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 193 #define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 194 #define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 195 #define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 196 #define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 197 #define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 198 #define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 199 #define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 200 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 201 202 /* RDC */ 203 #define RDC_VENDORID 0x17f3 204 #define HDA_RDC_M3010 HDA_MODEL_CONSTRUCT(RDC, 0x3010) 205 206 /* VIA */ 207 #define VIA_VENDORID 0x1106 208 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 209 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 210 211 /* SiS */ 212 #define SIS_VENDORID 0x1039 213 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 214 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 215 216 /* ULI */ 217 #define ULI_VENDORID 0x10b9 218 #define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 219 #define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 220 221 /* OEM/subvendors */ 222 223 /* Intel */ 224 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 225 226 /* HP/Compaq */ 227 #define HP_VENDORID 0x103c 228 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 229 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 230 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 231 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 232 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 233 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 234 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 235 #define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 236 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 237 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 238 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 239 #define HP_NX6325_SUBVENDORX 0x103c30b0 240 241 /* Dell */ 242 #define DELL_VENDORID 0x1028 243 #define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 244 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 245 #define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 246 #define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 247 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 248 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 249 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 250 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 251 252 /* Clevo */ 253 #define CLEVO_VENDORID 0x1558 254 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 255 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 256 257 /* Acer */ 258 #define ACER_VENDORID 0x1025 259 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 260 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 261 #define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 262 #define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 263 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 264 #define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 265 #define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 266 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 267 268 /* Asus */ 269 #define ASUS_VENDORID 0x1043 270 #define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 271 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 272 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 273 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 274 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 275 #define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 276 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 277 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 278 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 279 #define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 280 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 281 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 282 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 283 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 284 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 285 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 286 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 287 288 /* IBM / Lenovo */ 289 #define IBM_VENDORID 0x1014 290 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 291 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 292 293 /* Lenovo */ 294 #define LENOVO_VENDORID 0x17aa 295 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 296 #define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 297 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 298 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 299 300 /* Samsung */ 301 #define SAMSUNG_VENDORID 0x144d 302 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 303 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 304 305 /* Medion ? */ 306 #define MEDION_VENDORID 0x161f 307 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 308 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 309 310 /* Apple Computer Inc. */ 311 #define APPLE_VENDORID 0x106b 312 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 313 314 /* Sony */ 315 #define SONY_VENDORID 0x104d 316 #define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 317 #define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 318 319 /* 320 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 321 * instead of their own, which is beyond my comprehension 322 * (see HDA_CODEC_STAC9221 below). 323 */ 324 #define APPLE_INTEL_MAC 0x76808384 325 #define APPLE_MACBOOKPRO55 0xcb7910de 326 327 /* LG Electronics */ 328 #define LG_VENDORID 0x1854 329 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 330 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 331 332 /* Fujitsu Siemens */ 333 #define FS_VENDORID 0x1734 334 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 335 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 336 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 337 338 /* Fujitsu Limited */ 339 #define FL_VENDORID 0x10cf 340 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 341 #define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 342 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 343 344 /* Toshiba */ 345 #define TOSHIBA_VENDORID 0x1179 346 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 347 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 348 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 349 350 /* Micro-Star International (MSI) */ 351 #define MSI_VENDORID 0x1462 352 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 353 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 354 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 355 356 /* Giga-Byte Technology */ 357 #define GB_VENDORID 0x1458 358 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 359 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 360 361 /* Uniwill ? */ 362 #define UNIWILL_VENDORID 0x1584 363 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 364 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 365 366 367 /* Misc constants.. */ 368 #define HDA_AMP_VOL_DEFAULT (-1) 369 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 370 #define HDA_AMP_MUTE_NONE (0) 371 #define HDA_AMP_MUTE_LEFT (1 << 0) 372 #define HDA_AMP_MUTE_RIGHT (1 << 1) 373 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 374 375 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 376 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 377 378 #define HDA_ADC_MONITOR (1 << 0) 379 380 #define HDA_CTL_OUT 1 381 #define HDA_CTL_IN 2 382 383 #define HDA_GPIO_MAX 8 384 /* 0 - 7 = GPIO , 8 = Flush */ 385 #define HDA_QUIRK_GPIO0 (1 << 0) 386 #define HDA_QUIRK_GPIO1 (1 << 1) 387 #define HDA_QUIRK_GPIO2 (1 << 2) 388 #define HDA_QUIRK_GPIO3 (1 << 3) 389 #define HDA_QUIRK_GPIO4 (1 << 4) 390 #define HDA_QUIRK_GPIO5 (1 << 5) 391 #define HDA_QUIRK_GPIO6 (1 << 6) 392 #define HDA_QUIRK_GPIO7 (1 << 7) 393 #define HDA_QUIRK_GPIOFLUSH (1 << 8) 394 395 /* 9 - 25 = anything else */ 396 #define HDA_QUIRK_SOFTPCMVOL (1 << 9) 397 #define HDA_QUIRK_FIXEDRATE (1 << 10) 398 #define HDA_QUIRK_FORCESTEREO (1 << 11) 399 #define HDA_QUIRK_EAPDINV (1 << 12) 400 #define HDA_QUIRK_DMAPOS (1 << 13) 401 #define HDA_QUIRK_SENSEINV (1 << 14) 402 403 /* 26 - 31 = vrefs */ 404 #define HDA_QUIRK_IVREF50 (1 << 26) 405 #define HDA_QUIRK_IVREF80 (1 << 27) 406 #define HDA_QUIRK_IVREF100 (1 << 28) 407 #define HDA_QUIRK_OVREF50 (1 << 29) 408 #define HDA_QUIRK_OVREF80 (1 << 30) 409 #define HDA_QUIRK_OVREF100 (1 << 31) 410 411 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 412 HDA_QUIRK_IVREF100) 413 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 414 HDA_QUIRK_OVREF100) 415 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 416 417 #if __FreeBSD_version < 600000 418 #define taskqueue_drain(...) 419 #endif 420 421 static const struct { 422 char *key; 423 uint32_t value; 424 } hdac_quirks_tab[] = { 425 { "gpio0", HDA_QUIRK_GPIO0 }, 426 { "gpio1", HDA_QUIRK_GPIO1 }, 427 { "gpio2", HDA_QUIRK_GPIO2 }, 428 { "gpio3", HDA_QUIRK_GPIO3 }, 429 { "gpio4", HDA_QUIRK_GPIO4 }, 430 { "gpio5", HDA_QUIRK_GPIO5 }, 431 { "gpio6", HDA_QUIRK_GPIO6 }, 432 { "gpio7", HDA_QUIRK_GPIO7 }, 433 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 434 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 435 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 436 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 437 { "eapdinv", HDA_QUIRK_EAPDINV }, 438 { "dmapos", HDA_QUIRK_DMAPOS }, 439 { "senseinv", HDA_QUIRK_SENSEINV }, 440 { "ivref50", HDA_QUIRK_IVREF50 }, 441 { "ivref80", HDA_QUIRK_IVREF80 }, 442 { "ivref100", HDA_QUIRK_IVREF100 }, 443 { "ovref50", HDA_QUIRK_OVREF50 }, 444 { "ovref80", HDA_QUIRK_OVREF80 }, 445 { "ovref100", HDA_QUIRK_OVREF100 }, 446 { "ivref", HDA_QUIRK_IVREF }, 447 { "ovref", HDA_QUIRK_OVREF }, 448 { "vref", HDA_QUIRK_VREF }, 449 }; 450 #define HDAC_QUIRKS_TAB_LEN \ 451 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 452 453 #define HDA_BDL_MIN 2 454 #define HDA_BDL_MAX 256 455 #define HDA_BDL_DEFAULT HDA_BDL_MIN 456 457 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 458 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 459 460 #define HDA_BUFSZ_MIN 4096 461 #define HDA_BUFSZ_MAX 65536 462 #define HDA_BUFSZ_DEFAULT 16384 463 464 #define HDA_PARSE_MAXDEPTH 10 465 466 #define HDAC_UNSOLTAG_EVENT_HP 0x00 467 468 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 469 470 const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 471 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 472 "White", "Other"}; 473 474 const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 475 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 476 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 477 478 const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 479 480 /* Default */ 481 static uint32_t hdac_fmt[] = { 482 SND_FORMAT(AFMT_S16_LE, 2, 0), 483 0 484 }; 485 486 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 487 488 #define HDAC_NO_MSI 1 489 #define HDAC_NO_64BIT 2 490 491 static const struct { 492 uint32_t model; 493 char *desc; 494 char flags; 495 } hdac_devices[] = { 496 { HDA_INTEL_CPT, "Intel Cougar Point", 0 }, 497 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0 }, 498 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 499 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 500 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 501 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 502 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 503 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 504 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 505 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0 }, 506 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0 }, 507 { HDA_INTEL_SCH, "Intel SCH", 0 }, 508 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 509 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 510 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 511 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 512 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 513 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 514 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 515 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 516 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 517 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 518 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 519 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 520 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 521 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 522 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 523 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 524 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 525 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 526 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 527 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 528 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 529 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 530 { HDA_ATI_SB450, "ATI SB450", 0 }, 531 { HDA_ATI_SB600, "ATI SB600", 0 }, 532 { HDA_ATI_RS600, "ATI RS600", 0 }, 533 { HDA_ATI_RS690, "ATI RS690", 0 }, 534 { HDA_ATI_RS780, "ATI RS780", 0 }, 535 { HDA_ATI_R600, "ATI R600", 0 }, 536 { HDA_ATI_RV610, "ATI RV610", 0 }, 537 { HDA_ATI_RV620, "ATI RV620", 0 }, 538 { HDA_ATI_RV630, "ATI RV630", 0 }, 539 { HDA_ATI_RV635, "ATI RV635", 0 }, 540 { HDA_ATI_RV710, "ATI RV710", 0 }, 541 { HDA_ATI_RV730, "ATI RV730", 0 }, 542 { HDA_ATI_RV740, "ATI RV740", 0 }, 543 { HDA_ATI_RV770, "ATI RV770", 0 }, 544 { HDA_RDC_M3010, "RDC M3010", 0 }, 545 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 546 { HDA_SIS_966, "SiS 966", 0 }, 547 { HDA_ULI_M5461, "ULI M5461", 0 }, 548 /* Unknown */ 549 { HDA_INTEL_ALL, "Intel (Unknown)" }, 550 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 551 { HDA_ATI_ALL, "ATI (Unknown)" }, 552 { HDA_VIA_ALL, "VIA (Unknown)" }, 553 { HDA_SIS_ALL, "SiS (Unknown)" }, 554 { HDA_ULI_ALL, "ULI (Unknown)" }, 555 }; 556 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 557 558 static const struct { 559 uint16_t vendor; 560 uint8_t reg; 561 uint8_t mask; 562 uint8_t enable; 563 } hdac_pcie_snoop[] = { 564 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 565 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 566 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 567 }; 568 #define HDAC_PCIESNOOP_LEN \ 569 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 570 571 static const struct { 572 uint32_t rate; 573 int valid; 574 uint16_t base; 575 uint16_t mul; 576 uint16_t div; 577 } hda_rate_tab[] = { 578 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 579 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 580 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 581 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 582 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 583 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 584 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 585 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 586 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 587 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 588 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 589 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 590 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 591 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 592 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 593 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 594 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 595 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 596 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 597 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 598 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 599 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 600 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 601 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 602 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 603 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 604 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 605 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 606 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 607 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 608 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 609 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 610 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 611 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 612 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 613 }; 614 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 615 616 /* All codecs you can eat... */ 617 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 618 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 619 620 /* Cirrus Logic */ 621 #define CIRRUSLOGIC_VENDORID 0x1013 622 #define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206) 623 #define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207) 624 #define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff) 625 626 /* Realtek */ 627 #define REALTEK_VENDORID 0x10ec 628 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 629 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 630 #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 631 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 632 #define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 633 #define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270) 634 #define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 635 #define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273) 636 #define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275) 637 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 638 #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 639 #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 640 #define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665) 641 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 642 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 643 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 644 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 645 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 646 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 647 #define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) 648 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 649 #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 650 #define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892) 651 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 652 653 /* Analog Devices */ 654 #define ANALOGDEVICES_VENDORID 0x11d4 655 #define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 656 #define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 657 #define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 658 #define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 659 #define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 660 #define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 661 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 662 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 663 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 664 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 665 #define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 666 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 667 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 668 #define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 669 #define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 670 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 671 672 /* CMedia */ 673 #define CMEDIA_VENDORID 0x434d 674 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 675 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 676 677 /* Sigmatel */ 678 #define SIGMATEL_VENDORID 0x8384 679 #define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 680 #define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 681 #define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 682 #define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 683 #define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 684 #define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 685 #define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 686 #define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 687 #define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 688 #define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 689 #define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 690 #define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 691 #define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 692 #define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 693 #define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 694 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 695 #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 696 #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 697 #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 698 #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 699 #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 700 #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 701 #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 702 #define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 703 #define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661) 704 #define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 705 #define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664) 706 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 707 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 708 #define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 709 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 710 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 711 #define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 712 #define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 713 #define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 714 #define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 715 #define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 716 #define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 717 #define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 718 #define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 719 #define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 720 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 721 722 /* IDT */ 723 #define IDT_VENDORID 0x111d 724 #define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 725 #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 726 #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 727 #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 728 #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 729 #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 730 #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 731 #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 732 #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 733 #define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 734 #define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 735 #define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 736 #define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 737 738 /* Silicon Image */ 739 #define SII_VENDORID 0x1095 740 #define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 741 #define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 742 #define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 743 744 /* Lucent/Agere */ 745 #define AGERE_VENDORID 0x11c1 746 #define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 747 748 /* Conexant */ 749 #define CONEXANT_VENDORID 0x14f1 750 #define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 751 #define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 752 #define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 753 #define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066) 754 #define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067) 755 #define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069) 756 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 757 758 /* VIA */ 759 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 760 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 761 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 762 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 763 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 764 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 765 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 766 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 767 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 768 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 769 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 770 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 771 #define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 772 #define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 773 #define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 774 #define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 775 #define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 776 #define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 777 #define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 778 #define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 779 #define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 780 #define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 781 #define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 782 #define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 783 #define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 784 #define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 785 #define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 786 #define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 787 #define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 788 #define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 789 #define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 790 #define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 791 #define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 792 #define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 793 #define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 794 #define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 795 #define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433) 796 #define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721) 797 #define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428) 798 #define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428) 799 #define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448) 800 #define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440) 801 #define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441) 802 #define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438) 803 #define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438) 804 #define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441) 805 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 806 807 /* ATI */ 808 #define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 809 #define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 810 #define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 811 #define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 812 #define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 813 814 /* NVIDIA */ 815 #define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 816 #define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 817 #define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 818 #define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a) 819 #define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b) 820 #define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c) 821 #define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d) 822 #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 823 #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 824 #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 825 826 /* INTEL */ 827 #define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 828 #define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 829 #define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 830 #define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x2804) 831 #define HDA_CODEC_INTELG45_5 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 832 #define HDA_CODEC_INTELQ57 HDA_CODEC_CONSTRUCT(INTEL, 0x0054) 833 #define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 834 835 /* Codecs */ 836 static const struct { 837 uint32_t id; 838 char *name; 839 } hdac_codecs[] = { 840 { HDA_CODEC_CS4206, "Cirrus Logic CS4206" }, 841 { HDA_CODEC_CS4207, "Cirrus Logic CS4207" }, 842 { HDA_CODEC_ALC260, "Realtek ALC260" }, 843 { HDA_CODEC_ALC262, "Realtek ALC262" }, 844 { HDA_CODEC_ALC267, "Realtek ALC267" }, 845 { HDA_CODEC_ALC268, "Realtek ALC268" }, 846 { HDA_CODEC_ALC269, "Realtek ALC269" }, 847 { HDA_CODEC_ALC270, "Realtek ALC270" }, 848 { HDA_CODEC_ALC272, "Realtek ALC272" }, 849 { HDA_CODEC_ALC273, "Realtek ALC273" }, 850 { HDA_CODEC_ALC275, "Realtek ALC275" }, 851 { HDA_CODEC_ALC660, "Realtek ALC660" }, 852 { HDA_CODEC_ALC662, "Realtek ALC662" }, 853 { HDA_CODEC_ALC663, "Realtek ALC663" }, 854 { HDA_CODEC_ALC665, "Realtek ALC665" }, 855 { HDA_CODEC_ALC861, "Realtek ALC861" }, 856 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 857 { HDA_CODEC_ALC880, "Realtek ALC880" }, 858 { HDA_CODEC_ALC882, "Realtek ALC882" }, 859 { HDA_CODEC_ALC883, "Realtek ALC883" }, 860 { HDA_CODEC_ALC885, "Realtek ALC885" }, 861 { HDA_CODEC_ALC887, "Realtek ALC887" }, 862 { HDA_CODEC_ALC888, "Realtek ALC888" }, 863 { HDA_CODEC_ALC889, "Realtek ALC889" }, 864 { HDA_CODEC_ALC892, "Realtek ALC892" }, 865 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 866 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 867 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 868 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 869 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 870 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 871 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 872 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 873 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 874 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 875 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 876 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 877 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 878 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 879 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 880 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 881 { HDA_CODEC_CXD9872RDK, "Sigmatel CXD9872RD/K" }, 882 { HDA_CODEC_CXD9872AKD, "Sigmatel CXD9872AKD" }, 883 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 884 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 885 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 886 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 887 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 888 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 889 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 890 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 891 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 892 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 893 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 894 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 895 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 896 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 897 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 898 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 899 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 900 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 901 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 902 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 903 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 904 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 905 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 906 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 907 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 908 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 909 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 910 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 911 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 912 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 913 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 914 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 915 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 916 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 917 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 918 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 919 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 920 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 921 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 922 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 923 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 924 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 925 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 926 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 927 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 928 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 929 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 930 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 931 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 932 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 933 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 934 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 935 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 936 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 937 { HDA_CODEC_CX20582, "Conexant CX20582 (Pebble)" }, 938 { HDA_CODEC_CX20583, "Conexant CX20583 (Pebble HSF)" }, 939 { HDA_CODEC_CX20585, "Conexant CX20585" }, 940 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 941 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 942 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 943 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 944 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 945 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 946 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 947 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 948 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 949 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 950 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 951 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 952 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 953 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 954 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 955 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 956 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 957 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 958 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 959 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 960 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 961 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 962 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 963 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 964 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 965 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 966 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 967 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 968 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 969 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 970 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 971 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 972 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 973 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 974 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 975 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 976 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" }, 977 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" }, 978 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" }, 979 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" }, 980 { HDA_CODEC_VT1812, "VIA VT1812" }, 981 { HDA_CODEC_VT1818S, "VIA VT1818S" }, 982 { HDA_CODEC_VT1828S, "VIA VT1828S" }, 983 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" }, 984 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" }, 985 { HDA_CODEC_VT2020, "VIA VT2020" }, 986 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 987 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 988 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 989 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 990 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 991 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 992 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 993 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 994 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 995 { HDA_CODEC_NVIDIAGT220, "NVidia GT220 HDMI" }, 996 { HDA_CODEC_NVIDIAGT21X, "NVidia GT21x HDMI" }, 997 { HDA_CODEC_NVIDIAMCP89, "NVidia MCP89 HDMI" }, 998 { HDA_CODEC_NVIDIAGT240, "NVidia GT240 HDMI" }, 999 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 1000 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 1001 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 1002 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 1003 { HDA_CODEC_INTELG45_5, "Intel G45 HDMI" }, 1004 { HDA_CODEC_INTELQ57, "Intel Q57 HDMI" }, 1005 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 1006 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 1007 /* Unknown codec */ 1008 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 1009 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 1010 { HDA_CODEC_CSXXXX, "Cirrus Logic (Unknown)" }, 1011 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 1012 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 1013 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 1014 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 1015 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 1016 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 1017 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 1018 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 1019 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 1020 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 1021 }; 1022 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 1023 1024 1025 /**************************************************************************** 1026 * Function prototypes 1027 ****************************************************************************/ 1028 static void hdac_intr_handler(void *); 1029 static int hdac_reset(struct hdac_softc *, int); 1030 static int hdac_get_capabilities(struct hdac_softc *); 1031 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 1032 static int hdac_dma_alloc(struct hdac_softc *, 1033 struct hdac_dma *, bus_size_t); 1034 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 1035 static int hdac_mem_alloc(struct hdac_softc *); 1036 static void hdac_mem_free(struct hdac_softc *); 1037 static int hdac_irq_alloc(struct hdac_softc *); 1038 static void hdac_irq_free(struct hdac_softc *); 1039 static void hdac_corb_init(struct hdac_softc *); 1040 static void hdac_rirb_init(struct hdac_softc *); 1041 static void hdac_corb_start(struct hdac_softc *); 1042 static void hdac_rirb_start(struct hdac_softc *); 1043 static void hdac_scan_codecs(struct hdac_softc *); 1044 static void hdac_probe_codec(struct hdac_codec *); 1045 static void hdac_probe_function(struct hdac_codec *, nid_t); 1046 static int hdac_pcmchannel_setup(struct hdac_chan *); 1047 1048 static void hdac_attach2(void *); 1049 1050 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 1051 uint32_t, int); 1052 static void hdac_command_send_internal(struct hdac_softc *, 1053 struct hdac_command_list *, int); 1054 1055 static int hdac_probe(device_t); 1056 static int hdac_attach(device_t); 1057 static int hdac_detach(device_t); 1058 static int hdac_suspend(device_t); 1059 static int hdac_resume(device_t); 1060 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 1061 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 1062 uint32_t, int, int); 1063 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 1064 nid_t, int, int, int); 1065 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 1066 nid_t, nid_t, int, int, int, int, int, int); 1067 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 1068 1069 static int hdac_rirb_flush(struct hdac_softc *sc); 1070 static int hdac_unsolq_flush(struct hdac_softc *sc); 1071 1072 static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 1073 1074 #define hdac_command(a1, a2, a3) \ 1075 hdac_command_sendone_internal(a1, a2, a3) 1076 1077 #define hdac_codec_id(c) \ 1078 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1079 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1080 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1081 1082 static char * 1083 hdac_codec_name(struct hdac_codec *codec) 1084 { 1085 uint32_t id; 1086 int i; 1087 1088 id = hdac_codec_id(codec); 1089 1090 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1091 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1092 return (hdac_codecs[i].name); 1093 } 1094 1095 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1096 } 1097 1098 static char * 1099 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1100 { 1101 static char *ossname[] = SOUND_DEVICE_NAMES; 1102 int i, first = 1; 1103 1104 bzero(buf, len); 1105 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1106 if (mask & (1 << i)) { 1107 if (first == 0) 1108 strlcat(buf, ", ", len); 1109 strlcat(buf, ossname[i], len); 1110 first = 0; 1111 } 1112 } 1113 return (buf); 1114 } 1115 1116 static struct hdac_audio_ctl * 1117 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1118 { 1119 if (devinfo == NULL || 1120 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1121 index == NULL || devinfo->function.audio.ctl == NULL || 1122 devinfo->function.audio.ctlcnt < 1 || 1123 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1124 return (NULL); 1125 return (&devinfo->function.audio.ctl[(*index)++]); 1126 } 1127 1128 static struct hdac_audio_ctl * 1129 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1130 int index, int cnt) 1131 { 1132 struct hdac_audio_ctl *ctl; 1133 int i, found = 0; 1134 1135 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1136 return (NULL); 1137 1138 i = 0; 1139 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1140 if (ctl->enable == 0) 1141 continue; 1142 if (ctl->widget->nid != nid) 1143 continue; 1144 if (dir && ctl->ndir != dir) 1145 continue; 1146 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1147 ctl->dir == ctl->ndir && ctl->index != index) 1148 continue; 1149 found++; 1150 if (found == cnt || cnt <= 0) 1151 return (ctl); 1152 } 1153 1154 return (NULL); 1155 } 1156 1157 /* 1158 * Jack detection (Speaker/HP redirection) event handler. 1159 */ 1160 static void 1161 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1162 { 1163 struct hdac_audio_as *as; 1164 struct hdac_softc *sc; 1165 struct hdac_widget *w; 1166 struct hdac_audio_ctl *ctl; 1167 uint32_t val, res; 1168 int i, j; 1169 nid_t cad; 1170 1171 if (devinfo == NULL || devinfo->codec == NULL || 1172 devinfo->codec->sc == NULL) 1173 return; 1174 1175 sc = devinfo->codec->sc; 1176 cad = devinfo->codec->cad; 1177 as = devinfo->function.audio.as; 1178 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1179 if (as[i].hpredir < 0) 1180 continue; 1181 1182 w = hdac_widget_get(devinfo, as[i].pins[15]); 1183 if (w == NULL || w->enable == 0 || w->type != 1184 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1185 continue; 1186 1187 res = hdac_command(sc, 1188 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1189 1190 HDA_BOOTVERBOSE( 1191 device_printf(sc->dev, 1192 "Pin sense: nid=%d res=0x%08x\n", 1193 as[i].pins[15], res); 1194 ); 1195 1196 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1197 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1198 res ^= 1; 1199 1200 /* (Un)Mute headphone pin. */ 1201 ctl = hdac_audio_ctl_amp_get(devinfo, 1202 as[i].pins[15], HDA_CTL_IN, -1, 1); 1203 if (ctl != NULL && ctl->mute) { 1204 /* If pin has muter - use it. */ 1205 val = (res != 0) ? 0 : 1; 1206 if (val != ctl->forcemute) { 1207 ctl->forcemute = val; 1208 hdac_audio_ctl_amp_set(ctl, 1209 HDA_AMP_MUTE_DEFAULT, 1210 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1211 } 1212 } else { 1213 /* If there is no muter - disable pin output. */ 1214 w = hdac_widget_get(devinfo, as[i].pins[15]); 1215 if (w != NULL && w->type == 1216 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1217 if (res != 0) 1218 val = w->wclass.pin.ctrl | 1219 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1220 else 1221 val = w->wclass.pin.ctrl & 1222 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1223 if (val != w->wclass.pin.ctrl) { 1224 w->wclass.pin.ctrl = val; 1225 hdac_command(sc, 1226 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1227 w->nid, w->wclass.pin.ctrl), cad); 1228 } 1229 } 1230 } 1231 /* (Un)Mute other pins. */ 1232 for (j = 0; j < 15; j++) { 1233 if (as[i].pins[j] <= 0) 1234 continue; 1235 ctl = hdac_audio_ctl_amp_get(devinfo, 1236 as[i].pins[j], HDA_CTL_IN, -1, 1); 1237 if (ctl != NULL && ctl->mute) { 1238 /* If pin has muter - use it. */ 1239 val = (res != 0) ? 1 : 0; 1240 if (val == ctl->forcemute) 1241 continue; 1242 ctl->forcemute = val; 1243 hdac_audio_ctl_amp_set(ctl, 1244 HDA_AMP_MUTE_DEFAULT, 1245 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1246 continue; 1247 } 1248 /* If there is no muter - disable pin output. */ 1249 w = hdac_widget_get(devinfo, as[i].pins[j]); 1250 if (w != NULL && w->type == 1251 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1252 if (res != 0) 1253 val = w->wclass.pin.ctrl & 1254 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1255 else 1256 val = w->wclass.pin.ctrl | 1257 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1258 if (val != w->wclass.pin.ctrl) { 1259 w->wclass.pin.ctrl = val; 1260 hdac_command(sc, 1261 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1262 w->nid, w->wclass.pin.ctrl), cad); 1263 } 1264 } 1265 } 1266 } 1267 } 1268 1269 /* 1270 * Callback for poll based jack detection. 1271 */ 1272 static void 1273 hdac_jack_poll_callback(void *arg) 1274 { 1275 struct hdac_devinfo *devinfo = arg; 1276 struct hdac_softc *sc; 1277 1278 if (devinfo == NULL || devinfo->codec == NULL || 1279 devinfo->codec->sc == NULL) 1280 return; 1281 sc = devinfo->codec->sc; 1282 hdac_lock(sc); 1283 if (sc->poll_ival == 0) { 1284 hdac_unlock(sc); 1285 return; 1286 } 1287 hdac_hp_switch_handler(devinfo); 1288 callout_reset(&sc->poll_jack, sc->poll_ival, 1289 hdac_jack_poll_callback, devinfo); 1290 hdac_unlock(sc); 1291 } 1292 1293 /* 1294 * Jack detection initializer. 1295 */ 1296 static void 1297 hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1298 { 1299 struct hdac_softc *sc = devinfo->codec->sc; 1300 struct hdac_audio_as *as = devinfo->function.audio.as; 1301 struct hdac_widget *w; 1302 uint32_t id; 1303 int i, enable = 0, poll = 0; 1304 nid_t cad; 1305 1306 id = hdac_codec_id(devinfo->codec); 1307 cad = devinfo->codec->cad; 1308 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1309 if (as[i].hpredir < 0) 1310 continue; 1311 1312 w = hdac_widget_get(devinfo, as[i].pins[15]); 1313 if (w == NULL || w->enable == 0 || w->type != 1314 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1315 continue; 1316 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1317 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1318 device_printf(sc->dev, 1319 "No jack detection support at pin %d\n", 1320 as[i].pins[15]); 1321 continue; 1322 } 1323 enable = 1; 1324 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1325 hdac_command(sc, 1326 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1327 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1328 HDAC_UNSOLTAG_EVENT_HP), cad); 1329 } else 1330 poll = 1; 1331 HDA_BOOTVERBOSE( 1332 device_printf(sc->dev, 1333 "Enabling headphone/speaker " 1334 "audio routing switching:\n"); 1335 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1336 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1337 ); 1338 } 1339 if (enable) { 1340 hdac_hp_switch_handler(devinfo); 1341 if (poll) { 1342 callout_reset(&sc->poll_jack, 1, 1343 hdac_jack_poll_callback, devinfo); 1344 } 1345 } 1346 } 1347 1348 /* 1349 * Unsolicited messages handler. 1350 */ 1351 static void 1352 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1353 { 1354 struct hdac_softc *sc; 1355 struct hdac_devinfo *devinfo = NULL; 1356 int i; 1357 1358 if (codec == NULL || codec->sc == NULL) 1359 return; 1360 1361 sc = codec->sc; 1362 1363 HDA_BOOTVERBOSE( 1364 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1365 ); 1366 1367 for (i = 0; i < codec->num_fgs; i++) { 1368 if (codec->fgs[i].node_type == 1369 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1370 devinfo = &codec->fgs[i]; 1371 break; 1372 } 1373 } 1374 1375 if (devinfo == NULL) 1376 return; 1377 1378 switch (tag) { 1379 case HDAC_UNSOLTAG_EVENT_HP: 1380 hdac_hp_switch_handler(devinfo); 1381 break; 1382 default: 1383 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1384 break; 1385 } 1386 } 1387 1388 static int 1389 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1390 { 1391 /* XXX to be removed */ 1392 #ifdef HDAC_INTR_EXTRA 1393 uint32_t res; 1394 #endif 1395 1396 if (!(ch->flags & HDAC_CHN_RUNNING)) 1397 return (0); 1398 1399 /* XXX to be removed */ 1400 #ifdef HDAC_INTR_EXTRA 1401 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1402 #endif 1403 1404 /* XXX to be removed */ 1405 #ifdef HDAC_INTR_EXTRA 1406 HDA_BOOTVERBOSE( 1407 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1408 device_printf(ch->pdevinfo->dev, 1409 "PCMDIR_%s intr triggered beyond stream boundary:" 1410 "%08x\n", 1411 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1412 ); 1413 #endif 1414 1415 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1416 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1417 1418 /* XXX to be removed */ 1419 #ifdef HDAC_INTR_EXTRA 1420 if (res & HDAC_SDSTS_BCIS) { 1421 #endif 1422 return (1); 1423 /* XXX to be removed */ 1424 #ifdef HDAC_INTR_EXTRA 1425 } 1426 #endif 1427 1428 return (0); 1429 } 1430 1431 /**************************************************************************** 1432 * void hdac_intr_handler(void *) 1433 * 1434 * Interrupt handler. Processes interrupts received from the hdac. 1435 ****************************************************************************/ 1436 static void 1437 hdac_intr_handler(void *context) 1438 { 1439 struct hdac_softc *sc; 1440 uint32_t intsts; 1441 uint8_t rirbsts; 1442 struct hdac_rirb *rirb_base; 1443 uint32_t trigger; 1444 int i; 1445 1446 sc = (struct hdac_softc *)context; 1447 1448 hdac_lock(sc); 1449 if (sc->polling != 0) { 1450 hdac_unlock(sc); 1451 return; 1452 } 1453 1454 /* Do we have anything to do? */ 1455 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1456 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1457 hdac_unlock(sc); 1458 return; 1459 } 1460 1461 trigger = 0; 1462 1463 /* Was this a controller interrupt? */ 1464 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1465 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1466 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1467 /* Get as many responses that we can */ 1468 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1469 HDAC_WRITE_1(&sc->mem, 1470 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1471 if (hdac_rirb_flush(sc) != 0) 1472 trigger |= HDAC_TRIGGER_UNSOL; 1473 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1474 } 1475 /* XXX to be removed */ 1476 /* Clear interrupt and exit */ 1477 #ifdef HDAC_INTR_EXTRA 1478 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1479 #endif 1480 } 1481 1482 if (intsts & HDAC_INTSTS_SIS_MASK) { 1483 for (i = 0; i < sc->num_chans; i++) { 1484 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1485 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1486 trigger |= (1 << i); 1487 } 1488 /* XXX to be removed */ 1489 #ifdef HDAC_INTR_EXTRA 1490 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1491 HDAC_INTSTS_SIS_MASK); 1492 #endif 1493 } 1494 1495 hdac_unlock(sc); 1496 1497 for (i = 0; i < sc->num_chans; i++) { 1498 if (trigger & (1 << i)) 1499 chn_intr(sc->chans[i].c); 1500 } 1501 if (trigger & HDAC_TRIGGER_UNSOL) 1502 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1503 } 1504 1505 /**************************************************************************** 1506 * int hdac_reset(hdac_softc *, int) 1507 * 1508 * Reset the hdac to a quiescent and known state. 1509 ****************************************************************************/ 1510 static int 1511 hdac_reset(struct hdac_softc *sc, int wakeup) 1512 { 1513 uint32_t gctl; 1514 int count, i; 1515 1516 /* 1517 * Stop all Streams DMA engine 1518 */ 1519 for (i = 0; i < sc->num_iss; i++) 1520 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1521 for (i = 0; i < sc->num_oss; i++) 1522 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1523 for (i = 0; i < sc->num_bss; i++) 1524 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1525 1526 /* 1527 * Stop Control DMA engines. 1528 */ 1529 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1530 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1531 1532 /* 1533 * Reset DMA position buffer. 1534 */ 1535 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1536 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1537 1538 /* 1539 * Reset the controller. The reset must remain asserted for 1540 * a minimum of 100us. 1541 */ 1542 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1543 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1544 count = 10000; 1545 do { 1546 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1547 if (!(gctl & HDAC_GCTL_CRST)) 1548 break; 1549 DELAY(10); 1550 } while (--count); 1551 if (gctl & HDAC_GCTL_CRST) { 1552 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1553 return (ENXIO); 1554 } 1555 1556 /* If wakeup is not requested - leave the controller in reset state. */ 1557 if (!wakeup) 1558 return (0); 1559 1560 DELAY(100); 1561 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1562 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1563 count = 10000; 1564 do { 1565 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1566 if (gctl & HDAC_GCTL_CRST) 1567 break; 1568 DELAY(10); 1569 } while (--count); 1570 if (!(gctl & HDAC_GCTL_CRST)) { 1571 device_printf(sc->dev, "Device stuck in reset\n"); 1572 return (ENXIO); 1573 } 1574 1575 /* 1576 * Wait for codecs to finish their own reset sequence. The delay here 1577 * should be of 250us but for some reasons, on it's not enough on my 1578 * computer. Let's use twice as much as necessary to make sure that 1579 * it's reset properly. 1580 */ 1581 DELAY(1000); 1582 1583 return (0); 1584 } 1585 1586 1587 /**************************************************************************** 1588 * int hdac_get_capabilities(struct hdac_softc *); 1589 * 1590 * Retreive the general capabilities of the hdac; 1591 * Number of Input Streams 1592 * Number of Output Streams 1593 * Number of bidirectional Streams 1594 * 64bit ready 1595 * CORB and RIRB sizes 1596 ****************************************************************************/ 1597 static int 1598 hdac_get_capabilities(struct hdac_softc *sc) 1599 { 1600 uint16_t gcap; 1601 uint8_t corbsize, rirbsize; 1602 1603 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1604 sc->num_iss = HDAC_GCAP_ISS(gcap); 1605 sc->num_oss = HDAC_GCAP_OSS(gcap); 1606 sc->num_bss = HDAC_GCAP_BSS(gcap); 1607 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1608 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1609 1610 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1611 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1612 HDAC_CORBSIZE_CORBSZCAP_256) 1613 sc->corb_size = 256; 1614 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1615 HDAC_CORBSIZE_CORBSZCAP_16) 1616 sc->corb_size = 16; 1617 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1618 HDAC_CORBSIZE_CORBSZCAP_2) 1619 sc->corb_size = 2; 1620 else { 1621 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1622 __func__, corbsize); 1623 return (ENXIO); 1624 } 1625 1626 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1627 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1628 HDAC_RIRBSIZE_RIRBSZCAP_256) 1629 sc->rirb_size = 256; 1630 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1631 HDAC_RIRBSIZE_RIRBSZCAP_16) 1632 sc->rirb_size = 16; 1633 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1634 HDAC_RIRBSIZE_RIRBSZCAP_2) 1635 sc->rirb_size = 2; 1636 else { 1637 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1638 __func__, rirbsize); 1639 return (ENXIO); 1640 } 1641 1642 HDA_BOOTVERBOSE( 1643 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1644 "NSDO %d%s, CORB %d, RIRB %d\n", 1645 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1646 sc->support_64bit ? ", 64bit" : "", 1647 sc->corb_size, sc->rirb_size); 1648 ); 1649 1650 return (0); 1651 } 1652 1653 1654 /**************************************************************************** 1655 * void hdac_dma_cb 1656 * 1657 * This function is called by bus_dmamap_load when the mapping has been 1658 * established. We just record the physical address of the mapping into 1659 * the struct hdac_dma passed in. 1660 ****************************************************************************/ 1661 static void 1662 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1663 { 1664 struct hdac_dma *dma; 1665 1666 if (error == 0) { 1667 dma = (struct hdac_dma *)callback_arg; 1668 dma->dma_paddr = segs[0].ds_addr; 1669 } 1670 } 1671 1672 1673 /**************************************************************************** 1674 * int hdac_dma_alloc 1675 * 1676 * This function allocate and setup a dma region (struct hdac_dma). 1677 * It must be freed by a corresponding hdac_dma_free. 1678 ****************************************************************************/ 1679 static int 1680 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1681 { 1682 bus_size_t roundsz; 1683 int result; 1684 1685 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1686 bzero(dma, sizeof(*dma)); 1687 1688 /* 1689 * Create a DMA tag 1690 */ 1691 result = bus_dma_tag_create( 1692 bus_get_dma_tag(sc->dev), /* parent */ 1693 HDAC_DMA_ALIGNMENT, /* alignment */ 1694 0, /* boundary */ 1695 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1696 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1697 BUS_SPACE_MAXADDR, /* highaddr */ 1698 NULL, /* filtfunc */ 1699 NULL, /* fistfuncarg */ 1700 roundsz, /* maxsize */ 1701 1, /* nsegments */ 1702 roundsz, /* maxsegsz */ 1703 0, /* flags */ 1704 NULL, /* lockfunc */ 1705 NULL, /* lockfuncarg */ 1706 &dma->dma_tag); /* dmat */ 1707 if (result != 0) { 1708 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1709 __func__, result); 1710 goto hdac_dma_alloc_fail; 1711 } 1712 1713 /* 1714 * Allocate DMA memory 1715 */ 1716 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1717 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1718 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1719 &dma->dma_map); 1720 if (result != 0) { 1721 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1722 __func__, result); 1723 goto hdac_dma_alloc_fail; 1724 } 1725 1726 dma->dma_size = roundsz; 1727 1728 /* 1729 * Map the memory 1730 */ 1731 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1732 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1733 if (result != 0 || dma->dma_paddr == 0) { 1734 if (result == 0) 1735 result = ENOMEM; 1736 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1737 __func__, result); 1738 goto hdac_dma_alloc_fail; 1739 } 1740 1741 HDA_BOOTHVERBOSE( 1742 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1743 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1744 ); 1745 1746 return (0); 1747 1748 hdac_dma_alloc_fail: 1749 hdac_dma_free(sc, dma); 1750 1751 return (result); 1752 } 1753 1754 1755 /**************************************************************************** 1756 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1757 * 1758 * Free a struct dhac_dma that has been previously allocated via the 1759 * hdac_dma_alloc function. 1760 ****************************************************************************/ 1761 static void 1762 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1763 { 1764 if (dma->dma_map != NULL) { 1765 #if 0 1766 /* Flush caches */ 1767 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1768 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1769 #endif 1770 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1771 } 1772 if (dma->dma_vaddr != NULL) { 1773 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1774 dma->dma_vaddr = NULL; 1775 } 1776 dma->dma_map = NULL; 1777 if (dma->dma_tag != NULL) { 1778 bus_dma_tag_destroy(dma->dma_tag); 1779 dma->dma_tag = NULL; 1780 } 1781 dma->dma_size = 0; 1782 } 1783 1784 /**************************************************************************** 1785 * int hdac_mem_alloc(struct hdac_softc *) 1786 * 1787 * Allocate all the bus resources necessary to speak with the physical 1788 * controller. 1789 ****************************************************************************/ 1790 static int 1791 hdac_mem_alloc(struct hdac_softc *sc) 1792 { 1793 struct hdac_mem *mem; 1794 1795 mem = &sc->mem; 1796 mem->mem_rid = PCIR_BAR(0); 1797 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1798 &mem->mem_rid, RF_ACTIVE); 1799 if (mem->mem_res == NULL) { 1800 device_printf(sc->dev, 1801 "%s: Unable to allocate memory resource\n", __func__); 1802 return (ENOMEM); 1803 } 1804 mem->mem_tag = rman_get_bustag(mem->mem_res); 1805 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1806 1807 return (0); 1808 } 1809 1810 /**************************************************************************** 1811 * void hdac_mem_free(struct hdac_softc *) 1812 * 1813 * Free up resources previously allocated by hdac_mem_alloc. 1814 ****************************************************************************/ 1815 static void 1816 hdac_mem_free(struct hdac_softc *sc) 1817 { 1818 struct hdac_mem *mem; 1819 1820 mem = &sc->mem; 1821 if (mem->mem_res != NULL) 1822 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1823 mem->mem_res); 1824 mem->mem_res = NULL; 1825 } 1826 1827 /**************************************************************************** 1828 * int hdac_irq_alloc(struct hdac_softc *) 1829 * 1830 * Allocate and setup the resources necessary for interrupt handling. 1831 ****************************************************************************/ 1832 static int 1833 hdac_irq_alloc(struct hdac_softc *sc) 1834 { 1835 struct hdac_irq *irq; 1836 int result; 1837 1838 irq = &sc->irq; 1839 irq->irq_rid = 0x0; 1840 1841 if ((sc->flags & HDAC_F_MSI) && 1842 (result = pci_msi_count(sc->dev)) == 1 && 1843 pci_alloc_msi(sc->dev, &result) == 0) 1844 irq->irq_rid = 0x1; 1845 else 1846 sc->flags &= ~HDAC_F_MSI; 1847 1848 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1849 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1850 if (irq->irq_res == NULL) { 1851 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1852 __func__); 1853 goto hdac_irq_alloc_fail; 1854 } 1855 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1856 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1857 if (result != 0) { 1858 device_printf(sc->dev, 1859 "%s: Unable to setup interrupt handler (%x)\n", 1860 __func__, result); 1861 goto hdac_irq_alloc_fail; 1862 } 1863 1864 return (0); 1865 1866 hdac_irq_alloc_fail: 1867 hdac_irq_free(sc); 1868 1869 return (ENXIO); 1870 } 1871 1872 /**************************************************************************** 1873 * void hdac_irq_free(struct hdac_softc *) 1874 * 1875 * Free up resources previously allocated by hdac_irq_alloc. 1876 ****************************************************************************/ 1877 static void 1878 hdac_irq_free(struct hdac_softc *sc) 1879 { 1880 struct hdac_irq *irq; 1881 1882 irq = &sc->irq; 1883 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1884 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1885 if (irq->irq_res != NULL) 1886 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1887 irq->irq_res); 1888 if (irq->irq_rid == 0x1) 1889 pci_release_msi(sc->dev); 1890 irq->irq_handle = NULL; 1891 irq->irq_res = NULL; 1892 irq->irq_rid = 0x0; 1893 } 1894 1895 /**************************************************************************** 1896 * void hdac_corb_init(struct hdac_softc *) 1897 * 1898 * Initialize the corb registers for operations but do not start it up yet. 1899 * The CORB engine must not be running when this function is called. 1900 ****************************************************************************/ 1901 static void 1902 hdac_corb_init(struct hdac_softc *sc) 1903 { 1904 uint8_t corbsize; 1905 uint64_t corbpaddr; 1906 1907 /* Setup the CORB size. */ 1908 switch (sc->corb_size) { 1909 case 256: 1910 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1911 break; 1912 case 16: 1913 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1914 break; 1915 case 2: 1916 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1917 break; 1918 default: 1919 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1920 } 1921 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1922 1923 /* Setup the CORB Address in the hdac */ 1924 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1925 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1926 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1927 1928 /* Set the WP and RP */ 1929 sc->corb_wp = 0; 1930 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1931 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1932 /* 1933 * The HDA specification indicates that the CORBRPRST bit will always 1934 * read as zero. Unfortunately, it seems that at least the 82801G 1935 * doesn't reset the bit to zero, which stalls the corb engine. 1936 * manually reset the bit to zero before continuing. 1937 */ 1938 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1939 1940 /* Enable CORB error reporting */ 1941 #if 0 1942 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1943 #endif 1944 } 1945 1946 /**************************************************************************** 1947 * void hdac_rirb_init(struct hdac_softc *) 1948 * 1949 * Initialize the rirb registers for operations but do not start it up yet. 1950 * The RIRB engine must not be running when this function is called. 1951 ****************************************************************************/ 1952 static void 1953 hdac_rirb_init(struct hdac_softc *sc) 1954 { 1955 uint8_t rirbsize; 1956 uint64_t rirbpaddr; 1957 1958 /* Setup the RIRB size. */ 1959 switch (sc->rirb_size) { 1960 case 256: 1961 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1962 break; 1963 case 16: 1964 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1965 break; 1966 case 2: 1967 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1968 break; 1969 default: 1970 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1971 } 1972 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1973 1974 /* Setup the RIRB Address in the hdac */ 1975 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1976 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1977 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1978 1979 /* Setup the WP and RP */ 1980 sc->rirb_rp = 0; 1981 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1982 1983 /* Setup the interrupt threshold */ 1984 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1985 1986 /* Enable Overrun and response received reporting */ 1987 #if 0 1988 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1989 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1990 #else 1991 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1992 #endif 1993 1994 #if 0 1995 /* 1996 * Make sure that the Host CPU cache doesn't contain any dirty 1997 * cache lines that falls in the rirb. If I understood correctly, it 1998 * should be sufficient to do this only once as the rirb is purely 1999 * read-only from now on. 2000 */ 2001 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2002 BUS_DMASYNC_PREREAD); 2003 #endif 2004 } 2005 2006 /**************************************************************************** 2007 * void hdac_corb_start(hdac_softc *) 2008 * 2009 * Startup the corb DMA engine 2010 ****************************************************************************/ 2011 static void 2012 hdac_corb_start(struct hdac_softc *sc) 2013 { 2014 uint32_t corbctl; 2015 2016 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 2017 corbctl |= HDAC_CORBCTL_CORBRUN; 2018 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 2019 } 2020 2021 /**************************************************************************** 2022 * void hdac_rirb_start(hdac_softc *) 2023 * 2024 * Startup the rirb DMA engine 2025 ****************************************************************************/ 2026 static void 2027 hdac_rirb_start(struct hdac_softc *sc) 2028 { 2029 uint32_t rirbctl; 2030 2031 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 2032 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 2033 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 2034 } 2035 2036 2037 /**************************************************************************** 2038 * void hdac_scan_codecs(struct hdac_softc *, int) 2039 * 2040 * Scan the bus for available codecs, starting with num. 2041 ****************************************************************************/ 2042 static void 2043 hdac_scan_codecs(struct hdac_softc *sc) 2044 { 2045 struct hdac_codec *codec; 2046 int i; 2047 uint16_t statests; 2048 2049 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 2050 for (i = 0; i < HDAC_CODEC_MAX; i++) { 2051 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 2052 /* We have found a codec. */ 2053 codec = (struct hdac_codec *)malloc(sizeof(*codec), 2054 M_HDAC, M_ZERO | M_NOWAIT); 2055 if (codec == NULL) { 2056 device_printf(sc->dev, 2057 "Unable to allocate memory for codec\n"); 2058 continue; 2059 } 2060 codec->commands = NULL; 2061 codec->responses_received = 0; 2062 codec->verbs_sent = 0; 2063 codec->sc = sc; 2064 codec->cad = i; 2065 sc->codecs[i] = codec; 2066 hdac_probe_codec(codec); 2067 } 2068 } 2069 /* All codecs have been probed, now try to attach drivers to them */ 2070 /* bus_generic_attach(sc->dev); */ 2071 } 2072 2073 /**************************************************************************** 2074 * void hdac_probe_codec(struct hdac_softc *, int) 2075 * 2076 * Probe a the given codec_id for available function groups. 2077 ****************************************************************************/ 2078 static void 2079 hdac_probe_codec(struct hdac_codec *codec) 2080 { 2081 struct hdac_softc *sc = codec->sc; 2082 uint32_t vendorid, revisionid, subnode; 2083 int startnode; 2084 int endnode; 2085 int i; 2086 nid_t cad = codec->cad; 2087 2088 HDA_BOOTVERBOSE( 2089 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2090 ); 2091 vendorid = hdac_command(sc, 2092 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2093 cad); 2094 revisionid = hdac_command(sc, 2095 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2096 cad); 2097 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2098 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2099 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2100 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2101 2102 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2103 device_printf(sc->dev, "Codec #%d is not responding!" 2104 " Probing aborted.\n", cad); 2105 return; 2106 } 2107 2108 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2109 cad, hdac_codec_name(codec)); 2110 HDA_BOOTVERBOSE( 2111 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2112 hdac_codec_id(codec)); 2113 device_printf(sc->dev, " Vendor: 0x%04x\n", 2114 codec->vendor_id); 2115 device_printf(sc->dev, " Device: 0x%04x\n", 2116 codec->device_id); 2117 device_printf(sc->dev, " Revision: 0x%02x\n", 2118 codec->revision_id); 2119 device_printf(sc->dev, " Stepping: 0x%02x\n", 2120 codec->stepping_id); 2121 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2122 sc->pci_subvendor); 2123 ); 2124 subnode = hdac_command(sc, 2125 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2126 cad); 2127 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2128 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2129 2130 HDA_BOOTHVERBOSE( 2131 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2132 startnode, endnode); 2133 ); 2134 2135 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2136 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2137 if (codec->fgs == NULL) { 2138 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2139 __func__); 2140 return; 2141 } 2142 2143 for (i = startnode; i < endnode; i++) 2144 hdac_probe_function(codec, i); 2145 return; 2146 } 2147 2148 /* 2149 * Probe codec function and add it to the list. 2150 */ 2151 static void 2152 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2153 { 2154 struct hdac_softc *sc = codec->sc; 2155 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2156 uint32_t fctgrptype; 2157 uint32_t res; 2158 nid_t cad = codec->cad; 2159 2160 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2161 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2162 2163 devinfo->nid = nid; 2164 devinfo->node_type = fctgrptype; 2165 devinfo->codec = codec; 2166 2167 res = hdac_command(sc, 2168 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2169 2170 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2171 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2172 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2173 2174 HDA_BOOTVERBOSE( 2175 device_printf(sc->dev, 2176 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2177 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2178 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2179 "unknown", nid, devinfo->startnode, devinfo->endnode, 2180 devinfo->nodecnt); 2181 ); 2182 2183 if (devinfo->nodecnt > 0) 2184 devinfo->widget = (struct hdac_widget *)malloc( 2185 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2186 M_NOWAIT | M_ZERO); 2187 else 2188 devinfo->widget = NULL; 2189 2190 if (devinfo->widget == NULL) { 2191 device_printf(sc->dev, "unable to allocate widgets!\n"); 2192 devinfo->endnode = devinfo->startnode; 2193 devinfo->nodecnt = 0; 2194 return; 2195 } 2196 2197 codec->num_fgs++; 2198 } 2199 2200 static void 2201 hdac_widget_connection_parse(struct hdac_widget *w) 2202 { 2203 struct hdac_softc *sc = w->devinfo->codec->sc; 2204 uint32_t res; 2205 int i, j, max, ents, entnum; 2206 nid_t cad = w->devinfo->codec->cad; 2207 nid_t nid = w->nid; 2208 nid_t cnid, addcnid, prevcnid; 2209 2210 w->nconns = 0; 2211 2212 res = hdac_command(sc, 2213 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2214 2215 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2216 2217 if (ents < 1) 2218 return; 2219 2220 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2221 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2222 prevcnid = 0; 2223 2224 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2225 #define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2226 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2227 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2228 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2229 2230 for (i = 0; i < ents; i += entnum) { 2231 res = hdac_command(sc, 2232 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2233 for (j = 0; j < entnum; j++) { 2234 cnid = CONN_CNID(res, entnum, j); 2235 if (cnid == 0) { 2236 if (w->nconns < ents) 2237 device_printf(sc->dev, 2238 "%s: nid=%d WARNING: zero cnid " 2239 "entnum=%d j=%d index=%d " 2240 "entries=%d found=%d res=0x%08x\n", 2241 __func__, nid, entnum, j, i, 2242 ents, w->nconns, res); 2243 else 2244 goto getconns_out; 2245 } 2246 if (cnid < w->devinfo->startnode || 2247 cnid >= w->devinfo->endnode) { 2248 HDA_BOOTVERBOSE( 2249 device_printf(sc->dev, 2250 "GHOST: nid=%d j=%d " 2251 "entnum=%d index=%d res=0x%08x\n", 2252 nid, j, entnum, i, res); 2253 ); 2254 } 2255 if (CONN_RANGE(res, entnum, j) == 0) 2256 addcnid = cnid; 2257 else if (prevcnid == 0 || prevcnid >= cnid) { 2258 device_printf(sc->dev, 2259 "%s: WARNING: Invalid child range " 2260 "nid=%d index=%d j=%d entnum=%d " 2261 "prevcnid=%d cnid=%d res=0x%08x\n", 2262 __func__, nid, i, j, entnum, prevcnid, 2263 cnid, res); 2264 addcnid = cnid; 2265 } else 2266 addcnid = prevcnid + 1; 2267 while (addcnid <= cnid) { 2268 if (w->nconns > max) { 2269 device_printf(sc->dev, 2270 "Adding %d (nid=%d): " 2271 "Max connection reached! max=%d\n", 2272 addcnid, nid, max + 1); 2273 goto getconns_out; 2274 } 2275 w->connsenable[w->nconns] = 1; 2276 w->conns[w->nconns++] = addcnid++; 2277 } 2278 prevcnid = cnid; 2279 } 2280 } 2281 2282 getconns_out: 2283 return; 2284 } 2285 2286 static uint32_t 2287 hdac_widget_pin_patch(uint32_t config, const char *str) 2288 { 2289 char buf[256]; 2290 char *key, *value, *rest, *bad; 2291 int ival, i; 2292 2293 strlcpy(buf, str, sizeof(buf)); 2294 rest = buf; 2295 while ((key = strsep(&rest, "=")) != NULL) { 2296 value = strsep(&rest, " \t"); 2297 if (value == NULL) 2298 break; 2299 ival = strtol(value, &bad, 10); 2300 if (strcmp(key, "seq") == 0) { 2301 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2302 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2303 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2304 } else if (strcmp(key, "as") == 0) { 2305 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2306 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2307 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2308 } else if (strcmp(key, "misc") == 0) { 2309 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2310 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2311 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2312 } else if (strcmp(key, "color") == 0) { 2313 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2314 if (bad[0] == 0) { 2315 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2316 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2317 }; 2318 for (i = 0; i < 16; i++) { 2319 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2320 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2321 break; 2322 } 2323 } 2324 } else if (strcmp(key, "ctype") == 0) { 2325 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2326 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2327 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2328 } else if (strcmp(key, "device") == 0) { 2329 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2330 if (bad[0] == 0) { 2331 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2332 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2333 continue; 2334 }; 2335 for (i = 0; i < 16; i++) { 2336 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2337 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2338 break; 2339 } 2340 } 2341 } else if (strcmp(key, "loc") == 0) { 2342 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2343 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2344 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2345 } else if (strcmp(key, "conn") == 0) { 2346 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2347 if (bad[0] == 0) { 2348 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2349 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2350 continue; 2351 }; 2352 for (i = 0; i < 4; i++) { 2353 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2354 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2355 break; 2356 } 2357 } 2358 } 2359 } 2360 return (config); 2361 } 2362 2363 static uint32_t 2364 hdac_widget_pin_getconfig(struct hdac_widget *w) 2365 { 2366 struct hdac_softc *sc; 2367 uint32_t config, orig, id; 2368 nid_t cad, nid; 2369 char buf[32]; 2370 const char *res = NULL, *patch = NULL; 2371 2372 sc = w->devinfo->codec->sc; 2373 cad = w->devinfo->codec->cad; 2374 nid = w->nid; 2375 id = hdac_codec_id(w->devinfo->codec); 2376 2377 config = hdac_command(sc, 2378 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2379 cad); 2380 orig = config; 2381 2382 HDA_BOOTVERBOSE( 2383 hdac_dump_pin_config(w, orig); 2384 ); 2385 2386 /* XXX: Old patches require complete review. 2387 * Now they may create more problem then solve due to 2388 * incorrect associations. 2389 */ 2390 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2391 switch (nid) { 2392 case 26: 2393 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2394 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2395 break; 2396 case 27: 2397 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2398 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2399 break; 2400 default: 2401 break; 2402 } 2403 } else if (id == HDA_CODEC_ALC880 && 2404 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2405 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2406 /* 2407 * Super broken BIOS 2408 */ 2409 switch (nid) { 2410 case 24: /* MIC1 */ 2411 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2412 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2413 break; 2414 case 25: /* XXX MIC2 */ 2415 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2416 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2417 break; 2418 case 26: /* LINE1 */ 2419 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2420 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2421 break; 2422 case 27: /* XXX LINE2 */ 2423 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2424 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2425 break; 2426 case 28: /* CD */ 2427 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2428 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2429 break; 2430 } 2431 } else if (id == HDA_CODEC_ALC883 && 2432 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2433 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2434 switch (nid) { 2435 case 25: 2436 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2437 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2438 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2439 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2440 break; 2441 case 28: 2442 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2443 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2444 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2445 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2446 break; 2447 } 2448 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2449 HP_V3000_SUBVENDOR) { 2450 switch (nid) { 2451 case 18: 2452 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2453 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2454 break; 2455 case 20: 2456 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2457 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2458 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2459 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2460 break; 2461 case 21: 2462 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2463 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2464 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2465 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2466 break; 2467 } 2468 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2469 HP_DV5000_SUBVENDOR) { 2470 switch (nid) { 2471 case 20: 2472 case 21: 2473 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2474 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2475 break; 2476 } 2477 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2478 ASUS_W6F_SUBVENDOR) { 2479 switch (nid) { 2480 case 11: 2481 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2482 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2483 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2484 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2485 break; 2486 case 12: 2487 case 14: 2488 case 16: 2489 case 31: 2490 case 32: 2491 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2492 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2493 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2494 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2495 break; 2496 case 15: 2497 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2498 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2499 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2500 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2501 break; 2502 } 2503 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2504 UNIWILL_9075_SUBVENDOR) { 2505 switch (nid) { 2506 case 15: 2507 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2508 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2509 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2510 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2511 break; 2512 } 2513 } 2514 2515 /* New patches */ 2516 if (id == HDA_CODEC_AD1986A && 2517 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2518 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2519 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2520 switch (nid) { 2521 case 26: /* Headphones with redirection */ 2522 patch = "as=1 seq=15"; 2523 break; 2524 case 28: /* 5.1 out => 2.0 out + 1 input */ 2525 patch = "device=Line-in as=8 seq=1"; 2526 break; 2527 case 29: /* Can't use this as input, as the only available mic 2528 * preamplifier is busy by front panel mic (nid 31). 2529 * If you want to use this rear connector as mic input, 2530 * you have to disable the front panel one. */ 2531 patch = "as=0"; 2532 break; 2533 case 31: /* Lot of inputs configured with as=15 and unusable */ 2534 patch = "as=8 seq=3"; 2535 break; 2536 case 32: 2537 patch = "as=8 seq=4"; 2538 break; 2539 case 34: 2540 patch = "as=8 seq=5"; 2541 break; 2542 case 36: 2543 patch = "as=8 seq=6"; 2544 break; 2545 } 2546 } else if (id == HDA_CODEC_ALC260 && 2547 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2548 switch (nid) { 2549 case 16: 2550 patch = "seq=15 device=Headphones"; 2551 break; 2552 } 2553 } else if (id == HDA_CODEC_ALC268) { 2554 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2555 switch (nid) { 2556 case 20: /* Headphones Jack */ 2557 patch = "as=1 seq=15"; 2558 break; 2559 } 2560 } 2561 } 2562 2563 if (patch != NULL) 2564 config = hdac_widget_pin_patch(config, patch); 2565 2566 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2567 if (resource_string_value(device_get_name(sc->dev), 2568 device_get_unit(sc->dev), buf, &res) == 0) { 2569 if (strncmp(res, "0x", 2) == 0) { 2570 config = strtol(res + 2, NULL, 16); 2571 } else { 2572 config = hdac_widget_pin_patch(config, res); 2573 } 2574 } 2575 2576 HDA_BOOTVERBOSE( 2577 if (config != orig) 2578 device_printf(sc->dev, 2579 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2580 nid, orig, config); 2581 ); 2582 2583 return (config); 2584 } 2585 2586 static uint32_t 2587 hdac_widget_pin_getcaps(struct hdac_widget *w) 2588 { 2589 struct hdac_softc *sc; 2590 uint32_t caps, orig, id; 2591 nid_t cad, nid; 2592 2593 sc = w->devinfo->codec->sc; 2594 cad = w->devinfo->codec->cad; 2595 nid = w->nid; 2596 id = hdac_codec_id(w->devinfo->codec); 2597 2598 caps = hdac_command(sc, 2599 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2600 orig = caps; 2601 2602 HDA_BOOTVERBOSE( 2603 if (caps != orig) 2604 device_printf(sc->dev, 2605 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2606 nid, orig, caps); 2607 ); 2608 2609 return (caps); 2610 } 2611 2612 static void 2613 hdac_widget_pin_parse(struct hdac_widget *w) 2614 { 2615 struct hdac_softc *sc = w->devinfo->codec->sc; 2616 uint32_t config, pincap; 2617 const char *devstr; 2618 nid_t cad = w->devinfo->codec->cad; 2619 nid_t nid = w->nid; 2620 int conn, color; 2621 2622 config = hdac_widget_pin_getconfig(w); 2623 w->wclass.pin.config = config; 2624 2625 pincap = hdac_widget_pin_getcaps(w); 2626 w->wclass.pin.cap = pincap; 2627 2628 w->wclass.pin.ctrl = hdac_command(sc, 2629 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2630 2631 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2632 w->param.eapdbtl = hdac_command(sc, 2633 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2634 w->param.eapdbtl &= 0x7; 2635 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2636 } else 2637 w->param.eapdbtl = HDAC_INVALID; 2638 2639 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2640 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2641 2642 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2643 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2644 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2645 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2646 2647 strlcat(w->name, ": ", sizeof(w->name)); 2648 strlcat(w->name, devstr, sizeof(w->name)); 2649 strlcat(w->name, " (", sizeof(w->name)); 2650 if (conn == 0 && color != 0 && color != 15) { 2651 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2652 strlcat(w->name, " ", sizeof(w->name)); 2653 } 2654 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2655 strlcat(w->name, ")", sizeof(w->name)); 2656 } 2657 2658 static uint32_t 2659 hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2660 { 2661 struct hdac_softc *sc; 2662 uint32_t caps, orig, id; 2663 nid_t cad, nid, beeper = -1; 2664 2665 sc = w->devinfo->codec->sc; 2666 cad = w->devinfo->codec->cad; 2667 nid = w->nid; 2668 id = hdac_codec_id(w->devinfo->codec); 2669 2670 caps = hdac_command(sc, 2671 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2672 cad); 2673 orig = caps; 2674 2675 /* On some codecs beeper is an input pin, but it is not recordable 2676 alone. Also most of BIOSes does not declare beeper pin. 2677 Change beeper pin node type to beeper to help parser. */ 2678 *waspin = 0; 2679 switch (id) { 2680 case HDA_CODEC_AD1882: 2681 case HDA_CODEC_AD1883: 2682 case HDA_CODEC_AD1984: 2683 case HDA_CODEC_AD1984A: 2684 case HDA_CODEC_AD1984B: 2685 case HDA_CODEC_AD1987: 2686 case HDA_CODEC_AD1988: 2687 case HDA_CODEC_AD1988B: 2688 case HDA_CODEC_AD1989B: 2689 beeper = 26; 2690 break; 2691 case HDA_CODEC_ALC260: 2692 beeper = 23; 2693 break; 2694 case HDA_CODEC_ALC262: 2695 case HDA_CODEC_ALC268: 2696 case HDA_CODEC_ALC880: 2697 case HDA_CODEC_ALC882: 2698 case HDA_CODEC_ALC883: 2699 case HDA_CODEC_ALC885: 2700 case HDA_CODEC_ALC888: 2701 case HDA_CODEC_ALC889: 2702 beeper = 29; 2703 break; 2704 } 2705 if (nid == beeper) { 2706 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2707 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2708 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2709 *waspin = 1; 2710 } 2711 2712 HDA_BOOTVERBOSE( 2713 if (caps != orig) { 2714 device_printf(sc->dev, 2715 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2716 nid, orig, caps); 2717 } 2718 ); 2719 2720 return (caps); 2721 } 2722 2723 static void 2724 hdac_widget_parse(struct hdac_widget *w) 2725 { 2726 struct hdac_softc *sc = w->devinfo->codec->sc; 2727 uint32_t wcap, cap; 2728 char *typestr; 2729 nid_t cad = w->devinfo->codec->cad; 2730 nid_t nid = w->nid; 2731 2732 wcap = hdac_widget_getcaps(w, &w->waspin); 2733 2734 w->param.widget_cap = wcap; 2735 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2736 2737 switch (w->type) { 2738 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2739 typestr = "audio output"; 2740 break; 2741 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2742 typestr = "audio input"; 2743 break; 2744 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2745 typestr = "audio mixer"; 2746 break; 2747 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2748 typestr = "audio selector"; 2749 break; 2750 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2751 typestr = "pin"; 2752 break; 2753 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2754 typestr = "power widget"; 2755 break; 2756 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2757 typestr = "volume widget"; 2758 break; 2759 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2760 typestr = "beep widget"; 2761 break; 2762 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2763 typestr = "vendor widget"; 2764 break; 2765 default: 2766 typestr = "unknown type"; 2767 break; 2768 } 2769 2770 strlcpy(w->name, typestr, sizeof(w->name)); 2771 2772 hdac_widget_connection_parse(w); 2773 2774 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2775 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2776 w->param.outamp_cap = 2777 hdac_command(sc, 2778 HDA_CMD_GET_PARAMETER(cad, nid, 2779 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2780 else 2781 w->param.outamp_cap = 2782 w->devinfo->function.audio.outamp_cap; 2783 } else 2784 w->param.outamp_cap = 0; 2785 2786 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2787 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2788 w->param.inamp_cap = 2789 hdac_command(sc, 2790 HDA_CMD_GET_PARAMETER(cad, nid, 2791 HDA_PARAM_INPUT_AMP_CAP), cad); 2792 else 2793 w->param.inamp_cap = 2794 w->devinfo->function.audio.inamp_cap; 2795 } else 2796 w->param.inamp_cap = 0; 2797 2798 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2799 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2800 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2801 cap = hdac_command(sc, 2802 HDA_CMD_GET_PARAMETER(cad, nid, 2803 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2804 w->param.supp_stream_formats = (cap != 0) ? cap : 2805 w->devinfo->function.audio.supp_stream_formats; 2806 cap = hdac_command(sc, 2807 HDA_CMD_GET_PARAMETER(cad, nid, 2808 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2809 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2810 w->devinfo->function.audio.supp_pcm_size_rate; 2811 } else { 2812 w->param.supp_stream_formats = 2813 w->devinfo->function.audio.supp_stream_formats; 2814 w->param.supp_pcm_size_rate = 2815 w->devinfo->function.audio.supp_pcm_size_rate; 2816 } 2817 } else { 2818 w->param.supp_stream_formats = 0; 2819 w->param.supp_pcm_size_rate = 0; 2820 } 2821 2822 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2823 hdac_widget_pin_parse(w); 2824 } 2825 2826 static struct hdac_widget * 2827 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2828 { 2829 if (devinfo == NULL || devinfo->widget == NULL || 2830 nid < devinfo->startnode || nid >= devinfo->endnode) 2831 return (NULL); 2832 return (&devinfo->widget[nid - devinfo->startnode]); 2833 } 2834 2835 static __inline int 2836 hda_poll_channel(struct hdac_chan *ch) 2837 { 2838 uint32_t sz, delta; 2839 volatile uint32_t ptr; 2840 2841 if (!(ch->flags & HDAC_CHN_RUNNING)) 2842 return (0); 2843 2844 sz = ch->blksz * ch->blkcnt; 2845 if (ch->dmapos != NULL) 2846 ptr = *(ch->dmapos); 2847 else 2848 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2849 ch->off + HDAC_SDLPIB); 2850 ch->ptr = ptr; 2851 ptr %= sz; 2852 ptr &= ~(ch->blksz - 1); 2853 delta = (sz + ptr - ch->prevptr) % sz; 2854 2855 if (delta < ch->blksz) 2856 return (0); 2857 2858 ch->prevptr = ptr; 2859 2860 return (1); 2861 } 2862 2863 static void 2864 hda_poll_callback(void *arg) 2865 { 2866 struct hdac_softc *sc = arg; 2867 uint32_t trigger; 2868 int i, active = 0; 2869 2870 if (sc == NULL) 2871 return; 2872 2873 hdac_lock(sc); 2874 if (sc->polling == 0) { 2875 hdac_unlock(sc); 2876 return; 2877 } 2878 2879 trigger = 0; 2880 for (i = 0; i < sc->num_chans; i++) { 2881 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2882 continue; 2883 active = 1; 2884 if (hda_poll_channel(&sc->chans[i])) 2885 trigger |= (1 << i); 2886 } 2887 2888 /* XXX */ 2889 if (active) 2890 callout_reset(&sc->poll_hda, sc->poll_ticks, 2891 hda_poll_callback, sc); 2892 2893 hdac_unlock(sc); 2894 2895 for (i = 0; i < sc->num_chans; i++) { 2896 if (trigger & (1 << i)) 2897 chn_intr(sc->chans[i].c); 2898 } 2899 } 2900 2901 static int 2902 hdac_rirb_flush(struct hdac_softc *sc) 2903 { 2904 struct hdac_rirb *rirb_base, *rirb; 2905 struct hdac_codec *codec; 2906 struct hdac_command_list *commands; 2907 nid_t cad; 2908 uint32_t resp; 2909 uint8_t rirbwp; 2910 int ret; 2911 2912 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2913 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2914 #if 0 2915 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2916 BUS_DMASYNC_POSTREAD); 2917 #endif 2918 2919 ret = 0; 2920 2921 while (sc->rirb_rp != rirbwp) { 2922 sc->rirb_rp++; 2923 sc->rirb_rp %= sc->rirb_size; 2924 rirb = &rirb_base[sc->rirb_rp]; 2925 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2926 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2927 sc->codecs[cad] == NULL) 2928 continue; 2929 resp = rirb->response; 2930 codec = sc->codecs[cad]; 2931 commands = codec->commands; 2932 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2933 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2934 ((resp >> 26) & 0xffff); 2935 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2936 } else if (commands != NULL && commands->num_commands > 0 && 2937 codec->responses_received < commands->num_commands) 2938 commands->responses[codec->responses_received++] = 2939 resp; 2940 ret++; 2941 } 2942 2943 return (ret); 2944 } 2945 2946 static int 2947 hdac_unsolq_flush(struct hdac_softc *sc) 2948 { 2949 nid_t cad; 2950 uint32_t tag; 2951 int ret = 0; 2952 2953 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2954 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2955 while (sc->unsolq_rp != sc->unsolq_wp) { 2956 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2957 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2958 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2959 hdac_unsolicited_handler(sc->codecs[cad], tag); 2960 ret++; 2961 } 2962 sc->unsolq_st = HDAC_UNSOLQ_READY; 2963 } 2964 2965 return (ret); 2966 } 2967 2968 static void 2969 hdac_poll_callback(void *arg) 2970 { 2971 struct hdac_softc *sc = arg; 2972 if (sc == NULL) 2973 return; 2974 2975 hdac_lock(sc); 2976 if (sc->polling == 0 || sc->poll_ival == 0) { 2977 hdac_unlock(sc); 2978 return; 2979 } 2980 if (hdac_rirb_flush(sc) != 0) 2981 hdac_unsolq_flush(sc); 2982 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2983 hdac_unlock(sc); 2984 } 2985 2986 static void 2987 hdac_poll_reinit(struct hdac_softc *sc) 2988 { 2989 int i, pollticks, min = 1000000; 2990 struct hdac_chan *ch; 2991 2992 for (i = 0; i < sc->num_chans; i++) { 2993 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2994 continue; 2995 ch = &sc->chans[i]; 2996 pollticks = ((uint64_t)hz * ch->blksz) / 2997 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2998 pollticks >>= 1; 2999 if (pollticks > hz) 3000 pollticks = hz; 3001 if (pollticks < 1) { 3002 HDA_BOOTVERBOSE( 3003 device_printf(sc->dev, 3004 "%s: pollticks=%d < 1 !\n", 3005 __func__, pollticks); 3006 ); 3007 pollticks = 1; 3008 } 3009 if (min > pollticks) 3010 min = pollticks; 3011 } 3012 HDA_BOOTVERBOSE( 3013 device_printf(sc->dev, 3014 "%s: pollticks %d -> %d\n", 3015 __func__, sc->poll_ticks, min); 3016 ); 3017 sc->poll_ticks = min; 3018 if (min == 1000000) 3019 callout_stop(&sc->poll_hda); 3020 else 3021 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 3022 } 3023 3024 static void 3025 hdac_stream_stop(struct hdac_chan *ch) 3026 { 3027 struct hdac_softc *sc = ch->devinfo->codec->sc; 3028 uint32_t ctl; 3029 3030 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3031 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3032 HDAC_SDCTL_RUN); 3033 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3034 3035 ch->flags &= ~HDAC_CHN_RUNNING; 3036 3037 if (sc->polling != 0) 3038 hdac_poll_reinit(sc); 3039 3040 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3041 ctl &= ~(1 << (ch->off >> 5)); 3042 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3043 } 3044 3045 static void 3046 hdac_stream_start(struct hdac_chan *ch) 3047 { 3048 struct hdac_softc *sc = ch->devinfo->codec->sc; 3049 uint32_t ctl; 3050 3051 ch->flags |= HDAC_CHN_RUNNING; 3052 3053 if (sc->polling != 0) 3054 hdac_poll_reinit(sc); 3055 3056 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3057 ctl |= 1 << (ch->off >> 5); 3058 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3059 3060 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3061 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3062 HDAC_SDCTL_RUN; 3063 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3064 } 3065 3066 static void 3067 hdac_stream_reset(struct hdac_chan *ch) 3068 { 3069 struct hdac_softc *sc = ch->devinfo->codec->sc; 3070 int timeout = 1000; 3071 int to = timeout; 3072 uint32_t ctl; 3073 3074 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3075 ctl |= HDAC_SDCTL_SRST; 3076 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3077 do { 3078 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3079 if (ctl & HDAC_SDCTL_SRST) 3080 break; 3081 DELAY(10); 3082 } while (--to); 3083 if (!(ctl & HDAC_SDCTL_SRST)) { 3084 device_printf(sc->dev, "timeout in reset\n"); 3085 } 3086 ctl &= ~HDAC_SDCTL_SRST; 3087 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3088 to = timeout; 3089 do { 3090 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3091 if (!(ctl & HDAC_SDCTL_SRST)) 3092 break; 3093 DELAY(10); 3094 } while (--to); 3095 if (ctl & HDAC_SDCTL_SRST) 3096 device_printf(sc->dev, "can't reset!\n"); 3097 } 3098 3099 static void 3100 hdac_stream_setid(struct hdac_chan *ch) 3101 { 3102 struct hdac_softc *sc = ch->devinfo->codec->sc; 3103 uint32_t ctl; 3104 3105 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3106 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3107 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3108 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3109 } 3110 3111 static void 3112 hdac_bdl_setup(struct hdac_chan *ch) 3113 { 3114 struct hdac_softc *sc = ch->devinfo->codec->sc; 3115 struct hdac_bdle *bdle; 3116 uint64_t addr; 3117 uint32_t blksz, blkcnt; 3118 int i; 3119 3120 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3121 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3122 3123 blksz = ch->blksz; 3124 blkcnt = ch->blkcnt; 3125 3126 for (i = 0; i < blkcnt; i++, bdle++) { 3127 bdle->addrl = (uint32_t)addr; 3128 bdle->addrh = (uint32_t)(addr >> 32); 3129 bdle->len = blksz; 3130 bdle->ioc = 1; 3131 addr += blksz; 3132 } 3133 3134 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3135 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3136 addr = ch->bdl_dma.dma_paddr; 3137 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3138 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3139 if (ch->dmapos != NULL && 3140 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3141 addr = sc->pos_dma.dma_paddr; 3142 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3143 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3144 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3145 } 3146 } 3147 3148 static int 3149 hdac_bdl_alloc(struct hdac_chan *ch) 3150 { 3151 struct hdac_softc *sc = ch->devinfo->codec->sc; 3152 int rc; 3153 3154 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3155 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3156 if (rc) { 3157 device_printf(sc->dev, "can't alloc bdl\n"); 3158 return (rc); 3159 } 3160 3161 return (0); 3162 } 3163 3164 static void 3165 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3166 int index, int lmute, int rmute, 3167 int left, int right, int dir) 3168 { 3169 uint16_t v = 0; 3170 3171 if (sc == NULL) 3172 return; 3173 3174 if (left != right || lmute != rmute) { 3175 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3176 (lmute << 7) | left; 3177 hdac_command(sc, 3178 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3179 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3180 (rmute << 7) | right; 3181 } else 3182 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3183 (lmute << 7) | left; 3184 3185 hdac_command(sc, 3186 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3187 } 3188 3189 static void 3190 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3191 int left, int right) 3192 { 3193 struct hdac_softc *sc; 3194 nid_t nid, cad; 3195 int lmute, rmute; 3196 3197 sc = ctl->widget->devinfo->codec->sc; 3198 cad = ctl->widget->devinfo->codec->cad; 3199 nid = ctl->widget->nid; 3200 3201 /* Save new values if valid. */ 3202 if (mute != HDA_AMP_MUTE_DEFAULT) 3203 ctl->muted = mute; 3204 if (left != HDA_AMP_VOL_DEFAULT) 3205 ctl->left = left; 3206 if (right != HDA_AMP_VOL_DEFAULT) 3207 ctl->right = right; 3208 /* Prepare effective values */ 3209 if (ctl->forcemute) { 3210 lmute = 1; 3211 rmute = 1; 3212 left = 0; 3213 right = 0; 3214 } else { 3215 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3216 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3217 left = ctl->left; 3218 right = ctl->right; 3219 } 3220 /* Apply effective values */ 3221 if (ctl->dir & HDA_CTL_OUT) 3222 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3223 lmute, rmute, left, right, 0); 3224 if (ctl->dir & HDA_CTL_IN) 3225 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3226 lmute, rmute, left, right, 1); 3227 } 3228 3229 static void 3230 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3231 { 3232 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3233 return; 3234 hdac_command(w->devinfo->codec->sc, 3235 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3236 w->nid, index), w->devinfo->codec->cad); 3237 w->selconn = index; 3238 } 3239 3240 3241 /**************************************************************************** 3242 * uint32_t hdac_command_sendone_internal 3243 * 3244 * Wrapper function that sends only one command to a given codec 3245 ****************************************************************************/ 3246 static uint32_t 3247 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3248 { 3249 struct hdac_command_list cl; 3250 uint32_t response = HDAC_INVALID; 3251 3252 if (!hdac_lockowned(sc)) 3253 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3254 cl.num_commands = 1; 3255 cl.verbs = &verb; 3256 cl.responses = &response; 3257 3258 hdac_command_send_internal(sc, &cl, cad); 3259 3260 return (response); 3261 } 3262 3263 /**************************************************************************** 3264 * hdac_command_send_internal 3265 * 3266 * Send a command list to the codec via the corb. We queue as much verbs as 3267 * we can and msleep on the codec. When the interrupt get the responses 3268 * back from the rirb, it will wake us up so we can queue the remaining verbs 3269 * if any. 3270 ****************************************************************************/ 3271 static void 3272 hdac_command_send_internal(struct hdac_softc *sc, 3273 struct hdac_command_list *commands, nid_t cad) 3274 { 3275 struct hdac_codec *codec; 3276 int corbrp; 3277 uint32_t *corb; 3278 int timeout; 3279 int retry = 10; 3280 struct hdac_rirb *rirb_base; 3281 3282 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3283 commands->num_commands < 1) 3284 return; 3285 3286 codec = sc->codecs[cad]; 3287 codec->commands = commands; 3288 codec->responses_received = 0; 3289 codec->verbs_sent = 0; 3290 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3291 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3292 3293 do { 3294 if (codec->verbs_sent != commands->num_commands) { 3295 /* Queue as many verbs as possible */ 3296 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3297 #if 0 3298 bus_dmamap_sync(sc->corb_dma.dma_tag, 3299 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3300 #endif 3301 while (codec->verbs_sent != commands->num_commands && 3302 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3303 sc->corb_wp++; 3304 sc->corb_wp %= sc->corb_size; 3305 corb[sc->corb_wp] = 3306 commands->verbs[codec->verbs_sent++]; 3307 } 3308 3309 /* Send the verbs to the codecs */ 3310 #if 0 3311 bus_dmamap_sync(sc->corb_dma.dma_tag, 3312 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3313 #endif 3314 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3315 } 3316 3317 timeout = 1000; 3318 while (hdac_rirb_flush(sc) == 0 && --timeout) 3319 DELAY(10); 3320 } while ((codec->verbs_sent != commands->num_commands || 3321 codec->responses_received != commands->num_commands) && --retry); 3322 3323 if (retry == 0) 3324 device_printf(sc->dev, 3325 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3326 __func__, commands->num_commands, codec->verbs_sent, 3327 codec->responses_received); 3328 3329 codec->commands = NULL; 3330 codec->responses_received = 0; 3331 codec->verbs_sent = 0; 3332 3333 hdac_unsolq_flush(sc); 3334 } 3335 3336 3337 /**************************************************************************** 3338 * Device Methods 3339 ****************************************************************************/ 3340 3341 /**************************************************************************** 3342 * int hdac_probe(device_t) 3343 * 3344 * Probe for the presence of an hdac. If none is found, check for a generic 3345 * match using the subclass of the device. 3346 ****************************************************************************/ 3347 static int 3348 hdac_probe(device_t dev) 3349 { 3350 int i, result; 3351 uint32_t model; 3352 uint16_t class, subclass; 3353 char desc[64]; 3354 3355 model = (uint32_t)pci_get_device(dev) << 16; 3356 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3357 class = pci_get_class(dev); 3358 subclass = pci_get_subclass(dev); 3359 3360 bzero(desc, sizeof(desc)); 3361 result = ENXIO; 3362 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3363 if (hdac_devices[i].model == model) { 3364 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3365 result = BUS_PROBE_DEFAULT; 3366 break; 3367 } 3368 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3369 class == PCIC_MULTIMEDIA && 3370 subclass == PCIS_MULTIMEDIA_HDA) { 3371 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3372 result = BUS_PROBE_GENERIC; 3373 break; 3374 } 3375 } 3376 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3377 subclass == PCIS_MULTIMEDIA_HDA) { 3378 strlcpy(desc, "Generic", sizeof(desc)); 3379 result = BUS_PROBE_GENERIC; 3380 } 3381 if (result != ENXIO) { 3382 strlcat(desc, " High Definition Audio Controller", 3383 sizeof(desc)); 3384 device_set_desc_copy(dev, desc); 3385 } 3386 3387 return (result); 3388 } 3389 3390 static void * 3391 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3392 struct pcm_channel *c, int dir) 3393 { 3394 struct hdac_pcm_devinfo *pdevinfo = data; 3395 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3396 struct hdac_softc *sc = devinfo->codec->sc; 3397 struct hdac_chan *ch; 3398 int i, ord = 0, chid; 3399 3400 hdac_lock(sc); 3401 3402 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3403 ch = &sc->chans[chid]; 3404 for (i = 0; i < sc->num_chans && i < chid; i++) { 3405 if (ch->dir == sc->chans[i].dir) 3406 ord++; 3407 } 3408 if (dir == PCMDIR_PLAY) { 3409 ch->off = (sc->num_iss + ord) << 5; 3410 } else { 3411 ch->off = ord << 5; 3412 } 3413 3414 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3415 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3416 ch->pcmrates[0] = 48000; 3417 ch->pcmrates[1] = 0; 3418 } 3419 if (sc->pos_dma.dma_vaddr != NULL) 3420 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3421 (sc->streamcnt * 8)); 3422 else 3423 ch->dmapos = NULL; 3424 ch->sid = ++sc->streamcnt; 3425 ch->dir = dir; 3426 ch->b = b; 3427 ch->c = c; 3428 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3429 ch->blkcnt = pdevinfo->chan_blkcnt; 3430 hdac_unlock(sc); 3431 3432 if (hdac_bdl_alloc(ch) != 0) { 3433 ch->blkcnt = 0; 3434 return (NULL); 3435 } 3436 3437 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3438 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3439 pdevinfo->chan_size) != 0) 3440 return (NULL); 3441 3442 return (ch); 3443 } 3444 3445 static int 3446 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3447 { 3448 struct hdac_chan *ch = data; 3449 int i; 3450 3451 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3452 if (format == ch->caps.fmtlist[i]) { 3453 ch->fmt = format; 3454 return (0); 3455 } 3456 } 3457 3458 return (EINVAL); 3459 } 3460 3461 static uint32_t 3462 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3463 { 3464 struct hdac_chan *ch = data; 3465 uint32_t spd = 0, threshold; 3466 int i; 3467 3468 for (i = 0; ch->pcmrates[i] != 0; i++) { 3469 spd = ch->pcmrates[i]; 3470 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3471 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3472 if (speed < threshold) 3473 break; 3474 } 3475 3476 if (spd == 0) /* impossible */ 3477 ch->spd = 48000; 3478 else 3479 ch->spd = spd; 3480 3481 return (ch->spd); 3482 } 3483 3484 static void 3485 hdac_stream_setup(struct hdac_chan *ch) 3486 { 3487 struct hdac_softc *sc = ch->devinfo->codec->sc; 3488 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3489 struct hdac_widget *w; 3490 int i, chn, totalchn, c; 3491 nid_t cad = ch->devinfo->codec->cad; 3492 uint16_t fmt, dfmt; 3493 uint16_t chmap[2][5] = {{ 0x0010, 0x0001, 0x0201, 0x0231, 0x0231 }, /* 5.1 */ 3494 { 0x0010, 0x0001, 0x2001, 0x2031, 0x2431 }};/* 7.1 */ 3495 int map = -1; 3496 3497 totalchn = AFMT_CHANNEL(ch->fmt); 3498 HDA_BOOTHVERBOSE( 3499 device_printf(ch->pdevinfo->dev, 3500 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3501 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3502 ch->fmt, ch->spd); 3503 ); 3504 fmt = 0; 3505 if (ch->fmt & AFMT_S16_LE) 3506 fmt |= ch->bit16 << 4; 3507 else if (ch->fmt & AFMT_S32_LE) 3508 fmt |= ch->bit32 << 4; 3509 else 3510 fmt |= 1 << 4; 3511 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3512 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3513 fmt |= hda_rate_tab[i].base; 3514 fmt |= hda_rate_tab[i].mul; 3515 fmt |= hda_rate_tab[i].div; 3516 break; 3517 } 3518 } 3519 fmt |= (totalchn - 1); 3520 3521 /* Set channel mapping for known speaker setups. */ 3522 if (as->pinset == 0x0007 || as->pinset == 0x0013) /* Standard 5.1 */ 3523 map = 0; 3524 else if (as->pinset == 0x0017) /* Standard 7.1 */ 3525 map = 1; 3526 3527 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3528 3529 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3530 if (ch->fmt & AFMT_AC3) 3531 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3532 3533 chn = 0; 3534 for (i = 0; ch->io[i] != -1; i++) { 3535 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3536 if (w == NULL) 3537 continue; 3538 3539 /* If HP redirection is enabled, but failed to use same 3540 DAC, make last DAC to duplicate first one. */ 3541 if (as->fakeredir && i == (as->pincnt - 1)) { 3542 c = (ch->sid << 4); 3543 } else { 3544 if (map >= 0) /* Map known speaker setups. */ 3545 chn = (((chmap[map][totalchn / 2] >> i * 4) & 3546 0xf) - 1) * 2; 3547 if (chn < 0 || chn >= totalchn) { 3548 c = 0; 3549 } else { 3550 c = (ch->sid << 4) | chn; 3551 } 3552 } 3553 HDA_BOOTHVERBOSE( 3554 device_printf(ch->pdevinfo->dev, 3555 "PCMDIR_%s: Stream setup nid=%d: " 3556 "fmt=0x%04x, dfmt=0x%04x, chan=0x%04x\n", 3557 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3558 ch->io[i], fmt, dfmt, c); 3559 ); 3560 hdac_command(sc, 3561 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3562 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3563 hdac_command(sc, 3564 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3565 cad); 3566 } 3567 hdac_command(sc, 3568 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3569 #if 0 3570 hdac_command(sc, 3571 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3572 hdac_command(sc, 3573 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3574 hdac_command(sc, 3575 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3576 #endif 3577 chn += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 3578 } 3579 } 3580 3581 /* 3582 * Greatest Common Divisor. 3583 */ 3584 static unsigned 3585 gcd(unsigned a, unsigned b) 3586 { 3587 u_int c; 3588 3589 while (b != 0) { 3590 c = a; 3591 a = b; 3592 b = (c % b); 3593 } 3594 return (a); 3595 } 3596 3597 /* 3598 * Least Common Multiple. 3599 */ 3600 static unsigned 3601 lcm(unsigned a, unsigned b) 3602 { 3603 3604 return ((a * b) / gcd(a, b)); 3605 } 3606 3607 static int 3608 hdac_channel_setfragments(kobj_t obj, void *data, 3609 uint32_t blksz, uint32_t blkcnt) 3610 { 3611 struct hdac_chan *ch = data; 3612 struct hdac_softc *sc = ch->devinfo->codec->sc; 3613 3614 blksz -= blksz % lcm(HDAC_DMA_ALIGNMENT, sndbuf_getalign(ch->b)); 3615 3616 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3617 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3618 if (blksz < HDA_BLK_MIN) 3619 blksz = HDA_BLK_MIN; 3620 if (blkcnt > HDA_BDL_MAX) 3621 blkcnt = HDA_BDL_MAX; 3622 if (blkcnt < HDA_BDL_MIN) 3623 blkcnt = HDA_BDL_MIN; 3624 3625 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3626 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3627 blkcnt >>= 1; 3628 else if ((blksz >> 1) >= HDA_BLK_MIN) 3629 blksz >>= 1; 3630 else 3631 break; 3632 } 3633 3634 if ((sndbuf_getblksz(ch->b) != blksz || 3635 sndbuf_getblkcnt(ch->b) != blkcnt) && 3636 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3637 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3638 __func__, blksz, blkcnt); 3639 3640 ch->blksz = sndbuf_getblksz(ch->b); 3641 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3642 3643 return (0); 3644 } 3645 3646 static uint32_t 3647 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3648 { 3649 struct hdac_chan *ch = data; 3650 3651 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3652 3653 return (ch->blksz); 3654 } 3655 3656 static void 3657 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3658 { 3659 struct hdac_devinfo *devinfo = ch->devinfo; 3660 struct hdac_widget *w; 3661 nid_t cad = devinfo->codec->cad; 3662 int i; 3663 3664 hdac_stream_stop(ch); 3665 3666 for (i = 0; ch->io[i] != -1; i++) { 3667 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3668 if (w == NULL) 3669 continue; 3670 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3671 hdac_command(sc, 3672 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3673 cad); 3674 } 3675 hdac_command(sc, 3676 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3677 0), cad); 3678 } 3679 } 3680 3681 static void 3682 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3683 { 3684 ch->ptr = 0; 3685 ch->prevptr = 0; 3686 hdac_stream_stop(ch); 3687 hdac_stream_reset(ch); 3688 hdac_bdl_setup(ch); 3689 hdac_stream_setid(ch); 3690 hdac_stream_setup(ch); 3691 hdac_stream_start(ch); 3692 } 3693 3694 static int 3695 hdac_channel_trigger(kobj_t obj, void *data, int go) 3696 { 3697 struct hdac_chan *ch = data; 3698 struct hdac_softc *sc = ch->devinfo->codec->sc; 3699 3700 if (!PCMTRIG_COMMON(go)) 3701 return (0); 3702 3703 hdac_lock(sc); 3704 switch (go) { 3705 case PCMTRIG_START: 3706 hdac_channel_start(sc, ch); 3707 break; 3708 case PCMTRIG_STOP: 3709 case PCMTRIG_ABORT: 3710 hdac_channel_stop(sc, ch); 3711 break; 3712 default: 3713 break; 3714 } 3715 hdac_unlock(sc); 3716 3717 return (0); 3718 } 3719 3720 static uint32_t 3721 hdac_channel_getptr(kobj_t obj, void *data) 3722 { 3723 struct hdac_chan *ch = data; 3724 struct hdac_softc *sc = ch->devinfo->codec->sc; 3725 uint32_t ptr; 3726 3727 hdac_lock(sc); 3728 if (sc->polling != 0) 3729 ptr = ch->ptr; 3730 else if (ch->dmapos != NULL) 3731 ptr = *(ch->dmapos); 3732 else 3733 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3734 hdac_unlock(sc); 3735 3736 /* 3737 * Round to available space and force 128 bytes aligment. 3738 */ 3739 ptr %= ch->blksz * ch->blkcnt; 3740 ptr &= HDA_BLK_ALIGN; 3741 3742 return (ptr); 3743 } 3744 3745 static struct pcmchan_caps * 3746 hdac_channel_getcaps(kobj_t obj, void *data) 3747 { 3748 return (&((struct hdac_chan *)data)->caps); 3749 } 3750 3751 static kobj_method_t hdac_channel_methods[] = { 3752 KOBJMETHOD(channel_init, hdac_channel_init), 3753 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3754 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3755 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3756 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3757 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3758 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3759 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3760 KOBJMETHOD_END 3761 }; 3762 CHANNEL_DECLARE(hdac_channel); 3763 3764 static int 3765 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3766 { 3767 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3768 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3769 struct hdac_softc *sc = devinfo->codec->sc; 3770 struct hdac_widget *w, *cw; 3771 struct hdac_audio_ctl *ctl; 3772 uint32_t mask, recmask, id; 3773 int i, j, softpcmvol; 3774 3775 hdac_lock(sc); 3776 3777 /* Make sure that in case of soft volume it won't stay muted. */ 3778 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3779 pdevinfo->left[i] = 100; 3780 pdevinfo->right[i] = 100; 3781 } 3782 3783 mask = 0; 3784 recmask = 0; 3785 id = hdac_codec_id(devinfo->codec); 3786 3787 /* Declate EAPD as ogain control. */ 3788 if (pdevinfo->play >= 0) { 3789 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3790 w = hdac_widget_get(devinfo, i); 3791 if (w == NULL || w->enable == 0) 3792 continue; 3793 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3794 w->param.eapdbtl == HDAC_INVALID || 3795 w->bindas != sc->chans[pdevinfo->play].as) 3796 continue; 3797 mask |= SOUND_MASK_OGAIN; 3798 break; 3799 } 3800 } 3801 3802 /* Declare volume controls assigned to this association. */ 3803 i = 0; 3804 ctl = NULL; 3805 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3806 if (ctl->enable == 0) 3807 continue; 3808 if ((pdevinfo->play >= 0 && 3809 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3810 (pdevinfo->rec >= 0 && 3811 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3812 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3813 mask |= ctl->ossmask; 3814 } 3815 3816 /* Declare record sources available to this association. */ 3817 if (pdevinfo->rec >= 0) { 3818 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3819 for (i = 0; ch->io[i] != -1; i++) { 3820 w = hdac_widget_get(devinfo, ch->io[i]); 3821 if (w == NULL || w->enable == 0) 3822 continue; 3823 for (j = 0; j < w->nconns; j++) { 3824 if (w->connsenable[j] == 0) 3825 continue; 3826 cw = hdac_widget_get(devinfo, w->conns[j]); 3827 if (cw == NULL || cw->enable == 0) 3828 continue; 3829 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3830 cw->bindas != -2) 3831 continue; 3832 recmask |= cw->ossmask; 3833 } 3834 } 3835 } 3836 3837 /* Declare soft PCM volume if needed. */ 3838 if (pdevinfo->play >= 0) { 3839 ctl = NULL; 3840 if ((mask & SOUND_MASK_PCM) == 0 || 3841 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3842 softpcmvol = 1; 3843 mask |= SOUND_MASK_PCM; 3844 } else { 3845 softpcmvol = 0; 3846 i = 0; 3847 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3848 if (ctl->enable == 0) 3849 continue; 3850 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3851 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3852 continue; 3853 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3854 continue; 3855 if (ctl->step > 0) 3856 break; 3857 } 3858 } 3859 3860 if (softpcmvol == 1 || ctl == NULL) { 3861 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3862 HDA_BOOTVERBOSE( 3863 device_printf(pdevinfo->dev, 3864 "%s Soft PCM volume\n", 3865 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3866 ); 3867 } 3868 } 3869 3870 /* Declare master volume if needed. */ 3871 if (pdevinfo->play >= 0) { 3872 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3873 SOUND_MASK_PCM) { 3874 mask |= SOUND_MASK_VOLUME; 3875 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3876 SOUND_MASK_PCM); 3877 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3878 SOUND_MIXER_NONE); 3879 HDA_BOOTVERBOSE( 3880 device_printf(pdevinfo->dev, 3881 "Forcing master volume with PCM\n"); 3882 ); 3883 } 3884 } 3885 3886 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3887 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3888 3889 mix_setrecdevs(m, recmask); 3890 mix_setdevs(m, mask); 3891 3892 hdac_unlock(sc); 3893 3894 return (0); 3895 } 3896 3897 static int 3898 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3899 unsigned left, unsigned right) 3900 { 3901 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3902 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3903 struct hdac_softc *sc = devinfo->codec->sc; 3904 struct hdac_widget *w; 3905 struct hdac_audio_ctl *ctl; 3906 uint32_t mute; 3907 int lvol, rvol; 3908 int i, j; 3909 3910 hdac_lock(sc); 3911 /* Save new values. */ 3912 pdevinfo->left[dev] = left; 3913 pdevinfo->right[dev] = right; 3914 3915 /* 'ogain' is the special case implemented with EAPD. */ 3916 if (dev == SOUND_MIXER_OGAIN) { 3917 uint32_t orig; 3918 w = NULL; 3919 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3920 w = hdac_widget_get(devinfo, i); 3921 if (w == NULL || w->enable == 0) 3922 continue; 3923 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3924 w->param.eapdbtl == HDAC_INVALID) 3925 continue; 3926 break; 3927 } 3928 if (i >= devinfo->endnode) { 3929 hdac_unlock(sc); 3930 return (-1); 3931 } 3932 orig = w->param.eapdbtl; 3933 if (left == 0) 3934 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3935 else 3936 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3937 if (orig != w->param.eapdbtl) { 3938 uint32_t val; 3939 3940 val = w->param.eapdbtl; 3941 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3942 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3943 hdac_command(sc, 3944 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3945 w->nid, val), devinfo->codec->cad); 3946 } 3947 hdac_unlock(sc); 3948 return (left | (left << 8)); 3949 } 3950 3951 /* Recalculate all controls related to this OSS device. */ 3952 i = 0; 3953 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3954 if (ctl->enable == 0 || 3955 !(ctl->ossmask & (1 << dev))) 3956 continue; 3957 if (!((pdevinfo->play >= 0 && 3958 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3959 (pdevinfo->rec >= 0 && 3960 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3961 ctl->widget->bindas == -2)) 3962 continue; 3963 3964 lvol = 100; 3965 rvol = 100; 3966 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3967 if (ctl->ossmask & (1 << j)) { 3968 lvol = lvol * pdevinfo->left[j] / 100; 3969 rvol = rvol * pdevinfo->right[j] / 100; 3970 } 3971 } 3972 mute = (lvol == 0) ? HDA_AMP_MUTE_LEFT : 0; 3973 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3974 lvol = (lvol * ctl->step + 50) / 100; 3975 rvol = (rvol * ctl->step + 50) / 100; 3976 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3977 } 3978 hdac_unlock(sc); 3979 3980 return (left | (right << 8)); 3981 } 3982 3983 /* 3984 * Commutate specified record source. 3985 */ 3986 static uint32_t 3987 hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3988 { 3989 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3990 struct hdac_widget *w, *cw; 3991 struct hdac_audio_ctl *ctl; 3992 char buf[64]; 3993 int i, muted; 3994 uint32_t res = 0; 3995 3996 if (depth > HDA_PARSE_MAXDEPTH) 3997 return (0); 3998 3999 w = hdac_widget_get(devinfo, nid); 4000 if (w == NULL || w->enable == 0) 4001 return (0); 4002 4003 for (i = 0; i < w->nconns; i++) { 4004 if (w->connsenable[i] == 0) 4005 continue; 4006 cw = hdac_widget_get(devinfo, w->conns[i]); 4007 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 4008 continue; 4009 /* Call recursively to trace signal to it's source if needed. */ 4010 if ((src & cw->ossmask) != 0) { 4011 if (cw->ossdev < 0) { 4012 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 4013 w->conns[i], depth + 1); 4014 } else { 4015 res |= cw->ossmask; 4016 } 4017 } 4018 /* We have two special cases: mixers and others (selectors). */ 4019 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4020 ctl = hdac_audio_ctl_amp_get(devinfo, 4021 w->nid, HDA_CTL_IN, i, 1); 4022 if (ctl == NULL) 4023 continue; 4024 /* If we have input control on this node mute them 4025 * according to requested sources. */ 4026 muted = (src & cw->ossmask) ? 0 : 1; 4027 if (muted != ctl->forcemute) { 4028 ctl->forcemute = muted; 4029 hdac_audio_ctl_amp_set(ctl, 4030 HDA_AMP_MUTE_DEFAULT, 4031 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 4032 } 4033 HDA_BOOTHVERBOSE( 4034 device_printf(pdevinfo->dev, 4035 "Recsel (%s): nid %d source %d %s\n", 4036 hdac_audio_ctl_ossmixer_mask2allname( 4037 src, buf, sizeof(buf)), 4038 nid, i, muted?"mute":"unmute"); 4039 ); 4040 } else { 4041 if (w->nconns == 1) 4042 break; 4043 if ((src & cw->ossmask) == 0) 4044 continue; 4045 /* If we found requested source - select it and exit. */ 4046 hdac_widget_connection_select(w, i); 4047 HDA_BOOTHVERBOSE( 4048 device_printf(pdevinfo->dev, 4049 "Recsel (%s): nid %d source %d select\n", 4050 hdac_audio_ctl_ossmixer_mask2allname( 4051 src, buf, sizeof(buf)), 4052 nid, i); 4053 ); 4054 break; 4055 } 4056 } 4057 return (res); 4058 } 4059 4060 static uint32_t 4061 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 4062 { 4063 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 4064 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 4065 struct hdac_widget *w; 4066 struct hdac_softc *sc = devinfo->codec->sc; 4067 struct hdac_chan *ch; 4068 int i; 4069 uint32_t ret = 0xffffffff; 4070 4071 hdac_lock(sc); 4072 4073 /* Commutate requested recsrc for each ADC. */ 4074 ch = &sc->chans[pdevinfo->rec]; 4075 for (i = 0; ch->io[i] != -1; i++) { 4076 w = hdac_widget_get(devinfo, ch->io[i]); 4077 if (w == NULL || w->enable == 0) 4078 continue; 4079 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 4080 } 4081 4082 hdac_unlock(sc); 4083 4084 return ((ret == 0xffffffff)? 0 : ret); 4085 } 4086 4087 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 4088 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 4089 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 4090 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 4091 KOBJMETHOD_END 4092 }; 4093 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 4094 4095 static void 4096 hdac_unsolq_task(void *context, int pending) 4097 { 4098 struct hdac_softc *sc; 4099 4100 sc = (struct hdac_softc *)context; 4101 4102 hdac_lock(sc); 4103 hdac_unsolq_flush(sc); 4104 hdac_unlock(sc); 4105 } 4106 4107 /**************************************************************************** 4108 * int hdac_attach(device_t) 4109 * 4110 * Attach the device into the kernel. Interrupts usually won't be enabled 4111 * when this function is called. Setup everything that doesn't require 4112 * interrupts and defer probing of codecs until interrupts are enabled. 4113 ****************************************************************************/ 4114 static int 4115 hdac_attach(device_t dev) 4116 { 4117 struct hdac_softc *sc; 4118 int result; 4119 int i, devid = -1; 4120 uint32_t model; 4121 uint16_t class, subclass; 4122 uint16_t vendor; 4123 uint8_t v; 4124 4125 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4126 4127 model = (uint32_t)pci_get_device(dev) << 16; 4128 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4129 class = pci_get_class(dev); 4130 subclass = pci_get_subclass(dev); 4131 4132 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4133 if (hdac_devices[i].model == model) { 4134 devid = i; 4135 break; 4136 } 4137 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4138 class == PCIC_MULTIMEDIA && 4139 subclass == PCIS_MULTIMEDIA_HDA) { 4140 devid = i; 4141 break; 4142 } 4143 } 4144 4145 sc = device_get_softc(dev); 4146 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4147 sc->dev = dev; 4148 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4149 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4150 vendor = pci_get_vendor(dev); 4151 4152 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4153 /* Screw nx6325 - subdevice/subvendor swapped */ 4154 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4155 } 4156 4157 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4158 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4159 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4160 4161 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4162 4163 sc->poll_ticks = 1000000; 4164 sc->poll_ival = HDAC_POLL_INTERVAL; 4165 if (resource_int_value(device_get_name(dev), 4166 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4167 sc->polling = 1; 4168 else 4169 sc->polling = 0; 4170 4171 sc->hdabus = NULL; 4172 for (i = 0; i < HDAC_CODEC_MAX; i++) 4173 sc->codecs[i] = NULL; 4174 4175 pci_enable_busmaster(dev); 4176 4177 if (vendor == INTEL_VENDORID) { 4178 /* TCSEL -> TC0 */ 4179 v = pci_read_config(dev, 0x44, 1); 4180 pci_write_config(dev, 0x44, v & 0xf8, 1); 4181 HDA_BOOTHVERBOSE( 4182 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4183 pci_read_config(dev, 0x44, 1)); 4184 ); 4185 } 4186 4187 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4188 sc->flags &= ~HDAC_F_MSI; 4189 else 4190 sc->flags |= HDAC_F_MSI; 4191 if (resource_int_value(device_get_name(dev), 4192 device_get_unit(dev), "msi", &i) == 0) { 4193 if (i == 0) 4194 sc->flags &= ~HDAC_F_MSI; 4195 else 4196 sc->flags |= HDAC_F_MSI; 4197 } 4198 4199 #if defined(__i386__) || defined(__amd64__) 4200 sc->flags |= HDAC_F_DMA_NOCACHE; 4201 4202 if (resource_int_value(device_get_name(dev), 4203 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4204 #else 4205 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4206 #endif 4207 /* 4208 * Try to enable PCIe snoop to avoid messing around with 4209 * uncacheable DMA attribute. Since PCIe snoop register 4210 * config is pretty much vendor specific, there are no 4211 * general solutions on how to enable it, forcing us (even 4212 * Microsoft) to enable uncacheable or write combined DMA 4213 * by default. 4214 * 4215 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4216 */ 4217 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4218 if (hdac_pcie_snoop[i].vendor != vendor) 4219 continue; 4220 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4221 if (hdac_pcie_snoop[i].reg == 0x00) 4222 break; 4223 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4224 if ((v & hdac_pcie_snoop[i].enable) == 4225 hdac_pcie_snoop[i].enable) 4226 break; 4227 v &= hdac_pcie_snoop[i].mask; 4228 v |= hdac_pcie_snoop[i].enable; 4229 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4230 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4231 if ((v & hdac_pcie_snoop[i].enable) != 4232 hdac_pcie_snoop[i].enable) { 4233 HDA_BOOTVERBOSE( 4234 device_printf(dev, 4235 "WARNING: Failed to enable PCIe " 4236 "snoop!\n"); 4237 ); 4238 #if defined(__i386__) || defined(__amd64__) 4239 sc->flags |= HDAC_F_DMA_NOCACHE; 4240 #endif 4241 } 4242 break; 4243 } 4244 #if defined(__i386__) || defined(__amd64__) 4245 } 4246 #endif 4247 4248 HDA_BOOTHVERBOSE( 4249 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4250 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4251 "Uncacheable" : "PCIe snoop", vendor); 4252 ); 4253 4254 /* Allocate resources */ 4255 result = hdac_mem_alloc(sc); 4256 if (result != 0) 4257 goto hdac_attach_fail; 4258 result = hdac_irq_alloc(sc); 4259 if (result != 0) 4260 goto hdac_attach_fail; 4261 4262 /* Get Capabilities */ 4263 result = hdac_get_capabilities(sc); 4264 if (result != 0) 4265 goto hdac_attach_fail; 4266 4267 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4268 sc->support_64bit = 0; 4269 4270 /* Allocate CORB and RIRB dma memory */ 4271 result = hdac_dma_alloc(sc, &sc->corb_dma, 4272 sc->corb_size * sizeof(uint32_t)); 4273 if (result != 0) 4274 goto hdac_attach_fail; 4275 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4276 sc->rirb_size * sizeof(struct hdac_rirb)); 4277 if (result != 0) 4278 goto hdac_attach_fail; 4279 4280 result = bus_dma_tag_create( 4281 bus_get_dma_tag(sc->dev), /* parent */ 4282 HDAC_DMA_ALIGNMENT, /* alignment */ 4283 0, /* boundary */ 4284 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4285 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4286 BUS_SPACE_MAXADDR, /* highaddr */ 4287 NULL, /* filtfunc */ 4288 NULL, /* fistfuncarg */ 4289 HDA_BUFSZ_MAX, /* maxsize */ 4290 1, /* nsegments */ 4291 HDA_BUFSZ_MAX, /* maxsegsz */ 4292 0, /* flags */ 4293 NULL, /* lockfunc */ 4294 NULL, /* lockfuncarg */ 4295 &sc->chan_dmat); /* dmat */ 4296 if (result != 0) { 4297 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4298 __func__, result); 4299 goto hdac_attach_fail; 4300 } 4301 4302 /* Quiesce everything */ 4303 HDA_BOOTHVERBOSE( 4304 device_printf(dev, "Reset controller...\n"); 4305 ); 4306 hdac_reset(sc, 1); 4307 4308 /* Initialize the CORB and RIRB */ 4309 hdac_corb_init(sc); 4310 hdac_rirb_init(sc); 4311 4312 /* Defer remaining of initialization until interrupts are enabled */ 4313 sc->intrhook.ich_func = hdac_attach2; 4314 sc->intrhook.ich_arg = (void *)sc; 4315 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4316 sc->intrhook.ich_func = NULL; 4317 hdac_attach2((void *)sc); 4318 } 4319 4320 return (0); 4321 4322 hdac_attach_fail: 4323 hdac_irq_free(sc); 4324 hdac_dma_free(sc, &sc->rirb_dma); 4325 hdac_dma_free(sc, &sc->corb_dma); 4326 hdac_mem_free(sc); 4327 snd_mtxfree(sc->lock); 4328 4329 return (ENXIO); 4330 } 4331 4332 static void 4333 hdac_audio_parse(struct hdac_devinfo *devinfo) 4334 { 4335 struct hdac_codec *codec = devinfo->codec; 4336 struct hdac_softc *sc = codec->sc; 4337 struct hdac_widget *w; 4338 uint32_t res; 4339 int i; 4340 nid_t cad, nid; 4341 4342 cad = devinfo->codec->cad; 4343 nid = devinfo->nid; 4344 4345 res = hdac_command(sc, 4346 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4347 devinfo->function.audio.gpio = res; 4348 4349 HDA_BOOTVERBOSE( 4350 device_printf(sc->dev, "GPIO: 0x%08x " 4351 "NumGPIO=%d NumGPO=%d " 4352 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4353 devinfo->function.audio.gpio, 4354 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4355 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4356 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4357 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4358 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4359 ); 4360 4361 res = hdac_command(sc, 4362 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4363 cad); 4364 devinfo->function.audio.supp_stream_formats = res; 4365 4366 res = hdac_command(sc, 4367 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4368 cad); 4369 devinfo->function.audio.supp_pcm_size_rate = res; 4370 4371 res = hdac_command(sc, 4372 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4373 cad); 4374 devinfo->function.audio.outamp_cap = res; 4375 4376 res = hdac_command(sc, 4377 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4378 cad); 4379 devinfo->function.audio.inamp_cap = res; 4380 4381 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4382 w = hdac_widget_get(devinfo, i); 4383 if (w == NULL) 4384 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4385 else { 4386 w->devinfo = devinfo; 4387 w->nid = i; 4388 w->enable = 1; 4389 w->selconn = -1; 4390 w->pflags = 0; 4391 w->ossdev = -1; 4392 w->bindas = -1; 4393 w->param.eapdbtl = HDAC_INVALID; 4394 hdac_widget_parse(w); 4395 } 4396 } 4397 } 4398 4399 static void 4400 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4401 { 4402 struct hdac_softc *sc = devinfo->codec->sc; 4403 struct hdac_audio_ctl *ctls; 4404 struct hdac_widget *w, *cw; 4405 int i, j, cnt, max, ocap, icap; 4406 int mute, offset, step, size; 4407 4408 /* XXX This is redundant */ 4409 max = 0; 4410 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4411 w = hdac_widget_get(devinfo, i); 4412 if (w == NULL || w->enable == 0) 4413 continue; 4414 if (w->param.outamp_cap != 0) 4415 max++; 4416 if (w->param.inamp_cap != 0) { 4417 switch (w->type) { 4418 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4419 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4420 for (j = 0; j < w->nconns; j++) { 4421 cw = hdac_widget_get(devinfo, 4422 w->conns[j]); 4423 if (cw == NULL || cw->enable == 0) 4424 continue; 4425 max++; 4426 } 4427 break; 4428 default: 4429 max++; 4430 break; 4431 } 4432 } 4433 } 4434 4435 devinfo->function.audio.ctlcnt = max; 4436 4437 if (max < 1) 4438 return; 4439 4440 ctls = (struct hdac_audio_ctl *)malloc( 4441 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4442 4443 if (ctls == NULL) { 4444 /* Blekh! */ 4445 device_printf(sc->dev, "unable to allocate ctls!\n"); 4446 devinfo->function.audio.ctlcnt = 0; 4447 return; 4448 } 4449 4450 cnt = 0; 4451 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4452 if (cnt >= max) { 4453 device_printf(sc->dev, "%s: Ctl overflow!\n", 4454 __func__); 4455 break; 4456 } 4457 w = hdac_widget_get(devinfo, i); 4458 if (w == NULL || w->enable == 0) 4459 continue; 4460 ocap = w->param.outamp_cap; 4461 icap = w->param.inamp_cap; 4462 if (ocap != 0) { 4463 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4464 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4465 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4466 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4467 /*if (offset > step) { 4468 HDA_BOOTVERBOSE( 4469 device_printf(sc->dev, 4470 "BUGGY outamp: nid=%d " 4471 "[offset=%d > step=%d]\n", 4472 w->nid, offset, step); 4473 ); 4474 offset = step; 4475 }*/ 4476 ctls[cnt].enable = 1; 4477 ctls[cnt].widget = w; 4478 ctls[cnt].mute = mute; 4479 ctls[cnt].step = step; 4480 ctls[cnt].size = size; 4481 ctls[cnt].offset = offset; 4482 ctls[cnt].left = offset; 4483 ctls[cnt].right = offset; 4484 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4485 w->waspin) 4486 ctls[cnt].ndir = HDA_CTL_IN; 4487 else 4488 ctls[cnt].ndir = HDA_CTL_OUT; 4489 ctls[cnt++].dir = HDA_CTL_OUT; 4490 } 4491 4492 if (icap != 0) { 4493 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4494 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4495 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4496 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4497 /*if (offset > step) { 4498 HDA_BOOTVERBOSE( 4499 device_printf(sc->dev, 4500 "BUGGY inamp: nid=%d " 4501 "[offset=%d > step=%d]\n", 4502 w->nid, offset, step); 4503 ); 4504 offset = step; 4505 }*/ 4506 switch (w->type) { 4507 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4508 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4509 for (j = 0; j < w->nconns; j++) { 4510 if (cnt >= max) { 4511 device_printf(sc->dev, 4512 "%s: Ctl overflow!\n", 4513 __func__); 4514 break; 4515 } 4516 cw = hdac_widget_get(devinfo, 4517 w->conns[j]); 4518 if (cw == NULL || cw->enable == 0) 4519 continue; 4520 ctls[cnt].enable = 1; 4521 ctls[cnt].widget = w; 4522 ctls[cnt].childwidget = cw; 4523 ctls[cnt].index = j; 4524 ctls[cnt].mute = mute; 4525 ctls[cnt].step = step; 4526 ctls[cnt].size = size; 4527 ctls[cnt].offset = offset; 4528 ctls[cnt].left = offset; 4529 ctls[cnt].right = offset; 4530 ctls[cnt].ndir = HDA_CTL_IN; 4531 ctls[cnt++].dir = HDA_CTL_IN; 4532 } 4533 break; 4534 default: 4535 if (cnt >= max) { 4536 device_printf(sc->dev, 4537 "%s: Ctl overflow!\n", 4538 __func__); 4539 break; 4540 } 4541 ctls[cnt].enable = 1; 4542 ctls[cnt].widget = w; 4543 ctls[cnt].mute = mute; 4544 ctls[cnt].step = step; 4545 ctls[cnt].size = size; 4546 ctls[cnt].offset = offset; 4547 ctls[cnt].left = offset; 4548 ctls[cnt].right = offset; 4549 if (w->type == 4550 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4551 ctls[cnt].ndir = HDA_CTL_OUT; 4552 else 4553 ctls[cnt].ndir = HDA_CTL_IN; 4554 ctls[cnt++].dir = HDA_CTL_IN; 4555 break; 4556 } 4557 } 4558 } 4559 4560 devinfo->function.audio.ctl = ctls; 4561 } 4562 4563 static void 4564 hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4565 { 4566 struct hdac_softc *sc = devinfo->codec->sc; 4567 struct hdac_audio_as *as; 4568 struct hdac_widget *w; 4569 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4570 4571 /* Count present associations */ 4572 max = 0; 4573 for (j = 1; j < 16; j++) { 4574 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4575 w = hdac_widget_get(devinfo, i); 4576 if (w == NULL || w->enable == 0) 4577 continue; 4578 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4579 continue; 4580 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4581 != j) 4582 continue; 4583 max++; 4584 if (j != 15) /* There could be many 1-pin assocs #15 */ 4585 break; 4586 } 4587 } 4588 4589 devinfo->function.audio.ascnt = max; 4590 4591 if (max < 1) 4592 return; 4593 4594 as = (struct hdac_audio_as *)malloc( 4595 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4596 4597 if (as == NULL) { 4598 /* Blekh! */ 4599 device_printf(sc->dev, "unable to allocate assocs!\n"); 4600 devinfo->function.audio.ascnt = 0; 4601 return; 4602 } 4603 4604 for (i = 0; i < max; i++) { 4605 as[i].hpredir = -1; 4606 as[i].chan = -1; 4607 as[i].digital = 0; 4608 } 4609 4610 /* Scan associations skipping as=0. */ 4611 cnt = 0; 4612 for (j = 1; j < 16; j++) { 4613 first = 16; 4614 hpredir = 0; 4615 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4616 w = hdac_widget_get(devinfo, i); 4617 if (w == NULL || w->enable == 0) 4618 continue; 4619 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4620 continue; 4621 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4622 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4623 if (assoc != j) { 4624 continue; 4625 } 4626 KASSERT(cnt < max, 4627 ("%s: Associations owerflow (%d of %d)", 4628 __func__, cnt, max)); 4629 type = w->wclass.pin.config & 4630 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4631 /* Get pin direction. */ 4632 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4633 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4634 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4635 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4636 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4637 dir = HDA_CTL_OUT; 4638 else 4639 dir = HDA_CTL_IN; 4640 /* If this is a first pin - create new association. */ 4641 if (as[cnt].pincnt == 0) { 4642 as[cnt].enable = 1; 4643 as[cnt].index = j; 4644 as[cnt].dir = dir; 4645 } 4646 if (seq < first) 4647 first = seq; 4648 /* Check association correctness. */ 4649 if (as[cnt].pins[seq] != 0) { 4650 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4651 "in association %d! Disabling association.\n", 4652 __func__, seq, w->nid, j); 4653 as[cnt].enable = 0; 4654 } 4655 if (dir != as[cnt].dir) { 4656 device_printf(sc->dev, "%s: Pin %d has wrong " 4657 "direction for association %d! Disabling " 4658 "association.\n", 4659 __func__, w->nid, j); 4660 as[cnt].enable = 0; 4661 } 4662 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4663 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4664 as[cnt].digital = 3; 4665 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4666 as[cnt].digital = 2; 4667 else 4668 as[cnt].digital = 1; 4669 } 4670 /* Headphones with seq=15 may mean redirection. */ 4671 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4672 seq == 15) 4673 hpredir = 1; 4674 as[cnt].pins[seq] = w->nid; 4675 as[cnt].pincnt++; 4676 /* Association 15 is a multiple unassociated pins. */ 4677 if (j == 15) 4678 cnt++; 4679 } 4680 if (j != 15 && as[cnt].pincnt > 0) { 4681 if (hpredir && as[cnt].pincnt > 1) 4682 as[cnt].hpredir = first; 4683 cnt++; 4684 } 4685 } 4686 HDA_BOOTVERBOSE( 4687 device_printf(sc->dev, 4688 "%d associations found:\n", max); 4689 for (i = 0; i < max; i++) { 4690 device_printf(sc->dev, 4691 "Association %d (%d) %s%s:\n", 4692 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4693 as[i].enable?"":" (disabled)"); 4694 for (j = 0; j < 16; j++) { 4695 if (as[i].pins[j] == 0) 4696 continue; 4697 device_printf(sc->dev, 4698 " Pin nid=%d seq=%d\n", 4699 as[i].pins[j], j); 4700 } 4701 } 4702 ); 4703 4704 devinfo->function.audio.as = as; 4705 } 4706 4707 static const struct { 4708 uint32_t model; 4709 uint32_t id; 4710 uint32_t set, unset; 4711 } hdac_quirks[] = { 4712 /* 4713 * XXX Force stereo quirk. Monoural recording / playback 4714 * on few codecs (especially ALC880) seems broken or 4715 * perhaps unsupported. 4716 */ 4717 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4718 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4719 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4720 HDA_QUIRK_GPIO0, 0 }, 4721 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4722 HDA_QUIRK_GPIO0, 0 }, 4723 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4724 HDA_QUIRK_GPIO0, 0 }, 4725 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4726 HDA_QUIRK_GPIO0, 0 }, 4727 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4728 HDA_QUIRK_GPIO0, 0 }, 4729 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4730 HDA_QUIRK_GPIO0, 0 }, 4731 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4732 HDA_QUIRK_EAPDINV, 0 }, 4733 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4734 HDA_QUIRK_EAPDINV, 0 }, 4735 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4736 HDA_QUIRK_OVREF, 0 }, 4737 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4738 HDA_QUIRK_OVREF, 0 }, 4739 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4740 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4741 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4742 HDA_QUIRK_GPIO1, 0 }, 4743 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4744 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4745 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4746 HDA_QUIRK_EAPDINV, 0 }, 4747 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4748 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4749 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4750 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4751 { APPLE_MACBOOKPRO55, HDA_CODEC_CS4206, 4752 HDA_QUIRK_GPIO1 | HDA_QUIRK_GPIO3, 0 }, 4753 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4754 HDA_QUIRK_GPIO0, 0 }, 4755 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4756 HDA_QUIRK_GPIO2, 0 }, 4757 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4758 HDA_QUIRK_GPIO0, 0 }, 4759 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4760 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4761 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4762 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4763 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4764 0, HDA_QUIRK_FORCESTEREO } 4765 }; 4766 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4767 4768 static void 4769 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4770 { 4771 struct hdac_widget *w; 4772 uint32_t id, subvendor; 4773 int i; 4774 4775 id = hdac_codec_id(devinfo->codec); 4776 subvendor = devinfo->codec->sc->pci_subvendor; 4777 4778 /* 4779 * Quirks 4780 */ 4781 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4782 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4783 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4784 continue; 4785 if (hdac_quirks[i].set != 0) 4786 devinfo->function.audio.quirks |= 4787 hdac_quirks[i].set; 4788 if (hdac_quirks[i].unset != 0) 4789 devinfo->function.audio.quirks &= 4790 ~(hdac_quirks[i].unset); 4791 } 4792 4793 switch (id) { 4794 case HDA_CODEC_AD1983: 4795 /* 4796 * This codec has several possible usages, but none 4797 * fit the parser best. Help parser to choose better. 4798 */ 4799 /* Disable direct unmixed playback to get pcm volume. */ 4800 w = hdac_widget_get(devinfo, 5); 4801 if (w != NULL) 4802 w->connsenable[0] = 0; 4803 w = hdac_widget_get(devinfo, 6); 4804 if (w != NULL) 4805 w->connsenable[0] = 0; 4806 w = hdac_widget_get(devinfo, 11); 4807 if (w != NULL) 4808 w->connsenable[0] = 0; 4809 /* Disable mic and line selectors. */ 4810 w = hdac_widget_get(devinfo, 12); 4811 if (w != NULL) 4812 w->connsenable[1] = 0; 4813 w = hdac_widget_get(devinfo, 13); 4814 if (w != NULL) 4815 w->connsenable[1] = 0; 4816 /* Disable recording from mono playback mix. */ 4817 w = hdac_widget_get(devinfo, 20); 4818 if (w != NULL) 4819 w->connsenable[3] = 0; 4820 break; 4821 case HDA_CODEC_AD1986A: 4822 /* 4823 * This codec has overcomplicated input mixing. 4824 * Make some cleaning there. 4825 */ 4826 /* Disable input mono mixer. Not needed and not supported. */ 4827 w = hdac_widget_get(devinfo, 43); 4828 if (w != NULL) 4829 w->enable = 0; 4830 /* Disable any with any input mixing mesh. Use separately. */ 4831 w = hdac_widget_get(devinfo, 39); 4832 if (w != NULL) 4833 w->enable = 0; 4834 w = hdac_widget_get(devinfo, 40); 4835 if (w != NULL) 4836 w->enable = 0; 4837 w = hdac_widget_get(devinfo, 41); 4838 if (w != NULL) 4839 w->enable = 0; 4840 w = hdac_widget_get(devinfo, 42); 4841 if (w != NULL) 4842 w->enable = 0; 4843 /* Disable duplicate mixer node connector. */ 4844 w = hdac_widget_get(devinfo, 15); 4845 if (w != NULL) 4846 w->connsenable[3] = 0; 4847 /* There is only one mic preamplifier, use it effectively. */ 4848 w = hdac_widget_get(devinfo, 31); 4849 if (w != NULL) { 4850 if ((w->wclass.pin.config & 4851 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4852 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4853 w = hdac_widget_get(devinfo, 16); 4854 if (w != NULL) 4855 w->connsenable[2] = 0; 4856 } else { 4857 w = hdac_widget_get(devinfo, 15); 4858 if (w != NULL) 4859 w->connsenable[0] = 0; 4860 } 4861 } 4862 w = hdac_widget_get(devinfo, 32); 4863 if (w != NULL) { 4864 if ((w->wclass.pin.config & 4865 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4866 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4867 w = hdac_widget_get(devinfo, 16); 4868 if (w != NULL) 4869 w->connsenable[0] = 0; 4870 } else { 4871 w = hdac_widget_get(devinfo, 15); 4872 if (w != NULL) 4873 w->connsenable[1] = 0; 4874 } 4875 } 4876 4877 if (subvendor == ASUS_A8X_SUBVENDOR) { 4878 /* 4879 * This is just plain ridiculous.. There 4880 * are several A8 series that share the same 4881 * pci id but works differently (EAPD). 4882 */ 4883 w = hdac_widget_get(devinfo, 26); 4884 if (w != NULL && w->type == 4885 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4886 (w->wclass.pin.config & 4887 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4888 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4889 devinfo->function.audio.quirks &= 4890 ~HDA_QUIRK_EAPDINV; 4891 } 4892 break; 4893 case HDA_CODEC_AD1981HD: 4894 /* 4895 * This codec has very unusual design with several 4896 * points inappropriate for the present parser. 4897 */ 4898 /* Disable recording from mono playback mix. */ 4899 w = hdac_widget_get(devinfo, 21); 4900 if (w != NULL) 4901 w->connsenable[3] = 0; 4902 /* Disable rear to front mic mixer, use separately. */ 4903 w = hdac_widget_get(devinfo, 31); 4904 if (w != NULL) 4905 w->enable = 0; 4906 /* Disable direct playback, use mixer. */ 4907 w = hdac_widget_get(devinfo, 5); 4908 if (w != NULL) 4909 w->connsenable[0] = 0; 4910 w = hdac_widget_get(devinfo, 6); 4911 if (w != NULL) 4912 w->connsenable[0] = 0; 4913 w = hdac_widget_get(devinfo, 9); 4914 if (w != NULL) 4915 w->connsenable[0] = 0; 4916 w = hdac_widget_get(devinfo, 24); 4917 if (w != NULL) 4918 w->connsenable[0] = 0; 4919 break; 4920 } 4921 } 4922 4923 /* 4924 * Trace path from DAC to pin. 4925 */ 4926 static nid_t 4927 hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4928 int dupseq, int min, int only, int depth) 4929 { 4930 struct hdac_widget *w; 4931 int i, im = -1; 4932 nid_t m = 0, ret; 4933 4934 if (depth > HDA_PARSE_MAXDEPTH) 4935 return (0); 4936 w = hdac_widget_get(devinfo, nid); 4937 if (w == NULL || w->enable == 0) 4938 return (0); 4939 HDA_BOOTHVERBOSE( 4940 if (!only) { 4941 device_printf(devinfo->codec->sc->dev, 4942 " %*stracing via nid %d\n", 4943 depth + 1, "", w->nid); 4944 } 4945 ); 4946 /* Use only unused widgets */ 4947 if (w->bindas >= 0 && w->bindas != as) { 4948 HDA_BOOTHVERBOSE( 4949 if (!only) { 4950 device_printf(devinfo->codec->sc->dev, 4951 " %*snid %d busy by association %d\n", 4952 depth + 1, "", w->nid, w->bindas); 4953 } 4954 ); 4955 return (0); 4956 } 4957 if (dupseq < 0) { 4958 if (w->bindseqmask != 0) { 4959 HDA_BOOTHVERBOSE( 4960 if (!only) { 4961 device_printf(devinfo->codec->sc->dev, 4962 " %*snid %d busy by seqmask %x\n", 4963 depth + 1, "", w->nid, w->bindseqmask); 4964 } 4965 ); 4966 return (0); 4967 } 4968 } else { 4969 /* If this is headphones - allow duplicate first pin. */ 4970 if (w->bindseqmask != 0 && 4971 (w->bindseqmask & (1 << dupseq)) == 0) { 4972 HDA_BOOTHVERBOSE( 4973 device_printf(devinfo->codec->sc->dev, 4974 " %*snid %d busy by seqmask %x\n", 4975 depth + 1, "", w->nid, w->bindseqmask); 4976 ); 4977 return (0); 4978 } 4979 } 4980 4981 switch (w->type) { 4982 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4983 /* Do not traverse input. AD1988 has digital monitor 4984 for which we are not ready. */ 4985 break; 4986 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4987 /* If we are tracing HP take only dac of first pin. */ 4988 if ((only == 0 || only == w->nid) && 4989 (w->nid >= min) && (dupseq < 0 || w->nid == 4990 devinfo->function.audio.as[as].dacs[dupseq])) 4991 m = w->nid; 4992 break; 4993 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4994 if (depth > 0) 4995 break; 4996 /* Fall */ 4997 default: 4998 /* Find reachable DACs with smallest nid respecting constraints. */ 4999 for (i = 0; i < w->nconns; i++) { 5000 if (w->connsenable[i] == 0) 5001 continue; 5002 if (w->selconn != -1 && w->selconn != i) 5003 continue; 5004 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 5005 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 5006 if (m == 0 || ret < m) { 5007 m = ret; 5008 im = i; 5009 } 5010 if (only || dupseq >= 0) 5011 break; 5012 } 5013 } 5014 if (m && only && ((w->nconns > 1 && 5015 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5016 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 5017 w->selconn = im; 5018 break; 5019 } 5020 if (m && only) { 5021 w->bindas = as; 5022 w->bindseqmask |= (1 << seq); 5023 } 5024 HDA_BOOTHVERBOSE( 5025 if (!only) { 5026 device_printf(devinfo->codec->sc->dev, 5027 " %*snid %d returned %d\n", 5028 depth + 1, "", w->nid, m); 5029 } 5030 ); 5031 return (m); 5032 } 5033 5034 /* 5035 * Trace path from widget to ADC. 5036 */ 5037 static nid_t 5038 hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 5039 int only, int depth) 5040 { 5041 struct hdac_widget *w, *wc; 5042 int i, j; 5043 nid_t res = 0; 5044 5045 if (depth > HDA_PARSE_MAXDEPTH) 5046 return (0); 5047 w = hdac_widget_get(devinfo, nid); 5048 if (w == NULL || w->enable == 0) 5049 return (0); 5050 HDA_BOOTHVERBOSE( 5051 device_printf(devinfo->codec->sc->dev, 5052 " %*stracing via nid %d\n", 5053 depth + 1, "", w->nid); 5054 ); 5055 /* Use only unused widgets */ 5056 if (w->bindas >= 0 && w->bindas != as) { 5057 HDA_BOOTHVERBOSE( 5058 device_printf(devinfo->codec->sc->dev, 5059 " %*snid %d busy by association %d\n", 5060 depth + 1, "", w->nid, w->bindas); 5061 ); 5062 return (0); 5063 } 5064 5065 switch (w->type) { 5066 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5067 /* If we are tracing HP take only dac of first pin. */ 5068 if (only == w->nid) 5069 res = 1; 5070 break; 5071 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5072 if (depth > 0) 5073 break; 5074 /* Fall */ 5075 default: 5076 /* Try to find reachable ADCs with specified nid. */ 5077 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5078 wc = hdac_widget_get(devinfo, j); 5079 if (wc == NULL || wc->enable == 0) 5080 continue; 5081 for (i = 0; i < wc->nconns; i++) { 5082 if (wc->connsenable[i] == 0) 5083 continue; 5084 if (wc->conns[i] != nid) 5085 continue; 5086 if (hdac_audio_trace_adc(devinfo, as, seq, 5087 j, only, depth + 1) != 0) { 5088 res = 1; 5089 if (((wc->nconns > 1 && 5090 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5091 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5092 wc->selconn == -1) 5093 wc->selconn = i; 5094 } 5095 } 5096 } 5097 break; 5098 } 5099 if (res) { 5100 w->bindas = as; 5101 w->bindseqmask |= (1 << seq); 5102 } 5103 HDA_BOOTHVERBOSE( 5104 device_printf(devinfo->codec->sc->dev, 5105 " %*snid %d returned %d\n", 5106 depth + 1, "", w->nid, res); 5107 ); 5108 return (res); 5109 } 5110 5111 /* 5112 * Erase trace path of the specified association. 5113 */ 5114 static void 5115 hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5116 { 5117 struct hdac_widget *w; 5118 int i; 5119 5120 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5121 w = hdac_widget_get(devinfo, i); 5122 if (w == NULL || w->enable == 0) 5123 continue; 5124 if (w->bindas == as) { 5125 if (seq >= 0) { 5126 w->bindseqmask &= ~(1 << seq); 5127 if (w->bindseqmask == 0) { 5128 w->bindas = -1; 5129 w->selconn = -1; 5130 } 5131 } else { 5132 w->bindas = -1; 5133 w->bindseqmask = 0; 5134 w->selconn = -1; 5135 } 5136 } 5137 } 5138 } 5139 5140 /* 5141 * Trace association path from DAC to output 5142 */ 5143 static int 5144 hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5145 { 5146 struct hdac_audio_as *ases = devinfo->function.audio.as; 5147 int i, hpredir; 5148 nid_t min, res; 5149 5150 /* Find next pin */ 5151 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5152 ; 5153 /* Check if there is no any left. If so - we succeeded. */ 5154 if (i == 16) 5155 return (1); 5156 5157 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5158 min = 0; 5159 res = 0; 5160 do { 5161 HDA_BOOTHVERBOSE( 5162 device_printf(devinfo->codec->sc->dev, 5163 " Tracing pin %d with min nid %d", 5164 ases[as].pins[i], min); 5165 if (hpredir >= 0) 5166 printf(" and hpredir %d", hpredir); 5167 printf("\n"); 5168 ); 5169 /* Trace this pin taking min nid into account. */ 5170 res = hdac_audio_trace_dac(devinfo, as, i, 5171 ases[as].pins[i], hpredir, min, 0, 0); 5172 if (res == 0) { 5173 /* If we failed - return to previous and redo it. */ 5174 HDA_BOOTVERBOSE( 5175 device_printf(devinfo->codec->sc->dev, 5176 " Unable to trace pin %d seq %d with min " 5177 "nid %d", 5178 ases[as].pins[i], i, min); 5179 if (hpredir >= 0) 5180 printf(" and hpredir %d", hpredir); 5181 printf("\n"); 5182 ); 5183 return (0); 5184 } 5185 HDA_BOOTVERBOSE( 5186 device_printf(devinfo->codec->sc->dev, 5187 " Pin %d traced to DAC %d", 5188 ases[as].pins[i], res); 5189 if (hpredir >= 0) 5190 printf(" and hpredir %d", hpredir); 5191 if (ases[as].fakeredir) 5192 printf(" with fake redirection"); 5193 printf("\n"); 5194 ); 5195 /* Trace again to mark the path */ 5196 hdac_audio_trace_dac(devinfo, as, i, 5197 ases[as].pins[i], hpredir, min, res, 0); 5198 ases[as].dacs[i] = res; 5199 /* We succeeded, so call next. */ 5200 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5201 return (1); 5202 /* If next failed, we should retry with next min */ 5203 hdac_audio_undo_trace(devinfo, as, i); 5204 ases[as].dacs[i] = 0; 5205 min = res + 1; 5206 } while (1); 5207 } 5208 5209 /* 5210 * Trace association path from input to ADC 5211 */ 5212 static int 5213 hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5214 { 5215 struct hdac_audio_as *ases = devinfo->function.audio.as; 5216 struct hdac_widget *w; 5217 int i, j, k; 5218 5219 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5220 w = hdac_widget_get(devinfo, j); 5221 if (w == NULL || w->enable == 0) 5222 continue; 5223 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5224 continue; 5225 if (w->bindas >= 0 && w->bindas != as) 5226 continue; 5227 5228 /* Find next pin */ 5229 for (i = 0; i < 16; i++) { 5230 if (ases[as].pins[i] == 0) 5231 continue; 5232 5233 HDA_BOOTHVERBOSE( 5234 device_printf(devinfo->codec->sc->dev, 5235 " Tracing pin %d to ADC %d\n", 5236 ases[as].pins[i], j); 5237 ); 5238 /* Trace this pin taking goal into account. */ 5239 if (hdac_audio_trace_adc(devinfo, as, i, 5240 ases[as].pins[i], j, 0) == 0) { 5241 /* If we failed - return to previous and redo it. */ 5242 HDA_BOOTVERBOSE( 5243 device_printf(devinfo->codec->sc->dev, 5244 " Unable to trace pin %d to ADC %d, undo traces\n", 5245 ases[as].pins[i], j); 5246 ); 5247 hdac_audio_undo_trace(devinfo, as, -1); 5248 for (k = 0; k < 16; k++) 5249 ases[as].dacs[k] = 0; 5250 break; 5251 } 5252 HDA_BOOTVERBOSE( 5253 device_printf(devinfo->codec->sc->dev, 5254 " Pin %d traced to ADC %d\n", 5255 ases[as].pins[i], j); 5256 ); 5257 ases[as].dacs[i] = j; 5258 } 5259 if (i == 16) 5260 return (1); 5261 } 5262 return (0); 5263 } 5264 5265 /* 5266 * Trace input monitor path from mixer to output association. 5267 */ 5268 static int 5269 hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5270 { 5271 struct hdac_audio_as *ases = devinfo->function.audio.as; 5272 struct hdac_widget *w, *wc; 5273 int i, j; 5274 nid_t res = 0; 5275 5276 if (depth > HDA_PARSE_MAXDEPTH) 5277 return (0); 5278 w = hdac_widget_get(devinfo, nid); 5279 if (w == NULL || w->enable == 0) 5280 return (0); 5281 HDA_BOOTHVERBOSE( 5282 device_printf(devinfo->codec->sc->dev, 5283 " %*stracing via nid %d\n", 5284 depth + 1, "", w->nid); 5285 ); 5286 /* Use only unused widgets */ 5287 if (depth > 0 && w->bindas != -1) { 5288 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5289 HDA_BOOTHVERBOSE( 5290 device_printf(devinfo->codec->sc->dev, 5291 " %*snid %d found output association %d\n", 5292 depth + 1, "", w->nid, w->bindas); 5293 ); 5294 if (w->bindas >= 0) 5295 w->pflags |= HDA_ADC_MONITOR; 5296 return (1); 5297 } else { 5298 HDA_BOOTHVERBOSE( 5299 device_printf(devinfo->codec->sc->dev, 5300 " %*snid %d busy by input association %d\n", 5301 depth + 1, "", w->nid, w->bindas); 5302 ); 5303 return (0); 5304 } 5305 } 5306 5307 switch (w->type) { 5308 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5309 /* Do not traverse input. AD1988 has digital monitor 5310 for which we are not ready. */ 5311 break; 5312 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5313 if (depth > 0) 5314 break; 5315 /* Fall */ 5316 default: 5317 /* Try to find reachable ADCs with specified nid. */ 5318 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5319 wc = hdac_widget_get(devinfo, j); 5320 if (wc == NULL || wc->enable == 0) 5321 continue; 5322 for (i = 0; i < wc->nconns; i++) { 5323 if (wc->connsenable[i] == 0) 5324 continue; 5325 if (wc->conns[i] != nid) 5326 continue; 5327 if (hdac_audio_trace_to_out(devinfo, 5328 j, depth + 1) != 0) { 5329 res = 1; 5330 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5331 wc->selconn == -1) 5332 wc->selconn = i; 5333 } 5334 } 5335 } 5336 break; 5337 } 5338 if (res && w->bindas == -1) 5339 w->bindas = -2; 5340 5341 HDA_BOOTHVERBOSE( 5342 device_printf(devinfo->codec->sc->dev, 5343 " %*snid %d returned %d\n", 5344 depth + 1, "", w->nid, res); 5345 ); 5346 return (res); 5347 } 5348 5349 /* 5350 * Trace extra associations (beeper, monitor) 5351 */ 5352 static void 5353 hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5354 { 5355 struct hdac_audio_as *as = devinfo->function.audio.as; 5356 struct hdac_widget *w; 5357 int j; 5358 5359 /* Input monitor */ 5360 /* Find mixer associated with input, but supplying signal 5361 for output associations. Hope it will be input monitor. */ 5362 HDA_BOOTVERBOSE( 5363 device_printf(devinfo->codec->sc->dev, 5364 "Tracing input monitor\n"); 5365 ); 5366 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5367 w = hdac_widget_get(devinfo, j); 5368 if (w == NULL || w->enable == 0) 5369 continue; 5370 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5371 continue; 5372 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5373 continue; 5374 HDA_BOOTVERBOSE( 5375 device_printf(devinfo->codec->sc->dev, 5376 " Tracing nid %d to out\n", 5377 j); 5378 ); 5379 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5380 HDA_BOOTVERBOSE( 5381 device_printf(devinfo->codec->sc->dev, 5382 " nid %d is input monitor\n", 5383 w->nid); 5384 ); 5385 w->ossdev = SOUND_MIXER_IMIX; 5386 } 5387 } 5388 5389 /* Other inputs monitor */ 5390 /* Find input pins supplying signal for output associations. 5391 Hope it will be input monitoring. */ 5392 HDA_BOOTVERBOSE( 5393 device_printf(devinfo->codec->sc->dev, 5394 "Tracing other input monitors\n"); 5395 ); 5396 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5397 w = hdac_widget_get(devinfo, j); 5398 if (w == NULL || w->enable == 0) 5399 continue; 5400 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5401 continue; 5402 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5403 continue; 5404 HDA_BOOTVERBOSE( 5405 device_printf(devinfo->codec->sc->dev, 5406 " Tracing nid %d to out\n", 5407 j); 5408 ); 5409 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5410 HDA_BOOTVERBOSE( 5411 device_printf(devinfo->codec->sc->dev, 5412 " nid %d is input monitor\n", 5413 w->nid); 5414 ); 5415 } 5416 } 5417 5418 /* Beeper */ 5419 HDA_BOOTVERBOSE( 5420 device_printf(devinfo->codec->sc->dev, 5421 "Tracing beeper\n"); 5422 ); 5423 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5424 w = hdac_widget_get(devinfo, j); 5425 if (w == NULL || w->enable == 0) 5426 continue; 5427 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5428 continue; 5429 HDA_BOOTHVERBOSE( 5430 device_printf(devinfo->codec->sc->dev, 5431 " Tracing nid %d to out\n", 5432 j); 5433 ); 5434 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5435 HDA_BOOTVERBOSE( 5436 device_printf(devinfo->codec->sc->dev, 5437 " nid %d traced to out\n", 5438 j); 5439 ); 5440 } 5441 w->bindas = -2; 5442 } 5443 } 5444 5445 /* 5446 * Bind assotiations to PCM channels 5447 */ 5448 static void 5449 hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5450 { 5451 struct hdac_softc *sc = devinfo->codec->sc; 5452 struct hdac_audio_as *as = devinfo->function.audio.as; 5453 int j, cnt = 0, free; 5454 5455 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5456 if (as[j].enable) 5457 cnt++; 5458 } 5459 if (sc->num_chans == 0) { 5460 sc->chans = (struct hdac_chan *)malloc( 5461 sizeof(struct hdac_chan) * cnt, 5462 M_HDAC, M_ZERO | M_NOWAIT); 5463 if (sc->chans == NULL) { 5464 device_printf(sc->dev, 5465 "Channels memory allocation failed!\n"); 5466 return; 5467 } 5468 } else { 5469 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5470 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5471 M_HDAC, M_ZERO | M_NOWAIT); 5472 if (sc->chans == NULL) { 5473 sc->num_chans = 0; 5474 device_printf(sc->dev, 5475 "Channels memory allocation failed!\n"); 5476 return; 5477 } 5478 /* Fixup relative pointers after realloc */ 5479 for (j = 0; j < sc->num_chans; j++) 5480 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5481 } 5482 free = sc->num_chans; 5483 sc->num_chans += cnt; 5484 5485 for (j = free; j < free + cnt; j++) { 5486 sc->chans[j].devinfo = devinfo; 5487 sc->chans[j].as = -1; 5488 } 5489 5490 /* Assign associations in order of their numbers, */ 5491 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5492 if (as[j].enable == 0) 5493 continue; 5494 5495 as[j].chan = free; 5496 sc->chans[free].as = j; 5497 sc->chans[free].dir = 5498 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5499 hdac_pcmchannel_setup(&sc->chans[free]); 5500 free++; 5501 } 5502 } 5503 5504 static void 5505 hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5506 { 5507 struct hdac_widget *w; 5508 int i; 5509 5510 /* Disable power and volume widgets. */ 5511 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5512 w = hdac_widget_get(devinfo, i); 5513 if (w == NULL || w->enable == 0) 5514 continue; 5515 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5516 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5517 w->enable = 0; 5518 HDA_BOOTHVERBOSE( 5519 device_printf(devinfo->codec->sc->dev, 5520 " Disabling nid %d due to it's" 5521 " non-audio type.\n", 5522 w->nid); 5523 ); 5524 } 5525 } 5526 } 5527 5528 static void 5529 hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5530 { 5531 struct hdac_widget *w, *cw; 5532 struct hdac_audio_ctl *ctl; 5533 int done, found, i, j, k; 5534 5535 /* Disable useless pins. */ 5536 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5537 w = hdac_widget_get(devinfo, i); 5538 if (w == NULL || w->enable == 0) 5539 continue; 5540 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5541 if ((w->wclass.pin.config & 5542 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5543 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5544 w->enable = 0; 5545 HDA_BOOTHVERBOSE( 5546 device_printf(devinfo->codec->sc->dev, 5547 " Disabling pin nid %d due" 5548 " to None connectivity.\n", 5549 w->nid); 5550 ); 5551 } else if ((w->wclass.pin.config & 5552 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5553 w->enable = 0; 5554 HDA_BOOTHVERBOSE( 5555 device_printf(devinfo->codec->sc->dev, 5556 " Disabling unassociated" 5557 " pin nid %d.\n", 5558 w->nid); 5559 ); 5560 } 5561 } 5562 } 5563 do { 5564 done = 1; 5565 /* Disable and mute controls for disabled widgets. */ 5566 i = 0; 5567 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5568 if (ctl->enable == 0) 5569 continue; 5570 if (ctl->widget->enable == 0 || 5571 (ctl->childwidget != NULL && 5572 ctl->childwidget->enable == 0)) { 5573 ctl->forcemute = 1; 5574 ctl->muted = HDA_AMP_MUTE_ALL; 5575 ctl->left = 0; 5576 ctl->right = 0; 5577 ctl->enable = 0; 5578 if (ctl->ndir == HDA_CTL_IN) 5579 ctl->widget->connsenable[ctl->index] = 0; 5580 done = 0; 5581 HDA_BOOTHVERBOSE( 5582 device_printf(devinfo->codec->sc->dev, 5583 " Disabling ctl %d nid %d cnid %d due" 5584 " to disabled widget.\n", i, 5585 ctl->widget->nid, 5586 (ctl->childwidget != NULL)? 5587 ctl->childwidget->nid:-1); 5588 ); 5589 } 5590 } 5591 /* Disable useless widgets. */ 5592 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5593 w = hdac_widget_get(devinfo, i); 5594 if (w == NULL || w->enable == 0) 5595 continue; 5596 /* Disable inputs with disabled child widgets. */ 5597 for (j = 0; j < w->nconns; j++) { 5598 if (w->connsenable[j]) { 5599 cw = hdac_widget_get(devinfo, w->conns[j]); 5600 if (cw == NULL || cw->enable == 0) { 5601 w->connsenable[j] = 0; 5602 HDA_BOOTHVERBOSE( 5603 device_printf(devinfo->codec->sc->dev, 5604 " Disabling nid %d connection %d due" 5605 " to disabled child widget.\n", 5606 i, j); 5607 ); 5608 } 5609 } 5610 } 5611 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5612 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5613 continue; 5614 /* Disable mixers and selectors without inputs. */ 5615 found = 0; 5616 for (j = 0; j < w->nconns; j++) { 5617 if (w->connsenable[j]) { 5618 found = 1; 5619 break; 5620 } 5621 } 5622 if (found == 0) { 5623 w->enable = 0; 5624 done = 0; 5625 HDA_BOOTHVERBOSE( 5626 device_printf(devinfo->codec->sc->dev, 5627 " Disabling nid %d due to all it's" 5628 " inputs disabled.\n", w->nid); 5629 ); 5630 } 5631 /* Disable nodes without consumers. */ 5632 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5633 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5634 continue; 5635 found = 0; 5636 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5637 cw = hdac_widget_get(devinfo, k); 5638 if (cw == NULL || cw->enable == 0) 5639 continue; 5640 for (j = 0; j < cw->nconns; j++) { 5641 if (cw->connsenable[j] && cw->conns[j] == i) { 5642 found = 1; 5643 break; 5644 } 5645 } 5646 } 5647 if (found == 0) { 5648 w->enable = 0; 5649 done = 0; 5650 HDA_BOOTHVERBOSE( 5651 device_printf(devinfo->codec->sc->dev, 5652 " Disabling nid %d due to all it's" 5653 " consumers disabled.\n", w->nid); 5654 ); 5655 } 5656 } 5657 } while (done == 0); 5658 5659 } 5660 5661 static void 5662 hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5663 { 5664 struct hdac_audio_as *as = devinfo->function.audio.as; 5665 struct hdac_widget *w, *cw; 5666 struct hdac_audio_ctl *ctl; 5667 int i, j, k; 5668 5669 /* Disable unassosiated widgets. */ 5670 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5671 w = hdac_widget_get(devinfo, i); 5672 if (w == NULL || w->enable == 0) 5673 continue; 5674 if (w->bindas == -1) { 5675 w->enable = 0; 5676 HDA_BOOTHVERBOSE( 5677 device_printf(devinfo->codec->sc->dev, 5678 " Disabling unassociated nid %d.\n", 5679 w->nid); 5680 ); 5681 } 5682 } 5683 /* Disable input connections on input pin and 5684 * output on output. */ 5685 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5686 w = hdac_widget_get(devinfo, i); 5687 if (w == NULL || w->enable == 0) 5688 continue; 5689 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5690 continue; 5691 if (w->bindas < 0) 5692 continue; 5693 if (as[w->bindas].dir == HDA_CTL_IN) { 5694 for (j = 0; j < w->nconns; j++) { 5695 if (w->connsenable[j] == 0) 5696 continue; 5697 w->connsenable[j] = 0; 5698 HDA_BOOTHVERBOSE( 5699 device_printf(devinfo->codec->sc->dev, 5700 " Disabling connection to input pin " 5701 "nid %d conn %d.\n", 5702 i, j); 5703 ); 5704 } 5705 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5706 HDA_CTL_IN, -1, 1); 5707 if (ctl && ctl->enable) { 5708 ctl->forcemute = 1; 5709 ctl->muted = HDA_AMP_MUTE_ALL; 5710 ctl->left = 0; 5711 ctl->right = 0; 5712 ctl->enable = 0; 5713 } 5714 } else { 5715 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5716 HDA_CTL_OUT, -1, 1); 5717 if (ctl && ctl->enable) { 5718 ctl->forcemute = 1; 5719 ctl->muted = HDA_AMP_MUTE_ALL; 5720 ctl->left = 0; 5721 ctl->right = 0; 5722 ctl->enable = 0; 5723 } 5724 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5725 cw = hdac_widget_get(devinfo, k); 5726 if (cw == NULL || cw->enable == 0) 5727 continue; 5728 for (j = 0; j < cw->nconns; j++) { 5729 if (cw->connsenable[j] && cw->conns[j] == i) { 5730 cw->connsenable[j] = 0; 5731 HDA_BOOTHVERBOSE( 5732 device_printf(devinfo->codec->sc->dev, 5733 " Disabling connection from output pin " 5734 "nid %d conn %d cnid %d.\n", 5735 k, j, i); 5736 ); 5737 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5738 cw->nconns > 1) 5739 continue; 5740 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5741 HDA_CTL_IN, j, 1); 5742 if (ctl && ctl->enable) { 5743 ctl->forcemute = 1; 5744 ctl->muted = HDA_AMP_MUTE_ALL; 5745 ctl->left = 0; 5746 ctl->right = 0; 5747 ctl->enable = 0; 5748 } 5749 } 5750 } 5751 } 5752 } 5753 } 5754 } 5755 5756 static void 5757 hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5758 { 5759 struct hdac_audio_as *as = devinfo->function.audio.as; 5760 struct hdac_widget *w; 5761 int i, j; 5762 5763 /* On playback path we can safely disable all unseleted inputs. */ 5764 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5765 w = hdac_widget_get(devinfo, i); 5766 if (w == NULL || w->enable == 0) 5767 continue; 5768 if (w->nconns <= 1) 5769 continue; 5770 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5771 continue; 5772 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5773 continue; 5774 for (j = 0; j < w->nconns; j++) { 5775 if (w->connsenable[j] == 0) 5776 continue; 5777 if (w->selconn < 0 || w->selconn == j) 5778 continue; 5779 w->connsenable[j] = 0; 5780 HDA_BOOTHVERBOSE( 5781 device_printf(devinfo->codec->sc->dev, 5782 " Disabling unselected connection " 5783 "nid %d conn %d.\n", 5784 i, j); 5785 ); 5786 } 5787 } 5788 } 5789 5790 static void 5791 hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5792 { 5793 struct hdac_audio_as *ases = devinfo->function.audio.as; 5794 struct hdac_widget *w, *cw; 5795 struct hdac_audio_ctl *ctl; 5796 int i, j; 5797 5798 /* Disable crossassociatement and unwanted crosschannel connections. */ 5799 /* ... using selectors */ 5800 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5801 w = hdac_widget_get(devinfo, i); 5802 if (w == NULL || w->enable == 0) 5803 continue; 5804 if (w->nconns <= 1) 5805 continue; 5806 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5807 continue; 5808 if (w->bindas == -2) 5809 continue; 5810 for (j = 0; j < w->nconns; j++) { 5811 if (w->connsenable[j] == 0) 5812 continue; 5813 cw = hdac_widget_get(devinfo, w->conns[j]); 5814 if (cw == NULL || w->enable == 0) 5815 continue; 5816 if (cw->bindas == -2 || 5817 ((w->pflags & HDA_ADC_MONITOR) && 5818 cw->bindas >= 0 && 5819 ases[cw->bindas].dir == HDA_CTL_IN)) 5820 continue; 5821 if (w->bindas == cw->bindas && 5822 (w->bindseqmask & cw->bindseqmask) != 0) 5823 continue; 5824 w->connsenable[j] = 0; 5825 HDA_BOOTHVERBOSE( 5826 device_printf(devinfo->codec->sc->dev, 5827 " Disabling crossassociatement connection " 5828 "nid %d conn %d cnid %d.\n", 5829 i, j, cw->nid); 5830 ); 5831 } 5832 } 5833 /* ... using controls */ 5834 i = 0; 5835 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5836 if (ctl->enable == 0 || ctl->childwidget == NULL) 5837 continue; 5838 if (ctl->widget->bindas == -2) 5839 continue; 5840 if (ctl->childwidget->bindas == -2 || 5841 ((ctl->widget->pflags & HDA_ADC_MONITOR) && 5842 ctl->childwidget->bindas >= 0 && 5843 ases[ctl->childwidget->bindas].dir == HDA_CTL_IN)) 5844 continue; 5845 if (ctl->widget->bindas != ctl->childwidget->bindas || 5846 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5847 ctl->forcemute = 1; 5848 ctl->muted = HDA_AMP_MUTE_ALL; 5849 ctl->left = 0; 5850 ctl->right = 0; 5851 ctl->enable = 0; 5852 if (ctl->ndir == HDA_CTL_IN) 5853 ctl->widget->connsenable[ctl->index] = 0; 5854 HDA_BOOTHVERBOSE( 5855 device_printf(devinfo->codec->sc->dev, 5856 " Disabling crossassociatement connection " 5857 "ctl %d nid %d cnid %d.\n", i, 5858 ctl->widget->nid, 5859 ctl->childwidget->nid); 5860 ); 5861 } 5862 } 5863 5864 } 5865 5866 #define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5867 5868 /* 5869 * Find controls to control amplification for source. 5870 */ 5871 static int 5872 hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5873 int ossdev, int ctlable, int depth, int need) 5874 { 5875 struct hdac_widget *w, *wc; 5876 struct hdac_audio_ctl *ctl; 5877 int i, j, conns = 0, rneed; 5878 5879 if (depth > HDA_PARSE_MAXDEPTH) 5880 return (need); 5881 5882 w = hdac_widget_get(devinfo, nid); 5883 if (w == NULL || w->enable == 0) 5884 return (need); 5885 5886 /* Count number of active inputs. */ 5887 if (depth > 0) { 5888 for (j = 0; j < w->nconns; j++) { 5889 if (w->connsenable[j]) 5890 conns++; 5891 } 5892 } 5893 5894 /* If this is not a first step - use input mixer. 5895 Pins have common input ctl so care must be taken. */ 5896 if (depth > 0 && ctlable && (conns == 1 || 5897 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5898 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5899 index, 1); 5900 if (ctl) { 5901 if (HDA_CTL_GIVE(ctl) & need) 5902 ctl->ossmask |= (1 << ossdev); 5903 else 5904 ctl->possmask |= (1 << ossdev); 5905 need &= ~HDA_CTL_GIVE(ctl); 5906 } 5907 } 5908 5909 /* If widget has own ossdev - not traverse it. 5910 It will be traversed on it's own. */ 5911 if (w->ossdev >= 0 && depth > 0) 5912 return (need); 5913 5914 /* We must not traverse pin */ 5915 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5916 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5917 depth > 0) 5918 return (need); 5919 5920 /* record that this widget exports such signal, */ 5921 w->ossmask |= (1 << ossdev); 5922 5923 /* If signals mixed, we can't assign controls farther. 5924 * Ignore this on depth zero. Caller must knows why. 5925 * Ignore this for static selectors if this input selected. 5926 */ 5927 if (conns > 1) 5928 ctlable = 0; 5929 5930 if (ctlable) { 5931 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5932 if (ctl) { 5933 if (HDA_CTL_GIVE(ctl) & need) 5934 ctl->ossmask |= (1 << ossdev); 5935 else 5936 ctl->possmask |= (1 << ossdev); 5937 need &= ~HDA_CTL_GIVE(ctl); 5938 } 5939 } 5940 5941 rneed = 0; 5942 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5943 wc = hdac_widget_get(devinfo, i); 5944 if (wc == NULL || wc->enable == 0) 5945 continue; 5946 for (j = 0; j < wc->nconns; j++) { 5947 if (wc->connsenable[j] && wc->conns[j] == nid) { 5948 rneed |= hdac_audio_ctl_source_amp(devinfo, 5949 wc->nid, j, ossdev, ctlable, depth + 1, need); 5950 } 5951 } 5952 } 5953 rneed &= need; 5954 5955 return (rneed); 5956 } 5957 5958 /* 5959 * Find controls to control amplification for destination. 5960 */ 5961 static void 5962 hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5963 int ossdev, int depth, int need) 5964 { 5965 struct hdac_audio_as *as = devinfo->function.audio.as; 5966 struct hdac_widget *w, *wc; 5967 struct hdac_audio_ctl *ctl; 5968 int i, j, consumers; 5969 5970 if (depth > HDA_PARSE_MAXDEPTH) 5971 return; 5972 5973 w = hdac_widget_get(devinfo, nid); 5974 if (w == NULL || w->enable == 0) 5975 return; 5976 5977 if (depth > 0) { 5978 /* If this node produce output for several consumers, 5979 we can't touch it. */ 5980 consumers = 0; 5981 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5982 wc = hdac_widget_get(devinfo, i); 5983 if (wc == NULL || wc->enable == 0) 5984 continue; 5985 for (j = 0; j < wc->nconns; j++) { 5986 if (wc->connsenable[j] && wc->conns[j] == nid) 5987 consumers++; 5988 } 5989 } 5990 /* The only exception is if real HP redirection is configured 5991 and this is a duplication point. 5992 XXX: Actually exception is not completely correct. 5993 XXX: Duplication point check is not perfect. */ 5994 if ((consumers == 2 && (w->bindas < 0 || 5995 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5996 (w->bindseqmask & (1 << 15)) == 0)) || 5997 consumers > 2) 5998 return; 5999 6000 /* Else use it's output mixer. */ 6001 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 6002 HDA_CTL_OUT, -1, 1); 6003 if (ctl) { 6004 if (HDA_CTL_GIVE(ctl) & need) 6005 ctl->ossmask |= (1 << ossdev); 6006 else 6007 ctl->possmask |= (1 << ossdev); 6008 need &= ~HDA_CTL_GIVE(ctl); 6009 } 6010 } 6011 6012 /* We must not traverse pin */ 6013 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6014 depth > 0) 6015 return; 6016 6017 for (i = 0; i < w->nconns; i++) { 6018 int tneed = need; 6019 if (w->connsenable[i] == 0) 6020 continue; 6021 if (index >= 0 && i != index) 6022 continue; 6023 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 6024 HDA_CTL_IN, i, 1); 6025 if (ctl) { 6026 if (HDA_CTL_GIVE(ctl) & tneed) 6027 ctl->ossmask |= (1 << ossdev); 6028 else 6029 ctl->possmask |= (1 << ossdev); 6030 tneed &= ~HDA_CTL_GIVE(ctl); 6031 } 6032 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], -1, ossdev, 6033 depth + 1, tneed); 6034 } 6035 } 6036 6037 /* 6038 * Assign OSS names to sound sources 6039 */ 6040 static void 6041 hdac_audio_assign_names(struct hdac_devinfo *devinfo) 6042 { 6043 struct hdac_audio_as *as = devinfo->function.audio.as; 6044 struct hdac_widget *w; 6045 int i, j; 6046 int type = -1, use, used = 0; 6047 static const int types[7][13] = { 6048 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6049 SOUND_MIXER_LINE3, -1 }, /* line */ 6050 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 6051 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 6052 { SOUND_MIXER_CD, -1 }, /* cd */ 6053 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 6054 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 6055 -1 }, /* digital */ 6056 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6057 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 6058 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 6059 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 6060 -1 } /* others */ 6061 }; 6062 6063 /* Surely known names */ 6064 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6065 w = hdac_widget_get(devinfo, i); 6066 if (w == NULL || w->enable == 0) 6067 continue; 6068 if (w->bindas == -1) 6069 continue; 6070 use = -1; 6071 switch (w->type) { 6072 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 6073 if (as[w->bindas].dir == HDA_CTL_OUT) 6074 break; 6075 type = -1; 6076 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6077 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 6078 type = 0; 6079 break; 6080 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6081 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 6082 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 6083 break; 6084 type = 1; 6085 break; 6086 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 6087 type = 3; 6088 break; 6089 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6090 type = 4; 6091 break; 6092 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 6093 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 6094 type = 5; 6095 break; 6096 } 6097 if (type == -1) 6098 break; 6099 j = 0; 6100 while (types[type][j] >= 0 && 6101 (used & (1 << types[type][j])) != 0) { 6102 j++; 6103 } 6104 if (types[type][j] >= 0) 6105 use = types[type][j]; 6106 break; 6107 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 6108 use = SOUND_MIXER_PCM; 6109 break; 6110 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 6111 use = SOUND_MIXER_SPEAKER; 6112 break; 6113 default: 6114 break; 6115 } 6116 if (use >= 0) { 6117 w->ossdev = use; 6118 used |= (1 << use); 6119 } 6120 } 6121 /* Semi-known names */ 6122 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6123 w = hdac_widget_get(devinfo, i); 6124 if (w == NULL || w->enable == 0) 6125 continue; 6126 if (w->ossdev >= 0) 6127 continue; 6128 if (w->bindas == -1) 6129 continue; 6130 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6131 continue; 6132 if (as[w->bindas].dir == HDA_CTL_OUT) 6133 continue; 6134 type = -1; 6135 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6136 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6137 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6138 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6139 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6140 type = 0; 6141 break; 6142 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6143 type = 2; 6144 break; 6145 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6146 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6147 type = 5; 6148 break; 6149 } 6150 if (type == -1) 6151 break; 6152 j = 0; 6153 while (types[type][j] >= 0 && 6154 (used & (1 << types[type][j])) != 0) { 6155 j++; 6156 } 6157 if (types[type][j] >= 0) { 6158 w->ossdev = types[type][j]; 6159 used |= (1 << types[type][j]); 6160 } 6161 } 6162 /* Others */ 6163 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6164 w = hdac_widget_get(devinfo, i); 6165 if (w == NULL || w->enable == 0) 6166 continue; 6167 if (w->ossdev >= 0) 6168 continue; 6169 if (w->bindas == -1) 6170 continue; 6171 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6172 continue; 6173 if (as[w->bindas].dir == HDA_CTL_OUT) 6174 continue; 6175 j = 0; 6176 while (types[6][j] >= 0 && 6177 (used & (1 << types[6][j])) != 0) { 6178 j++; 6179 } 6180 if (types[6][j] >= 0) { 6181 w->ossdev = types[6][j]; 6182 used |= (1 << types[6][j]); 6183 } 6184 } 6185 } 6186 6187 static void 6188 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6189 { 6190 struct hdac_audio_as *as = devinfo->function.audio.as; 6191 int j, res; 6192 6193 /* Trace all associations in order of their numbers, */ 6194 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6195 if (as[j].enable == 0) 6196 continue; 6197 HDA_BOOTVERBOSE( 6198 device_printf(devinfo->codec->sc->dev, 6199 "Tracing association %d (%d)\n", j, as[j].index); 6200 ); 6201 if (as[j].dir == HDA_CTL_OUT) { 6202 retry: 6203 res = hdac_audio_trace_as_out(devinfo, j, 0); 6204 if (res == 0 && as[j].hpredir >= 0 && 6205 as[j].fakeredir == 0) { 6206 /* If codec can't do analog HP redirection 6207 try to make it using one more DAC. */ 6208 as[j].fakeredir = 1; 6209 goto retry; 6210 } 6211 } else { 6212 res = hdac_audio_trace_as_in(devinfo, j); 6213 } 6214 if (res) { 6215 HDA_BOOTVERBOSE( 6216 device_printf(devinfo->codec->sc->dev, 6217 "Association %d (%d) trace succeeded\n", 6218 j, as[j].index); 6219 ); 6220 } else { 6221 HDA_BOOTVERBOSE( 6222 device_printf(devinfo->codec->sc->dev, 6223 "Association %d (%d) trace failed\n", 6224 j, as[j].index); 6225 ); 6226 as[j].enable = 0; 6227 } 6228 } 6229 6230 /* Trace mixer and beeper pseudo associations. */ 6231 hdac_audio_trace_as_extra(devinfo); 6232 } 6233 6234 static void 6235 hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6236 { 6237 struct hdac_audio_as *as = devinfo->function.audio.as; 6238 struct hdac_audio_ctl *ctl; 6239 struct hdac_widget *w, *cw; 6240 int i, j; 6241 6242 /* Assign mixers to the tree. */ 6243 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6244 w = hdac_widget_get(devinfo, i); 6245 if (w == NULL || w->enable == 0) 6246 continue; 6247 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6248 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6249 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6250 as[w->bindas].dir == HDA_CTL_IN)) { 6251 if (w->ossdev < 0) 6252 continue; 6253 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6254 w->ossdev, 1, 0, 1); 6255 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6256 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6257 SOUND_MIXER_RECLEV, 0, 1); 6258 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6259 as[w->bindas].dir == HDA_CTL_OUT) { 6260 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6261 SOUND_MIXER_VOLUME, 0, 1); 6262 } 6263 if (w->ossdev == SOUND_MIXER_IMIX) { 6264 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6265 w->ossdev, 1, 0, 1)) { 6266 /* If we are unable to control input monitor 6267 as source - try to control it as destination. */ 6268 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6269 w->ossdev, 0, 1); 6270 } 6271 } 6272 if (w->pflags & HDA_ADC_MONITOR) { 6273 for (j = 0; j < w->nconns; j++) { 6274 if (!w->connsenable[j]) 6275 continue; 6276 cw = hdac_widget_get(devinfo, w->conns[j]); 6277 if (cw == NULL || cw->enable == 0) 6278 continue; 6279 if (cw->bindas == -1) 6280 continue; 6281 if (cw->bindas >= 0 && 6282 as[cw->bindas].dir != HDA_CTL_IN) 6283 continue; 6284 hdac_audio_ctl_dest_amp(devinfo, 6285 w->nid, j, SOUND_MIXER_IGAIN, 0, 1); 6286 } 6287 } 6288 } 6289 /* Treat unrequired as possible. */ 6290 i = 0; 6291 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6292 if (ctl->ossmask == 0) 6293 ctl->ossmask = ctl->possmask; 6294 } 6295 } 6296 6297 static void 6298 hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6299 { 6300 struct hdac_audio_as *as = devinfo->function.audio.as; 6301 struct hdac_widget *w; 6302 uint32_t pincap; 6303 int i; 6304 6305 for (i = 0; i < devinfo->nodecnt; i++) { 6306 w = &devinfo->widget[i]; 6307 if (w == NULL) 6308 continue; 6309 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6310 continue; 6311 6312 pincap = w->wclass.pin.cap; 6313 6314 /* Disable everything. */ 6315 w->wclass.pin.ctrl &= ~( 6316 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6317 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6318 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6319 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6320 6321 if (w->enable == 0 || 6322 w->bindas < 0 || as[w->bindas].enable == 0) { 6323 /* Pin is unused so left it disabled. */ 6324 continue; 6325 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6326 /* Input pin, configure for input. */ 6327 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6328 w->wclass.pin.ctrl |= 6329 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6330 6331 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6332 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6333 w->wclass.pin.ctrl |= 6334 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6335 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6336 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6337 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6338 w->wclass.pin.ctrl |= 6339 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6340 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6341 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6342 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6343 w->wclass.pin.ctrl |= 6344 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6345 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6346 } else { 6347 /* Output pin, configure for output. */ 6348 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6349 w->wclass.pin.ctrl |= 6350 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6351 6352 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6353 (w->wclass.pin.config & 6354 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6355 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6356 w->wclass.pin.ctrl |= 6357 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6358 6359 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6360 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6361 w->wclass.pin.ctrl |= 6362 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6363 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6364 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6365 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6366 w->wclass.pin.ctrl |= 6367 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6368 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6369 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6370 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6371 w->wclass.pin.ctrl |= 6372 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6373 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6374 } 6375 } 6376 } 6377 6378 static void 6379 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6380 { 6381 struct hdac_audio_ctl *ctl; 6382 int i, z; 6383 6384 i = 0; 6385 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6386 if (ctl->enable == 0 || ctl->ossmask != 0) { 6387 /* Mute disabled and mixer controllable controls. 6388 * Last will be initialized by mixer_init(). 6389 * This expected to reduce click on startup. */ 6390 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6391 continue; 6392 } 6393 /* Init fixed controls to 0dB amplification. */ 6394 z = ctl->offset; 6395 if (z > ctl->step) 6396 z = ctl->step; 6397 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6398 } 6399 } 6400 6401 static void 6402 hdac_audio_commit(struct hdac_devinfo *devinfo) 6403 { 6404 struct hdac_softc *sc = devinfo->codec->sc; 6405 struct hdac_widget *w; 6406 nid_t cad; 6407 uint32_t gdata, gmask, gdir; 6408 int commitgpio, numgpio; 6409 int i; 6410 6411 cad = devinfo->codec->cad; 6412 6413 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6414 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6415 0x7e7, 0), cad); 6416 6417 /* Commit controls. */ 6418 hdac_audio_ctl_commit(devinfo); 6419 6420 /* Commit selectors, pins and EAPD. */ 6421 for (i = 0; i < devinfo->nodecnt; i++) { 6422 w = &devinfo->widget[i]; 6423 if (w == NULL) 6424 continue; 6425 if (w->selconn == -1) 6426 w->selconn = 0; 6427 if (w->nconns > 0) 6428 hdac_widget_connection_select(w, w->selconn); 6429 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6430 hdac_command(sc, 6431 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6432 w->wclass.pin.ctrl), cad); 6433 } 6434 if (w->param.eapdbtl != HDAC_INVALID) { 6435 uint32_t val; 6436 6437 val = w->param.eapdbtl; 6438 if (devinfo->function.audio.quirks & 6439 HDA_QUIRK_EAPDINV) 6440 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6441 hdac_command(sc, 6442 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6443 val), cad); 6444 } 6445 } 6446 6447 /* Commit GPIOs. */ 6448 gdata = 0; 6449 gmask = 0; 6450 gdir = 0; 6451 commitgpio = 0; 6452 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6453 devinfo->function.audio.gpio); 6454 6455 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6456 commitgpio = (numgpio > 0) ? 1 : 0; 6457 else { 6458 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6459 if (!(devinfo->function.audio.quirks & 6460 (1 << i))) 6461 continue; 6462 if (commitgpio == 0) { 6463 commitgpio = 1; 6464 HDA_BOOTVERBOSE( 6465 gdata = hdac_command(sc, 6466 HDA_CMD_GET_GPIO_DATA(cad, 6467 devinfo->nid), cad); 6468 gmask = hdac_command(sc, 6469 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6470 devinfo->nid), cad); 6471 gdir = hdac_command(sc, 6472 HDA_CMD_GET_GPIO_DIRECTION(cad, 6473 devinfo->nid), cad); 6474 device_printf(sc->dev, 6475 "GPIO init: data=0x%08x " 6476 "mask=0x%08x dir=0x%08x\n", 6477 gdata, gmask, gdir); 6478 gdata = 0; 6479 gmask = 0; 6480 gdir = 0; 6481 ); 6482 } 6483 gdata |= 1 << i; 6484 gmask |= 1 << i; 6485 gdir |= 1 << i; 6486 } 6487 } 6488 6489 if (commitgpio != 0) { 6490 HDA_BOOTVERBOSE( 6491 device_printf(sc->dev, 6492 "GPIO commit: data=0x%08x mask=0x%08x " 6493 "dir=0x%08x\n", 6494 gdata, gmask, gdir); 6495 ); 6496 hdac_command(sc, 6497 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6498 gmask), cad); 6499 hdac_command(sc, 6500 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6501 gdir), cad); 6502 hdac_command(sc, 6503 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6504 gdata), cad); 6505 } 6506 } 6507 6508 static void 6509 hdac_powerup(struct hdac_devinfo *devinfo) 6510 { 6511 struct hdac_softc *sc = devinfo->codec->sc; 6512 nid_t cad = devinfo->codec->cad; 6513 int i; 6514 6515 hdac_command(sc, 6516 HDA_CMD_SET_POWER_STATE(cad, 6517 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6518 cad); 6519 DELAY(100); 6520 6521 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6522 hdac_command(sc, 6523 HDA_CMD_SET_POWER_STATE(cad, 6524 i, HDA_CMD_POWER_STATE_D0), 6525 cad); 6526 } 6527 DELAY(1000); 6528 } 6529 6530 static int 6531 hdac_pcmchannel_setup(struct hdac_chan *ch) 6532 { 6533 struct hdac_devinfo *devinfo = ch->devinfo; 6534 struct hdac_audio_as *as = devinfo->function.audio.as; 6535 struct hdac_widget *w; 6536 uint32_t cap, fmtcap, pcmcap; 6537 int i, j, ret, channels, onlystereo; 6538 uint16_t pinset; 6539 6540 ch->caps = hdac_caps; 6541 ch->caps.fmtlist = ch->fmtlist; 6542 ch->bit16 = 1; 6543 ch->bit32 = 0; 6544 ch->pcmrates[0] = 48000; 6545 ch->pcmrates[1] = 0; 6546 6547 ret = 0; 6548 channels = 0; 6549 onlystereo = 1; 6550 pinset = 0; 6551 fmtcap = devinfo->function.audio.supp_stream_formats; 6552 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6553 6554 for (i = 0; i < 16; i++) { 6555 /* Check as is correct */ 6556 if (ch->as < 0) 6557 break; 6558 /* Cound only present DACs */ 6559 if (as[ch->as].dacs[i] <= 0) 6560 continue; 6561 /* Ignore duplicates */ 6562 for (j = 0; j < ret; j++) { 6563 if (ch->io[j] == as[ch->as].dacs[i]) 6564 break; 6565 } 6566 if (j < ret) 6567 continue; 6568 6569 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6570 if (w == NULL || w->enable == 0) 6571 continue; 6572 cap = w->param.supp_stream_formats; 6573 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6574 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6575 continue; 6576 /* Many CODECs does not declare AC3 support on SPDIF. 6577 I don't beleave that they doesn't support it! */ 6578 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6579 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6580 if (ret == 0) { 6581 fmtcap = cap; 6582 pcmcap = w->param.supp_pcm_size_rate; 6583 } else { 6584 fmtcap &= cap; 6585 pcmcap &= w->param.supp_pcm_size_rate; 6586 } 6587 ch->io[ret++] = as[ch->as].dacs[i]; 6588 /* Do not count redirection pin/dac channels. */ 6589 if (i == 15 && as[ch->as].hpredir >= 0) 6590 continue; 6591 channels += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 6592 if (HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) != 1) 6593 onlystereo = 0; 6594 pinset |= (1 << i); 6595 } 6596 ch->io[ret] = -1; 6597 6598 if (as[ch->as].fakeredir) 6599 ret--; 6600 /* Standard speaks only about stereo pins and playback, ... */ 6601 if ((!onlystereo) || as[ch->as].dir != HDA_CTL_OUT) 6602 pinset = 0; 6603 /* ..., but there it gives us info about speakers layout. */ 6604 as[ch->as].pinset = pinset; 6605 6606 ch->supp_stream_formats = fmtcap; 6607 ch->supp_pcm_size_rate = pcmcap; 6608 6609 /* 6610 * 8bit = 0 6611 * 16bit = 1 6612 * 20bit = 2 6613 * 24bit = 3 6614 * 32bit = 4 6615 */ 6616 if (ret > 0) { 6617 i = 0; 6618 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6619 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6620 ch->bit16 = 1; 6621 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6622 ch->bit16 = 0; 6623 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6624 ch->bit32 = 4; 6625 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6626 ch->bit32 = 3; 6627 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6628 ch->bit32 = 2; 6629 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) { 6630 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 1, 0); 6631 if (ch->bit32) 6632 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 1, 0); 6633 } 6634 if (channels >= 2) { 6635 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6636 if (ch->bit32) 6637 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 2, 0); 6638 } 6639 if (channels == 4 || /* Any 4-channel */ 6640 pinset == 0x0007 || /* 5.1 */ 6641 pinset == 0x0013 || /* 5.1 */ 6642 pinset == 0x0017) { /* 7.1 */ 6643 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 4, 0); 6644 if (ch->bit32) 6645 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 4, 0); 6646 } 6647 if (channels == 6 || /* Any 6-channel */ 6648 pinset == 0x0017) { /* 7.1 */ 6649 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 6, 1); 6650 if (ch->bit32) 6651 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 6, 1); 6652 } 6653 if (channels == 8) { /* Any 8-channel */ 6654 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 8, 1); 6655 if (ch->bit32) 6656 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 8, 1); 6657 } 6658 } 6659 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6660 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6661 } 6662 ch->fmtlist[i] = 0; 6663 i = 0; 6664 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6665 ch->pcmrates[i++] = 8000; 6666 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6667 ch->pcmrates[i++] = 11025; 6668 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6669 ch->pcmrates[i++] = 16000; 6670 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6671 ch->pcmrates[i++] = 22050; 6672 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6673 ch->pcmrates[i++] = 32000; 6674 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6675 ch->pcmrates[i++] = 44100; 6676 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6677 ch->pcmrates[i++] = 48000; 6678 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6679 ch->pcmrates[i++] = 88200; 6680 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6681 ch->pcmrates[i++] = 96000; 6682 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6683 ch->pcmrates[i++] = 176400; 6684 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6685 ch->pcmrates[i++] = 192000; 6686 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6687 ch->pcmrates[i] = 0; 6688 if (i > 0) { 6689 ch->caps.minspeed = ch->pcmrates[0]; 6690 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6691 } 6692 } 6693 6694 return (ret); 6695 } 6696 6697 static void 6698 hdac_create_pcms(struct hdac_devinfo *devinfo) 6699 { 6700 struct hdac_softc *sc = devinfo->codec->sc; 6701 struct hdac_audio_as *as = devinfo->function.audio.as; 6702 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6703 6704 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6705 if (as[i].enable == 0) 6706 continue; 6707 if (as[i].dir == HDA_CTL_IN) { 6708 if (as[i].digital) 6709 drdev++; 6710 else 6711 ardev++; 6712 } else { 6713 if (as[i].digital) 6714 dpdev++; 6715 else 6716 apdev++; 6717 } 6718 } 6719 devinfo->function.audio.num_devs = 6720 max(ardev, apdev) + max(drdev, dpdev); 6721 devinfo->function.audio.devs = 6722 (struct hdac_pcm_devinfo *)malloc( 6723 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6724 M_HDAC, M_ZERO | M_NOWAIT); 6725 if (devinfo->function.audio.devs == NULL) { 6726 device_printf(sc->dev, 6727 "Unable to allocate memory for devices\n"); 6728 return; 6729 } 6730 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6731 devinfo->function.audio.devs[i].index = i; 6732 devinfo->function.audio.devs[i].devinfo = devinfo; 6733 devinfo->function.audio.devs[i].play = -1; 6734 devinfo->function.audio.devs[i].rec = -1; 6735 devinfo->function.audio.devs[i].digital = 255; 6736 } 6737 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6738 if (as[i].enable == 0) 6739 continue; 6740 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6741 if (devinfo->function.audio.devs[j].digital != 255 && 6742 (!devinfo->function.audio.devs[j].digital) != 6743 (!as[i].digital)) 6744 continue; 6745 if (as[i].dir == HDA_CTL_IN) { 6746 if (devinfo->function.audio.devs[j].rec >= 0) 6747 continue; 6748 devinfo->function.audio.devs[j].rec 6749 = as[i].chan; 6750 } else { 6751 if (devinfo->function.audio.devs[j].play >= 0) 6752 continue; 6753 devinfo->function.audio.devs[j].play 6754 = as[i].chan; 6755 } 6756 sc->chans[as[i].chan].pdevinfo = 6757 &devinfo->function.audio.devs[j]; 6758 devinfo->function.audio.devs[j].digital = 6759 as[i].digital; 6760 break; 6761 } 6762 } 6763 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6764 struct hdac_pcm_devinfo *pdevinfo = 6765 &devinfo->function.audio.devs[i]; 6766 pdevinfo->dev = 6767 device_add_child(sc->dev, "pcm", -1); 6768 device_set_ivars(pdevinfo->dev, 6769 (void *)pdevinfo); 6770 } 6771 } 6772 6773 static void 6774 hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6775 { 6776 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6777 struct hdac_audio_ctl *ctl; 6778 struct hdac_softc *sc = devinfo->codec->sc; 6779 char buf[64]; 6780 int i, j, printed; 6781 6782 if (flag == 0) { 6783 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6784 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6785 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_IGAIN | 6786 SOUND_MASK_OGAIN | SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6787 } 6788 6789 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6790 if ((flag & (1 << j)) == 0) 6791 continue; 6792 i = 0; 6793 printed = 0; 6794 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6795 if (ctl->enable == 0 || 6796 ctl->widget->enable == 0) 6797 continue; 6798 if (!((pdevinfo->play >= 0 && 6799 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6800 (pdevinfo->rec >= 0 && 6801 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6802 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6803 continue; 6804 if ((ctl->ossmask & (1 << j)) == 0) 6805 continue; 6806 6807 if (printed == 0) { 6808 device_printf(pdevinfo->dev, "\n"); 6809 if (banner != NULL) { 6810 device_printf(pdevinfo->dev, "%s", banner); 6811 } else { 6812 device_printf(pdevinfo->dev, "Unknown Ctl"); 6813 } 6814 printf(" (OSS: %s)\n", 6815 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6816 buf, sizeof(buf))); 6817 device_printf(pdevinfo->dev, " |\n"); 6818 printed = 1; 6819 } 6820 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6821 ctl->widget->nid, 6822 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6823 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6824 printf(" %2d): ", ctl->index); 6825 else 6826 printf("): "); 6827 if (ctl->step > 0) { 6828 printf("%+d/%+ddB (%d steps)%s\n", 6829 (0 - ctl->offset) * (ctl->size + 1) / 4, 6830 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6831 ctl->step + 1, 6832 ctl->mute?" + mute":""); 6833 } else 6834 printf("%s\n", ctl->mute?"mute":""); 6835 } 6836 } 6837 } 6838 6839 static void 6840 hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6841 { 6842 uint32_t cap; 6843 6844 cap = fcap; 6845 if (cap != 0) { 6846 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6847 device_printf(dev, " "); 6848 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6849 printf(" AC3"); 6850 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6851 printf(" FLOAT32"); 6852 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6853 printf(" PCM"); 6854 printf("\n"); 6855 } 6856 cap = pcmcap; 6857 if (cap != 0) { 6858 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6859 device_printf(dev, " "); 6860 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6861 printf(" 8"); 6862 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6863 printf(" 16"); 6864 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6865 printf(" 20"); 6866 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6867 printf(" 24"); 6868 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6869 printf(" 32"); 6870 printf(" bits,"); 6871 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6872 printf(" 8"); 6873 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6874 printf(" 11"); 6875 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6876 printf(" 16"); 6877 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6878 printf(" 22"); 6879 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6880 printf(" 32"); 6881 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6882 printf(" 44"); 6883 printf(" 48"); 6884 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6885 printf(" 88"); 6886 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6887 printf(" 96"); 6888 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6889 printf(" 176"); 6890 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6891 printf(" 192"); 6892 printf(" KHz\n"); 6893 } 6894 } 6895 6896 static void 6897 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6898 { 6899 uint32_t pincap; 6900 6901 pincap = w->wclass.pin.cap; 6902 6903 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6904 device_printf(sc->dev, " "); 6905 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6906 printf(" ISC"); 6907 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6908 printf(" TRQD"); 6909 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6910 printf(" PDC"); 6911 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6912 printf(" HP"); 6913 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6914 printf(" OUT"); 6915 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6916 printf(" IN"); 6917 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6918 printf(" BAL"); 6919 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6920 printf(" HDMI"); 6921 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6922 printf(" VREF["); 6923 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6924 printf(" 50"); 6925 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6926 printf(" 80"); 6927 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6928 printf(" 100"); 6929 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6930 printf(" GROUND"); 6931 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6932 printf(" HIZ"); 6933 printf(" ]"); 6934 } 6935 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6936 printf(" EAPD"); 6937 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6938 printf(" DP"); 6939 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6940 printf(" HBR"); 6941 printf("\n"); 6942 device_printf(sc->dev, " Pin config: 0x%08x\n", 6943 w->wclass.pin.config); 6944 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6945 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6946 printf(" HP"); 6947 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6948 printf(" IN"); 6949 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6950 printf(" OUT"); 6951 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6952 printf(" VREFs"); 6953 printf("\n"); 6954 } 6955 6956 static void 6957 hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6958 { 6959 struct hdac_softc *sc = w->devinfo->codec->sc; 6960 6961 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6962 "jack %2d loc %2d color %7s misc %d%s\n", 6963 w->nid, conf, 6964 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6965 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6966 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6967 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6968 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6969 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6970 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6971 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6972 (w->enable == 0)?" [DISABLED]":""); 6973 } 6974 6975 static void 6976 hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6977 { 6978 struct hdac_widget *w; 6979 int i; 6980 6981 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6982 w = hdac_widget_get(devinfo, i); 6983 if (w == NULL) 6984 continue; 6985 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6986 continue; 6987 hdac_dump_pin_config(w, w->wclass.pin.config); 6988 } 6989 } 6990 6991 static void 6992 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6993 { 6994 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6995 device_printf(sc->dev, " " 6996 "mute=%d step=%d size=%d offset=%d\n", 6997 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6998 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6999 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 7000 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 7001 } 7002 7003 static void 7004 hdac_dump_nodes(struct hdac_devinfo *devinfo) 7005 { 7006 struct hdac_softc *sc = devinfo->codec->sc; 7007 static char *ossname[] = SOUND_DEVICE_NAMES; 7008 struct hdac_widget *w, *cw; 7009 char buf[64]; 7010 int i, j; 7011 7012 device_printf(sc->dev, "\n"); 7013 device_printf(sc->dev, "Default Parameter\n"); 7014 device_printf(sc->dev, "-----------------\n"); 7015 hdac_dump_audio_formats(sc->dev, 7016 devinfo->function.audio.supp_stream_formats, 7017 devinfo->function.audio.supp_pcm_size_rate); 7018 device_printf(sc->dev, " IN amp: 0x%08x\n", 7019 devinfo->function.audio.inamp_cap); 7020 device_printf(sc->dev, " OUT amp: 0x%08x\n", 7021 devinfo->function.audio.outamp_cap); 7022 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7023 w = hdac_widget_get(devinfo, i); 7024 if (w == NULL) { 7025 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 7026 continue; 7027 } 7028 device_printf(sc->dev, "\n"); 7029 device_printf(sc->dev, " nid: %d%s\n", w->nid, 7030 (w->enable == 0) ? " [DISABLED]" : ""); 7031 device_printf(sc->dev, " Name: %s\n", w->name); 7032 device_printf(sc->dev, " Widget cap: 0x%08x\n", 7033 w->param.widget_cap); 7034 if (w->param.widget_cap & 0x0ee1) { 7035 device_printf(sc->dev, " "); 7036 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 7037 printf(" LRSWAP"); 7038 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 7039 printf(" PWR"); 7040 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 7041 printf(" DIGITAL"); 7042 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 7043 printf(" UNSOL"); 7044 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 7045 printf(" PROC"); 7046 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 7047 printf(" STRIPE"); 7048 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 7049 if (j == 1) 7050 printf(" STEREO"); 7051 else if (j > 1) 7052 printf(" %dCH", j + 1); 7053 printf("\n"); 7054 } 7055 if (w->bindas != -1) { 7056 device_printf(sc->dev, " Association: %d (0x%08x)\n", 7057 w->bindas, w->bindseqmask); 7058 } 7059 if (w->ossmask != 0 || w->ossdev >= 0) { 7060 device_printf(sc->dev, " OSS: %s", 7061 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 7062 if (w->ossdev >= 0) 7063 printf(" (%s)", ossname[w->ossdev]); 7064 printf("\n"); 7065 } 7066 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 7067 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 7068 hdac_dump_audio_formats(sc->dev, 7069 w->param.supp_stream_formats, 7070 w->param.supp_pcm_size_rate); 7071 } else if (w->type == 7072 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7073 hdac_dump_pin(sc, w); 7074 if (w->param.eapdbtl != HDAC_INVALID) 7075 device_printf(sc->dev, " EAPD: 0x%08x\n", 7076 w->param.eapdbtl); 7077 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 7078 w->param.outamp_cap != 0) 7079 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 7080 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 7081 w->param.inamp_cap != 0) 7082 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 7083 if (w->nconns > 0) { 7084 device_printf(sc->dev, " connections: %d\n", w->nconns); 7085 device_printf(sc->dev, " |\n"); 7086 } 7087 for (j = 0; j < w->nconns; j++) { 7088 cw = hdac_widget_get(devinfo, w->conns[j]); 7089 device_printf(sc->dev, " + %s<- nid=%d [%s]", 7090 (w->connsenable[j] == 0)?"[DISABLED] ":"", 7091 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 7092 if (cw == NULL) 7093 printf(" [UNKNOWN]"); 7094 else if (cw->enable == 0) 7095 printf(" [DISABLED]"); 7096 if (w->nconns > 1 && w->selconn == j && w->type != 7097 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 7098 printf(" (selected)"); 7099 printf("\n"); 7100 } 7101 } 7102 7103 } 7104 7105 static void 7106 hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 7107 { 7108 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7109 struct hdac_widget *w, *cw; 7110 char buf[64]; 7111 int i, printed = 0; 7112 7113 if (depth > HDA_PARSE_MAXDEPTH) 7114 return; 7115 7116 w = hdac_widget_get(devinfo, nid); 7117 if (w == NULL || w->enable == 0) 7118 return; 7119 7120 if (depth == 0) 7121 device_printf(pdevinfo->dev, "%*s", 4, ""); 7122 else 7123 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 7124 printf("nid=%d [%s]", w->nid, w->name); 7125 7126 if (depth > 0) { 7127 if (w->ossmask == 0) { 7128 printf("\n"); 7129 return; 7130 } 7131 printf(" [src: %s]", 7132 hdac_audio_ctl_ossmixer_mask2allname( 7133 w->ossmask, buf, sizeof(buf))); 7134 if (w->ossdev >= 0) { 7135 printf("\n"); 7136 return; 7137 } 7138 } 7139 printf("\n"); 7140 7141 for (i = 0; i < w->nconns; i++) { 7142 if (w->connsenable[i] == 0) 7143 continue; 7144 cw = hdac_widget_get(devinfo, w->conns[i]); 7145 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 7146 continue; 7147 if (printed == 0) { 7148 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 7149 printed = 1; 7150 } 7151 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 7152 } 7153 7154 } 7155 7156 static void 7157 hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 7158 { 7159 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7160 struct hdac_softc *sc = devinfo->codec->sc; 7161 struct hdac_audio_as *as; 7162 struct hdac_widget *w; 7163 int i, printed = 0; 7164 7165 if (pdevinfo->play < 0) 7166 return; 7167 7168 as = &devinfo->function.audio.as[sc->chans[pdevinfo->play].as]; 7169 for (i = 0; i < 16; i++) { 7170 if (as->pins[i] <= 0) 7171 continue; 7172 w = hdac_widget_get(devinfo, as->pins[i]); 7173 if (w == NULL || w->enable == 0) 7174 continue; 7175 if (printed == 0) { 7176 printed = 1; 7177 device_printf(pdevinfo->dev, "\n"); 7178 device_printf(pdevinfo->dev, "Playback:\n"); 7179 } 7180 device_printf(pdevinfo->dev, "\n"); 7181 hdac_dump_dst_nid(pdevinfo, as->pins[i], 0); 7182 } 7183 } 7184 7185 static void 7186 hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7187 { 7188 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7189 struct hdac_softc *sc = devinfo->codec->sc; 7190 struct hdac_widget *w; 7191 int i; 7192 int printed = 0; 7193 7194 if (pdevinfo->rec < 0) 7195 return; 7196 7197 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7198 w = hdac_widget_get(devinfo, i); 7199 if (w == NULL || w->enable == 0) 7200 continue; 7201 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7202 continue; 7203 if (w->bindas != sc->chans[pdevinfo->rec].as) 7204 continue; 7205 if (printed == 0) { 7206 printed = 1; 7207 device_printf(pdevinfo->dev, "\n"); 7208 device_printf(pdevinfo->dev, "Record:\n"); 7209 } 7210 device_printf(pdevinfo->dev, "\n"); 7211 hdac_dump_dst_nid(pdevinfo, i, 0); 7212 } 7213 } 7214 7215 static void 7216 hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7217 { 7218 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7219 struct hdac_widget *w; 7220 int i; 7221 int printed = 0; 7222 7223 if (pdevinfo->index != 0) 7224 return; 7225 7226 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7227 w = hdac_widget_get(devinfo, i); 7228 if (w == NULL || w->enable == 0) 7229 continue; 7230 if (w->ossdev != SOUND_MIXER_IMIX) 7231 continue; 7232 if (printed == 0) { 7233 printed = 1; 7234 device_printf(pdevinfo->dev, "\n"); 7235 device_printf(pdevinfo->dev, "Input Mix:\n"); 7236 } 7237 device_printf(pdevinfo->dev, "\n"); 7238 hdac_dump_dst_nid(pdevinfo, i, 0); 7239 } 7240 } 7241 7242 static void 7243 hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7244 { 7245 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7246 nid_t *nids; 7247 int i; 7248 7249 if (pdevinfo->play >= 0) { 7250 i = pdevinfo->play; 7251 device_printf(pdevinfo->dev, "\n"); 7252 device_printf(pdevinfo->dev, "Playback:\n"); 7253 device_printf(pdevinfo->dev, "\n"); 7254 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7255 sc->chans[i].supp_pcm_size_rate); 7256 device_printf(pdevinfo->dev, " DAC:"); 7257 for (nids = sc->chans[i].io; *nids != -1; nids++) 7258 printf(" %d", *nids); 7259 printf("\n"); 7260 } 7261 if (pdevinfo->rec >= 0) { 7262 i = pdevinfo->rec; 7263 device_printf(pdevinfo->dev, "\n"); 7264 device_printf(pdevinfo->dev, "Record:\n"); 7265 device_printf(pdevinfo->dev, "\n"); 7266 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7267 sc->chans[i].supp_pcm_size_rate); 7268 device_printf(pdevinfo->dev, " ADC:"); 7269 for (nids = sc->chans[i].io; *nids != -1; nids++) 7270 printf(" %d", *nids); 7271 printf("\n"); 7272 } 7273 } 7274 7275 static void 7276 hdac_release_resources(struct hdac_softc *sc) 7277 { 7278 int i, j; 7279 7280 if (sc == NULL) 7281 return; 7282 7283 hdac_lock(sc); 7284 sc->polling = 0; 7285 sc->poll_ival = 0; 7286 callout_stop(&sc->poll_hda); 7287 callout_stop(&sc->poll_hdac); 7288 callout_stop(&sc->poll_jack); 7289 hdac_reset(sc, 0); 7290 hdac_unlock(sc); 7291 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7292 callout_drain(&sc->poll_hda); 7293 callout_drain(&sc->poll_hdac); 7294 callout_drain(&sc->poll_jack); 7295 7296 hdac_irq_free(sc); 7297 7298 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7299 if (sc->codecs[i] == NULL) 7300 continue; 7301 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7302 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7303 if (sc->codecs[i]->fgs[j].node_type == 7304 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7305 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7306 M_HDAC); 7307 free(sc->codecs[i]->fgs[j].function.audio.as, 7308 M_HDAC); 7309 free(sc->codecs[i]->fgs[j].function.audio.devs, 7310 M_HDAC); 7311 } 7312 } 7313 free(sc->codecs[i]->fgs, M_HDAC); 7314 free(sc->codecs[i], M_HDAC); 7315 sc->codecs[i] = NULL; 7316 } 7317 7318 hdac_dma_free(sc, &sc->pos_dma); 7319 hdac_dma_free(sc, &sc->rirb_dma); 7320 hdac_dma_free(sc, &sc->corb_dma); 7321 for (i = 0; i < sc->num_chans; i++) { 7322 if (sc->chans[i].blkcnt > 0) 7323 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7324 } 7325 free(sc->chans, M_HDAC); 7326 if (sc->chan_dmat != NULL) { 7327 bus_dma_tag_destroy(sc->chan_dmat); 7328 sc->chan_dmat = NULL; 7329 } 7330 hdac_mem_free(sc); 7331 snd_mtxfree(sc->lock); 7332 } 7333 7334 /* This function surely going to make its way into upper level someday. */ 7335 static void 7336 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7337 { 7338 const char *res = NULL; 7339 int i = 0, j, k, len, inv; 7340 7341 if (on != NULL) 7342 *on = 0; 7343 if (off != NULL) 7344 *off = 0; 7345 if (sc == NULL) 7346 return; 7347 if (resource_string_value(device_get_name(sc->dev), 7348 device_get_unit(sc->dev), "config", &res) != 0) 7349 return; 7350 if (!(res != NULL && strlen(res) > 0)) 7351 return; 7352 HDA_BOOTVERBOSE( 7353 device_printf(sc->dev, "HDA Config:"); 7354 ); 7355 for (;;) { 7356 while (res[i] != '\0' && 7357 (res[i] == ',' || isspace(res[i]) != 0)) 7358 i++; 7359 if (res[i] == '\0') { 7360 HDA_BOOTVERBOSE( 7361 printf("\n"); 7362 ); 7363 return; 7364 } 7365 j = i; 7366 while (res[j] != '\0' && 7367 !(res[j] == ',' || isspace(res[j]) != 0)) 7368 j++; 7369 len = j - i; 7370 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7371 inv = 2; 7372 else 7373 inv = 0; 7374 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7375 if (strncmp(res + i + inv, 7376 hdac_quirks_tab[k].key, len - inv) != 0) 7377 continue; 7378 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7379 continue; 7380 HDA_BOOTVERBOSE( 7381 printf(" %s%s", (inv != 0) ? "no" : "", 7382 hdac_quirks_tab[k].key); 7383 ); 7384 if (inv == 0 && on != NULL) 7385 *on |= hdac_quirks_tab[k].value; 7386 else if (inv != 0 && off != NULL) 7387 *off |= hdac_quirks_tab[k].value; 7388 break; 7389 } 7390 i = j; 7391 } 7392 } 7393 7394 static int 7395 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7396 { 7397 struct hdac_softc *sc; 7398 device_t dev; 7399 uint32_t ctl; 7400 int err, val; 7401 7402 dev = oidp->oid_arg1; 7403 sc = device_get_softc(dev); 7404 if (sc == NULL) 7405 return (EINVAL); 7406 hdac_lock(sc); 7407 val = sc->polling; 7408 hdac_unlock(sc); 7409 err = sysctl_handle_int(oidp, &val, 0, req); 7410 7411 if (err != 0 || req->newptr == NULL) 7412 return (err); 7413 if (val < 0 || val > 1) 7414 return (EINVAL); 7415 7416 hdac_lock(sc); 7417 if (val != sc->polling) { 7418 if (val == 0) { 7419 callout_stop(&sc->poll_hda); 7420 callout_stop(&sc->poll_hdac); 7421 hdac_unlock(sc); 7422 callout_drain(&sc->poll_hda); 7423 callout_drain(&sc->poll_hdac); 7424 hdac_lock(sc); 7425 sc->polling = 0; 7426 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7427 ctl |= HDAC_INTCTL_GIE; 7428 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7429 } else { 7430 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7431 ctl &= ~HDAC_INTCTL_GIE; 7432 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7433 hdac_unlock(sc); 7434 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7435 hdac_lock(sc); 7436 sc->polling = 1; 7437 hdac_poll_reinit(sc); 7438 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7439 } 7440 } 7441 hdac_unlock(sc); 7442 7443 return (err); 7444 } 7445 7446 static int 7447 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7448 { 7449 struct hdac_softc *sc; 7450 device_t dev; 7451 int err, val; 7452 7453 dev = oidp->oid_arg1; 7454 sc = device_get_softc(dev); 7455 if (sc == NULL) 7456 return (EINVAL); 7457 hdac_lock(sc); 7458 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7459 hdac_unlock(sc); 7460 err = sysctl_handle_int(oidp, &val, 0, req); 7461 7462 if (err != 0 || req->newptr == NULL) 7463 return (err); 7464 7465 if (val < 1) 7466 val = 1; 7467 if (val > 5000) 7468 val = 5000; 7469 val = ((uint64_t)val * hz) / 1000; 7470 if (val < 1) 7471 val = 1; 7472 if (val > (hz * 5)) 7473 val = hz * 5; 7474 7475 hdac_lock(sc); 7476 sc->poll_ival = val; 7477 hdac_unlock(sc); 7478 7479 return (err); 7480 } 7481 7482 static int 7483 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7484 { 7485 struct hdac_softc *sc; 7486 struct hdac_codec *codec; 7487 struct hdac_devinfo *devinfo; 7488 struct hdac_widget *w; 7489 device_t dev; 7490 uint32_t res, pincap, delay; 7491 int codec_index, fg_index; 7492 int i, err, val; 7493 nid_t cad; 7494 7495 dev = oidp->oid_arg1; 7496 sc = device_get_softc(dev); 7497 if (sc == NULL) 7498 return (EINVAL); 7499 val = 0; 7500 err = sysctl_handle_int(oidp, &val, 0, req); 7501 if (err != 0 || req->newptr == NULL || val == 0) 7502 return (err); 7503 7504 /* XXX: Temporary. For debugging. */ 7505 if (val == 100) { 7506 hdac_suspend(dev); 7507 return (0); 7508 } else if (val == 101) { 7509 hdac_resume(dev); 7510 return (0); 7511 } 7512 7513 hdac_lock(sc); 7514 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7515 codec = sc->codecs[codec_index]; 7516 if (codec == NULL) 7517 continue; 7518 cad = codec->cad; 7519 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7520 devinfo = &codec->fgs[fg_index]; 7521 if (devinfo->node_type != 7522 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7523 continue; 7524 7525 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7526 codec_index, devinfo->nid); 7527 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7528 w = hdac_widget_get(devinfo, i); 7529 if (w == NULL || w->type != 7530 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7531 continue; 7532 hdac_dump_pin_config(w, w->wclass.pin.config); 7533 pincap = w->wclass.pin.cap; 7534 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7535 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7536 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7537 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7538 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7539 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7540 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7541 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7542 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7543 delay = 0; 7544 hdac_command(sc, 7545 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7546 do { 7547 res = hdac_command(sc, 7548 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7549 if (res != 0x7fffffff && res != 0xffffffff) 7550 break; 7551 DELAY(10); 7552 } while (++delay < 10000); 7553 } else { 7554 delay = 0; 7555 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7556 w->nid), cad); 7557 } 7558 printf(" Sense: 0x%08x", res); 7559 if (delay > 0) 7560 printf(" delay %dus", delay * 10); 7561 } 7562 printf("\n"); 7563 } 7564 device_printf(dev, 7565 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7566 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7567 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7568 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7569 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7570 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7571 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7572 device_printf(dev, " GPI:"); 7573 res = hdac_command(sc, 7574 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7575 printf(" data=0x%08x", res); 7576 res = hdac_command(sc, 7577 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7578 cad); 7579 printf(" wake=0x%08x", res); 7580 res = hdac_command(sc, 7581 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7582 cad); 7583 printf(" unsol=0x%08x", res); 7584 res = hdac_command(sc, 7585 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7586 printf(" sticky=0x%08x\n", res); 7587 } 7588 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7589 device_printf(dev, " GPO:"); 7590 res = hdac_command(sc, 7591 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7592 printf(" data=0x%08x\n", res); 7593 } 7594 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7595 device_printf(dev, "GPIO:"); 7596 res = hdac_command(sc, 7597 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7598 printf(" data=0x%08x", res); 7599 res = hdac_command(sc, 7600 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7601 printf(" enable=0x%08x", res); 7602 res = hdac_command(sc, 7603 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7604 printf(" direction=0x%08x\n", res); 7605 res = hdac_command(sc, 7606 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7607 device_printf(dev, " wake=0x%08x", res); 7608 res = hdac_command(sc, 7609 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7610 cad); 7611 printf(" unsol=0x%08x", res); 7612 res = hdac_command(sc, 7613 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7614 printf(" sticky=0x%08x\n", res); 7615 } 7616 } 7617 } 7618 hdac_unlock(sc); 7619 return (0); 7620 } 7621 7622 static void 7623 hdac_attach2(void *arg) 7624 { 7625 struct hdac_codec *codec; 7626 struct hdac_softc *sc; 7627 struct hdac_audio_ctl *ctl; 7628 uint32_t quirks_on, quirks_off; 7629 int codec_index, fg_index; 7630 int i, dmaalloc = 0; 7631 struct hdac_devinfo *devinfo; 7632 7633 sc = (struct hdac_softc *)arg; 7634 7635 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7636 7637 HDA_BOOTHVERBOSE( 7638 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7639 quirks_on, quirks_off); 7640 ); 7641 7642 hdac_lock(sc); 7643 7644 /* Remove ourselves from the config hooks */ 7645 if (sc->intrhook.ich_func != NULL) { 7646 config_intrhook_disestablish(&sc->intrhook); 7647 sc->intrhook.ich_func = NULL; 7648 } 7649 7650 /* Start the corb and rirb engines */ 7651 HDA_BOOTHVERBOSE( 7652 device_printf(sc->dev, "Starting CORB Engine...\n"); 7653 ); 7654 hdac_corb_start(sc); 7655 HDA_BOOTHVERBOSE( 7656 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7657 ); 7658 hdac_rirb_start(sc); 7659 7660 HDA_BOOTHVERBOSE( 7661 device_printf(sc->dev, 7662 "Enabling controller interrupt...\n"); 7663 ); 7664 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7665 HDAC_GCTL_UNSOL); 7666 if (sc->polling == 0) { 7667 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7668 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7669 } else { 7670 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7671 } 7672 DELAY(1000); 7673 7674 HDA_BOOTHVERBOSE( 7675 device_printf(sc->dev, 7676 "Scanning HDA codecs ...\n"); 7677 ); 7678 hdac_scan_codecs(sc); 7679 7680 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7681 codec = sc->codecs[codec_index]; 7682 if (codec == NULL) 7683 continue; 7684 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7685 devinfo = &codec->fgs[fg_index]; 7686 HDA_BOOTVERBOSE( 7687 device_printf(sc->dev, "\n"); 7688 device_printf(sc->dev, 7689 "Processing %s FG cad=%d nid=%d...\n", 7690 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7691 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7692 "unknown", 7693 devinfo->codec->cad, devinfo->nid); 7694 ); 7695 if (devinfo->node_type != 7696 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7697 HDA_BOOTHVERBOSE( 7698 device_printf(sc->dev, 7699 "Powering down...\n"); 7700 ); 7701 hdac_command(sc, 7702 HDA_CMD_SET_POWER_STATE(codec->cad, 7703 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7704 codec->cad); 7705 continue; 7706 } 7707 7708 HDA_BOOTHVERBOSE( 7709 device_printf(sc->dev, "Powering up...\n"); 7710 ); 7711 hdac_powerup(devinfo); 7712 HDA_BOOTHVERBOSE( 7713 device_printf(sc->dev, "Parsing audio FG...\n"); 7714 ); 7715 hdac_audio_parse(devinfo); 7716 HDA_BOOTHVERBOSE( 7717 device_printf(sc->dev, "Parsing Ctls...\n"); 7718 ); 7719 hdac_audio_ctl_parse(devinfo); 7720 HDA_BOOTHVERBOSE( 7721 device_printf(sc->dev, "Parsing vendor patch...\n"); 7722 ); 7723 hdac_vendor_patch_parse(devinfo); 7724 devinfo->function.audio.quirks |= quirks_on; 7725 devinfo->function.audio.quirks &= ~quirks_off; 7726 7727 HDA_BOOTHVERBOSE( 7728 device_printf(sc->dev, "Disabling nonaudio...\n"); 7729 ); 7730 hdac_audio_disable_nonaudio(devinfo); 7731 HDA_BOOTHVERBOSE( 7732 device_printf(sc->dev, "Disabling useless...\n"); 7733 ); 7734 hdac_audio_disable_useless(devinfo); 7735 HDA_BOOTVERBOSE( 7736 device_printf(sc->dev, "Patched pins configuration:\n"); 7737 hdac_dump_pin_configs(devinfo); 7738 ); 7739 HDA_BOOTHVERBOSE( 7740 device_printf(sc->dev, "Parsing pin associations...\n"); 7741 ); 7742 hdac_audio_as_parse(devinfo); 7743 HDA_BOOTHVERBOSE( 7744 device_printf(sc->dev, "Building AFG tree...\n"); 7745 ); 7746 hdac_audio_build_tree(devinfo); 7747 HDA_BOOTHVERBOSE( 7748 device_printf(sc->dev, "Disabling unassociated " 7749 "widgets...\n"); 7750 ); 7751 hdac_audio_disable_unas(devinfo); 7752 HDA_BOOTHVERBOSE( 7753 device_printf(sc->dev, "Disabling nonselected " 7754 "inputs...\n"); 7755 ); 7756 hdac_audio_disable_notselected(devinfo); 7757 HDA_BOOTHVERBOSE( 7758 device_printf(sc->dev, "Disabling useless...\n"); 7759 ); 7760 hdac_audio_disable_useless(devinfo); 7761 HDA_BOOTHVERBOSE( 7762 device_printf(sc->dev, "Disabling " 7763 "crossassociatement connections...\n"); 7764 ); 7765 hdac_audio_disable_crossas(devinfo); 7766 HDA_BOOTHVERBOSE( 7767 device_printf(sc->dev, "Disabling useless...\n"); 7768 ); 7769 hdac_audio_disable_useless(devinfo); 7770 HDA_BOOTHVERBOSE( 7771 device_printf(sc->dev, "Binding associations to channels...\n"); 7772 ); 7773 hdac_audio_bind_as(devinfo); 7774 HDA_BOOTHVERBOSE( 7775 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7776 ); 7777 hdac_audio_assign_names(devinfo); 7778 HDA_BOOTHVERBOSE( 7779 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7780 ); 7781 hdac_audio_assign_mixers(devinfo); 7782 HDA_BOOTHVERBOSE( 7783 device_printf(sc->dev, "Preparing pin controls...\n"); 7784 ); 7785 hdac_audio_prepare_pin_ctrl(devinfo); 7786 HDA_BOOTHVERBOSE( 7787 device_printf(sc->dev, "AFG commit...\n"); 7788 ); 7789 hdac_audio_commit(devinfo); 7790 HDA_BOOTHVERBOSE( 7791 device_printf(sc->dev, "HP switch init...\n"); 7792 ); 7793 hdac_hp_switch_init(devinfo); 7794 7795 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7796 dmaalloc == 0) { 7797 if (hdac_dma_alloc(sc, &sc->pos_dma, 7798 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7799 HDA_BOOTVERBOSE( 7800 device_printf(sc->dev, "Failed to " 7801 "allocate DMA pos buffer " 7802 "(non-fatal)\n"); 7803 ); 7804 } else 7805 dmaalloc = 1; 7806 } 7807 7808 HDA_BOOTHVERBOSE( 7809 device_printf(sc->dev, "Creating PCM devices...\n"); 7810 ); 7811 hdac_create_pcms(devinfo); 7812 7813 HDA_BOOTVERBOSE( 7814 if (devinfo->function.audio.quirks != 0) { 7815 device_printf(sc->dev, "FG config/quirks:"); 7816 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7817 if ((devinfo->function.audio.quirks & 7818 hdac_quirks_tab[i].value) == 7819 hdac_quirks_tab[i].value) 7820 printf(" %s", hdac_quirks_tab[i].key); 7821 } 7822 printf("\n"); 7823 } 7824 7825 device_printf(sc->dev, "\n"); 7826 device_printf(sc->dev, "+-------------------+\n"); 7827 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7828 device_printf(sc->dev, "+-------------------+\n"); 7829 hdac_dump_nodes(devinfo); 7830 ); 7831 7832 HDA_BOOTHVERBOSE( 7833 device_printf(sc->dev, "\n"); 7834 device_printf(sc->dev, "+------------------------+\n"); 7835 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7836 device_printf(sc->dev, "+------------------------+\n"); 7837 device_printf(sc->dev, "\n"); 7838 i = 0; 7839 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7840 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7841 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7842 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7843 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7844 ctl->index); 7845 if (ctl->childwidget != NULL) 7846 printf(" cnid %3d", ctl->childwidget->nid); 7847 else 7848 printf(" "); 7849 printf(" ossmask=0x%08x\n", 7850 ctl->ossmask); 7851 device_printf(sc->dev, 7852 " mute: %d step: %3d size: %3d off: %3d%s\n", 7853 ctl->mute, ctl->step, ctl->size, ctl->offset, 7854 (ctl->enable == 0) ? " [DISABLED]" : 7855 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7856 } 7857 ); 7858 } 7859 } 7860 hdac_unlock(sc); 7861 7862 HDA_BOOTVERBOSE( 7863 device_printf(sc->dev, "\n"); 7864 ); 7865 7866 bus_generic_attach(sc->dev); 7867 7868 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7869 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7870 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7871 sysctl_hdac_polling, "I", "Enable polling mode"); 7872 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7873 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7874 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7875 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7876 "Controller/Jack Sense polling interval (1-1000 ms)"); 7877 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7878 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7879 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7880 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7881 } 7882 7883 /**************************************************************************** 7884 * int hdac_suspend(device_t) 7885 * 7886 * Suspend and power down HDA bus and codecs. 7887 ****************************************************************************/ 7888 static int 7889 hdac_suspend(device_t dev) 7890 { 7891 struct hdac_softc *sc; 7892 struct hdac_codec *codec; 7893 struct hdac_devinfo *devinfo; 7894 int codec_index, fg_index, i; 7895 7896 HDA_BOOTHVERBOSE( 7897 device_printf(dev, "Suspend...\n"); 7898 ); 7899 7900 sc = device_get_softc(dev); 7901 hdac_lock(sc); 7902 7903 HDA_BOOTHVERBOSE( 7904 device_printf(dev, "Stop streams...\n"); 7905 ); 7906 for (i = 0; i < sc->num_chans; i++) { 7907 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7908 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7909 hdac_channel_stop(sc, &sc->chans[i]); 7910 } 7911 } 7912 7913 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7914 codec = sc->codecs[codec_index]; 7915 if (codec == NULL) 7916 continue; 7917 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7918 devinfo = &codec->fgs[fg_index]; 7919 HDA_BOOTHVERBOSE( 7920 device_printf(dev, 7921 "Power down FG" 7922 " cad=%d nid=%d to the D3 state...\n", 7923 codec->cad, devinfo->nid); 7924 ); 7925 hdac_command(sc, 7926 HDA_CMD_SET_POWER_STATE(codec->cad, 7927 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7928 codec->cad); 7929 } 7930 } 7931 7932 HDA_BOOTHVERBOSE( 7933 device_printf(dev, "Reset controller...\n"); 7934 ); 7935 callout_stop(&sc->poll_hda); 7936 callout_stop(&sc->poll_hdac); 7937 callout_stop(&sc->poll_jack); 7938 hdac_reset(sc, 0); 7939 hdac_unlock(sc); 7940 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7941 callout_drain(&sc->poll_hda); 7942 callout_drain(&sc->poll_hdac); 7943 callout_drain(&sc->poll_jack); 7944 7945 HDA_BOOTHVERBOSE( 7946 device_printf(dev, "Suspend done\n"); 7947 ); 7948 7949 return (0); 7950 } 7951 7952 /**************************************************************************** 7953 * int hdac_resume(device_t) 7954 * 7955 * Powerup and restore HDA bus and codecs state. 7956 ****************************************************************************/ 7957 static int 7958 hdac_resume(device_t dev) 7959 { 7960 struct hdac_softc *sc; 7961 struct hdac_codec *codec; 7962 struct hdac_devinfo *devinfo; 7963 int codec_index, fg_index, i; 7964 7965 HDA_BOOTHVERBOSE( 7966 device_printf(dev, "Resume...\n"); 7967 ); 7968 7969 sc = device_get_softc(dev); 7970 hdac_lock(sc); 7971 7972 /* Quiesce everything */ 7973 HDA_BOOTHVERBOSE( 7974 device_printf(dev, "Reset controller...\n"); 7975 ); 7976 hdac_reset(sc, 1); 7977 7978 /* Initialize the CORB and RIRB */ 7979 hdac_corb_init(sc); 7980 hdac_rirb_init(sc); 7981 7982 /* Start the corb and rirb engines */ 7983 HDA_BOOTHVERBOSE( 7984 device_printf(dev, "Starting CORB Engine...\n"); 7985 ); 7986 hdac_corb_start(sc); 7987 HDA_BOOTHVERBOSE( 7988 device_printf(dev, "Starting RIRB Engine...\n"); 7989 ); 7990 hdac_rirb_start(sc); 7991 7992 HDA_BOOTHVERBOSE( 7993 device_printf(dev, 7994 "Enabling controller interrupt...\n"); 7995 ); 7996 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7997 HDAC_GCTL_UNSOL); 7998 if (sc->polling == 0) { 7999 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 8000 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 8001 } else { 8002 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 8003 } 8004 DELAY(1000); 8005 8006 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 8007 codec = sc->codecs[codec_index]; 8008 if (codec == NULL) 8009 continue; 8010 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 8011 devinfo = &codec->fgs[fg_index]; 8012 if (devinfo->node_type != 8013 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 8014 HDA_BOOTHVERBOSE( 8015 device_printf(dev, 8016 "Power down unsupported non-audio FG" 8017 " cad=%d nid=%d to the D3 state...\n", 8018 codec->cad, devinfo->nid); 8019 ); 8020 hdac_command(sc, 8021 HDA_CMD_SET_POWER_STATE(codec->cad, 8022 devinfo->nid, HDA_CMD_POWER_STATE_D3), 8023 codec->cad); 8024 continue; 8025 } 8026 8027 HDA_BOOTHVERBOSE( 8028 device_printf(dev, 8029 "Power up audio FG cad=%d nid=%d...\n", 8030 devinfo->codec->cad, devinfo->nid); 8031 ); 8032 hdac_powerup(devinfo); 8033 HDA_BOOTHVERBOSE( 8034 device_printf(dev, "AFG commit...\n"); 8035 ); 8036 hdac_audio_commit(devinfo); 8037 HDA_BOOTHVERBOSE( 8038 device_printf(dev, "HP switch init...\n"); 8039 ); 8040 hdac_hp_switch_init(devinfo); 8041 8042 hdac_unlock(sc); 8043 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 8044 struct hdac_pcm_devinfo *pdevinfo = 8045 &devinfo->function.audio.devs[i]; 8046 HDA_BOOTHVERBOSE( 8047 device_printf(pdevinfo->dev, 8048 "OSS mixer reinitialization...\n"); 8049 ); 8050 if (mixer_reinit(pdevinfo->dev) == -1) 8051 device_printf(pdevinfo->dev, 8052 "unable to reinitialize the mixer\n"); 8053 } 8054 hdac_lock(sc); 8055 } 8056 } 8057 8058 HDA_BOOTHVERBOSE( 8059 device_printf(dev, "Start streams...\n"); 8060 ); 8061 for (i = 0; i < sc->num_chans; i++) { 8062 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 8063 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 8064 hdac_channel_start(sc, &sc->chans[i]); 8065 } 8066 } 8067 8068 hdac_unlock(sc); 8069 8070 HDA_BOOTHVERBOSE( 8071 device_printf(dev, "Resume done\n"); 8072 ); 8073 8074 return (0); 8075 } 8076 /**************************************************************************** 8077 * int hdac_detach(device_t) 8078 * 8079 * Detach and free up resources utilized by the hdac device. 8080 ****************************************************************************/ 8081 static int 8082 hdac_detach(device_t dev) 8083 { 8084 struct hdac_softc *sc; 8085 device_t *devlist; 8086 int i, devcount, error; 8087 8088 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 8089 return (error); 8090 for (i = 0; i < devcount; i++) { 8091 if ((error = device_delete_child(dev, devlist[i])) != 0) { 8092 free(devlist, M_TEMP); 8093 return (error); 8094 } 8095 } 8096 free(devlist, M_TEMP); 8097 8098 sc = device_get_softc(dev); 8099 hdac_release_resources(sc); 8100 8101 return (0); 8102 } 8103 8104 static int 8105 hdac_print_child(device_t dev, device_t child) 8106 { 8107 struct hdac_pcm_devinfo *pdevinfo = 8108 (struct hdac_pcm_devinfo *)device_get_ivars(child); 8109 int retval; 8110 8111 retval = bus_print_child_header(dev, child); 8112 retval += printf(" at cad %d nid %d", 8113 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 8114 retval += bus_print_child_footer(dev, child); 8115 8116 return (retval); 8117 } 8118 8119 static device_method_t hdac_methods[] = { 8120 /* device interface */ 8121 DEVMETHOD(device_probe, hdac_probe), 8122 DEVMETHOD(device_attach, hdac_attach), 8123 DEVMETHOD(device_detach, hdac_detach), 8124 DEVMETHOD(device_suspend, hdac_suspend), 8125 DEVMETHOD(device_resume, hdac_resume), 8126 /* Bus interface */ 8127 DEVMETHOD(bus_print_child, hdac_print_child), 8128 { 0, 0 } 8129 }; 8130 8131 static driver_t hdac_driver = { 8132 "hdac", 8133 hdac_methods, 8134 sizeof(struct hdac_softc), 8135 }; 8136 8137 static devclass_t hdac_devclass; 8138 8139 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 8140 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 8141 MODULE_VERSION(snd_hda, 1); 8142 8143 static int 8144 hdac_pcm_probe(device_t dev) 8145 { 8146 struct hdac_pcm_devinfo *pdevinfo = 8147 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8148 char buf[128]; 8149 8150 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 8151 hdac_codec_name(pdevinfo->devinfo->codec), 8152 pdevinfo->index, 8153 (pdevinfo->digital == 3)?"DisplayPort": 8154 ((pdevinfo->digital == 2)?"HDMI": 8155 ((pdevinfo->digital)?"Digital":"Analog"))); 8156 device_set_desc_copy(dev, buf); 8157 return (0); 8158 } 8159 8160 static int 8161 hdac_pcm_attach(device_t dev) 8162 { 8163 struct hdac_pcm_devinfo *pdevinfo = 8164 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8165 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 8166 char status[SND_STATUSLEN]; 8167 int i; 8168 8169 pdevinfo->chan_size = pcm_getbuffersize(dev, 8170 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8171 8172 HDA_BOOTVERBOSE( 8173 device_printf(dev, "+--------------------------------------+\n"); 8174 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8175 device_printf(dev, "+--------------------------------------+\n"); 8176 hdac_dump_pcmchannels(pdevinfo); 8177 device_printf(dev, "\n"); 8178 device_printf(dev, "+-------------------------------+\n"); 8179 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8180 device_printf(dev, "+-------------------------------+\n"); 8181 hdac_dump_dac(pdevinfo); 8182 hdac_dump_adc(pdevinfo); 8183 hdac_dump_mix(pdevinfo); 8184 device_printf(dev, "\n"); 8185 device_printf(dev, "+-------------------------+\n"); 8186 device_printf(dev, "| DUMPING Volume Controls |\n"); 8187 device_printf(dev, "+-------------------------+\n"); 8188 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8189 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8190 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8191 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8192 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8193 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8194 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8195 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8196 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8197 hdac_dump_ctls(pdevinfo, "Input Monitoring Level", SOUND_MASK_IGAIN); 8198 hdac_dump_ctls(pdevinfo, NULL, 0); 8199 device_printf(dev, "\n"); 8200 ); 8201 8202 if (resource_int_value(device_get_name(dev), 8203 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8204 i &= HDA_BLK_ALIGN; 8205 if (i < HDA_BLK_MIN) 8206 i = HDA_BLK_MIN; 8207 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8208 i = 0; 8209 while (pdevinfo->chan_blkcnt >> i) 8210 i++; 8211 pdevinfo->chan_blkcnt = 1 << (i - 1); 8212 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8213 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8214 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8215 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8216 } else 8217 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8218 8219 /* 8220 * We don't register interrupt handler with snd_setup_intr 8221 * in pcm device. Mark pcm device as MPSAFE manually. 8222 */ 8223 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8224 8225 HDA_BOOTHVERBOSE( 8226 device_printf(dev, "OSS mixer initialization...\n"); 8227 ); 8228 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8229 device_printf(dev, "Can't register mixer\n"); 8230 8231 HDA_BOOTHVERBOSE( 8232 device_printf(dev, "Registering PCM channels...\n"); 8233 ); 8234 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8235 (pdevinfo->rec >= 0)?1:0) != 0) 8236 device_printf(dev, "Can't register PCM\n"); 8237 8238 pdevinfo->registered++; 8239 8240 if (pdevinfo->play >= 0) 8241 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8242 if (pdevinfo->rec >= 0) 8243 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8244 8245 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8246 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8247 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8248 pcm_setstatus(dev, status); 8249 8250 return (0); 8251 } 8252 8253 static int 8254 hdac_pcm_detach(device_t dev) 8255 { 8256 struct hdac_pcm_devinfo *pdevinfo = 8257 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8258 int err; 8259 8260 if (pdevinfo->registered > 0) { 8261 err = pcm_unregister(dev); 8262 if (err != 0) 8263 return (err); 8264 } 8265 8266 return (0); 8267 } 8268 8269 static device_method_t hdac_pcm_methods[] = { 8270 /* device interface */ 8271 DEVMETHOD(device_probe, hdac_pcm_probe), 8272 DEVMETHOD(device_attach, hdac_pcm_attach), 8273 DEVMETHOD(device_detach, hdac_pcm_detach), 8274 { 0, 0 } 8275 }; 8276 8277 static driver_t hdac_pcm_driver = { 8278 "pcm", 8279 hdac_pcm_methods, 8280 PCM_SOFTC_SIZE, 8281 }; 8282 8283 DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8284 8285