1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70 #include <sys/ctype.h> 71 72 #include <dev/sound/pcm/sound.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 76 #include <dev/sound/pci/hda/hdac_private.h> 77 #include <dev/sound/pci/hda/hdac_reg.h> 78 #include <dev/sound/pci/hda/hda_reg.h> 79 #include <dev/sound/pci/hda/hdac.h> 80 81 #include "mixer_if.h" 82 83 #define HDA_DRV_TEST_REV "20070505_0044" 84 #define HDA_WIDGET_PARSER_REV 1 85 86 SND_DECLARE_FILE("$FreeBSD$"); 87 88 #define HDA_BOOTVERBOSE(stmt) do { \ 89 if (bootverbose != 0 || snd_verbose > 3) { \ 90 stmt \ 91 } \ 92 } while(0) 93 94 #if 1 95 #undef HDAC_INTR_EXTRA 96 #define HDAC_INTR_EXTRA 1 97 #endif 98 99 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 100 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 101 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 102 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 103 104 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 105 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 106 (fl) == 0xffffffff || \ 107 (((fl) & 0xffff0000) == 0xffff0000 && \ 108 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 109 (((fl) & 0x0000ffff) == 0x0000ffff && \ 110 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 111 #define HDA_MATCH_ALL 0xffffffff 112 #define HDAC_INVALID 0xffffffff 113 114 /* Default controller / jack sense poll: 250ms */ 115 #define HDAC_POLL_INTERVAL max(hz >> 2, 1) 116 117 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 118 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 119 120 /* Controller models */ 121 122 /* Intel */ 123 #define INTEL_VENDORID 0x8086 124 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 125 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 126 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 127 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 128 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 129 130 /* Nvidia */ 131 #define NVIDIA_VENDORID 0x10de 132 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 133 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 134 #define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 135 #define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 136 #define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 137 #define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 138 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 139 140 /* ATI */ 141 #define ATI_VENDORID 0x1002 142 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 143 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 144 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 145 146 /* VIA */ 147 #define VIA_VENDORID 0x1106 148 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 149 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 150 151 /* SiS */ 152 #define SIS_VENDORID 0x1039 153 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 154 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 155 156 /* OEM/subvendors */ 157 158 /* Intel */ 159 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 160 161 /* HP/Compaq */ 162 #define HP_VENDORID 0x103c 163 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 164 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 165 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 166 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 167 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 168 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 169 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 170 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 171 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 172 #define HP_NX6325_SUBVENDORX 0x103c30b0 173 174 /* Dell */ 175 #define DELL_VENDORID 0x1028 176 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 177 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 178 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 179 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 180 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 181 182 /* Clevo */ 183 #define CLEVO_VENDORID 0x1558 184 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 185 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 186 187 /* Acer */ 188 #define ACER_VENDORID 0x1025 189 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 190 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 191 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 192 193 /* Asus */ 194 #define ASUS_VENDORID 0x1043 195 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 196 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 197 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 198 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 199 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 200 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 201 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 202 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 203 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 204 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 205 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 206 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 207 208 /* IBM / Lenovo */ 209 #define IBM_VENDORID 0x1014 210 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 211 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 212 213 /* Lenovo */ 214 #define LENOVO_VENDORID 0x17aa 215 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 216 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 217 218 /* Samsung */ 219 #define SAMSUNG_VENDORID 0x144d 220 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 221 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 222 223 /* Medion ? */ 224 #define MEDION_VENDORID 0x161f 225 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 226 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 227 228 /* 229 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 230 * instead of their own, which is beyond my comprehension 231 * (see HDA_CODEC_STAC9221 below). 232 */ 233 #define APPLE_INTEL_MAC 0x76808384 234 235 /* LG Electronics */ 236 #define LG_VENDORID 0x1854 237 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 238 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 239 240 /* Fujitsu Siemens */ 241 #define FS_VENDORID 0x1734 242 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 243 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 244 245 /* Toshiba */ 246 #define TOSHIBA_VENDORID 0x1179 247 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 248 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 249 250 /* Micro-Star International (MSI) */ 251 #define MSI_VENDORID 0x1462 252 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 253 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 254 255 /* Uniwill ? */ 256 #define UNIWILL_VENDORID 0x1584 257 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 258 259 260 /* Misc constants.. */ 261 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 262 #define HDA_AMP_MUTE_NONE (0) 263 #define HDA_AMP_MUTE_LEFT (1 << 0) 264 #define HDA_AMP_MUTE_RIGHT (1 << 1) 265 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 266 267 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 268 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 269 270 #define HDA_DAC_PATH (1 << 0) 271 #define HDA_ADC_PATH (1 << 1) 272 #define HDA_ADC_RECSEL (1 << 2) 273 274 #define HDA_DAC_LOCKED (1 << 3) 275 #define HDA_ADC_LOCKED (1 << 4) 276 277 #define HDA_CTL_OUT (1 << 0) 278 #define HDA_CTL_IN (1 << 1) 279 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 280 281 #define HDA_GPIO_MAX 8 282 /* 0 - 7 = GPIO , 8 = Flush */ 283 #define HDA_QUIRK_GPIO0 (1 << 0) 284 #define HDA_QUIRK_GPIO1 (1 << 1) 285 #define HDA_QUIRK_GPIO2 (1 << 2) 286 #define HDA_QUIRK_GPIO3 (1 << 3) 287 #define HDA_QUIRK_GPIO4 (1 << 4) 288 #define HDA_QUIRK_GPIO5 (1 << 5) 289 #define HDA_QUIRK_GPIO6 (1 << 6) 290 #define HDA_QUIRK_GPIO7 (1 << 7) 291 #define HDA_QUIRK_GPIOFLUSH (1 << 8) 292 293 /* 9 - 25 = anything else */ 294 #define HDA_QUIRK_SOFTPCMVOL (1 << 9) 295 #define HDA_QUIRK_FIXEDRATE (1 << 10) 296 #define HDA_QUIRK_FORCESTEREO (1 << 11) 297 #define HDA_QUIRK_EAPDINV (1 << 12) 298 #define HDA_QUIRK_DMAPOS (1 << 13) 299 300 /* 26 - 31 = vrefs */ 301 #define HDA_QUIRK_IVREF50 (1 << 26) 302 #define HDA_QUIRK_IVREF80 (1 << 27) 303 #define HDA_QUIRK_IVREF100 (1 << 28) 304 #define HDA_QUIRK_OVREF50 (1 << 29) 305 #define HDA_QUIRK_OVREF80 (1 << 30) 306 #define HDA_QUIRK_OVREF100 (1 << 31) 307 308 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 309 HDA_QUIRK_IVREF100) 310 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 311 HDA_QUIRK_OVREF100) 312 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 313 314 #define SOUND_MASK_SKIP (1 << 30) 315 #define SOUND_MASK_DISABLE (1 << 31) 316 317 static const struct { 318 char *key; 319 uint32_t value; 320 } hdac_quirks_tab[] = { 321 { "gpio0", HDA_QUIRK_GPIO0 }, 322 { "gpio1", HDA_QUIRK_GPIO1 }, 323 { "gpio2", HDA_QUIRK_GPIO2 }, 324 { "gpio3", HDA_QUIRK_GPIO3 }, 325 { "gpio4", HDA_QUIRK_GPIO4 }, 326 { "gpio5", HDA_QUIRK_GPIO5 }, 327 { "gpio6", HDA_QUIRK_GPIO6 }, 328 { "gpio7", HDA_QUIRK_GPIO7 }, 329 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 330 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 331 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 332 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 333 { "eapdinv", HDA_QUIRK_EAPDINV }, 334 { "dmapos", HDA_QUIRK_DMAPOS }, 335 { "ivref50", HDA_QUIRK_IVREF50 }, 336 { "ivref80", HDA_QUIRK_IVREF80 }, 337 { "ivref100", HDA_QUIRK_IVREF100 }, 338 { "ovref50", HDA_QUIRK_OVREF50 }, 339 { "ovref80", HDA_QUIRK_OVREF80 }, 340 { "ovref100", HDA_QUIRK_OVREF100 }, 341 { "ivref", HDA_QUIRK_IVREF }, 342 { "ovref", HDA_QUIRK_OVREF }, 343 { "vref", HDA_QUIRK_VREF }, 344 }; 345 #define HDAC_QUIRKS_TAB_LEN \ 346 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 347 348 #define HDA_BDL_MIN 2 349 #define HDA_BDL_MAX 256 350 #define HDA_BDL_DEFAULT HDA_BDL_MIN 351 352 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 353 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 354 355 #define HDA_BUFSZ_MIN 4096 356 #define HDA_BUFSZ_MAX 65536 357 #define HDA_BUFSZ_DEFAULT 16384 358 359 #define HDA_PARSE_MAXDEPTH 10 360 361 #define HDAC_UNSOLTAG_EVENT_HP 0x00 362 #define HDAC_UNSOLTAG_EVENT_TEST 0x01 363 364 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 365 366 enum { 367 HDA_PARSE_MIXER, 368 HDA_PARSE_DIRECT 369 }; 370 371 /* Default */ 372 static uint32_t hdac_fmt[] = { 373 AFMT_STEREO | AFMT_S16_LE, 374 0 375 }; 376 377 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 378 379 static const struct { 380 uint32_t model; 381 char *desc; 382 } hdac_devices[] = { 383 { HDA_INTEL_82801F, "Intel 82801F" }, 384 { HDA_INTEL_82801G, "Intel 82801G" }, 385 { HDA_INTEL_82801H, "Intel 82801H" }, 386 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 387 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 388 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 389 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 390 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 391 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 392 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 393 { HDA_ATI_SB450, "ATI SB450" }, 394 { HDA_ATI_SB600, "ATI SB600" }, 395 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 396 { HDA_SIS_966, "SiS 966" }, 397 /* Unknown */ 398 { HDA_INTEL_ALL, "Intel (Unknown)" }, 399 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 400 { HDA_ATI_ALL, "ATI (Unknown)" }, 401 { HDA_VIA_ALL, "VIA (Unknown)" }, 402 { HDA_SIS_ALL, "SiS (Unknown)" }, 403 }; 404 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 405 406 static const struct { 407 uint16_t vendor; 408 uint8_t reg; 409 uint8_t mask; 410 uint8_t enable; 411 } hdac_pcie_snoop[] = { 412 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 413 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 414 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 415 }; 416 #define HDAC_PCIESNOOP_LEN \ 417 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 418 419 static const struct { 420 uint32_t rate; 421 int valid; 422 uint16_t base; 423 uint16_t mul; 424 uint16_t div; 425 } hda_rate_tab[] = { 426 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 427 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 428 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 429 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 430 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 431 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 432 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 433 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 434 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 435 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 436 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 437 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 438 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 439 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 440 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 441 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 442 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 443 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 444 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 445 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 446 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 447 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 448 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 449 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 450 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 451 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 452 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 453 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 454 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 455 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 456 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 457 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 458 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 459 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 460 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 461 }; 462 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 463 464 /* All codecs you can eat... */ 465 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 466 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 467 468 /* Realtek */ 469 #define REALTEK_VENDORID 0x10ec 470 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 471 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 472 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 473 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 474 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 475 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 476 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 477 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 478 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 479 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 480 481 /* Analog Devices */ 482 #define ANALOGDEVICES_VENDORID 0x11d4 483 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 484 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 485 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 486 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 487 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 488 489 /* CMedia */ 490 #define CMEDIA_VENDORID 0x434d 491 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 492 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 493 494 /* Sigmatel */ 495 #define SIGMATEL_VENDORID 0x8384 496 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 497 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 498 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 499 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 500 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 501 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 502 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 503 504 /* 505 * Conexant 506 * 507 * Ok, the truth is, I don't have any idea at all whether 508 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 509 * place that tell me it is "Venice" is from its Windows driver INF. 510 * 511 * Venice - CX????? 512 * Waikiki - CX20551-22 513 */ 514 #define CONEXANT_VENDORID 0x14f1 515 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 516 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 517 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 518 519 /* VIA */ 520 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 521 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 522 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 523 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 524 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 525 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 526 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 527 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 528 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 529 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 530 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 531 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 532 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 533 534 535 /* Codecs */ 536 static const struct { 537 uint32_t id; 538 char *name; 539 } hdac_codecs[] = { 540 { HDA_CODEC_ALC260, "Realtek ALC260" }, 541 { HDA_CODEC_ALC262, "Realtek ALC262" }, 542 { HDA_CODEC_ALC861, "Realtek ALC861" }, 543 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 544 { HDA_CODEC_ALC880, "Realtek ALC880" }, 545 { HDA_CODEC_ALC882, "Realtek ALC882" }, 546 { HDA_CODEC_ALC883, "Realtek ALC883" }, 547 { HDA_CODEC_ALC885, "Realtek ALC885" }, 548 { HDA_CODEC_ALC888, "Realtek ALC888" }, 549 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 550 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 551 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 552 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 553 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 554 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 555 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 556 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 557 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 558 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 559 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 560 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 561 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 562 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 563 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 564 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 565 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 566 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 567 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 568 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 569 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 570 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 571 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 572 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 573 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 574 /* Unknown codec */ 575 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 576 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 577 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 578 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 579 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 580 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 581 }; 582 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 583 584 enum { 585 HDAC_HP_SWITCH_CTL, 586 HDAC_HP_SWITCH_CTRL, 587 HDAC_HP_SWITCH_DEBUG 588 }; 589 590 static const struct { 591 uint32_t model; 592 uint32_t id; 593 int type; 594 int inverted; 595 int polling; 596 int execsense; 597 nid_t hpnid; 598 nid_t spkrnid[8]; 599 nid_t eapdnid; 600 } hdac_hp_switch[] = { 601 /* Specific OEM models */ 602 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 603 0, 0, -1, 17, { 16, -1 }, 16 }, 604 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 605 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 606 /*{ HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 607 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 },*/ 608 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 609 0, 0, -1, 6, { 5, -1 }, 5 }, 610 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 611 0, 0, -1, 6, { 5, -1 }, 5 }, 612 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 613 0, 0, -1, 6, { 5, -1 }, 5 }, 614 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 615 0, 0, -1, 6, { 5, -1 }, -1 }, 616 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 617 0, 0, -1, 13, { 14, -1 }, -1 }, 618 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 619 0, 0, -1, 13, { 14, -1 }, -1 }, 620 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 621 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 622 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 623 0, 0, -1, 10, { 13, -1 }, -1 }, 624 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 625 1, 0, -1, 26, { 27, -1 }, -1 }, 626 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 627 0, 0, -1, 27, { 20, -1 }, -1 }, 628 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 629 0, 0, -1, 20, { 21, -1 }, -1 }, 630 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 631 0, 0, -1, 20, { 21, -1 }, -1 }, 632 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 633 0, 0, -1, 20, { 27, -1 }, -1 }, 634 /* 635 * All models that at least come from the same vendor with 636 * simmilar codec. 637 */ 638 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 639 0, 0, -1, 17, { 16, -1 }, 16 }, 640 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 641 0, 0, -1, 6, { 5, -1 }, 5 }, 642 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 643 0, 0, -1, 6, { 5, -1 }, -1 }, 644 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 645 0, 0, -1, 13, { 14, -1 }, -1 }, 646 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 647 1, 0, -1, 26, { 27, -1 }, -1 }, 648 #if 0 649 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 650 0, 0, -1, 20, { 21, -1 }, -1 }, 651 #endif 652 }; 653 #define HDAC_HP_SWITCH_LEN \ 654 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 655 656 static const struct { 657 uint32_t model; 658 uint32_t id; 659 nid_t eapdnid; 660 int hp_switch; 661 } hdac_eapd_switch[] = { 662 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 663 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 664 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 665 }; 666 #define HDAC_EAPD_SWITCH_LEN \ 667 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 668 669 /**************************************************************************** 670 * Function prototypes 671 ****************************************************************************/ 672 static void hdac_intr_handler(void *); 673 static int hdac_reset(struct hdac_softc *); 674 static int hdac_get_capabilities(struct hdac_softc *); 675 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 676 static int hdac_dma_alloc(struct hdac_softc *, 677 struct hdac_dma *, bus_size_t); 678 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 679 static int hdac_mem_alloc(struct hdac_softc *); 680 static void hdac_mem_free(struct hdac_softc *); 681 static int hdac_irq_alloc(struct hdac_softc *); 682 static void hdac_irq_free(struct hdac_softc *); 683 static void hdac_corb_init(struct hdac_softc *); 684 static void hdac_rirb_init(struct hdac_softc *); 685 static void hdac_corb_start(struct hdac_softc *); 686 static void hdac_rirb_start(struct hdac_softc *); 687 static void hdac_scan_codecs(struct hdac_softc *); 688 static int hdac_probe_codec(struct hdac_codec *); 689 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 690 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 691 692 static void hdac_attach2(void *); 693 694 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 695 uint32_t, int); 696 static void hdac_command_send_internal(struct hdac_softc *, 697 struct hdac_command_list *, int); 698 699 static int hdac_probe(device_t); 700 static int hdac_attach(device_t); 701 static int hdac_detach(device_t); 702 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 703 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 704 uint32_t, int, int); 705 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 706 nid_t, int, int); 707 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 708 nid_t, nid_t, int, int, int, int, int, int); 709 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 710 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 711 712 static int hdac_rirb_flush(struct hdac_softc *sc); 713 static int hdac_unsolq_flush(struct hdac_softc *sc); 714 715 #define hdac_command(a1, a2, a3) \ 716 hdac_command_sendone_internal(a1, a2, a3) 717 718 #define hdac_codec_id(d) \ 719 ((uint32_t)((d == NULL) ? 0x00000000 : \ 720 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 721 ((uint32_t)(d)->device_id & 0x0000ffff)))) 722 723 static char * 724 hdac_codec_name(struct hdac_devinfo *devinfo) 725 { 726 uint32_t id; 727 int i; 728 729 id = hdac_codec_id(devinfo); 730 731 for (i = 0; i < HDAC_CODECS_LEN; i++) { 732 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 733 return (hdac_codecs[i].name); 734 } 735 736 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 737 } 738 739 static char * 740 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 741 { 742 static char *ossname[] = SOUND_DEVICE_NAMES; 743 static char *unknown = "???"; 744 int i; 745 746 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 747 if (devmask & (1 << i)) 748 return (ossname[i]); 749 } 750 return (unknown); 751 } 752 753 static void 754 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 755 { 756 static char *ossname[] = SOUND_DEVICE_NAMES; 757 int i, first = 1; 758 759 bzero(buf, len); 760 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 761 if (mask & (1 << i)) { 762 if (first == 0) 763 strlcat(buf, ", ", len); 764 strlcat(buf, ossname[i], len); 765 first = 0; 766 } 767 } 768 } 769 770 static struct hdac_audio_ctl * 771 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 772 { 773 if (devinfo == NULL || 774 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 775 index == NULL || devinfo->function.audio.ctl == NULL || 776 devinfo->function.audio.ctlcnt < 1 || 777 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 778 return (NULL); 779 return (&devinfo->function.audio.ctl[(*index)++]); 780 } 781 782 static struct hdac_audio_ctl * 783 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 784 int index, int cnt) 785 { 786 struct hdac_audio_ctl *ctl, *retctl = NULL; 787 int i, at, atindex, found = 0; 788 789 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 790 return (NULL); 791 792 at = cnt; 793 if (at == 0) 794 at = 1; 795 else if (at < 0) 796 at = -1; 797 atindex = index; 798 if (atindex < 0) 799 atindex = -1; 800 801 i = 0; 802 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 803 if (ctl->enable == 0 || ctl->widget == NULL) 804 continue; 805 if (!(ctl->widget->nid == nid && (atindex == -1 || 806 ctl->index == atindex))) 807 continue; 808 found++; 809 if (found == cnt) 810 return (ctl); 811 retctl = ctl; 812 } 813 814 return ((at == -1) ? retctl : NULL); 815 } 816 817 static void 818 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 819 { 820 struct hdac_softc *sc; 821 struct hdac_widget *w; 822 struct hdac_audio_ctl *ctl; 823 uint32_t val, id, res; 824 int i = 0, j, forcemute; 825 nid_t cad; 826 827 if (devinfo == NULL || devinfo->codec == NULL || 828 devinfo->codec->sc == NULL) 829 return; 830 831 sc = devinfo->codec->sc; 832 cad = devinfo->codec->cad; 833 id = hdac_codec_id(devinfo); 834 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 835 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 836 sc->pci_subvendor) && 837 hdac_hp_switch[i].id == id) 838 break; 839 } 840 841 if (i >= HDAC_HP_SWITCH_LEN) 842 return; 843 844 forcemute = 0; 845 if (hdac_hp_switch[i].eapdnid != -1) { 846 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 847 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 848 forcemute = (w->param.eapdbtl & 849 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 850 } 851 852 if (hdac_hp_switch[i].execsense != -1) 853 hdac_command(sc, 854 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 855 hdac_hp_switch[i].execsense), cad); 856 res = hdac_command(sc, 857 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 858 HDA_BOOTVERBOSE( 859 device_printf(sc->dev, 860 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 861 hdac_hp_switch[i].hpnid, res); 862 ); 863 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 864 res ^= hdac_hp_switch[i].inverted; 865 866 switch (hdac_hp_switch[i].type) { 867 case HDAC_HP_SWITCH_CTL: 868 ctl = hdac_audio_ctl_amp_get(devinfo, 869 hdac_hp_switch[i].hpnid, 0, 1); 870 if (ctl != NULL) { 871 val = (res != 0 && forcemute == 0) ? 872 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 873 if (val != ctl->muted) { 874 ctl->muted = val; 875 hdac_audio_ctl_amp_set(ctl, 876 HDA_AMP_MUTE_DEFAULT, ctl->left, 877 ctl->right); 878 } 879 } 880 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 881 ctl = hdac_audio_ctl_amp_get(devinfo, 882 hdac_hp_switch[i].spkrnid[j], 0, 1); 883 if (ctl == NULL) 884 continue; 885 val = (res != 0 || forcemute == 1) ? 886 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 887 if (val == ctl->muted) 888 continue; 889 ctl->muted = val; 890 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 891 ctl->left, ctl->right); 892 } 893 break; 894 case HDAC_HP_SWITCH_CTRL: 895 if (res != 0) { 896 /* HP in */ 897 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 898 if (w != NULL && w->type == 899 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 900 if (forcemute == 0) 901 val = w->wclass.pin.ctrl | 902 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 903 else 904 val = w->wclass.pin.ctrl & 905 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 906 if (val != w->wclass.pin.ctrl) { 907 w->wclass.pin.ctrl = val; 908 hdac_command(sc, 909 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 910 w->nid, w->wclass.pin.ctrl), cad); 911 } 912 } 913 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 914 w = hdac_widget_get(devinfo, 915 hdac_hp_switch[i].spkrnid[j]); 916 if (w == NULL || w->type != 917 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 918 continue; 919 val = w->wclass.pin.ctrl & 920 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 921 if (val == w->wclass.pin.ctrl) 922 continue; 923 w->wclass.pin.ctrl = val; 924 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 925 cad, w->nid, w->wclass.pin.ctrl), cad); 926 } 927 } else { 928 /* HP out */ 929 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 930 if (w != NULL && w->type == 931 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 932 val = w->wclass.pin.ctrl & 933 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 934 if (val != w->wclass.pin.ctrl) { 935 w->wclass.pin.ctrl = val; 936 hdac_command(sc, 937 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 938 w->nid, w->wclass.pin.ctrl), cad); 939 } 940 } 941 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 942 w = hdac_widget_get(devinfo, 943 hdac_hp_switch[i].spkrnid[j]); 944 if (w == NULL || w->type != 945 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 946 continue; 947 if (forcemute == 0) 948 val = w->wclass.pin.ctrl | 949 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 950 else 951 val = w->wclass.pin.ctrl & 952 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 953 if (val == w->wclass.pin.ctrl) 954 continue; 955 w->wclass.pin.ctrl = val; 956 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 957 cad, w->nid, w->wclass.pin.ctrl), cad); 958 } 959 } 960 break; 961 case HDAC_HP_SWITCH_DEBUG: 962 if (hdac_hp_switch[i].execsense != -1) 963 hdac_command(sc, 964 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 965 hdac_hp_switch[i].execsense), cad); 966 res = hdac_command(sc, 967 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 968 device_printf(sc->dev, 969 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 970 hdac_hp_switch[i].hpnid, res); 971 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 972 w = hdac_widget_get(devinfo, 973 hdac_hp_switch[i].spkrnid[j]); 974 if (w == NULL || w->type != 975 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 976 continue; 977 if (hdac_hp_switch[i].execsense != -1) 978 hdac_command(sc, 979 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 980 hdac_hp_switch[i].execsense), cad); 981 res = hdac_command(sc, 982 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 983 device_printf(sc->dev, 984 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 985 j + 1, w->nid, res); 986 } 987 break; 988 default: 989 break; 990 } 991 } 992 993 static void 994 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 995 { 996 struct hdac_softc *sc; 997 struct hdac_devinfo *devinfo = NULL; 998 device_t *devlist = NULL; 999 int devcount, i; 1000 1001 if (codec == NULL || codec->sc == NULL) 1002 return; 1003 1004 sc = codec->sc; 1005 1006 HDA_BOOTVERBOSE( 1007 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1008 ); 1009 1010 device_get_children(sc->dev, &devlist, &devcount); 1011 for (i = 0; devlist != NULL && i < devcount; i++) { 1012 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1013 if (devinfo != NULL && devinfo->node_type == 1014 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1015 devinfo->codec != NULL && 1016 devinfo->codec->cad == codec->cad) { 1017 break; 1018 } else 1019 devinfo = NULL; 1020 } 1021 if (devlist != NULL) 1022 free(devlist, M_TEMP); 1023 1024 if (devinfo == NULL) 1025 return; 1026 1027 switch (tag) { 1028 case HDAC_UNSOLTAG_EVENT_HP: 1029 hdac_hp_switch_handler(devinfo); 1030 break; 1031 case HDAC_UNSOLTAG_EVENT_TEST: 1032 device_printf(sc->dev, "Unsol Test!\n"); 1033 break; 1034 default: 1035 break; 1036 } 1037 } 1038 1039 static int 1040 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1041 { 1042 /* XXX to be removed */ 1043 #ifdef HDAC_INTR_EXTRA 1044 uint32_t res; 1045 #endif 1046 1047 if (ch->blkcnt == 0) 1048 return (0); 1049 1050 /* XXX to be removed */ 1051 #ifdef HDAC_INTR_EXTRA 1052 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1053 #endif 1054 1055 /* XXX to be removed */ 1056 #ifdef HDAC_INTR_EXTRA 1057 HDA_BOOTVERBOSE( 1058 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1059 device_printf(sc->dev, 1060 "PCMDIR_%s intr triggered beyond stream boundary:" 1061 "%08x\n", 1062 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1063 ); 1064 #endif 1065 1066 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1067 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1068 1069 /* XXX to be removed */ 1070 #ifdef HDAC_INTR_EXTRA 1071 if (res & HDAC_SDSTS_BCIS) { 1072 #endif 1073 return (1); 1074 /* XXX to be removed */ 1075 #ifdef HDAC_INTR_EXTRA 1076 } 1077 #endif 1078 1079 return (0); 1080 } 1081 1082 /**************************************************************************** 1083 * void hdac_intr_handler(void *) 1084 * 1085 * Interrupt handler. Processes interrupts received from the hdac. 1086 ****************************************************************************/ 1087 static void 1088 hdac_intr_handler(void *context) 1089 { 1090 struct hdac_softc *sc; 1091 uint32_t intsts; 1092 uint8_t rirbsts; 1093 struct hdac_rirb *rirb_base; 1094 uint32_t trigger = 0; 1095 1096 sc = (struct hdac_softc *)context; 1097 1098 hdac_lock(sc); 1099 if (sc->polling != 0) { 1100 hdac_unlock(sc); 1101 return; 1102 } 1103 /* Do we have anything to do? */ 1104 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1105 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1106 hdac_unlock(sc); 1107 return; 1108 } 1109 1110 /* Was this a controller interrupt? */ 1111 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1112 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1113 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1114 /* Get as many responses that we can */ 1115 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1116 HDAC_WRITE_1(&sc->mem, 1117 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1118 hdac_rirb_flush(sc); 1119 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1120 } 1121 /* XXX to be removed */ 1122 /* Clear interrupt and exit */ 1123 #ifdef HDAC_INTR_EXTRA 1124 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1125 #endif 1126 } 1127 1128 hdac_unsolq_flush(sc); 1129 1130 if (intsts & HDAC_INTSTS_SIS_MASK) { 1131 if ((intsts & (1 << sc->num_iss)) && 1132 hdac_stream_intr(sc, &sc->play) != 0) 1133 trigger |= 1; 1134 if ((intsts & (1 << 0)) && 1135 hdac_stream_intr(sc, &sc->rec) != 0) 1136 trigger |= 2; 1137 /* XXX to be removed */ 1138 #ifdef HDAC_INTR_EXTRA 1139 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1140 HDAC_INTSTS_SIS_MASK); 1141 #endif 1142 } 1143 1144 hdac_unlock(sc); 1145 1146 if (trigger & 1) 1147 chn_intr(sc->play.c); 1148 if (trigger & 2) 1149 chn_intr(sc->rec.c); 1150 } 1151 1152 /**************************************************************************** 1153 * int hdac_reset(hdac_softc *) 1154 * 1155 * Reset the hdac to a quiescent and known state. 1156 ****************************************************************************/ 1157 static int 1158 hdac_reset(struct hdac_softc *sc) 1159 { 1160 uint32_t gctl; 1161 int count, i; 1162 1163 /* 1164 * Stop all Streams DMA engine 1165 */ 1166 for (i = 0; i < sc->num_iss; i++) 1167 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1168 for (i = 0; i < sc->num_oss; i++) 1169 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1170 for (i = 0; i < sc->num_bss; i++) 1171 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1172 1173 /* 1174 * Stop Control DMA engines. 1175 */ 1176 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1177 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1178 1179 /* 1180 * Reset DMA position buffer. 1181 */ 1182 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1183 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1184 1185 /* 1186 * Reset the controller. The reset must remain asserted for 1187 * a minimum of 100us. 1188 */ 1189 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1190 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1191 count = 10000; 1192 do { 1193 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1194 if (!(gctl & HDAC_GCTL_CRST)) 1195 break; 1196 DELAY(10); 1197 } while (--count); 1198 if (gctl & HDAC_GCTL_CRST) { 1199 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1200 return (ENXIO); 1201 } 1202 DELAY(100); 1203 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1204 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1205 count = 10000; 1206 do { 1207 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1208 if (gctl & HDAC_GCTL_CRST) 1209 break; 1210 DELAY(10); 1211 } while (--count); 1212 if (!(gctl & HDAC_GCTL_CRST)) { 1213 device_printf(sc->dev, "Device stuck in reset\n"); 1214 return (ENXIO); 1215 } 1216 1217 /* 1218 * Wait for codecs to finish their own reset sequence. The delay here 1219 * should be of 250us but for some reasons, on it's not enough on my 1220 * computer. Let's use twice as much as necessary to make sure that 1221 * it's reset properly. 1222 */ 1223 DELAY(1000); 1224 1225 return (0); 1226 } 1227 1228 1229 /**************************************************************************** 1230 * int hdac_get_capabilities(struct hdac_softc *); 1231 * 1232 * Retreive the general capabilities of the hdac; 1233 * Number of Input Streams 1234 * Number of Output Streams 1235 * Number of bidirectional Streams 1236 * 64bit ready 1237 * CORB and RIRB sizes 1238 ****************************************************************************/ 1239 static int 1240 hdac_get_capabilities(struct hdac_softc *sc) 1241 { 1242 uint16_t gcap; 1243 uint8_t corbsize, rirbsize; 1244 1245 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1246 sc->num_iss = HDAC_GCAP_ISS(gcap); 1247 sc->num_oss = HDAC_GCAP_OSS(gcap); 1248 sc->num_bss = HDAC_GCAP_BSS(gcap); 1249 1250 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1251 1252 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1253 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1254 HDAC_CORBSIZE_CORBSZCAP_256) 1255 sc->corb_size = 256; 1256 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1257 HDAC_CORBSIZE_CORBSZCAP_16) 1258 sc->corb_size = 16; 1259 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1260 HDAC_CORBSIZE_CORBSZCAP_2) 1261 sc->corb_size = 2; 1262 else { 1263 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1264 __func__, corbsize); 1265 return (ENXIO); 1266 } 1267 1268 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1269 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1270 HDAC_RIRBSIZE_RIRBSZCAP_256) 1271 sc->rirb_size = 256; 1272 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1273 HDAC_RIRBSIZE_RIRBSZCAP_16) 1274 sc->rirb_size = 16; 1275 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1276 HDAC_RIRBSIZE_RIRBSZCAP_2) 1277 sc->rirb_size = 2; 1278 else { 1279 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1280 __func__, rirbsize); 1281 return (ENXIO); 1282 } 1283 1284 return (0); 1285 } 1286 1287 1288 /**************************************************************************** 1289 * void hdac_dma_cb 1290 * 1291 * This function is called by bus_dmamap_load when the mapping has been 1292 * established. We just record the physical address of the mapping into 1293 * the struct hdac_dma passed in. 1294 ****************************************************************************/ 1295 static void 1296 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1297 { 1298 struct hdac_dma *dma; 1299 1300 if (error == 0) { 1301 dma = (struct hdac_dma *)callback_arg; 1302 dma->dma_paddr = segs[0].ds_addr; 1303 } 1304 } 1305 1306 1307 /**************************************************************************** 1308 * int hdac_dma_alloc 1309 * 1310 * This function allocate and setup a dma region (struct hdac_dma). 1311 * It must be freed by a corresponding hdac_dma_free. 1312 ****************************************************************************/ 1313 static int 1314 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1315 { 1316 bus_size_t roundsz; 1317 int result; 1318 int lowaddr; 1319 1320 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1321 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1322 BUS_SPACE_MAXADDR_32BIT; 1323 bzero(dma, sizeof(*dma)); 1324 1325 /* 1326 * Create a DMA tag 1327 */ 1328 result = bus_dma_tag_create(NULL, /* parent */ 1329 HDAC_DMA_ALIGNMENT, /* alignment */ 1330 0, /* boundary */ 1331 lowaddr, /* lowaddr */ 1332 BUS_SPACE_MAXADDR, /* highaddr */ 1333 NULL, /* filtfunc */ 1334 NULL, /* fistfuncarg */ 1335 roundsz, /* maxsize */ 1336 1, /* nsegments */ 1337 roundsz, /* maxsegsz */ 1338 0, /* flags */ 1339 NULL, /* lockfunc */ 1340 NULL, /* lockfuncarg */ 1341 &dma->dma_tag); /* dmat */ 1342 if (result != 0) { 1343 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1344 __func__, result); 1345 goto hdac_dma_alloc_fail; 1346 } 1347 1348 /* 1349 * Allocate DMA memory 1350 */ 1351 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1352 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1353 ((sc->nocache != 0) ? BUS_DMA_NOCACHE : 0), &dma->dma_map); 1354 if (result != 0) { 1355 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1356 __func__, result); 1357 goto hdac_dma_alloc_fail; 1358 } 1359 1360 dma->dma_size = roundsz; 1361 1362 /* 1363 * Map the memory 1364 */ 1365 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1366 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1367 if (result != 0 || dma->dma_paddr == 0) { 1368 if (result == 0) 1369 result = ENOMEM; 1370 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1371 __func__, result); 1372 goto hdac_dma_alloc_fail; 1373 } 1374 1375 HDA_BOOTVERBOSE( 1376 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1377 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1378 ); 1379 1380 return (0); 1381 1382 hdac_dma_alloc_fail: 1383 hdac_dma_free(sc, dma); 1384 1385 return (result); 1386 } 1387 1388 1389 /**************************************************************************** 1390 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1391 * 1392 * Free a struct dhac_dma that has been previously allocated via the 1393 * hdac_dma_alloc function. 1394 ****************************************************************************/ 1395 static void 1396 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1397 { 1398 if (dma->dma_map != NULL) { 1399 #if 0 1400 /* Flush caches */ 1401 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1402 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1403 #endif 1404 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1405 } 1406 if (dma->dma_vaddr != NULL) { 1407 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1408 dma->dma_vaddr = NULL; 1409 } 1410 dma->dma_map = NULL; 1411 if (dma->dma_tag != NULL) { 1412 bus_dma_tag_destroy(dma->dma_tag); 1413 dma->dma_tag = NULL; 1414 } 1415 dma->dma_size = 0; 1416 } 1417 1418 /**************************************************************************** 1419 * int hdac_mem_alloc(struct hdac_softc *) 1420 * 1421 * Allocate all the bus resources necessary to speak with the physical 1422 * controller. 1423 ****************************************************************************/ 1424 static int 1425 hdac_mem_alloc(struct hdac_softc *sc) 1426 { 1427 struct hdac_mem *mem; 1428 1429 mem = &sc->mem; 1430 mem->mem_rid = PCIR_BAR(0); 1431 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1432 &mem->mem_rid, RF_ACTIVE); 1433 if (mem->mem_res == NULL) { 1434 device_printf(sc->dev, 1435 "%s: Unable to allocate memory resource\n", __func__); 1436 return (ENOMEM); 1437 } 1438 mem->mem_tag = rman_get_bustag(mem->mem_res); 1439 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1440 1441 return (0); 1442 } 1443 1444 /**************************************************************************** 1445 * void hdac_mem_free(struct hdac_softc *) 1446 * 1447 * Free up resources previously allocated by hdac_mem_alloc. 1448 ****************************************************************************/ 1449 static void 1450 hdac_mem_free(struct hdac_softc *sc) 1451 { 1452 struct hdac_mem *mem; 1453 1454 mem = &sc->mem; 1455 if (mem->mem_res != NULL) 1456 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1457 mem->mem_res); 1458 mem->mem_res = NULL; 1459 } 1460 1461 /**************************************************************************** 1462 * int hdac_irq_alloc(struct hdac_softc *) 1463 * 1464 * Allocate and setup the resources necessary for interrupt handling. 1465 ****************************************************************************/ 1466 static int 1467 hdac_irq_alloc(struct hdac_softc *sc) 1468 { 1469 struct hdac_irq *irq; 1470 int result; 1471 1472 irq = &sc->irq; 1473 irq->irq_rid = 0x0; 1474 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1475 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1476 if (irq->irq_res == NULL) { 1477 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1478 __func__); 1479 goto hdac_irq_alloc_fail; 1480 } 1481 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1482 hdac_intr_handler, sc, &irq->irq_handle); 1483 if (result != 0) { 1484 device_printf(sc->dev, 1485 "%s: Unable to setup interrupt handler (%x)\n", 1486 __func__, result); 1487 goto hdac_irq_alloc_fail; 1488 } 1489 1490 return (0); 1491 1492 hdac_irq_alloc_fail: 1493 hdac_irq_free(sc); 1494 1495 return (ENXIO); 1496 } 1497 1498 /**************************************************************************** 1499 * void hdac_irq_free(struct hdac_softc *) 1500 * 1501 * Free up resources previously allocated by hdac_irq_alloc. 1502 ****************************************************************************/ 1503 static void 1504 hdac_irq_free(struct hdac_softc *sc) 1505 { 1506 struct hdac_irq *irq; 1507 1508 irq = &sc->irq; 1509 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1510 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1511 if (irq->irq_res != NULL) 1512 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1513 irq->irq_res); 1514 irq->irq_handle = NULL; 1515 irq->irq_res = NULL; 1516 } 1517 1518 /**************************************************************************** 1519 * void hdac_corb_init(struct hdac_softc *) 1520 * 1521 * Initialize the corb registers for operations but do not start it up yet. 1522 * The CORB engine must not be running when this function is called. 1523 ****************************************************************************/ 1524 static void 1525 hdac_corb_init(struct hdac_softc *sc) 1526 { 1527 uint8_t corbsize; 1528 uint64_t corbpaddr; 1529 1530 /* Setup the CORB size. */ 1531 switch (sc->corb_size) { 1532 case 256: 1533 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1534 break; 1535 case 16: 1536 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1537 break; 1538 case 2: 1539 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1540 break; 1541 default: 1542 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1543 } 1544 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1545 1546 /* Setup the CORB Address in the hdac */ 1547 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1548 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1549 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1550 1551 /* Set the WP and RP */ 1552 sc->corb_wp = 0; 1553 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1554 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1555 /* 1556 * The HDA specification indicates that the CORBRPRST bit will always 1557 * read as zero. Unfortunately, it seems that at least the 82801G 1558 * doesn't reset the bit to zero, which stalls the corb engine. 1559 * manually reset the bit to zero before continuing. 1560 */ 1561 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1562 1563 /* Enable CORB error reporting */ 1564 #if 0 1565 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1566 #endif 1567 } 1568 1569 /**************************************************************************** 1570 * void hdac_rirb_init(struct hdac_softc *) 1571 * 1572 * Initialize the rirb registers for operations but do not start it up yet. 1573 * The RIRB engine must not be running when this function is called. 1574 ****************************************************************************/ 1575 static void 1576 hdac_rirb_init(struct hdac_softc *sc) 1577 { 1578 uint8_t rirbsize; 1579 uint64_t rirbpaddr; 1580 1581 /* Setup the RIRB size. */ 1582 switch (sc->rirb_size) { 1583 case 256: 1584 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1585 break; 1586 case 16: 1587 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1588 break; 1589 case 2: 1590 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1591 break; 1592 default: 1593 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1594 } 1595 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1596 1597 /* Setup the RIRB Address in the hdac */ 1598 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1599 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1600 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1601 1602 /* Setup the WP and RP */ 1603 sc->rirb_rp = 0; 1604 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1605 1606 if (sc->polling == 0) { 1607 /* Setup the interrupt threshold */ 1608 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1609 1610 /* Enable Overrun and response received reporting */ 1611 #if 0 1612 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1613 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1614 #else 1615 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1616 #endif 1617 } 1618 1619 #if 0 1620 /* 1621 * Make sure that the Host CPU cache doesn't contain any dirty 1622 * cache lines that falls in the rirb. If I understood correctly, it 1623 * should be sufficient to do this only once as the rirb is purely 1624 * read-only from now on. 1625 */ 1626 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1627 BUS_DMASYNC_PREREAD); 1628 #endif 1629 } 1630 1631 /**************************************************************************** 1632 * void hdac_corb_start(hdac_softc *) 1633 * 1634 * Startup the corb DMA engine 1635 ****************************************************************************/ 1636 static void 1637 hdac_corb_start(struct hdac_softc *sc) 1638 { 1639 uint32_t corbctl; 1640 1641 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1642 corbctl |= HDAC_CORBCTL_CORBRUN; 1643 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1644 } 1645 1646 /**************************************************************************** 1647 * void hdac_rirb_start(hdac_softc *) 1648 * 1649 * Startup the rirb DMA engine 1650 ****************************************************************************/ 1651 static void 1652 hdac_rirb_start(struct hdac_softc *sc) 1653 { 1654 uint32_t rirbctl; 1655 1656 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1657 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1658 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1659 } 1660 1661 1662 /**************************************************************************** 1663 * void hdac_scan_codecs(struct hdac_softc *) 1664 * 1665 * Scan the bus for available codecs. 1666 ****************************************************************************/ 1667 static void 1668 hdac_scan_codecs(struct hdac_softc *sc) 1669 { 1670 struct hdac_codec *codec; 1671 int i; 1672 uint16_t statests; 1673 1674 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1675 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1676 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1677 /* We have found a codec. */ 1678 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1679 M_HDAC, M_ZERO | M_NOWAIT); 1680 if (codec == NULL) { 1681 device_printf(sc->dev, 1682 "Unable to allocate memory for codec\n"); 1683 continue; 1684 } 1685 codec->commands = NULL; 1686 codec->responses_received = 0; 1687 codec->verbs_sent = 0; 1688 codec->sc = sc; 1689 codec->cad = i; 1690 sc->codecs[i] = codec; 1691 if (hdac_probe_codec(codec) != 0) 1692 break; 1693 } 1694 } 1695 /* All codecs have been probed, now try to attach drivers to them */ 1696 /* bus_generic_attach(sc->dev); */ 1697 } 1698 1699 /**************************************************************************** 1700 * void hdac_probe_codec(struct hdac_softc *, int) 1701 * 1702 * Probe a the given codec_id for available function groups. 1703 ****************************************************************************/ 1704 static int 1705 hdac_probe_codec(struct hdac_codec *codec) 1706 { 1707 struct hdac_softc *sc = codec->sc; 1708 struct hdac_devinfo *devinfo; 1709 uint32_t vendorid, revisionid, subnode; 1710 int startnode; 1711 int endnode; 1712 int i; 1713 nid_t cad = codec->cad; 1714 1715 HDA_BOOTVERBOSE( 1716 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1717 ); 1718 vendorid = hdac_command(sc, 1719 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1720 cad); 1721 revisionid = hdac_command(sc, 1722 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1723 cad); 1724 subnode = hdac_command(sc, 1725 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1726 cad); 1727 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1728 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1729 1730 HDA_BOOTVERBOSE( 1731 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1732 startnode, endnode); 1733 ); 1734 for (i = startnode; i < endnode; i++) { 1735 devinfo = hdac_probe_function(codec, i); 1736 if (devinfo != NULL) { 1737 /* XXX Ignore other FG. */ 1738 devinfo->vendor_id = 1739 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1740 devinfo->device_id = 1741 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1742 devinfo->revision_id = 1743 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1744 devinfo->stepping_id = 1745 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1746 HDA_BOOTVERBOSE( 1747 device_printf(sc->dev, 1748 "HDA_DEBUG: \tFound AFG nid=%d " 1749 "[startnode=%d endnode=%d]\n", 1750 devinfo->nid, startnode, endnode); 1751 ); 1752 return (1); 1753 } 1754 } 1755 1756 HDA_BOOTVERBOSE( 1757 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1758 ); 1759 return (0); 1760 } 1761 1762 static struct hdac_devinfo * 1763 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1764 { 1765 struct hdac_softc *sc = codec->sc; 1766 struct hdac_devinfo *devinfo; 1767 uint32_t fctgrptype; 1768 nid_t cad = codec->cad; 1769 1770 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1771 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1772 1773 /* XXX For now, ignore other FG. */ 1774 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1775 return (NULL); 1776 1777 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1778 M_NOWAIT | M_ZERO); 1779 if (devinfo == NULL) { 1780 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1781 __func__); 1782 return (NULL); 1783 } 1784 1785 devinfo->nid = nid; 1786 devinfo->node_type = fctgrptype; 1787 devinfo->codec = codec; 1788 1789 hdac_add_child(sc, devinfo); 1790 1791 return (devinfo); 1792 } 1793 1794 static void 1795 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1796 { 1797 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1798 device_set_ivars(devinfo->dev, (void *)devinfo); 1799 /* XXX - Print more information when booting verbose??? */ 1800 } 1801 1802 static void 1803 hdac_widget_connection_parse(struct hdac_widget *w) 1804 { 1805 struct hdac_softc *sc = w->devinfo->codec->sc; 1806 uint32_t res; 1807 int i, j, max, ents, entnum; 1808 nid_t cad = w->devinfo->codec->cad; 1809 nid_t nid = w->nid; 1810 nid_t cnid, addcnid, prevcnid; 1811 1812 w->nconns = 0; 1813 1814 res = hdac_command(sc, 1815 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1816 1817 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1818 1819 if (ents < 1) 1820 return; 1821 1822 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1823 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1824 prevcnid = 0; 1825 1826 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1827 #define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1828 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1829 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1830 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1831 1832 for (i = 0; i < ents; i += entnum) { 1833 res = hdac_command(sc, 1834 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1835 for (j = 0; j < entnum; j++) { 1836 cnid = CONN_CNID(res, entnum, j); 1837 if (cnid == 0) { 1838 if (w->nconns < ents) 1839 device_printf(sc->dev, 1840 "%s: nid=%d WARNING: zero cnid " 1841 "entnum=%d j=%d index=%d " 1842 "entries=%d found=%d res=0x%08x\n", 1843 __func__, nid, entnum, j, i, 1844 ents, w->nconns, res); 1845 else 1846 goto getconns_out; 1847 } 1848 if (cnid < w->devinfo->startnode || 1849 cnid >= w->devinfo->endnode) { 1850 HDA_BOOTVERBOSE( 1851 device_printf(sc->dev, 1852 "%s: GHOST: nid=%d j=%d " 1853 "entnum=%d index=%d res=0x%08x\n", 1854 __func__, nid, j, entnum, i, res); 1855 ); 1856 } 1857 if (CONN_RANGE(res, entnum, j) == 0) 1858 addcnid = cnid; 1859 else if (prevcnid == 0 || prevcnid >= cnid) { 1860 device_printf(sc->dev, 1861 "%s: WARNING: Invalid child range " 1862 "nid=%d index=%d j=%d entnum=%d " 1863 "prevcnid=%d cnid=%d res=0x%08x\n", 1864 __func__, nid, i, j, entnum, prevcnid, 1865 cnid, res); 1866 addcnid = cnid; 1867 } else 1868 addcnid = prevcnid + 1; 1869 while (addcnid <= cnid) { 1870 if (w->nconns > max) { 1871 device_printf(sc->dev, 1872 "%s: nid=%d: Adding %d: " 1873 "Max connection reached! max=%d\n", 1874 __func__, nid, addcnid, max + 1); 1875 goto getconns_out; 1876 } 1877 w->conns[w->nconns++] = addcnid++; 1878 } 1879 prevcnid = cnid; 1880 } 1881 } 1882 1883 getconns_out: 1884 HDA_BOOTVERBOSE( 1885 device_printf(sc->dev, 1886 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1887 __func__, nid, ents, w->nconns); 1888 ); 1889 return; 1890 } 1891 1892 static uint32_t 1893 hdac_widget_pin_getconfig(struct hdac_widget *w) 1894 { 1895 struct hdac_softc *sc; 1896 uint32_t config, orig, id; 1897 nid_t cad, nid; 1898 1899 sc = w->devinfo->codec->sc; 1900 cad = w->devinfo->codec->cad; 1901 nid = w->nid; 1902 id = hdac_codec_id(w->devinfo); 1903 1904 config = hdac_command(sc, 1905 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1906 cad); 1907 orig = config; 1908 1909 /* 1910 * XXX REWRITE!!!! Don't argue! 1911 */ 1912 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1913 switch (nid) { 1914 case 26: 1915 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1916 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1917 break; 1918 case 27: 1919 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1920 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1921 break; 1922 default: 1923 break; 1924 } 1925 } else if (id == HDA_CODEC_ALC880 && 1926 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1927 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1928 /* 1929 * Super broken BIOS 1930 */ 1931 switch (nid) { 1932 case 20: 1933 break; 1934 case 21: 1935 break; 1936 case 22: 1937 break; 1938 case 23: 1939 break; 1940 case 24: /* MIC1 */ 1941 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1942 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1943 break; 1944 case 25: /* XXX MIC2 */ 1945 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1946 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1947 break; 1948 case 26: /* LINE1 */ 1949 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1950 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1951 break; 1952 case 27: /* XXX LINE2 */ 1953 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1954 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1955 break; 1956 case 28: /* CD */ 1957 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1958 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1959 break; 1960 case 30: 1961 break; 1962 case 31: 1963 break; 1964 default: 1965 break; 1966 } 1967 } else if (id == HDA_CODEC_ALC883 && 1968 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 1969 switch (nid) { 1970 case 25: 1971 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1972 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1973 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1974 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1975 break; 1976 case 28: 1977 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1978 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1979 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 1980 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1981 break; 1982 default: 1983 break; 1984 } 1985 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 1986 HP_V3000_SUBVENDOR) { 1987 switch (nid) { 1988 case 18: 1989 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 1990 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 1991 break; 1992 case 20: 1993 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1994 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1995 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1996 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1997 break; 1998 case 21: 1999 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2000 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2001 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2002 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2003 break; 2004 default: 2005 break; 2006 } 2007 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2008 HP_DV5000_SUBVENDOR) { 2009 switch (nid) { 2010 case 20: 2011 case 21: 2012 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2013 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2014 break; 2015 default: 2016 break; 2017 } 2018 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2019 ASUS_W6F_SUBVENDOR) { 2020 switch (nid) { 2021 case 11: 2022 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2023 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2024 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2025 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2026 break; 2027 case 15: 2028 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2029 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2030 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2031 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2032 break; 2033 default: 2034 break; 2035 } 2036 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2037 UNIWILL_9075_SUBVENDOR) { 2038 switch (nid) { 2039 case 15: 2040 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2041 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2042 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2043 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2044 break; 2045 default: 2046 break; 2047 } 2048 } else if (id == HDA_CODEC_AD1986A && sc->pci_subvendor == 2049 ASUS_M2NPVMX_SUBVENDOR) { 2050 switch (nid) { 2051 case 28: /* LINE */ 2052 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2053 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2054 break; 2055 case 29: /* MIC */ 2056 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2057 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2058 break; 2059 default: 2060 break; 2061 } 2062 } 2063 2064 HDA_BOOTVERBOSE( 2065 if (config != orig) 2066 device_printf(sc->dev, 2067 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2068 nid, orig, config); 2069 ); 2070 2071 return (config); 2072 } 2073 2074 static uint32_t 2075 hdac_widget_pin_getcaps(struct hdac_widget *w) 2076 { 2077 struct hdac_softc *sc; 2078 uint32_t caps, orig, id; 2079 nid_t cad, nid; 2080 2081 sc = w->devinfo->codec->sc; 2082 cad = w->devinfo->codec->cad; 2083 nid = w->nid; 2084 id = hdac_codec_id(w->devinfo); 2085 2086 caps = hdac_command(sc, 2087 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2088 orig = caps; 2089 2090 HDA_BOOTVERBOSE( 2091 if (caps != orig) 2092 device_printf(sc->dev, 2093 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2094 nid, orig, caps); 2095 ); 2096 2097 return (caps); 2098 } 2099 2100 static void 2101 hdac_widget_pin_parse(struct hdac_widget *w) 2102 { 2103 struct hdac_softc *sc = w->devinfo->codec->sc; 2104 uint32_t config, pincap; 2105 char *devstr, *connstr; 2106 nid_t cad = w->devinfo->codec->cad; 2107 nid_t nid = w->nid; 2108 2109 config = hdac_widget_pin_getconfig(w); 2110 w->wclass.pin.config = config; 2111 2112 pincap = hdac_widget_pin_getcaps(w); 2113 w->wclass.pin.cap = pincap; 2114 2115 w->wclass.pin.ctrl = hdac_command(sc, 2116 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2117 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2118 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2119 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2120 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2121 2122 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2123 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2124 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2125 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2126 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2127 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2128 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2129 w->param.eapdbtl = hdac_command(sc, 2130 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2131 w->param.eapdbtl &= 0x7; 2132 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2133 } else 2134 w->param.eapdbtl = HDAC_INVALID; 2135 2136 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2137 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2138 devstr = "line out"; 2139 break; 2140 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2141 devstr = "speaker"; 2142 break; 2143 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2144 devstr = "headphones out"; 2145 break; 2146 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2147 devstr = "CD"; 2148 break; 2149 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2150 devstr = "SPDIF out"; 2151 break; 2152 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2153 devstr = "digital (other) out"; 2154 break; 2155 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2156 devstr = "modem, line side"; 2157 break; 2158 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2159 devstr = "modem, handset side"; 2160 break; 2161 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2162 devstr = "line in"; 2163 break; 2164 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2165 devstr = "AUX"; 2166 break; 2167 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2168 devstr = "Mic in"; 2169 break; 2170 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2171 devstr = "telephony"; 2172 break; 2173 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2174 devstr = "SPDIF in"; 2175 break; 2176 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2177 devstr = "digital (other) in"; 2178 break; 2179 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2180 devstr = "other"; 2181 break; 2182 default: 2183 devstr = "unknown"; 2184 break; 2185 } 2186 2187 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2188 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2189 connstr = "jack"; 2190 break; 2191 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2192 connstr = "none"; 2193 break; 2194 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2195 connstr = "fixed"; 2196 break; 2197 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2198 connstr = "jack / fixed"; 2199 break; 2200 default: 2201 connstr = "unknown"; 2202 break; 2203 } 2204 2205 strlcat(w->name, ": ", sizeof(w->name)); 2206 strlcat(w->name, devstr, sizeof(w->name)); 2207 strlcat(w->name, " (", sizeof(w->name)); 2208 strlcat(w->name, connstr, sizeof(w->name)); 2209 strlcat(w->name, ")", sizeof(w->name)); 2210 } 2211 2212 static void 2213 hdac_widget_parse(struct hdac_widget *w) 2214 { 2215 struct hdac_softc *sc = w->devinfo->codec->sc; 2216 uint32_t wcap, cap; 2217 char *typestr; 2218 nid_t cad = w->devinfo->codec->cad; 2219 nid_t nid = w->nid; 2220 2221 wcap = hdac_command(sc, 2222 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2223 cad); 2224 w->param.widget_cap = wcap; 2225 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2226 2227 switch (w->type) { 2228 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2229 typestr = "audio output"; 2230 break; 2231 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2232 typestr = "audio input"; 2233 break; 2234 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2235 typestr = "audio mixer"; 2236 break; 2237 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2238 typestr = "audio selector"; 2239 break; 2240 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2241 typestr = "pin"; 2242 break; 2243 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2244 typestr = "power widget"; 2245 break; 2246 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2247 typestr = "volume widget"; 2248 break; 2249 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2250 typestr = "beep widget"; 2251 break; 2252 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2253 typestr = "vendor widget"; 2254 break; 2255 default: 2256 typestr = "unknown type"; 2257 break; 2258 } 2259 2260 strlcpy(w->name, typestr, sizeof(w->name)); 2261 2262 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2263 hdac_command(sc, 2264 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2265 cad); 2266 DELAY(1000); 2267 } 2268 2269 hdac_widget_connection_parse(w); 2270 2271 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2272 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2273 w->param.outamp_cap = 2274 hdac_command(sc, 2275 HDA_CMD_GET_PARAMETER(cad, nid, 2276 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2277 else 2278 w->param.outamp_cap = 2279 w->devinfo->function.audio.outamp_cap; 2280 } else 2281 w->param.outamp_cap = 0; 2282 2283 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2284 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2285 w->param.inamp_cap = 2286 hdac_command(sc, 2287 HDA_CMD_GET_PARAMETER(cad, nid, 2288 HDA_PARAM_INPUT_AMP_CAP), cad); 2289 else 2290 w->param.inamp_cap = 2291 w->devinfo->function.audio.inamp_cap; 2292 } else 2293 w->param.inamp_cap = 0; 2294 2295 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2296 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2297 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2298 cap = hdac_command(sc, 2299 HDA_CMD_GET_PARAMETER(cad, nid, 2300 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2301 w->param.supp_stream_formats = (cap != 0) ? cap : 2302 w->devinfo->function.audio.supp_stream_formats; 2303 cap = hdac_command(sc, 2304 HDA_CMD_GET_PARAMETER(cad, nid, 2305 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2306 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2307 w->devinfo->function.audio.supp_pcm_size_rate; 2308 } else { 2309 w->param.supp_stream_formats = 2310 w->devinfo->function.audio.supp_stream_formats; 2311 w->param.supp_pcm_size_rate = 2312 w->devinfo->function.audio.supp_pcm_size_rate; 2313 } 2314 } else { 2315 w->param.supp_stream_formats = 0; 2316 w->param.supp_pcm_size_rate = 0; 2317 } 2318 2319 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2320 hdac_widget_pin_parse(w); 2321 } 2322 2323 static struct hdac_widget * 2324 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2325 { 2326 if (devinfo == NULL || devinfo->widget == NULL || 2327 nid < devinfo->startnode || nid >= devinfo->endnode) 2328 return (NULL); 2329 return (&devinfo->widget[nid - devinfo->startnode]); 2330 } 2331 2332 static __inline int 2333 hda_poll_channel(struct hdac_chan *ch) 2334 { 2335 uint32_t sz, delta; 2336 volatile uint32_t ptr; 2337 2338 if (ch->active == 0) 2339 return (0); 2340 2341 sz = ch->blksz * ch->blkcnt; 2342 if (ch->dmapos != NULL) 2343 ptr = *(ch->dmapos); 2344 else 2345 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2346 ch->off + HDAC_SDLPIB); 2347 ch->ptr = ptr; 2348 ptr %= sz; 2349 ptr &= ~(ch->blksz - 1); 2350 delta = (sz + ptr - ch->prevptr) % sz; 2351 2352 if (delta < ch->blksz) 2353 return (0); 2354 2355 ch->prevptr = ptr; 2356 2357 return (1); 2358 } 2359 2360 #define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2361 2362 static void 2363 hda_poll_callback(void *arg) 2364 { 2365 struct hdac_softc *sc = arg; 2366 uint32_t trigger = 0; 2367 2368 if (sc == NULL) 2369 return; 2370 2371 hdac_lock(sc); 2372 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2373 hdac_unlock(sc); 2374 return; 2375 } 2376 2377 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2378 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2379 2380 /* XXX */ 2381 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2382 hda_poll_callback, sc); 2383 2384 hdac_unlock(sc); 2385 2386 if (trigger & 1) 2387 chn_intr(sc->play.c); 2388 if (trigger & 2) 2389 chn_intr(sc->rec.c); 2390 } 2391 2392 static int 2393 hdac_rirb_flush(struct hdac_softc *sc) 2394 { 2395 struct hdac_rirb *rirb_base, *rirb; 2396 struct hdac_codec *codec; 2397 struct hdac_command_list *commands; 2398 nid_t cad; 2399 uint32_t resp; 2400 uint8_t rirbwp; 2401 int ret = 0; 2402 2403 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2404 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2405 #if 0 2406 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2407 BUS_DMASYNC_POSTREAD); 2408 #endif 2409 2410 while (sc->rirb_rp != rirbwp) { 2411 sc->rirb_rp++; 2412 sc->rirb_rp %= sc->rirb_size; 2413 rirb = &rirb_base[sc->rirb_rp]; 2414 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2415 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2416 sc->codecs[cad] == NULL) 2417 continue; 2418 resp = rirb->response; 2419 codec = sc->codecs[cad]; 2420 commands = codec->commands; 2421 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2422 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2423 ((resp >> 26) & 0xffff); 2424 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2425 } else if (commands != NULL && commands->num_commands > 0 && 2426 codec->responses_received < commands->num_commands) 2427 commands->responses[codec->responses_received++] = 2428 resp; 2429 ret++; 2430 } 2431 2432 return (ret); 2433 } 2434 2435 static int 2436 hdac_unsolq_flush(struct hdac_softc *sc) 2437 { 2438 nid_t cad; 2439 uint32_t tag; 2440 int ret = 0; 2441 2442 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2443 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2444 while (sc->unsolq_rp != sc->unsolq_wp) { 2445 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2446 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2447 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2448 hdac_unsolicited_handler(sc->codecs[cad], tag); 2449 ret++; 2450 } 2451 sc->unsolq_st = HDAC_UNSOLQ_READY; 2452 } 2453 2454 return (ret); 2455 } 2456 2457 static void 2458 hdac_poll_callback(void *arg) 2459 { 2460 struct hdac_softc *sc = arg; 2461 if (sc == NULL) 2462 return; 2463 2464 hdac_lock(sc); 2465 if (sc->polling == 0 || sc->poll_ival == 0) { 2466 hdac_unlock(sc); 2467 return; 2468 } 2469 hdac_rirb_flush(sc); 2470 hdac_unsolq_flush(sc); 2471 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2472 hdac_unlock(sc); 2473 } 2474 2475 static void 2476 hdac_stream_stop(struct hdac_chan *ch) 2477 { 2478 struct hdac_softc *sc = ch->devinfo->codec->sc; 2479 uint32_t ctl; 2480 2481 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2482 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2483 HDAC_SDCTL_RUN); 2484 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2485 2486 ch->active = 0; 2487 2488 if (sc->polling != 0) { 2489 int pollticks; 2490 2491 if (hda_chan_active(sc) == 0) { 2492 callout_stop(&sc->poll_hda); 2493 sc->poll_ticks = 1; 2494 } else { 2495 if (sc->play.active != 0) 2496 ch = &sc->play; 2497 else 2498 ch = &sc->rec; 2499 pollticks = ((uint64_t)hz * ch->blksz) / 2500 ((uint64_t)sndbuf_getbps(ch->b) * 2501 sndbuf_getspd(ch->b)); 2502 pollticks >>= 2; 2503 if (pollticks > hz) 2504 pollticks = hz; 2505 if (pollticks < 1) { 2506 HDA_BOOTVERBOSE( 2507 device_printf(sc->dev, 2508 "%s: pollticks=%d < 1 !\n", 2509 __func__, pollticks); 2510 ); 2511 pollticks = 1; 2512 } 2513 if (pollticks > sc->poll_ticks) { 2514 HDA_BOOTVERBOSE( 2515 device_printf(sc->dev, 2516 "%s: pollticks %d -> %d\n", 2517 __func__, sc->poll_ticks, 2518 pollticks); 2519 ); 2520 sc->poll_ticks = pollticks; 2521 callout_reset(&sc->poll_hda, 1, 2522 hda_poll_callback, sc); 2523 } 2524 } 2525 } else { 2526 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2527 ctl &= ~(1 << (ch->off >> 5)); 2528 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2529 } 2530 } 2531 2532 static void 2533 hdac_stream_start(struct hdac_chan *ch) 2534 { 2535 struct hdac_softc *sc = ch->devinfo->codec->sc; 2536 uint32_t ctl; 2537 2538 if (sc->polling != 0) { 2539 int pollticks; 2540 2541 pollticks = ((uint64_t)hz * ch->blksz) / 2542 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2543 pollticks >>= 2; 2544 if (pollticks > hz) 2545 pollticks = hz; 2546 if (pollticks < 1) { 2547 HDA_BOOTVERBOSE( 2548 device_printf(sc->dev, 2549 "%s: pollticks=%d < 1 !\n", 2550 __func__, pollticks); 2551 ); 2552 pollticks = 1; 2553 } 2554 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2555 HDA_BOOTVERBOSE( 2556 if (hda_chan_active(sc) == 0) { 2557 device_printf(sc->dev, 2558 "%s: pollticks=%d\n", 2559 __func__, pollticks); 2560 } else { 2561 device_printf(sc->dev, 2562 "%s: pollticks %d -> %d\n", 2563 __func__, sc->poll_ticks, 2564 pollticks); 2565 } 2566 ); 2567 sc->poll_ticks = pollticks; 2568 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2569 sc); 2570 } 2571 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2572 ctl |= HDAC_SDCTL_RUN; 2573 } else { 2574 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2575 ctl |= 1 << (ch->off >> 5); 2576 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2577 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2578 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2579 HDAC_SDCTL_RUN; 2580 } 2581 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2582 2583 ch->active = 1; 2584 } 2585 2586 static void 2587 hdac_stream_reset(struct hdac_chan *ch) 2588 { 2589 struct hdac_softc *sc = ch->devinfo->codec->sc; 2590 int timeout = 1000; 2591 int to = timeout; 2592 uint32_t ctl; 2593 2594 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2595 ctl |= HDAC_SDCTL_SRST; 2596 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2597 do { 2598 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2599 if (ctl & HDAC_SDCTL_SRST) 2600 break; 2601 DELAY(10); 2602 } while (--to); 2603 if (!(ctl & HDAC_SDCTL_SRST)) { 2604 device_printf(sc->dev, "timeout in reset\n"); 2605 } 2606 ctl &= ~HDAC_SDCTL_SRST; 2607 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2608 to = timeout; 2609 do { 2610 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2611 if (!(ctl & HDAC_SDCTL_SRST)) 2612 break; 2613 DELAY(10); 2614 } while (--to); 2615 if (ctl & HDAC_SDCTL_SRST) 2616 device_printf(sc->dev, "can't reset!\n"); 2617 } 2618 2619 static void 2620 hdac_stream_setid(struct hdac_chan *ch) 2621 { 2622 struct hdac_softc *sc = ch->devinfo->codec->sc; 2623 uint32_t ctl; 2624 2625 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2626 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2627 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2628 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2629 } 2630 2631 static void 2632 hdac_bdl_setup(struct hdac_chan *ch) 2633 { 2634 struct hdac_softc *sc = ch->devinfo->codec->sc; 2635 struct hdac_bdle *bdle; 2636 uint64_t addr; 2637 uint32_t blksz, blkcnt; 2638 int i; 2639 2640 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2641 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2642 2643 if (sc->polling != 0) { 2644 blksz = ch->blksz * ch->blkcnt; 2645 blkcnt = 1; 2646 } else { 2647 blksz = ch->blksz; 2648 blkcnt = ch->blkcnt; 2649 } 2650 2651 for (i = 0; i < blkcnt; i++, bdle++) { 2652 bdle->addrl = (uint32_t)addr; 2653 bdle->addrh = (uint32_t)(addr >> 32); 2654 bdle->len = blksz; 2655 bdle->ioc = 1 ^ sc->polling; 2656 addr += blksz; 2657 } 2658 2659 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2660 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2661 addr = ch->bdl_dma.dma_paddr; 2662 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2663 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2664 if (ch->dmapos != NULL && 2665 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2666 addr = sc->pos_dma.dma_paddr; 2667 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2668 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2669 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2670 } 2671 } 2672 2673 static int 2674 hdac_bdl_alloc(struct hdac_chan *ch) 2675 { 2676 struct hdac_softc *sc = ch->devinfo->codec->sc; 2677 int rc; 2678 2679 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2680 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2681 if (rc) { 2682 device_printf(sc->dev, "can't alloc bdl\n"); 2683 return (rc); 2684 } 2685 2686 return (0); 2687 } 2688 2689 static void 2690 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2691 int index, int lmute, int rmute, 2692 int left, int right, int dir) 2693 { 2694 uint16_t v = 0; 2695 2696 if (sc == NULL) 2697 return; 2698 2699 if (left != right || lmute != rmute) { 2700 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2701 (lmute << 7) | left; 2702 hdac_command(sc, 2703 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2704 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2705 (rmute << 7) | right; 2706 } else 2707 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2708 (lmute << 7) | left; 2709 2710 hdac_command(sc, 2711 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2712 } 2713 2714 static void 2715 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2716 int left, int right) 2717 { 2718 struct hdac_softc *sc; 2719 nid_t nid, cad; 2720 int lmute, rmute; 2721 2722 if (ctl == NULL || ctl->widget == NULL || 2723 ctl->widget->devinfo == NULL || 2724 ctl->widget->devinfo->codec == NULL || 2725 ctl->widget->devinfo->codec->sc == NULL) 2726 return; 2727 2728 sc = ctl->widget->devinfo->codec->sc; 2729 cad = ctl->widget->devinfo->codec->cad; 2730 nid = ctl->widget->nid; 2731 2732 if (mute == HDA_AMP_MUTE_DEFAULT) { 2733 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2734 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2735 } else { 2736 lmute = HDA_AMP_LEFT_MUTED(mute); 2737 rmute = HDA_AMP_RIGHT_MUTED(mute); 2738 } 2739 2740 if (ctl->dir & HDA_CTL_OUT) 2741 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2742 lmute, rmute, left, right, 0); 2743 if (ctl->dir & HDA_CTL_IN) 2744 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2745 lmute, rmute, left, right, 1); 2746 ctl->left = left; 2747 ctl->right = right; 2748 } 2749 2750 static void 2751 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2752 { 2753 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2754 return; 2755 hdac_command(w->devinfo->codec->sc, 2756 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2757 w->nid, index), w->devinfo->codec->cad); 2758 w->selconn = index; 2759 } 2760 2761 2762 /**************************************************************************** 2763 * uint32_t hdac_command_sendone_internal 2764 * 2765 * Wrapper function that sends only one command to a given codec 2766 ****************************************************************************/ 2767 static uint32_t 2768 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2769 { 2770 struct hdac_command_list cl; 2771 uint32_t response = HDAC_INVALID; 2772 2773 if (!hdac_lockowned(sc)) 2774 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2775 cl.num_commands = 1; 2776 cl.verbs = &verb; 2777 cl.responses = &response; 2778 2779 hdac_command_send_internal(sc, &cl, cad); 2780 2781 return (response); 2782 } 2783 2784 /**************************************************************************** 2785 * hdac_command_send_internal 2786 * 2787 * Send a command list to the codec via the corb. We queue as much verbs as 2788 * we can and msleep on the codec. When the interrupt get the responses 2789 * back from the rirb, it will wake us up so we can queue the remaining verbs 2790 * if any. 2791 ****************************************************************************/ 2792 static void 2793 hdac_command_send_internal(struct hdac_softc *sc, 2794 struct hdac_command_list *commands, nid_t cad) 2795 { 2796 struct hdac_codec *codec; 2797 int corbrp; 2798 uint32_t *corb; 2799 int timeout; 2800 int retry = 10; 2801 struct hdac_rirb *rirb_base; 2802 2803 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2804 commands->num_commands < 1) 2805 return; 2806 2807 codec = sc->codecs[cad]; 2808 codec->commands = commands; 2809 codec->responses_received = 0; 2810 codec->verbs_sent = 0; 2811 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2812 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2813 2814 do { 2815 if (codec->verbs_sent != commands->num_commands) { 2816 /* Queue as many verbs as possible */ 2817 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2818 #if 0 2819 bus_dmamap_sync(sc->corb_dma.dma_tag, 2820 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2821 #endif 2822 while (codec->verbs_sent != commands->num_commands && 2823 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2824 sc->corb_wp++; 2825 sc->corb_wp %= sc->corb_size; 2826 corb[sc->corb_wp] = 2827 commands->verbs[codec->verbs_sent++]; 2828 } 2829 2830 /* Send the verbs to the codecs */ 2831 #if 0 2832 bus_dmamap_sync(sc->corb_dma.dma_tag, 2833 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2834 #endif 2835 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2836 } 2837 2838 timeout = 1000; 2839 while (hdac_rirb_flush(sc) == 0 && --timeout) 2840 DELAY(10); 2841 } while ((codec->verbs_sent != commands->num_commands || 2842 codec->responses_received != commands->num_commands) && --retry); 2843 2844 if (retry == 0) 2845 device_printf(sc->dev, 2846 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2847 __func__, commands->num_commands, codec->verbs_sent, 2848 codec->responses_received); 2849 2850 codec->commands = NULL; 2851 codec->responses_received = 0; 2852 codec->verbs_sent = 0; 2853 2854 hdac_unsolq_flush(sc); 2855 } 2856 2857 2858 /**************************************************************************** 2859 * Device Methods 2860 ****************************************************************************/ 2861 2862 /**************************************************************************** 2863 * int hdac_probe(device_t) 2864 * 2865 * Probe for the presence of an hdac. If none is found, check for a generic 2866 * match using the subclass of the device. 2867 ****************************************************************************/ 2868 static int 2869 hdac_probe(device_t dev) 2870 { 2871 int i, result; 2872 uint32_t model; 2873 uint16_t class, subclass; 2874 char desc[64]; 2875 2876 model = (uint32_t)pci_get_device(dev) << 16; 2877 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2878 class = pci_get_class(dev); 2879 subclass = pci_get_subclass(dev); 2880 2881 bzero(desc, sizeof(desc)); 2882 result = ENXIO; 2883 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2884 if (hdac_devices[i].model == model) { 2885 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2886 result = BUS_PROBE_DEFAULT; 2887 break; 2888 } 2889 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2890 class == PCIC_MULTIMEDIA && 2891 subclass == PCIS_MULTIMEDIA_HDA) { 2892 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2893 result = BUS_PROBE_GENERIC; 2894 break; 2895 } 2896 } 2897 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2898 subclass == PCIS_MULTIMEDIA_HDA) { 2899 strlcpy(desc, "Generic", sizeof(desc)); 2900 result = BUS_PROBE_GENERIC; 2901 } 2902 if (result != ENXIO) { 2903 strlcat(desc, " High Definition Audio Controller", 2904 sizeof(desc)); 2905 device_set_desc_copy(dev, desc); 2906 } 2907 2908 return (result); 2909 } 2910 2911 static void * 2912 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2913 struct pcm_channel *c, int dir) 2914 { 2915 struct hdac_devinfo *devinfo = data; 2916 struct hdac_softc *sc = devinfo->codec->sc; 2917 struct hdac_chan *ch; 2918 2919 hdac_lock(sc); 2920 if (dir == PCMDIR_PLAY) { 2921 ch = &sc->play; 2922 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2923 devinfo->function.audio.playcnt++; 2924 } else { 2925 ch = &sc->rec; 2926 ch->off = devinfo->function.audio.reccnt << 5; 2927 devinfo->function.audio.reccnt++; 2928 } 2929 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2930 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2931 ch->pcmrates[0] = 48000; 2932 ch->pcmrates[1] = 0; 2933 } 2934 if (sc->pos_dma.dma_vaddr != NULL) 2935 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 2936 (sc->streamcnt * 8)); 2937 else 2938 ch->dmapos = NULL; 2939 ch->sid = ++sc->streamcnt; 2940 ch->dir = dir; 2941 ch->b = b; 2942 ch->c = c; 2943 ch->devinfo = devinfo; 2944 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2945 ch->blkcnt = sc->chan_blkcnt; 2946 hdac_unlock(sc); 2947 2948 if (hdac_bdl_alloc(ch) != 0) { 2949 ch->blkcnt = 0; 2950 return (NULL); 2951 } 2952 2953 if (sndbuf_alloc(ch->b, sc->chan_dmat, 2954 (sc->nocache != 0) ? BUS_DMA_NOCACHE : 0, sc->chan_size) != 0) 2955 return (NULL); 2956 2957 return (ch); 2958 } 2959 2960 static int 2961 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2962 { 2963 struct hdac_chan *ch = data; 2964 int i; 2965 2966 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2967 if (format == ch->caps.fmtlist[i]) { 2968 ch->fmt = format; 2969 return (0); 2970 } 2971 } 2972 2973 return (EINVAL); 2974 } 2975 2976 static int 2977 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2978 { 2979 struct hdac_chan *ch = data; 2980 uint32_t spd = 0, threshold; 2981 int i; 2982 2983 for (i = 0; ch->pcmrates[i] != 0; i++) { 2984 spd = ch->pcmrates[i]; 2985 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2986 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2987 if (speed < threshold) 2988 break; 2989 } 2990 2991 if (spd == 0) /* impossible */ 2992 ch->spd = 48000; 2993 else 2994 ch->spd = spd; 2995 2996 return (ch->spd); 2997 } 2998 2999 static void 3000 hdac_stream_setup(struct hdac_chan *ch) 3001 { 3002 struct hdac_softc *sc = ch->devinfo->codec->sc; 3003 int i; 3004 nid_t cad = ch->devinfo->codec->cad; 3005 uint16_t fmt; 3006 3007 fmt = 0; 3008 if (ch->fmt & AFMT_S16_LE) 3009 fmt |= ch->bit16 << 4; 3010 else if (ch->fmt & AFMT_S32_LE) 3011 fmt |= ch->bit32 << 4; 3012 else 3013 fmt |= 1 << 4; 3014 3015 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3016 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3017 fmt |= hda_rate_tab[i].base; 3018 fmt |= hda_rate_tab[i].mul; 3019 fmt |= hda_rate_tab[i].div; 3020 break; 3021 } 3022 } 3023 3024 if (ch->fmt & AFMT_STEREO) 3025 fmt |= 1; 3026 3027 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3028 3029 for (i = 0; ch->io[i] != -1; i++) { 3030 HDA_BOOTVERBOSE( 3031 device_printf(sc->dev, 3032 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3033 "fmt=0x%08x\n", 3034 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3035 ch->io[i], fmt); 3036 ); 3037 hdac_command(sc, 3038 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3039 hdac_command(sc, 3040 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3041 ch->sid << 4), cad); 3042 } 3043 } 3044 3045 static int 3046 hdac_channel_setfragments(kobj_t obj, void *data, 3047 uint32_t blksz, uint32_t blkcnt) 3048 { 3049 struct hdac_chan *ch = data; 3050 struct hdac_softc *sc = ch->devinfo->codec->sc; 3051 3052 blksz &= HDA_BLK_ALIGN; 3053 3054 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3055 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3056 if (blksz < HDA_BLK_MIN) 3057 blksz = HDA_BLK_MIN; 3058 if (blkcnt > HDA_BDL_MAX) 3059 blkcnt = HDA_BDL_MAX; 3060 if (blkcnt < HDA_BDL_MIN) 3061 blkcnt = HDA_BDL_MIN; 3062 3063 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3064 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3065 blkcnt >>= 1; 3066 else if ((blksz >> 1) >= HDA_BLK_MIN) 3067 blksz >>= 1; 3068 else 3069 break; 3070 } 3071 3072 if ((sndbuf_getblksz(ch->b) != blksz || 3073 sndbuf_getblkcnt(ch->b) != blkcnt) && 3074 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3075 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3076 __func__, blksz, blkcnt); 3077 3078 ch->blksz = sndbuf_getblksz(ch->b); 3079 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3080 3081 return (1); 3082 } 3083 3084 static int 3085 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3086 { 3087 struct hdac_chan *ch = data; 3088 struct hdac_softc *sc = ch->devinfo->codec->sc; 3089 3090 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3091 3092 return (ch->blksz); 3093 } 3094 3095 static void 3096 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3097 { 3098 struct hdac_devinfo *devinfo = ch->devinfo; 3099 nid_t cad = devinfo->codec->cad; 3100 int i; 3101 3102 hdac_stream_stop(ch); 3103 3104 for (i = 0; ch->io[i] != -1; i++) { 3105 hdac_command(sc, 3106 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3107 0), cad); 3108 } 3109 } 3110 3111 static void 3112 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3113 { 3114 ch->ptr = 0; 3115 ch->prevptr = 0; 3116 hdac_stream_stop(ch); 3117 hdac_stream_reset(ch); 3118 hdac_bdl_setup(ch); 3119 hdac_stream_setid(ch); 3120 hdac_stream_setup(ch); 3121 hdac_stream_start(ch); 3122 } 3123 3124 static int 3125 hdac_channel_trigger(kobj_t obj, void *data, int go) 3126 { 3127 struct hdac_chan *ch = data; 3128 struct hdac_softc *sc = ch->devinfo->codec->sc; 3129 3130 hdac_lock(sc); 3131 switch (go) { 3132 case PCMTRIG_START: 3133 hdac_channel_start(sc, ch); 3134 break; 3135 case PCMTRIG_STOP: 3136 case PCMTRIG_ABORT: 3137 hdac_channel_stop(sc, ch); 3138 break; 3139 default: 3140 break; 3141 } 3142 hdac_unlock(sc); 3143 3144 return (0); 3145 } 3146 3147 static int 3148 hdac_channel_getptr(kobj_t obj, void *data) 3149 { 3150 struct hdac_chan *ch = data; 3151 struct hdac_softc *sc = ch->devinfo->codec->sc; 3152 uint32_t ptr; 3153 3154 hdac_lock(sc); 3155 if (sc->polling != 0) 3156 ptr = ch->ptr; 3157 else if (ch->dmapos != NULL) 3158 ptr = *(ch->dmapos); 3159 else 3160 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3161 hdac_unlock(sc); 3162 3163 /* 3164 * Round to available space and force 128 bytes aligment. 3165 */ 3166 ptr %= ch->blksz * ch->blkcnt; 3167 ptr &= HDA_BLK_ALIGN; 3168 3169 return (ptr); 3170 } 3171 3172 static struct pcmchan_caps * 3173 hdac_channel_getcaps(kobj_t obj, void *data) 3174 { 3175 return (&((struct hdac_chan *)data)->caps); 3176 } 3177 3178 static kobj_method_t hdac_channel_methods[] = { 3179 KOBJMETHOD(channel_init, hdac_channel_init), 3180 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3181 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3182 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3183 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3184 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3185 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3186 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3187 { 0, 0 } 3188 }; 3189 CHANNEL_DECLARE(hdac_channel); 3190 3191 static void 3192 hdac_jack_poll_callback(void *arg) 3193 { 3194 struct hdac_devinfo *devinfo = arg; 3195 struct hdac_softc *sc; 3196 3197 if (devinfo == NULL || devinfo->codec == NULL || 3198 devinfo->codec->sc == NULL) 3199 return; 3200 sc = devinfo->codec->sc; 3201 hdac_lock(sc); 3202 if (sc->poll_ival == 0) { 3203 hdac_unlock(sc); 3204 return; 3205 } 3206 hdac_hp_switch_handler(devinfo); 3207 callout_reset(&sc->poll_jack, sc->poll_ival, 3208 hdac_jack_poll_callback, devinfo); 3209 hdac_unlock(sc); 3210 } 3211 3212 static int 3213 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3214 { 3215 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3216 struct hdac_softc *sc = devinfo->codec->sc; 3217 struct hdac_widget *w, *cw; 3218 struct hdac_audio_ctl *ctl; 3219 uint32_t mask, recmask, id; 3220 int i, j, softpcmvol; 3221 nid_t cad; 3222 3223 hdac_lock(sc); 3224 3225 mask = 0; 3226 recmask = 0; 3227 3228 id = hdac_codec_id(devinfo); 3229 cad = devinfo->codec->cad; 3230 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3231 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3232 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3233 continue; 3234 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3235 if (w == NULL || w->enable == 0 || w->type != 3236 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3237 continue; 3238 if (hdac_hp_switch[i].polling != 0) 3239 callout_reset(&sc->poll_jack, 1, 3240 hdac_jack_poll_callback, devinfo); 3241 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3242 hdac_command(sc, 3243 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3244 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3245 HDAC_UNSOLTAG_EVENT_HP), cad); 3246 else 3247 continue; 3248 hdac_hp_switch_handler(devinfo); 3249 HDA_BOOTVERBOSE( 3250 device_printf(sc->dev, 3251 "HDA_DEBUG: Enabling headphone/speaker " 3252 "audio routing switching:\n"); 3253 device_printf(sc->dev, 3254 "HDA_DEBUG: \tindex=%d nid=%d " 3255 "pci_subvendor=0x%08x " 3256 "codec=0x%08x [%s]\n", 3257 i, w->nid, sc->pci_subvendor, id, 3258 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3259 "UNSOL"); 3260 ); 3261 break; 3262 } 3263 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3264 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3265 sc->pci_subvendor) && 3266 hdac_eapd_switch[i].id == id)) 3267 continue; 3268 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3269 if (w == NULL || w->enable == 0) 3270 break; 3271 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3272 w->param.eapdbtl == HDAC_INVALID) 3273 break; 3274 mask |= SOUND_MASK_OGAIN; 3275 break; 3276 } 3277 3278 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3279 w = hdac_widget_get(devinfo, i); 3280 if (w == NULL || w->enable == 0) 3281 continue; 3282 mask |= w->ctlflags; 3283 if (!(w->pflags & HDA_ADC_RECSEL)) 3284 continue; 3285 for (j = 0; j < w->nconns; j++) { 3286 cw = hdac_widget_get(devinfo, w->conns[j]); 3287 if (cw == NULL || cw->enable == 0) 3288 continue; 3289 recmask |= cw->ctlflags; 3290 } 3291 } 3292 3293 if (!(mask & SOUND_MASK_PCM)) { 3294 softpcmvol = 1; 3295 mask |= SOUND_MASK_PCM; 3296 } else 3297 softpcmvol = (devinfo->function.audio.quirks & 3298 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3299 3300 i = 0; 3301 ctl = NULL; 3302 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3303 if (ctl->widget == NULL || ctl->enable == 0) 3304 continue; 3305 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3306 continue; 3307 if (ctl->step > 0) 3308 break; 3309 } 3310 3311 if (softpcmvol == 1 || ctl == NULL) { 3312 struct snddev_info *d = NULL; 3313 d = device_get_softc(sc->dev); 3314 if (d != NULL) { 3315 d->flags |= SD_F_SOFTPCMVOL; 3316 HDA_BOOTVERBOSE( 3317 device_printf(sc->dev, 3318 "HDA_DEBUG: %s Soft PCM volume\n", 3319 (softpcmvol == 1) ? 3320 "Forcing" : "Enabling"); 3321 ); 3322 } 3323 i = 0; 3324 /* 3325 * XXX Temporary quirk for STAC9220, until the parser 3326 * become smarter. 3327 */ 3328 if (id == HDA_CODEC_STAC9220) { 3329 mask |= SOUND_MASK_VOLUME; 3330 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3331 NULL) { 3332 if (ctl->widget == NULL || ctl->enable == 0) 3333 continue; 3334 if (ctl->widget->nid == 11 && ctl->index == 0) { 3335 ctl->ossmask = SOUND_MASK_VOLUME; 3336 ctl->ossval = 100 | (100 << 8); 3337 } else 3338 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3339 } 3340 } else if (id == HDA_CODEC_STAC9221) { 3341 mask |= SOUND_MASK_VOLUME; 3342 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3343 NULL) { 3344 if (ctl->widget == NULL) 3345 continue; 3346 if (ctl->widget->type == 3347 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3348 ctl->index == 0 && (ctl->widget->nid == 2 || 3349 ctl->widget->enable != 0)) { 3350 ctl->enable = 1; 3351 ctl->ossmask = SOUND_MASK_VOLUME; 3352 ctl->ossval = 100 | (100 << 8); 3353 } else if (ctl->enable == 0) 3354 continue; 3355 else 3356 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3357 } 3358 } else { 3359 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3360 SOUND_MASK_PCM); 3361 if (!(mask & SOUND_MASK_VOLUME)) 3362 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3363 SOUND_MIXER_NONE); 3364 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3365 NULL) { 3366 if (ctl->widget == NULL || ctl->enable == 0) 3367 continue; 3368 if (!HDA_FLAG_MATCH(ctl->ossmask, 3369 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3370 continue; 3371 if (!(ctl->mute == 1 && ctl->step == 0)) 3372 ctl->enable = 0; 3373 } 3374 } 3375 } 3376 3377 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3378 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3379 SOUND_MASK_OGAIN); 3380 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3381 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3382 3383 mix_setrecdevs(m, recmask); 3384 mix_setdevs(m, mask); 3385 3386 hdac_unlock(sc); 3387 3388 return (0); 3389 } 3390 3391 static int 3392 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3393 unsigned left, unsigned right) 3394 { 3395 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3396 struct hdac_softc *sc = devinfo->codec->sc; 3397 struct hdac_widget *w; 3398 struct hdac_audio_ctl *ctl; 3399 uint32_t id, mute; 3400 int lvol, rvol, mlvol, mrvol; 3401 int i = 0; 3402 3403 hdac_lock(sc); 3404 if (dev == SOUND_MIXER_OGAIN) { 3405 uint32_t orig; 3406 /*if (left != right || !(left == 0 || left == 1)) { 3407 hdac_unlock(sc); 3408 return (-1); 3409 }*/ 3410 id = hdac_codec_id(devinfo); 3411 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3412 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3413 sc->pci_subvendor) && 3414 hdac_eapd_switch[i].id == id) 3415 break; 3416 } 3417 if (i >= HDAC_EAPD_SWITCH_LEN) { 3418 hdac_unlock(sc); 3419 return (-1); 3420 } 3421 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3422 if (w == NULL || 3423 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3424 w->param.eapdbtl == HDAC_INVALID) { 3425 hdac_unlock(sc); 3426 return (-1); 3427 } 3428 orig = w->param.eapdbtl; 3429 if (left == 0) 3430 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3431 else 3432 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3433 if (orig != w->param.eapdbtl) { 3434 uint32_t val; 3435 3436 if (hdac_eapd_switch[i].hp_switch != 0) 3437 hdac_hp_switch_handler(devinfo); 3438 val = w->param.eapdbtl; 3439 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3440 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3441 hdac_command(sc, 3442 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3443 w->nid, val), devinfo->codec->cad); 3444 } 3445 hdac_unlock(sc); 3446 return (left | (left << 8)); 3447 } 3448 if (dev == SOUND_MIXER_VOLUME) 3449 devinfo->function.audio.mvol = left | (right << 8); 3450 3451 mlvol = devinfo->function.audio.mvol & 0x7f; 3452 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3453 lvol = 0; 3454 rvol = 0; 3455 3456 i = 0; 3457 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3458 if (ctl->widget == NULL || ctl->enable == 0 || 3459 !(ctl->ossmask & (1 << dev))) 3460 continue; 3461 switch (dev) { 3462 case SOUND_MIXER_VOLUME: 3463 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3464 lvol = (lvol * ctl->step) / 100; 3465 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3466 rvol = (rvol * ctl->step) / 100; 3467 break; 3468 default: 3469 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3470 lvol = (left * mlvol) / 100; 3471 lvol = (lvol * ctl->step) / 100; 3472 rvol = (right * mrvol) / 100; 3473 rvol = (rvol * ctl->step) / 100; 3474 } else { 3475 lvol = (left * ctl->step) / 100; 3476 rvol = (right * ctl->step) / 100; 3477 } 3478 ctl->ossval = left | (right << 8); 3479 break; 3480 } 3481 mute = 0; 3482 if (ctl->step < 1) { 3483 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3484 (ctl->muted & HDA_AMP_MUTE_LEFT); 3485 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3486 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3487 } else { 3488 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3489 (ctl->muted & HDA_AMP_MUTE_LEFT); 3490 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3491 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3492 } 3493 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3494 } 3495 hdac_unlock(sc); 3496 3497 return (left | (right << 8)); 3498 } 3499 3500 static int 3501 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3502 { 3503 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3504 struct hdac_widget *w, *cw; 3505 struct hdac_softc *sc = devinfo->codec->sc; 3506 uint32_t ret = src, target; 3507 int i, j; 3508 3509 target = 0; 3510 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3511 if (src & (1 << i)) { 3512 target = 1 << i; 3513 break; 3514 } 3515 } 3516 3517 hdac_lock(sc); 3518 3519 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3520 w = hdac_widget_get(devinfo, i); 3521 if (w == NULL || w->enable == 0) 3522 continue; 3523 if (!(w->pflags & HDA_ADC_RECSEL)) 3524 continue; 3525 for (j = 0; j < w->nconns; j++) { 3526 cw = hdac_widget_get(devinfo, w->conns[j]); 3527 if (cw == NULL || cw->enable == 0) 3528 continue; 3529 if ((target == SOUND_MASK_VOLUME && 3530 cw->type != 3531 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3532 (target != SOUND_MASK_VOLUME && 3533 cw->type == 3534 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3535 continue; 3536 if (cw->ctlflags & target) { 3537 if (!(w->pflags & HDA_ADC_LOCKED)) 3538 hdac_widget_connection_select(w, j); 3539 ret = target; 3540 j += w->nconns; 3541 } 3542 } 3543 } 3544 3545 hdac_unlock(sc); 3546 3547 return (ret); 3548 } 3549 3550 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3551 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3552 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3553 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3554 { 0, 0 } 3555 }; 3556 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3557 3558 /**************************************************************************** 3559 * int hdac_attach(device_t) 3560 * 3561 * Attach the device into the kernel. Interrupts usually won't be enabled 3562 * when this function is called. Setup everything that doesn't require 3563 * interrupts and defer probing of codecs until interrupts are enabled. 3564 ****************************************************************************/ 3565 static int 3566 hdac_attach(device_t dev) 3567 { 3568 struct hdac_softc *sc; 3569 int result; 3570 int i; 3571 uint16_t vendor; 3572 uint8_t v; 3573 3574 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3575 if (sc == NULL) { 3576 device_printf(dev, "cannot allocate softc\n"); 3577 return (ENOMEM); 3578 } 3579 3580 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3581 sc->dev = dev; 3582 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3583 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3584 vendor = pci_get_vendor(dev); 3585 3586 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3587 /* Screw nx6325 - subdevice/subvendor swapped */ 3588 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3589 } 3590 3591 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3592 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3593 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3594 3595 sc->poll_ticks = 1; 3596 sc->poll_ival = HDAC_POLL_INTERVAL; 3597 if (resource_int_value(device_get_name(dev), 3598 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3599 sc->polling = 1; 3600 else 3601 sc->polling = 0; 3602 3603 sc->chan_size = pcm_getbuffersize(dev, 3604 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3605 3606 if (resource_int_value(device_get_name(dev), 3607 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3608 i &= HDA_BLK_ALIGN; 3609 if (i < HDA_BLK_MIN) 3610 i = HDA_BLK_MIN; 3611 sc->chan_blkcnt = sc->chan_size / i; 3612 i = 0; 3613 while (sc->chan_blkcnt >> i) 3614 i++; 3615 sc->chan_blkcnt = 1 << (i - 1); 3616 if (sc->chan_blkcnt < HDA_BDL_MIN) 3617 sc->chan_blkcnt = HDA_BDL_MIN; 3618 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3619 sc->chan_blkcnt = HDA_BDL_MAX; 3620 } else 3621 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3622 3623 result = bus_dma_tag_create(NULL, /* parent */ 3624 HDAC_DMA_ALIGNMENT, /* alignment */ 3625 0, /* boundary */ 3626 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3627 BUS_SPACE_MAXADDR, /* highaddr */ 3628 NULL, /* filtfunc */ 3629 NULL, /* fistfuncarg */ 3630 sc->chan_size, /* maxsize */ 3631 1, /* nsegments */ 3632 sc->chan_size, /* maxsegsz */ 3633 0, /* flags */ 3634 NULL, /* lockfunc */ 3635 NULL, /* lockfuncarg */ 3636 &sc->chan_dmat); /* dmat */ 3637 if (result != 0) { 3638 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3639 __func__, result); 3640 snd_mtxfree(sc->lock); 3641 free(sc, M_DEVBUF); 3642 return (ENXIO); 3643 } 3644 3645 3646 sc->hdabus = NULL; 3647 for (i = 0; i < HDAC_CODEC_MAX; i++) 3648 sc->codecs[i] = NULL; 3649 3650 pci_enable_busmaster(dev); 3651 3652 if (vendor == INTEL_VENDORID) { 3653 /* TCSEL -> TC0 */ 3654 v = pci_read_config(dev, 0x44, 1); 3655 pci_write_config(dev, 0x44, v & 0xf8, 1); 3656 HDA_BOOTVERBOSE( 3657 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3658 pci_read_config(dev, 0x44, 1)); 3659 ); 3660 } 3661 3662 #if defined(__i386__) || defined(__amd64__) 3663 sc->nocache = 1; 3664 3665 if (resource_int_value(device_get_name(dev), 3666 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3667 #else 3668 sc->nocache = 0; 3669 #endif 3670 /* 3671 * Try to enable PCIe snoop to avoid messing around with 3672 * uncacheable DMA attribute. Since PCIe snoop register 3673 * config is pretty much vendor specific, there are no 3674 * general solutions on how to enable it, forcing us (even 3675 * Microsoft) to enable uncacheable or write combined DMA 3676 * by default. 3677 * 3678 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3679 */ 3680 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3681 if (hdac_pcie_snoop[i].vendor != vendor) 3682 continue; 3683 sc->nocache = 0; 3684 if (hdac_pcie_snoop[i].reg == 0x00) 3685 break; 3686 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3687 if ((v & hdac_pcie_snoop[i].enable) == 3688 hdac_pcie_snoop[i].enable) 3689 break; 3690 v &= hdac_pcie_snoop[i].mask; 3691 v |= hdac_pcie_snoop[i].enable; 3692 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3693 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3694 if ((v & hdac_pcie_snoop[i].enable) != 3695 hdac_pcie_snoop[i].enable) { 3696 HDA_BOOTVERBOSE( 3697 device_printf(dev, 3698 "WARNING: Failed to enable PCIe " 3699 "snoop!\n"); 3700 ); 3701 #if defined(__i386__) || defined(__amd64__) 3702 sc->nocache = 1; 3703 #endif 3704 } 3705 break; 3706 } 3707 #if defined(__i386__) || defined(__amd64__) 3708 } 3709 #endif 3710 3711 HDA_BOOTVERBOSE( 3712 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3713 (sc->nocache == 0) ? "PCIe snoop" : "Uncacheable", vendor); 3714 ); 3715 3716 /* Allocate resources */ 3717 result = hdac_mem_alloc(sc); 3718 if (result != 0) 3719 goto hdac_attach_fail; 3720 result = hdac_irq_alloc(sc); 3721 if (result != 0) 3722 goto hdac_attach_fail; 3723 3724 /* Get Capabilities */ 3725 result = hdac_get_capabilities(sc); 3726 if (result != 0) 3727 goto hdac_attach_fail; 3728 3729 /* Allocate CORB and RIRB dma memory */ 3730 result = hdac_dma_alloc(sc, &sc->corb_dma, 3731 sc->corb_size * sizeof(uint32_t)); 3732 if (result != 0) 3733 goto hdac_attach_fail; 3734 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3735 sc->rirb_size * sizeof(struct hdac_rirb)); 3736 if (result != 0) 3737 goto hdac_attach_fail; 3738 3739 /* Quiesce everything */ 3740 hdac_reset(sc); 3741 3742 /* Initialize the CORB and RIRB */ 3743 hdac_corb_init(sc); 3744 hdac_rirb_init(sc); 3745 3746 /* Defer remaining of initialization until interrupts are enabled */ 3747 sc->intrhook.ich_func = hdac_attach2; 3748 sc->intrhook.ich_arg = (void *)sc; 3749 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3750 sc->intrhook.ich_func = NULL; 3751 hdac_attach2((void *)sc); 3752 } 3753 3754 return (0); 3755 3756 hdac_attach_fail: 3757 hdac_irq_free(sc); 3758 hdac_dma_free(sc, &sc->rirb_dma); 3759 hdac_dma_free(sc, &sc->corb_dma); 3760 hdac_mem_free(sc); 3761 snd_mtxfree(sc->lock); 3762 free(sc, M_DEVBUF); 3763 3764 return (ENXIO); 3765 } 3766 3767 static void 3768 hdac_audio_parse(struct hdac_devinfo *devinfo) 3769 { 3770 struct hdac_softc *sc = devinfo->codec->sc; 3771 struct hdac_widget *w; 3772 uint32_t res; 3773 int i; 3774 nid_t cad, nid; 3775 3776 cad = devinfo->codec->cad; 3777 nid = devinfo->nid; 3778 3779 hdac_command(sc, 3780 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3781 3782 DELAY(100); 3783 3784 res = hdac_command(sc, 3785 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3786 3787 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3788 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3789 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3790 3791 res = hdac_command(sc, 3792 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3793 devinfo->function.audio.gpio = res; 3794 3795 HDA_BOOTVERBOSE( 3796 device_printf(sc->dev, " Vendor: 0x%08x\n", 3797 devinfo->vendor_id); 3798 device_printf(sc->dev, " Device: 0x%08x\n", 3799 devinfo->device_id); 3800 device_printf(sc->dev, " Revision: 0x%08x\n", 3801 devinfo->revision_id); 3802 device_printf(sc->dev, " Stepping: 0x%08x\n", 3803 devinfo->stepping_id); 3804 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3805 sc->pci_subvendor); 3806 device_printf(sc->dev, " Nodes: start=%d " 3807 "endnode=%d total=%d\n", 3808 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3809 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3810 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3811 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3812 sc->num_iss, sc->num_oss, sc->num_bss); 3813 device_printf(sc->dev, " GPIO: 0x%08x\n", 3814 devinfo->function.audio.gpio); 3815 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3816 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3817 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3818 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3819 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3820 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3821 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3822 ); 3823 3824 res = hdac_command(sc, 3825 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3826 cad); 3827 devinfo->function.audio.supp_stream_formats = res; 3828 3829 res = hdac_command(sc, 3830 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3831 cad); 3832 devinfo->function.audio.supp_pcm_size_rate = res; 3833 3834 res = hdac_command(sc, 3835 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3836 cad); 3837 devinfo->function.audio.outamp_cap = res; 3838 3839 res = hdac_command(sc, 3840 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3841 cad); 3842 devinfo->function.audio.inamp_cap = res; 3843 3844 if (devinfo->nodecnt > 0) 3845 devinfo->widget = (struct hdac_widget *)malloc( 3846 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3847 M_NOWAIT | M_ZERO); 3848 else 3849 devinfo->widget = NULL; 3850 3851 if (devinfo->widget == NULL) { 3852 device_printf(sc->dev, "unable to allocate widgets!\n"); 3853 devinfo->endnode = devinfo->startnode; 3854 devinfo->nodecnt = 0; 3855 return; 3856 } 3857 3858 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3859 w = hdac_widget_get(devinfo, i); 3860 if (w == NULL) 3861 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3862 else { 3863 w->devinfo = devinfo; 3864 w->nid = i; 3865 w->enable = 1; 3866 w->selconn = -1; 3867 w->pflags = 0; 3868 w->ctlflags = 0; 3869 w->param.eapdbtl = HDAC_INVALID; 3870 hdac_widget_parse(w); 3871 } 3872 } 3873 } 3874 3875 static void 3876 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3877 { 3878 struct hdac_softc *sc = devinfo->codec->sc; 3879 struct hdac_audio_ctl *ctls; 3880 struct hdac_widget *w, *cw; 3881 int i, j, cnt, max, ocap, icap; 3882 int mute, offset, step, size; 3883 3884 /* XXX This is redundant */ 3885 max = 0; 3886 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3887 w = hdac_widget_get(devinfo, i); 3888 if (w == NULL || w->enable == 0) 3889 continue; 3890 if (w->param.outamp_cap != 0) 3891 max++; 3892 if (w->param.inamp_cap != 0) { 3893 switch (w->type) { 3894 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3895 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3896 for (j = 0; j < w->nconns; j++) { 3897 cw = hdac_widget_get(devinfo, 3898 w->conns[j]); 3899 if (cw == NULL || cw->enable == 0) 3900 continue; 3901 max++; 3902 } 3903 break; 3904 default: 3905 max++; 3906 break; 3907 } 3908 } 3909 } 3910 3911 devinfo->function.audio.ctlcnt = max; 3912 3913 if (max < 1) 3914 return; 3915 3916 ctls = (struct hdac_audio_ctl *)malloc( 3917 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3918 3919 if (ctls == NULL) { 3920 /* Blekh! */ 3921 device_printf(sc->dev, "unable to allocate ctls!\n"); 3922 devinfo->function.audio.ctlcnt = 0; 3923 return; 3924 } 3925 3926 cnt = 0; 3927 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3928 if (cnt >= max) { 3929 device_printf(sc->dev, "%s: Ctl overflow!\n", 3930 __func__); 3931 break; 3932 } 3933 w = hdac_widget_get(devinfo, i); 3934 if (w == NULL || w->enable == 0) 3935 continue; 3936 ocap = w->param.outamp_cap; 3937 icap = w->param.inamp_cap; 3938 if (ocap != 0) { 3939 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3940 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3941 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3942 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3943 /*if (offset > step) { 3944 HDA_BOOTVERBOSE( 3945 device_printf(sc->dev, 3946 "HDA_DEBUG: BUGGY outamp: nid=%d " 3947 "[offset=%d > step=%d]\n", 3948 w->nid, offset, step); 3949 ); 3950 offset = step; 3951 }*/ 3952 ctls[cnt].enable = 1; 3953 ctls[cnt].widget = w; 3954 ctls[cnt].mute = mute; 3955 ctls[cnt].step = step; 3956 ctls[cnt].size = size; 3957 ctls[cnt].offset = offset; 3958 ctls[cnt].left = offset; 3959 ctls[cnt].right = offset; 3960 ctls[cnt++].dir = HDA_CTL_OUT; 3961 } 3962 3963 if (icap != 0) { 3964 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3965 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3966 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3967 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3968 /*if (offset > step) { 3969 HDA_BOOTVERBOSE( 3970 device_printf(sc->dev, 3971 "HDA_DEBUG: BUGGY inamp: nid=%d " 3972 "[offset=%d > step=%d]\n", 3973 w->nid, offset, step); 3974 ); 3975 offset = step; 3976 }*/ 3977 switch (w->type) { 3978 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3979 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3980 for (j = 0; j < w->nconns; j++) { 3981 if (cnt >= max) { 3982 device_printf(sc->dev, 3983 "%s: Ctl overflow!\n", 3984 __func__); 3985 break; 3986 } 3987 cw = hdac_widget_get(devinfo, 3988 w->conns[j]); 3989 if (cw == NULL || cw->enable == 0) 3990 continue; 3991 ctls[cnt].enable = 1; 3992 ctls[cnt].widget = w; 3993 ctls[cnt].childwidget = cw; 3994 ctls[cnt].index = j; 3995 ctls[cnt].mute = mute; 3996 ctls[cnt].step = step; 3997 ctls[cnt].size = size; 3998 ctls[cnt].offset = offset; 3999 ctls[cnt].left = offset; 4000 ctls[cnt].right = offset; 4001 ctls[cnt++].dir = HDA_CTL_IN; 4002 } 4003 break; 4004 default: 4005 if (cnt >= max) { 4006 device_printf(sc->dev, 4007 "%s: Ctl overflow!\n", 4008 __func__); 4009 break; 4010 } 4011 ctls[cnt].enable = 1; 4012 ctls[cnt].widget = w; 4013 ctls[cnt].mute = mute; 4014 ctls[cnt].step = step; 4015 ctls[cnt].size = size; 4016 ctls[cnt].offset = offset; 4017 ctls[cnt].left = offset; 4018 ctls[cnt].right = offset; 4019 ctls[cnt++].dir = HDA_CTL_IN; 4020 break; 4021 } 4022 } 4023 } 4024 4025 devinfo->function.audio.ctl = ctls; 4026 } 4027 4028 static const struct { 4029 uint32_t model; 4030 uint32_t id; 4031 uint32_t set, unset; 4032 } hdac_quirks[] = { 4033 /* 4034 * XXX Force stereo quirk. Monoural recording / playback 4035 * on few codecs (especially ALC880) seems broken or 4036 * perhaps unsupported. 4037 */ 4038 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4039 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4040 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4041 HDA_QUIRK_GPIO0, 0 }, 4042 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4043 HDA_QUIRK_GPIO0, 0 }, 4044 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4045 HDA_QUIRK_GPIO0, 0 }, 4046 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4047 HDA_QUIRK_GPIO0, 0 }, 4048 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4049 HDA_QUIRK_GPIO0, 0 }, 4050 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4051 HDA_QUIRK_EAPDINV, 0 }, 4052 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4053 HDA_QUIRK_EAPDINV, 0 }, 4054 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4055 HDA_QUIRK_OVREF, 0 }, 4056 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4057 HDA_QUIRK_OVREF, 0 }, 4058 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4059 HDA_QUIRK_OVREF, 0 }, 4060 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4061 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4062 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4063 HDA_QUIRK_GPIO1, 0 }, 4064 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4065 HDA_QUIRK_EAPDINV, 0 }, 4066 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4067 HDA_QUIRK_EAPDINV, 0 }, 4068 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4069 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4070 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4071 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4072 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4073 0, HDA_QUIRK_FORCESTEREO }, 4074 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4075 HDA_QUIRK_SOFTPCMVOL, 0 } 4076 }; 4077 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4078 4079 static void 4080 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4081 { 4082 struct hdac_widget *w; 4083 struct hdac_audio_ctl *ctl; 4084 uint32_t id, subvendor; 4085 int i; 4086 4087 id = hdac_codec_id(devinfo); 4088 subvendor = devinfo->codec->sc->pci_subvendor; 4089 4090 /* 4091 * Quirks 4092 */ 4093 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4094 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4095 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4096 continue; 4097 if (hdac_quirks[i].set != 0) 4098 devinfo->function.audio.quirks |= 4099 hdac_quirks[i].set; 4100 if (hdac_quirks[i].unset != 0) 4101 devinfo->function.audio.quirks &= 4102 ~(hdac_quirks[i].unset); 4103 } 4104 4105 switch (id) { 4106 case HDA_CODEC_ALC260: 4107 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4108 w = hdac_widget_get(devinfo, i); 4109 if (w == NULL || w->enable == 0) 4110 continue; 4111 if (w->type != 4112 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4113 continue; 4114 if (w->nid != 5) 4115 w->enable = 0; 4116 } 4117 if (subvendor == HP_XW4300_SUBVENDOR) { 4118 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4119 if (ctl != NULL && ctl->widget != NULL) { 4120 ctl->ossmask = SOUND_MASK_SPEAKER; 4121 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4122 } 4123 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4124 if (ctl != NULL && ctl->widget != NULL) { 4125 ctl->ossmask = SOUND_MASK_SPEAKER; 4126 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4127 } 4128 } else if (subvendor == HP_3010_SUBVENDOR) { 4129 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4130 if (ctl != NULL && ctl->widget != NULL) { 4131 ctl->ossmask = SOUND_MASK_SPEAKER; 4132 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4133 } 4134 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4135 if (ctl != NULL && ctl->widget != NULL) { 4136 ctl->ossmask = SOUND_MASK_SPEAKER; 4137 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4138 } 4139 } 4140 break; 4141 case HDA_CODEC_ALC861: 4142 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4143 if (ctl != NULL) 4144 ctl->muted = HDA_AMP_MUTE_ALL; 4145 break; 4146 case HDA_CODEC_ALC880: 4147 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4148 w = hdac_widget_get(devinfo, i); 4149 if (w == NULL || w->enable == 0) 4150 continue; 4151 if (w->type == 4152 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4153 w->nid != 9 && w->nid != 29) { 4154 w->enable = 0; 4155 } else if (w->type != 4156 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4157 w->nid == 29) { 4158 w->type = 4159 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4160 w->param.widget_cap &= 4161 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4162 w->param.widget_cap |= 4163 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4164 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4165 strlcpy(w->name, "beep widget", sizeof(w->name)); 4166 } 4167 } 4168 break; 4169 case HDA_CODEC_ALC883: 4170 /* 4171 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4172 * Clear vref cap for jack connectivity. 4173 */ 4174 w = hdac_widget_get(devinfo, 24); 4175 if (w != NULL && w->enable != 0 && w->type == 4176 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4177 (w->wclass.pin.config & 4178 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4179 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4180 w->wclass.pin.cap &= ~( 4181 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4182 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4183 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4184 w = hdac_widget_get(devinfo, 25); 4185 if (w != NULL && w->enable != 0 && w->type == 4186 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4187 (w->wclass.pin.config & 4188 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4189 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4190 w->wclass.pin.cap &= ~( 4191 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4192 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4193 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4194 /* 4195 * nid: 26 = Line-in, leave it alone. 4196 */ 4197 break; 4198 case HDA_CODEC_AD1981HD: 4199 w = hdac_widget_get(devinfo, 11); 4200 if (w != NULL && w->enable != 0 && w->nconns > 3) 4201 w->selconn = 3; 4202 if (subvendor == IBM_M52_SUBVENDOR) { 4203 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4204 if (ctl != NULL) 4205 ctl->ossmask = SOUND_MASK_SPEAKER; 4206 } 4207 break; 4208 case HDA_CODEC_AD1986A: 4209 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4210 w = hdac_widget_get(devinfo, i); 4211 if (w == NULL || w->enable == 0) 4212 continue; 4213 if (w->type != 4214 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4215 continue; 4216 if (w->nid != 3) 4217 w->enable = 0; 4218 } 4219 if (subvendor == ASUS_M2NPVMX_SUBVENDOR) { 4220 /* nid 28 is mic, nid 29 is line-in */ 4221 w = hdac_widget_get(devinfo, 15); 4222 if (w != NULL) 4223 w->selconn = 2; 4224 w = hdac_widget_get(devinfo, 16); 4225 if (w != NULL) 4226 w->selconn = 1; 4227 } 4228 break; 4229 case HDA_CODEC_AD1988: 4230 /*w = hdac_widget_get(devinfo, 12); 4231 if (w != NULL) { 4232 w->selconn = 1; 4233 w->pflags |= HDA_ADC_LOCKED; 4234 } 4235 w = hdac_widget_get(devinfo, 13); 4236 if (w != NULL) { 4237 w->selconn = 4; 4238 w->pflags |= HDA_ADC_LOCKED; 4239 } 4240 w = hdac_widget_get(devinfo, 14); 4241 if (w != NULL) { 4242 w->selconn = 2; 4243 w->pflags |= HDA_ADC_LOCKED; 4244 }*/ 4245 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4246 if (ctl != NULL) { 4247 ctl->ossmask = SOUND_MASK_IGAIN; 4248 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4249 } 4250 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4251 if (ctl != NULL) { 4252 ctl->ossmask = SOUND_MASK_IGAIN; 4253 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4254 } 4255 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4256 if (ctl != NULL) { 4257 ctl->ossmask = SOUND_MASK_IGAIN; 4258 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4259 } 4260 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4261 if (ctl != NULL) { 4262 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4263 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4264 } 4265 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4266 if (ctl != NULL) { 4267 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4268 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4269 } 4270 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4271 if (ctl != NULL) { 4272 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4273 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4274 } 4275 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4276 if (ctl != NULL) { 4277 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4278 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4279 } 4280 break; 4281 case HDA_CODEC_STAC9221: 4282 /* 4283 * Dell XPS M1210 need all DACs for each output jacks 4284 */ 4285 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4286 break; 4287 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4288 w = hdac_widget_get(devinfo, i); 4289 if (w == NULL || w->enable == 0) 4290 continue; 4291 if (w->type != 4292 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4293 continue; 4294 if (w->nid != 2) 4295 w->enable = 0; 4296 } 4297 break; 4298 case HDA_CODEC_STAC9221D: 4299 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4300 w = hdac_widget_get(devinfo, i); 4301 if (w == NULL || w->enable == 0) 4302 continue; 4303 if (w->type == 4304 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4305 w->nid != 6) 4306 w->enable = 0; 4307 4308 } 4309 break; 4310 case HDA_CODEC_STAC9227: 4311 w = hdac_widget_get(devinfo, 8); 4312 if (w != NULL) 4313 w->enable = 0; 4314 w = hdac_widget_get(devinfo, 9); 4315 if (w != NULL) 4316 w->enable = 0; 4317 break; 4318 case HDA_CODEC_CXWAIKIKI: 4319 if (subvendor == HP_DV5000_SUBVENDOR) { 4320 w = hdac_widget_get(devinfo, 27); 4321 if (w != NULL) 4322 w->enable = 0; 4323 } 4324 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4325 if (ctl != NULL) 4326 ctl->ossmask = SOUND_MASK_SKIP; 4327 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4328 if (ctl != NULL && ctl->childwidget != NULL && 4329 ctl->childwidget->enable != 0) { 4330 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4331 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4332 } 4333 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4334 if (ctl != NULL && ctl->childwidget != NULL && 4335 ctl->childwidget->enable != 0) { 4336 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4337 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4338 } 4339 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4340 if (ctl != NULL && ctl->childwidget != NULL && 4341 ctl->childwidget->enable != 0) { 4342 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4343 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4344 } 4345 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4346 if (ctl != NULL) { 4347 ctl->ossmask = SOUND_MASK_SKIP; 4348 /* XXX mixer \=rec mic broken.. why?!? */ 4349 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4350 } 4351 break; 4352 default: 4353 break; 4354 } 4355 } 4356 4357 static int 4358 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4359 { 4360 int *dev = &devinfo->function.audio.ossidx; 4361 4362 while (*dev < SOUND_MIXER_NRDEVICES) { 4363 switch (*dev) { 4364 case SOUND_MIXER_VOLUME: 4365 case SOUND_MIXER_BASS: 4366 case SOUND_MIXER_TREBLE: 4367 case SOUND_MIXER_PCM: 4368 case SOUND_MIXER_SPEAKER: 4369 case SOUND_MIXER_LINE: 4370 case SOUND_MIXER_MIC: 4371 case SOUND_MIXER_CD: 4372 case SOUND_MIXER_RECLEV: 4373 case SOUND_MIXER_IGAIN: 4374 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4375 (*dev)++; 4376 break; 4377 default: 4378 return (*dev)++; 4379 break; 4380 } 4381 } 4382 4383 return (-1); 4384 } 4385 4386 static int 4387 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4388 { 4389 struct hdac_widget *w; 4390 int i, ret = 0; 4391 4392 if (depth > HDA_PARSE_MAXDEPTH) 4393 return (0); 4394 w = hdac_widget_get(devinfo, nid); 4395 if (w == NULL || w->enable == 0) 4396 return (0); 4397 switch (w->type) { 4398 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4399 w->pflags |= HDA_DAC_PATH; 4400 ret = 1; 4401 break; 4402 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4403 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4404 for (i = 0; i < w->nconns; i++) { 4405 if (hdac_widget_find_dac_path(devinfo, 4406 w->conns[i], depth + 1) != 0) { 4407 if (w->selconn == -1) 4408 w->selconn = i; 4409 ret = 1; 4410 w->pflags |= HDA_DAC_PATH; 4411 } 4412 } 4413 break; 4414 default: 4415 break; 4416 } 4417 return (ret); 4418 } 4419 4420 static int 4421 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4422 { 4423 struct hdac_widget *w; 4424 int i, conndev, ret = 0; 4425 4426 if (depth > HDA_PARSE_MAXDEPTH) 4427 return (0); 4428 w = hdac_widget_get(devinfo, nid); 4429 if (w == NULL || w->enable == 0) 4430 return (0); 4431 switch (w->type) { 4432 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4433 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4434 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4435 for (i = 0; i < w->nconns; i++) { 4436 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4437 depth + 1) != 0) { 4438 if (w->selconn == -1) 4439 w->selconn = i; 4440 w->pflags |= HDA_ADC_PATH; 4441 ret = 1; 4442 } 4443 } 4444 break; 4445 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4446 conndev = w->wclass.pin.config & 4447 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4448 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4449 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4450 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4451 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4452 w->pflags |= HDA_ADC_PATH; 4453 ret = 1; 4454 } 4455 break; 4456 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4457 if (w->pflags & HDA_DAC_PATH) { 4458 w->pflags |= HDA_ADC_PATH; 4459 ret = 1; 4460 } 4461 break;*/ 4462 default: 4463 break; 4464 } 4465 return (ret); 4466 } 4467 4468 static uint32_t 4469 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4470 nid_t nid, nid_t pnid, int index, int depth) 4471 { 4472 struct hdac_widget *w, *pw; 4473 struct hdac_audio_ctl *ctl; 4474 uint32_t fl = 0; 4475 int i, ossdev, conndev, strategy; 4476 4477 if (depth > HDA_PARSE_MAXDEPTH) 4478 return (0); 4479 4480 w = hdac_widget_get(devinfo, nid); 4481 if (w == NULL || w->enable == 0) 4482 return (0); 4483 4484 pw = hdac_widget_get(devinfo, pnid); 4485 strategy = devinfo->function.audio.parsing_strategy; 4486 4487 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4488 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4489 for (i = 0; i < w->nconns; i++) { 4490 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4491 w->nid, i, depth + 1); 4492 } 4493 w->ctlflags |= fl; 4494 return (fl); 4495 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4496 (w->pflags & HDA_DAC_PATH)) { 4497 i = 0; 4498 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4499 if (ctl->enable == 0 || ctl->widget == NULL) 4500 continue; 4501 /* XXX This should be compressed! */ 4502 if (((ctl->widget->nid == w->nid) || 4503 (ctl->widget->nid == pnid && ctl->index == index && 4504 (ctl->dir & HDA_CTL_IN)) || 4505 (ctl->widget->nid == pnid && pw != NULL && 4506 pw->type == 4507 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4508 (pw->nconns < 2 || pw->selconn == index || 4509 pw->selconn == -1) && 4510 (ctl->dir & HDA_CTL_OUT)) || 4511 (strategy == HDA_PARSE_DIRECT && 4512 ctl->widget->nid == w->nid)) && 4513 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4514 /*if (pw != NULL && pw->selconn == -1) 4515 pw->selconn = index; 4516 fl |= SOUND_MASK_VOLUME; 4517 fl |= SOUND_MASK_PCM; 4518 ctl->ossmask |= SOUND_MASK_VOLUME; 4519 ctl->ossmask |= SOUND_MASK_PCM; 4520 ctl->ossdev = SOUND_MIXER_PCM;*/ 4521 if (!(w->ctlflags & SOUND_MASK_PCM) || 4522 (pw != NULL && 4523 !(pw->ctlflags & SOUND_MASK_PCM))) { 4524 fl |= SOUND_MASK_VOLUME; 4525 fl |= SOUND_MASK_PCM; 4526 ctl->ossmask |= SOUND_MASK_VOLUME; 4527 ctl->ossmask |= SOUND_MASK_PCM; 4528 ctl->ossdev = SOUND_MIXER_PCM; 4529 w->ctlflags |= SOUND_MASK_VOLUME; 4530 w->ctlflags |= SOUND_MASK_PCM; 4531 if (pw != NULL) { 4532 if (pw->selconn == -1) 4533 pw->selconn = index; 4534 pw->ctlflags |= 4535 SOUND_MASK_VOLUME; 4536 pw->ctlflags |= 4537 SOUND_MASK_PCM; 4538 } 4539 } 4540 } 4541 } 4542 w->ctlflags |= fl; 4543 return (fl); 4544 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4545 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4546 (w->pflags & HDA_ADC_PATH)) { 4547 conndev = w->wclass.pin.config & 4548 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4549 i = 0; 4550 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4551 if (ctl->enable == 0 || ctl->widget == NULL) 4552 continue; 4553 /* XXX This should be compressed! */ 4554 if (((ctl->widget->nid == pnid && ctl->index == index && 4555 (ctl->dir & HDA_CTL_IN)) || 4556 (ctl->widget->nid == pnid && pw != NULL && 4557 pw->type == 4558 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4559 (pw->nconns < 2 || pw->selconn == index || 4560 pw->selconn == -1) && 4561 (ctl->dir & HDA_CTL_OUT)) || 4562 (strategy == HDA_PARSE_DIRECT && 4563 ctl->widget->nid == w->nid)) && 4564 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4565 if (pw != NULL && pw->selconn == -1) 4566 pw->selconn = index; 4567 ossdev = 0; 4568 switch (conndev) { 4569 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4570 ossdev = SOUND_MIXER_MIC; 4571 break; 4572 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4573 ossdev = SOUND_MIXER_LINE; 4574 break; 4575 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4576 ossdev = SOUND_MIXER_CD; 4577 break; 4578 default: 4579 ossdev = 4580 hdac_audio_ctl_ossmixer_getnextdev( 4581 devinfo); 4582 if (ossdev < 0) 4583 ossdev = 0; 4584 break; 4585 } 4586 if (strategy == HDA_PARSE_MIXER) { 4587 fl |= SOUND_MASK_VOLUME; 4588 ctl->ossmask |= SOUND_MASK_VOLUME; 4589 } 4590 fl |= 1 << ossdev; 4591 ctl->ossmask |= 1 << ossdev; 4592 ctl->ossdev = ossdev; 4593 } 4594 } 4595 w->ctlflags |= fl; 4596 return (fl); 4597 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4598 i = 0; 4599 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4600 if (ctl->enable == 0 || ctl->widget == NULL) 4601 continue; 4602 /* XXX This should be compressed! */ 4603 if (((ctl->widget->nid == pnid && ctl->index == index && 4604 (ctl->dir & HDA_CTL_IN)) || 4605 (ctl->widget->nid == pnid && pw != NULL && 4606 pw->type == 4607 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4608 (pw->nconns < 2 || pw->selconn == index || 4609 pw->selconn == -1) && 4610 (ctl->dir & HDA_CTL_OUT)) || 4611 (strategy == HDA_PARSE_DIRECT && 4612 ctl->widget->nid == w->nid)) && 4613 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4614 if (pw != NULL && pw->selconn == -1) 4615 pw->selconn = index; 4616 fl |= SOUND_MASK_VOLUME; 4617 fl |= SOUND_MASK_SPEAKER; 4618 ctl->ossmask |= SOUND_MASK_VOLUME; 4619 ctl->ossmask |= SOUND_MASK_SPEAKER; 4620 ctl->ossdev = SOUND_MIXER_SPEAKER; 4621 } 4622 } 4623 w->ctlflags |= fl; 4624 return (fl); 4625 } 4626 return (0); 4627 } 4628 4629 static uint32_t 4630 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4631 { 4632 struct hdac_widget *w, *cw; 4633 struct hdac_audio_ctl *ctl; 4634 uint32_t fl; 4635 int i; 4636 4637 if (depth > HDA_PARSE_MAXDEPTH) 4638 return (0); 4639 4640 w = hdac_widget_get(devinfo, nid); 4641 if (w == NULL || w->enable == 0) 4642 return (0); 4643 /*if (!(w->pflags & HDA_ADC_PATH)) 4644 return (0); 4645 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4646 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4647 return (0);*/ 4648 i = 0; 4649 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4650 if (ctl->enable == 0 || ctl->widget == NULL) 4651 continue; 4652 if (ctl->widget->nid == nid) { 4653 ctl->ossmask |= SOUND_MASK_RECLEV; 4654 w->ctlflags |= SOUND_MASK_RECLEV; 4655 return (SOUND_MASK_RECLEV); 4656 } 4657 } 4658 for (i = 0; i < w->nconns; i++) { 4659 cw = hdac_widget_get(devinfo, w->conns[i]); 4660 if (cw == NULL || cw->enable == 0) 4661 continue; 4662 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4663 continue; 4664 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4665 if (fl != 0) { 4666 cw->ctlflags |= fl; 4667 w->ctlflags |= fl; 4668 return (fl); 4669 } 4670 } 4671 return (0); 4672 } 4673 4674 static int 4675 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4676 { 4677 struct hdac_widget *w, *cw; 4678 int i, child = 0; 4679 4680 if (depth > HDA_PARSE_MAXDEPTH) 4681 return (0); 4682 4683 w = hdac_widget_get(devinfo, nid); 4684 if (w == NULL || w->enable == 0) 4685 return (0); 4686 /*if (!(w->pflags & HDA_ADC_PATH)) 4687 return (0); 4688 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4689 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4690 return (0);*/ 4691 /* XXX weak! */ 4692 for (i = 0; i < w->nconns; i++) { 4693 cw = hdac_widget_get(devinfo, w->conns[i]); 4694 if (cw == NULL) 4695 continue; 4696 if (++child > 1) { 4697 w->pflags |= HDA_ADC_RECSEL; 4698 return (1); 4699 } 4700 } 4701 for (i = 0; i < w->nconns; i++) { 4702 if (hdac_audio_ctl_recsel_build(devinfo, 4703 w->conns[i], depth + 1) != 0) 4704 return (1); 4705 } 4706 return (0); 4707 } 4708 4709 static int 4710 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4711 { 4712 struct hdac_widget *w, *cw; 4713 int i, j, conndev, found_dac = 0; 4714 int strategy; 4715 4716 strategy = devinfo->function.audio.parsing_strategy; 4717 4718 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4719 w = hdac_widget_get(devinfo, i); 4720 if (w == NULL || w->enable == 0) 4721 continue; 4722 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4723 continue; 4724 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4725 continue; 4726 conndev = w->wclass.pin.config & 4727 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4728 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4729 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4730 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4731 continue; 4732 for (j = 0; j < w->nconns; j++) { 4733 cw = hdac_widget_get(devinfo, w->conns[j]); 4734 if (cw == NULL || cw->enable == 0) 4735 continue; 4736 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4737 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4738 cw->type == 4739 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4740 continue; 4741 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4742 != 0) { 4743 if (w->selconn == -1) 4744 w->selconn = j; 4745 w->pflags |= HDA_DAC_PATH; 4746 found_dac++; 4747 } 4748 } 4749 } 4750 4751 return (found_dac); 4752 } 4753 4754 static void 4755 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4756 { 4757 struct hdac_widget *w; 4758 struct hdac_audio_ctl *ctl; 4759 int i, j, dacs, strategy; 4760 4761 /* Construct DAC path */ 4762 strategy = HDA_PARSE_MIXER; 4763 devinfo->function.audio.parsing_strategy = strategy; 4764 HDA_BOOTVERBOSE( 4765 device_printf(devinfo->codec->sc->dev, 4766 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4767 HDA_WIDGET_PARSER_REV); 4768 ); 4769 dacs = hdac_audio_build_tree_strategy(devinfo); 4770 if (dacs == 0) { 4771 HDA_BOOTVERBOSE( 4772 device_printf(devinfo->codec->sc->dev, 4773 "HDA_DEBUG: HWiP: 0 DAC path found! " 4774 "Retrying parser " 4775 "using HDA_PARSE_DIRECT strategy.\n"); 4776 ); 4777 strategy = HDA_PARSE_DIRECT; 4778 devinfo->function.audio.parsing_strategy = strategy; 4779 dacs = hdac_audio_build_tree_strategy(devinfo); 4780 } 4781 4782 HDA_BOOTVERBOSE( 4783 device_printf(devinfo->codec->sc->dev, 4784 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4785 "strategy.\n", 4786 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4787 ); 4788 4789 /* Construct ADC path */ 4790 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4791 w = hdac_widget_get(devinfo, i); 4792 if (w == NULL || w->enable == 0) 4793 continue; 4794 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4795 continue; 4796 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4797 } 4798 4799 /* Output mixers */ 4800 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4801 w = hdac_widget_get(devinfo, i); 4802 if (w == NULL || w->enable == 0) 4803 continue; 4804 if ((strategy == HDA_PARSE_MIXER && 4805 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4806 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4807 && (w->pflags & HDA_DAC_PATH)) || 4808 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4809 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4810 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4811 w->nid, devinfo->startnode - 1, 0, 0); 4812 } else if (w->type == 4813 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4814 j = 0; 4815 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4816 NULL) { 4817 if (ctl->enable == 0 || ctl->widget == NULL) 4818 continue; 4819 if (ctl->widget->nid != w->nid) 4820 continue; 4821 ctl->ossmask |= SOUND_MASK_VOLUME; 4822 ctl->ossmask |= SOUND_MASK_SPEAKER; 4823 ctl->ossdev = SOUND_MIXER_SPEAKER; 4824 w->ctlflags |= SOUND_MASK_VOLUME; 4825 w->ctlflags |= SOUND_MASK_SPEAKER; 4826 } 4827 } 4828 } 4829 4830 /* Input mixers (rec) */ 4831 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4832 w = hdac_widget_get(devinfo, i); 4833 if (w == NULL || w->enable == 0) 4834 continue; 4835 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4836 w->pflags & HDA_ADC_PATH)) 4837 continue; 4838 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4839 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4840 } 4841 } 4842 4843 #define HDA_COMMIT_CONN (1 << 0) 4844 #define HDA_COMMIT_CTRL (1 << 1) 4845 #define HDA_COMMIT_EAPD (1 << 2) 4846 #define HDA_COMMIT_GPIO (1 << 3) 4847 #define HDA_COMMIT_MISC (1 << 4) 4848 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4849 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 4850 4851 static void 4852 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4853 { 4854 struct hdac_softc *sc = devinfo->codec->sc; 4855 struct hdac_widget *w; 4856 nid_t cad; 4857 int i; 4858 4859 if (!(cfl & HDA_COMMIT_ALL)) 4860 return; 4861 4862 cad = devinfo->codec->cad; 4863 4864 if ((cfl & HDA_COMMIT_MISC)) { 4865 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4866 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4867 0x7e7, 0), cad); 4868 } 4869 4870 if (cfl & HDA_COMMIT_GPIO) { 4871 uint32_t gdata, gmask, gdir; 4872 int commitgpio, numgpio; 4873 4874 gdata = 0; 4875 gmask = 0; 4876 gdir = 0; 4877 commitgpio = 0; 4878 4879 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 4880 devinfo->function.audio.gpio); 4881 4882 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4883 commitgpio = (numgpio > 0) ? 1 : 0; 4884 else { 4885 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 4886 if (!(devinfo->function.audio.quirks & 4887 (1 << i))) 4888 continue; 4889 if (commitgpio == 0) { 4890 commitgpio = 1; 4891 HDA_BOOTVERBOSE( 4892 gdata = hdac_command(sc, 4893 HDA_CMD_GET_GPIO_DATA(cad, 4894 devinfo->nid), cad); 4895 gmask = hdac_command(sc, 4896 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4897 devinfo->nid), cad); 4898 gdir = hdac_command(sc, 4899 HDA_CMD_GET_GPIO_DIRECTION(cad, 4900 devinfo->nid), cad); 4901 device_printf(sc->dev, 4902 "GPIO init: data=0x%08x " 4903 "mask=0x%08x dir=0x%08x\n", 4904 gdata, gmask, gdir); 4905 gdata = 0; 4906 gmask = 0; 4907 gdir = 0; 4908 ); 4909 } 4910 gdata |= 1 << i; 4911 gmask |= 1 << i; 4912 gdir |= 1 << i; 4913 } 4914 } 4915 4916 if (commitgpio != 0) { 4917 HDA_BOOTVERBOSE( 4918 device_printf(sc->dev, 4919 "GPIO commit: data=0x%08x mask=0x%08x " 4920 "dir=0x%08x\n", 4921 gdata, gmask, gdir); 4922 ); 4923 hdac_command(sc, 4924 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4925 gmask), cad); 4926 hdac_command(sc, 4927 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4928 gdir), cad); 4929 hdac_command(sc, 4930 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4931 gdata), cad); 4932 } 4933 } 4934 4935 for (i = 0; i < devinfo->nodecnt; i++) { 4936 w = &devinfo->widget[i]; 4937 if (w == NULL || w->enable == 0) 4938 continue; 4939 if (cfl & HDA_COMMIT_CONN) { 4940 if (w->selconn == -1) 4941 w->selconn = 0; 4942 if (w->nconns > 0) 4943 hdac_widget_connection_select(w, w->selconn); 4944 } 4945 if ((cfl & HDA_COMMIT_CTRL) && 4946 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4947 uint32_t pincap; 4948 4949 pincap = w->wclass.pin.cap; 4950 4951 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4952 (HDA_DAC_PATH | HDA_ADC_PATH)) 4953 device_printf(sc->dev, "WARNING: node %d " 4954 "participate both for DAC/ADC!\n", w->nid); 4955 if (w->pflags & HDA_DAC_PATH) { 4956 w->wclass.pin.ctrl &= 4957 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4958 if ((w->wclass.pin.config & 4959 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4960 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4961 w->wclass.pin.ctrl &= 4962 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4963 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 4964 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4965 w->wclass.pin.ctrl |= 4966 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4967 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 4968 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 4969 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4970 w->wclass.pin.ctrl |= 4971 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4972 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 4973 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 4974 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4975 w->wclass.pin.ctrl |= 4976 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4977 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 4978 } else if (w->pflags & HDA_ADC_PATH) { 4979 w->wclass.pin.ctrl &= 4980 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4981 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4982 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 4983 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4984 w->wclass.pin.ctrl |= 4985 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4986 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 4987 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 4988 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4989 w->wclass.pin.ctrl |= 4990 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4991 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 4992 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 4993 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4994 w->wclass.pin.ctrl |= 4995 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4996 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 4997 } else 4998 w->wclass.pin.ctrl &= ~( 4999 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5000 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5001 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5002 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5003 hdac_command(sc, 5004 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5005 w->wclass.pin.ctrl), cad); 5006 } 5007 if ((cfl & HDA_COMMIT_EAPD) && 5008 w->param.eapdbtl != HDAC_INVALID) { 5009 uint32_t val; 5010 5011 val = w->param.eapdbtl; 5012 if (devinfo->function.audio.quirks & 5013 HDA_QUIRK_EAPDINV) 5014 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5015 hdac_command(sc, 5016 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5017 val), cad); 5018 5019 } 5020 DELAY(1000); 5021 } 5022 } 5023 5024 static void 5025 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5026 { 5027 struct hdac_softc *sc = devinfo->codec->sc; 5028 struct hdac_audio_ctl *ctl; 5029 int i; 5030 5031 devinfo->function.audio.mvol = 100 | (100 << 8); 5032 i = 0; 5033 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5034 if (ctl->enable == 0 || ctl->widget == NULL) { 5035 HDA_BOOTVERBOSE( 5036 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5037 i, (ctl->widget != NULL) ? 5038 ctl->widget->nid : -1); 5039 if (ctl->childwidget != NULL) 5040 printf(" childnid=%d", 5041 ctl->childwidget->nid); 5042 if (ctl->widget == NULL) 5043 printf(" NULL WIDGET!"); 5044 printf(" DISABLED\n"); 5045 ); 5046 continue; 5047 } 5048 HDA_BOOTVERBOSE( 5049 if (ctl->ossmask == 0) { 5050 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5051 i, ctl->widget->nid); 5052 if (ctl->childwidget != NULL) 5053 printf(" childnid=%d", 5054 ctl->childwidget->nid); 5055 printf(" Bind to NONE\n"); 5056 } 5057 ); 5058 if (ctl->step > 0) { 5059 ctl->ossval = (ctl->left * 100) / ctl->step; 5060 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5061 } else 5062 ctl->ossval = 0; 5063 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5064 ctl->left, ctl->right); 5065 } 5066 } 5067 5068 static int 5069 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5070 { 5071 struct hdac_chan *ch; 5072 struct hdac_widget *w; 5073 uint32_t cap, fmtcap, pcmcap, path; 5074 int i, type, ret, max; 5075 5076 if (dir == PCMDIR_PLAY) { 5077 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5078 ch = &devinfo->codec->sc->play; 5079 path = HDA_DAC_PATH; 5080 } else { 5081 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5082 ch = &devinfo->codec->sc->rec; 5083 path = HDA_ADC_PATH; 5084 } 5085 5086 ch->caps = hdac_caps; 5087 ch->caps.fmtlist = ch->fmtlist; 5088 ch->bit16 = 1; 5089 ch->bit32 = 0; 5090 ch->pcmrates[0] = 48000; 5091 ch->pcmrates[1] = 0; 5092 5093 ret = 0; 5094 fmtcap = devinfo->function.audio.supp_stream_formats; 5095 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5096 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5097 5098 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5099 w = hdac_widget_get(devinfo, i); 5100 if (w == NULL || w->enable == 0 || w->type != type || 5101 !(w->pflags & path)) 5102 continue; 5103 cap = w->param.widget_cap; 5104 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5105 continue;*/ 5106 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5107 continue; 5108 cap = w->param.supp_stream_formats; 5109 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5110 } 5111 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5112 }*/ 5113 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5114 continue; 5115 if (ret == 0) { 5116 fmtcap = w->param.supp_stream_formats; 5117 pcmcap = w->param.supp_pcm_size_rate; 5118 } else { 5119 fmtcap &= w->param.supp_stream_formats; 5120 pcmcap &= w->param.supp_pcm_size_rate; 5121 } 5122 ch->io[ret++] = i; 5123 } 5124 ch->io[ret] = -1; 5125 5126 ch->supp_stream_formats = fmtcap; 5127 ch->supp_pcm_size_rate = pcmcap; 5128 5129 /* 5130 * 8bit = 0 5131 * 16bit = 1 5132 * 20bit = 2 5133 * 24bit = 3 5134 * 32bit = 4 5135 */ 5136 if (ret > 0) { 5137 cap = pcmcap; 5138 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5139 ch->bit16 = 1; 5140 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5141 ch->bit16 = 0; 5142 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5143 ch->bit32 = 4; 5144 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5145 ch->bit32 = 3; 5146 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5147 ch->bit32 = 2; 5148 i = 0; 5149 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5150 ch->fmtlist[i++] = AFMT_S16_LE; 5151 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5152 if (ch->bit32 > 0) { 5153 if (!(devinfo->function.audio.quirks & 5154 HDA_QUIRK_FORCESTEREO)) 5155 ch->fmtlist[i++] = AFMT_S32_LE; 5156 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5157 } 5158 ch->fmtlist[i] = 0; 5159 i = 0; 5160 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5161 ch->pcmrates[i++] = 8000; 5162 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5163 ch->pcmrates[i++] = 11025; 5164 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5165 ch->pcmrates[i++] = 16000; 5166 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5167 ch->pcmrates[i++] = 22050; 5168 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5169 ch->pcmrates[i++] = 32000; 5170 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5171 ch->pcmrates[i++] = 44100; 5172 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5173 ch->pcmrates[i++] = 48000; 5174 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5175 ch->pcmrates[i++] = 88200; 5176 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5177 ch->pcmrates[i++] = 96000; 5178 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5179 ch->pcmrates[i++] = 176400; 5180 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5181 ch->pcmrates[i++] = 192000; 5182 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5183 ch->pcmrates[i] = 0; 5184 if (i > 0) { 5185 ch->caps.minspeed = ch->pcmrates[0]; 5186 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5187 } 5188 } 5189 5190 return (ret); 5191 } 5192 5193 static void 5194 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5195 { 5196 struct hdac_audio_ctl *ctl; 5197 struct hdac_softc *sc = devinfo->codec->sc; 5198 int i; 5199 uint32_t fl = 0; 5200 5201 5202 if (flag == 0) { 5203 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5204 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5205 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5206 } 5207 5208 i = 0; 5209 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5210 if (ctl->enable == 0 || ctl->widget == NULL || 5211 ctl->widget->enable == 0 || (ctl->ossmask & 5212 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5213 continue; 5214 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5215 (flag != 0 && (ctl->ossmask & flag))) { 5216 if (banner != NULL) { 5217 device_printf(sc->dev, "\n"); 5218 device_printf(sc->dev, "%s\n", banner); 5219 } 5220 goto hdac_ctl_dump_it_all; 5221 } 5222 } 5223 5224 return; 5225 5226 hdac_ctl_dump_it_all: 5227 i = 0; 5228 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5229 if (ctl->enable == 0 || ctl->widget == NULL || 5230 ctl->widget->enable == 0) 5231 continue; 5232 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5233 (flag != 0 && (ctl->ossmask & flag)))) 5234 continue; 5235 if (flag == 0) { 5236 device_printf(sc->dev, "\n"); 5237 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5238 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5239 } 5240 device_printf(sc->dev, " |\n"); 5241 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5242 ctl->widget->nid, ctl->index); 5243 if (ctl->childwidget != NULL) 5244 printf("(nid: %2d) ", ctl->childwidget->nid); 5245 else 5246 printf(" "); 5247 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5248 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5249 ctl->ossmask); 5250 } 5251 } 5252 5253 static void 5254 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5255 { 5256 uint32_t cap; 5257 5258 cap = fcap; 5259 if (cap != 0) { 5260 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5261 device_printf(sc->dev, " Format:"); 5262 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5263 printf(" AC3"); 5264 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5265 printf(" FLOAT32"); 5266 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5267 printf(" PCM"); 5268 printf("\n"); 5269 } 5270 cap = pcmcap; 5271 if (cap != 0) { 5272 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5273 device_printf(sc->dev, " PCM size:"); 5274 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5275 printf(" 8"); 5276 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5277 printf(" 16"); 5278 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5279 printf(" 20"); 5280 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5281 printf(" 24"); 5282 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5283 printf(" 32"); 5284 printf("\n"); 5285 device_printf(sc->dev, " PCM rate:"); 5286 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5287 printf(" 8"); 5288 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5289 printf(" 11"); 5290 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5291 printf(" 16"); 5292 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5293 printf(" 22"); 5294 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5295 printf(" 32"); 5296 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5297 printf(" 44"); 5298 printf(" 48"); 5299 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5300 printf(" 88"); 5301 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5302 printf(" 96"); 5303 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5304 printf(" 176"); 5305 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5306 printf(" 192"); 5307 printf("\n"); 5308 } 5309 } 5310 5311 static void 5312 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5313 { 5314 uint32_t pincap, wcap; 5315 5316 pincap = w->wclass.pin.cap; 5317 wcap = w->param.widget_cap; 5318 5319 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5320 device_printf(sc->dev, " "); 5321 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5322 printf(" ISC"); 5323 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5324 printf(" TRQD"); 5325 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5326 printf(" PDC"); 5327 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5328 printf(" HP"); 5329 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5330 printf(" OUT"); 5331 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5332 printf(" IN"); 5333 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5334 printf(" BAL"); 5335 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5336 printf(" VREF["); 5337 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5338 printf(" 50"); 5339 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5340 printf(" 80"); 5341 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5342 printf(" 100"); 5343 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5344 printf(" GROUND"); 5345 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5346 printf(" HIZ"); 5347 printf(" ]"); 5348 } 5349 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5350 printf(" EAPD"); 5351 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5352 printf(" : UNSOL"); 5353 printf("\n"); 5354 device_printf(sc->dev, " Pin config: 0x%08x\n", 5355 w->wclass.pin.config); 5356 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5357 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5358 printf(" HP"); 5359 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5360 printf(" IN"); 5361 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5362 printf(" OUT"); 5363 printf("\n"); 5364 } 5365 5366 static void 5367 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5368 { 5369 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5370 device_printf(sc->dev, " " 5371 "mute=%d step=%d size=%d offset=%d\n", 5372 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5373 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5374 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5375 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5376 } 5377 5378 static void 5379 hdac_dump_nodes(struct hdac_devinfo *devinfo) 5380 { 5381 struct hdac_softc *sc = devinfo->codec->sc; 5382 struct hdac_widget *w, *cw; 5383 int i, j; 5384 5385 device_printf(sc->dev, "\n"); 5386 device_printf(sc->dev, "Default Parameter\n"); 5387 device_printf(sc->dev, "-----------------\n"); 5388 hdac_dump_audio_formats(sc, 5389 devinfo->function.audio.supp_stream_formats, 5390 devinfo->function.audio.supp_pcm_size_rate); 5391 device_printf(sc->dev, " IN amp: 0x%08x\n", 5392 devinfo->function.audio.inamp_cap); 5393 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5394 devinfo->function.audio.outamp_cap); 5395 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5396 w = hdac_widget_get(devinfo, i); 5397 if (w == NULL) { 5398 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5399 continue; 5400 } 5401 device_printf(sc->dev, "\n"); 5402 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5403 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5404 "DIGITAL" : "ANALOG", 5405 (w->enable == 0) ? " [DISABLED]" : ""); 5406 device_printf(sc->dev, " name: %s\n", w->name); 5407 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5408 w->param.widget_cap); 5409 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5410 w->pflags); 5411 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5412 w->ctlflags); 5413 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5414 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5415 hdac_dump_audio_formats(sc, 5416 w->param.supp_stream_formats, 5417 w->param.supp_pcm_size_rate); 5418 } else if (w->type == 5419 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5420 hdac_dump_pin(sc, w); 5421 if (w->param.eapdbtl != HDAC_INVALID) 5422 device_printf(sc->dev, " EAPD: 0x%08x\n", 5423 w->param.eapdbtl); 5424 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5425 w->param.outamp_cap != 0) 5426 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5427 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5428 w->param.inamp_cap != 0) 5429 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5430 device_printf(sc->dev, " connections: %d\n", w->nconns); 5431 for (j = 0; j < w->nconns; j++) { 5432 cw = hdac_widget_get(devinfo, w->conns[j]); 5433 device_printf(sc->dev, " |\n"); 5434 device_printf(sc->dev, " + <- nid=%d [%s]", 5435 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5436 if (cw == NULL) 5437 printf(" [UNKNOWN]"); 5438 else if (cw->enable == 0) 5439 printf(" [DISABLED]"); 5440 if (w->nconns > 1 && w->selconn == j && w->type != 5441 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5442 printf(" (selected)"); 5443 printf("\n"); 5444 } 5445 } 5446 5447 } 5448 5449 static int 5450 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5451 { 5452 struct hdac_widget *w, *cw; 5453 struct hdac_softc *sc = devinfo->codec->sc; 5454 int i; 5455 5456 if (depth > HDA_PARSE_MAXDEPTH) 5457 return (0); 5458 5459 w = hdac_widget_get(devinfo, nid); 5460 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5461 return (0); 5462 5463 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5464 device_printf(sc->dev, "\n"); 5465 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5466 device_printf(sc->dev, " ^\n"); 5467 device_printf(sc->dev, " |\n"); 5468 device_printf(sc->dev, " +-----<------+\n"); 5469 } else { 5470 device_printf(sc->dev, " ^\n"); 5471 device_printf(sc->dev, " |\n"); 5472 device_printf(sc->dev, " "); 5473 printf(" nid=%d [%s]\n", w->nid, w->name); 5474 } 5475 5476 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5477 return (1); 5478 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5479 for (i = 0; i < w->nconns; i++) { 5480 cw = hdac_widget_get(devinfo, w->conns[i]); 5481 if (cw == NULL || cw->enable == 0 || cw->type == 5482 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5483 continue; 5484 if (hdac_dump_dac_internal(devinfo, cw->nid, 5485 depth + 1) != 0) 5486 return (1); 5487 } 5488 } else if ((w->type == 5489 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5490 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5491 w->selconn > -1 && w->selconn < w->nconns) { 5492 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5493 depth + 1) != 0) 5494 return (1); 5495 } 5496 5497 return (0); 5498 } 5499 5500 static void 5501 hdac_dump_dac(struct hdac_devinfo *devinfo) 5502 { 5503 struct hdac_widget *w; 5504 struct hdac_softc *sc = devinfo->codec->sc; 5505 int i, printed = 0; 5506 5507 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5508 w = hdac_widget_get(devinfo, i); 5509 if (w == NULL || w->enable == 0) 5510 continue; 5511 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5512 !(w->pflags & HDA_DAC_PATH)) 5513 continue; 5514 if (printed == 0) { 5515 printed = 1; 5516 device_printf(sc->dev, "\n"); 5517 device_printf(sc->dev, "Playback path:\n"); 5518 } 5519 hdac_dump_dac_internal(devinfo, w->nid, 0); 5520 } 5521 } 5522 5523 static void 5524 hdac_dump_adc(struct hdac_devinfo *devinfo) 5525 { 5526 struct hdac_widget *w, *cw; 5527 struct hdac_softc *sc = devinfo->codec->sc; 5528 int i, j; 5529 int printed = 0; 5530 char ossdevs[256]; 5531 5532 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5533 w = hdac_widget_get(devinfo, i); 5534 if (w == NULL || w->enable == 0) 5535 continue; 5536 if (!(w->pflags & HDA_ADC_RECSEL)) 5537 continue; 5538 if (printed == 0) { 5539 printed = 1; 5540 device_printf(sc->dev, "\n"); 5541 device_printf(sc->dev, "Recording sources:\n"); 5542 } 5543 device_printf(sc->dev, "\n"); 5544 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5545 for (j = 0; j < w->nconns; j++) { 5546 cw = hdac_widget_get(devinfo, w->conns[j]); 5547 if (cw == NULL || cw->enable == 0) 5548 continue; 5549 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5550 ossdevs, sizeof(ossdevs)); 5551 device_printf(sc->dev, " |\n"); 5552 device_printf(sc->dev, " + <- nid=%d [%s]", 5553 cw->nid, cw->name); 5554 if (strlen(ossdevs) > 0) { 5555 printf(" [recsrc: %s]", ossdevs); 5556 } 5557 printf("\n"); 5558 } 5559 } 5560 } 5561 5562 static void 5563 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5564 { 5565 nid_t *nids; 5566 5567 if (pcnt > 0) { 5568 device_printf(sc->dev, "\n"); 5569 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5570 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5571 sc->play.supp_pcm_size_rate); 5572 device_printf(sc->dev, " DAC:"); 5573 for (nids = sc->play.io; *nids != -1; nids++) 5574 printf(" %d", *nids); 5575 printf("\n"); 5576 } 5577 5578 if (rcnt > 0) { 5579 device_printf(sc->dev, "\n"); 5580 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5581 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5582 sc->rec.supp_pcm_size_rate); 5583 device_printf(sc->dev, " ADC:"); 5584 for (nids = sc->rec.io; *nids != -1; nids++) 5585 printf(" %d", *nids); 5586 printf("\n"); 5587 } 5588 } 5589 5590 static void 5591 hdac_release_resources(struct hdac_softc *sc) 5592 { 5593 struct hdac_devinfo *devinfo = NULL; 5594 device_t *devlist = NULL; 5595 int i, devcount; 5596 5597 if (sc == NULL) 5598 return; 5599 5600 hdac_lock(sc); 5601 sc->polling = 0; 5602 sc->poll_ival = 0; 5603 callout_stop(&sc->poll_hdac); 5604 callout_stop(&sc->poll_jack); 5605 hdac_reset(sc); 5606 hdac_unlock(sc); 5607 callout_drain(&sc->poll_hdac); 5608 callout_drain(&sc->poll_jack); 5609 5610 hdac_irq_free(sc); 5611 5612 device_get_children(sc->dev, &devlist, &devcount); 5613 for (i = 0; devlist != NULL && i < devcount; i++) { 5614 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5615 if (devinfo == NULL) 5616 continue; 5617 if (devinfo->widget != NULL) 5618 free(devinfo->widget, M_HDAC); 5619 if (devinfo->node_type == 5620 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5621 devinfo->function.audio.ctl != NULL) 5622 free(devinfo->function.audio.ctl, M_HDAC); 5623 free(devinfo, M_HDAC); 5624 device_delete_child(sc->dev, devlist[i]); 5625 } 5626 if (devlist != NULL) 5627 free(devlist, M_TEMP); 5628 5629 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5630 if (sc->codecs[i] != NULL) 5631 free(sc->codecs[i], M_HDAC); 5632 sc->codecs[i] = NULL; 5633 } 5634 5635 hdac_dma_free(sc, &sc->pos_dma); 5636 hdac_dma_free(sc, &sc->rirb_dma); 5637 hdac_dma_free(sc, &sc->corb_dma); 5638 if (sc->play.blkcnt > 0) 5639 hdac_dma_free(sc, &sc->play.bdl_dma); 5640 if (sc->rec.blkcnt > 0) 5641 hdac_dma_free(sc, &sc->rec.bdl_dma); 5642 if (sc->chan_dmat != NULL) { 5643 bus_dma_tag_destroy(sc->chan_dmat); 5644 sc->chan_dmat = NULL; 5645 } 5646 hdac_mem_free(sc); 5647 snd_mtxfree(sc->lock); 5648 free(sc, M_DEVBUF); 5649 } 5650 5651 /* This function surely going to make its way into upper level someday. */ 5652 static void 5653 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5654 { 5655 const char *res = NULL; 5656 int i = 0, j, k, len, inv; 5657 5658 if (on != NULL) 5659 *on = 0; 5660 if (off != NULL) 5661 *off = 0; 5662 if (sc == NULL) 5663 return; 5664 if (resource_string_value(device_get_name(sc->dev), 5665 device_get_unit(sc->dev), "config", &res) != 0) 5666 return; 5667 if (!(res != NULL && strlen(res) > 0)) 5668 return; 5669 HDA_BOOTVERBOSE( 5670 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5671 ); 5672 for (;;) { 5673 while (res[i] != '\0' && 5674 (res[i] == ',' || isspace(res[i]) != 0)) 5675 i++; 5676 if (res[i] == '\0') { 5677 HDA_BOOTVERBOSE( 5678 printf("\n"); 5679 ); 5680 return; 5681 } 5682 j = i; 5683 while (res[j] != '\0' && 5684 !(res[j] == ',' || isspace(res[j]) != 0)) 5685 j++; 5686 len = j - i; 5687 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5688 inv = 2; 5689 else 5690 inv = 0; 5691 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5692 if (strncmp(res + i + inv, 5693 hdac_quirks_tab[k].key, len - inv) != 0) 5694 continue; 5695 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5696 break; 5697 HDA_BOOTVERBOSE( 5698 printf(" %s%s", (inv != 0) ? "no" : "", 5699 hdac_quirks_tab[k].key); 5700 ); 5701 if (inv == 0 && on != NULL) 5702 *on |= hdac_quirks_tab[k].value; 5703 else if (inv != 0 && off != NULL) 5704 *off |= hdac_quirks_tab[k].value; 5705 break; 5706 } 5707 i = j; 5708 } 5709 } 5710 5711 #ifdef SND_DYNSYSCTL 5712 static int 5713 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5714 { 5715 struct hdac_softc *sc; 5716 struct hdac_devinfo *devinfo; 5717 device_t dev; 5718 uint32_t ctl; 5719 int err, val; 5720 5721 dev = oidp->oid_arg1; 5722 devinfo = pcm_getdevinfo(dev); 5723 if (devinfo == NULL || devinfo->codec == NULL || 5724 devinfo->codec->sc == NULL) 5725 return (EINVAL); 5726 sc = devinfo->codec->sc; 5727 hdac_lock(sc); 5728 val = sc->polling; 5729 hdac_unlock(sc); 5730 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5731 5732 if (err != 0 || req->newptr == NULL) 5733 return (err); 5734 if (val < 0 || val > 1) 5735 return (EINVAL); 5736 5737 hdac_lock(sc); 5738 if (val != sc->polling) { 5739 if (hda_chan_active(sc) != 0) 5740 err = EBUSY; 5741 else if (val == 0) { 5742 callout_stop(&sc->poll_hdac); 5743 hdac_unlock(sc); 5744 callout_drain(&sc->poll_hdac); 5745 hdac_lock(sc); 5746 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5747 sc->rirb_size / 2); 5748 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5749 ctl |= HDAC_RIRBCTL_RINTCTL; 5750 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5751 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5752 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5753 sc->polling = 0; 5754 DELAY(1000); 5755 } else { 5756 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5757 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5758 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5759 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5760 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5761 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5762 sc); 5763 sc->polling = 1; 5764 DELAY(1000); 5765 } 5766 } 5767 hdac_unlock(sc); 5768 5769 return (err); 5770 } 5771 5772 static int 5773 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5774 { 5775 struct hdac_softc *sc; 5776 struct hdac_devinfo *devinfo; 5777 device_t dev; 5778 int err, val; 5779 5780 dev = oidp->oid_arg1; 5781 devinfo = pcm_getdevinfo(dev); 5782 if (devinfo == NULL || devinfo->codec == NULL || 5783 devinfo->codec->sc == NULL) 5784 return (EINVAL); 5785 sc = devinfo->codec->sc; 5786 hdac_lock(sc); 5787 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5788 hdac_unlock(sc); 5789 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5790 5791 if (err != 0 || req->newptr == NULL) 5792 return (err); 5793 5794 if (val < 1) 5795 val = 1; 5796 if (val > 5000) 5797 val = 5000; 5798 val = ((uint64_t)val * hz) / 1000; 5799 if (val < 1) 5800 val = 1; 5801 if (val > (hz * 5)) 5802 val = hz * 5; 5803 5804 hdac_lock(sc); 5805 sc->poll_ival = val; 5806 hdac_unlock(sc); 5807 5808 return (err); 5809 } 5810 5811 #ifdef SND_DEBUG 5812 static int 5813 sysctl_hdac_dump(SYSCTL_HANDLER_ARGS) 5814 { 5815 struct hdac_softc *sc; 5816 struct hdac_devinfo *devinfo; 5817 struct hdac_widget *w; 5818 device_t dev; 5819 uint32_t res, execres; 5820 int i, err, val; 5821 nid_t cad; 5822 5823 dev = oidp->oid_arg1; 5824 devinfo = pcm_getdevinfo(dev); 5825 if (devinfo == NULL || devinfo->codec == NULL || 5826 devinfo->codec->sc == NULL) 5827 return (EINVAL); 5828 val = 0; 5829 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5830 if (err != 0 || req->newptr == NULL || val == 0) 5831 return (err); 5832 sc = devinfo->codec->sc; 5833 cad = devinfo->codec->cad; 5834 hdac_lock(sc); 5835 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 5836 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5837 w = hdac_widget_get(devinfo, i); 5838 if (w == NULL || w->type != 5839 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5840 continue; 5841 execres = hdac_command(sc, HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), 5842 cad); 5843 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 5844 device_printf(dev, "nid=%-3d exec=0x%08x sense=0x%08x [%s]\n", 5845 w->nid, execres, res, 5846 (w->enable == 0) ? "DISABLED" : "ENABLED"); 5847 } 5848 device_printf(dev, 5849 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 5850 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 5851 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 5852 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 5853 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 5854 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 5855 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 5856 device_printf(dev, " GPI:"); 5857 res = hdac_command(sc, 5858 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 5859 printf(" data=0x%08x", res); 5860 res = hdac_command(sc, 5861 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 5862 cad); 5863 printf(" wake=0x%08x", res); 5864 res = hdac_command(sc, 5865 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 5866 cad); 5867 printf(" unsol=0x%08x", res); 5868 res = hdac_command(sc, 5869 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 5870 printf(" sticky=0x%08x\n", res); 5871 } 5872 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 5873 device_printf(dev, " GPO:"); 5874 res = hdac_command(sc, 5875 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 5876 printf(" data=0x%08x\n", res); 5877 } 5878 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 5879 device_printf(dev, "GPI0:"); 5880 res = hdac_command(sc, 5881 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 5882 printf(" data=0x%08x", res); 5883 res = hdac_command(sc, 5884 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 5885 printf(" enable=0x%08x", res); 5886 res = hdac_command(sc, 5887 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 5888 printf(" direction=0x%08x\n", res); 5889 res = hdac_command(sc, 5890 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 5891 device_printf(dev, " wake=0x%08x", res); 5892 res = hdac_command(sc, 5893 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 5894 cad); 5895 printf(" unsol=0x%08x", res); 5896 res = hdac_command(sc, 5897 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 5898 printf(" sticky=0x%08x\n", res); 5899 } 5900 hdac_unlock(sc); 5901 return (0); 5902 } 5903 #endif 5904 #endif 5905 5906 static void 5907 hdac_attach2(void *arg) 5908 { 5909 struct hdac_softc *sc; 5910 struct hdac_widget *w; 5911 struct hdac_audio_ctl *ctl; 5912 uint32_t quirks_on, quirks_off; 5913 int pcnt, rcnt; 5914 int i; 5915 char status[SND_STATUSLEN]; 5916 device_t *devlist = NULL; 5917 int devcount; 5918 struct hdac_devinfo *devinfo = NULL; 5919 5920 sc = (struct hdac_softc *)arg; 5921 5922 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5923 5924 HDA_BOOTVERBOSE( 5925 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5926 quirks_on, quirks_off); 5927 ); 5928 5929 hdac_lock(sc); 5930 5931 /* Remove ourselves from the config hooks */ 5932 if (sc->intrhook.ich_func != NULL) { 5933 config_intrhook_disestablish(&sc->intrhook); 5934 sc->intrhook.ich_func = NULL; 5935 } 5936 5937 /* Start the corb and rirb engines */ 5938 HDA_BOOTVERBOSE( 5939 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5940 ); 5941 hdac_corb_start(sc); 5942 HDA_BOOTVERBOSE( 5943 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5944 ); 5945 hdac_rirb_start(sc); 5946 5947 HDA_BOOTVERBOSE( 5948 device_printf(sc->dev, 5949 "HDA_DEBUG: Enabling controller interrupt...\n"); 5950 ); 5951 if (sc->polling == 0) 5952 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5953 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5954 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5955 HDAC_GCTL_UNSOL); 5956 5957 DELAY(1000); 5958 5959 HDA_BOOTVERBOSE( 5960 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5961 ); 5962 hdac_scan_codecs(sc); 5963 5964 device_get_children(sc->dev, &devlist, &devcount); 5965 for (i = 0; devlist != NULL && i < devcount; i++) { 5966 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5967 if (devinfo != NULL && devinfo->node_type == 5968 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5969 break; 5970 } else 5971 devinfo = NULL; 5972 } 5973 if (devlist != NULL) 5974 free(devlist, M_TEMP); 5975 5976 if (devinfo == NULL) { 5977 hdac_unlock(sc); 5978 device_printf(sc->dev, "Audio Function Group not found!\n"); 5979 hdac_release_resources(sc); 5980 return; 5981 } 5982 5983 HDA_BOOTVERBOSE( 5984 device_printf(sc->dev, 5985 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5986 devinfo->nid, devinfo->codec->cad); 5987 ); 5988 hdac_audio_parse(devinfo); 5989 HDA_BOOTVERBOSE( 5990 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5991 ); 5992 hdac_audio_ctl_parse(devinfo); 5993 HDA_BOOTVERBOSE( 5994 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5995 ); 5996 hdac_vendor_patch_parse(devinfo); 5997 if (quirks_on != 0) 5998 devinfo->function.audio.quirks |= quirks_on; 5999 if (quirks_off != 0) 6000 devinfo->function.audio.quirks &= ~quirks_off; 6001 6002 /* XXX Disable all DIGITAL path. */ 6003 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6004 w = hdac_widget_get(devinfo, i); 6005 if (w == NULL) 6006 continue; 6007 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6008 w->enable = 0; 6009 continue; 6010 } 6011 /* XXX Disable useless pin ? */ 6012 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6013 (w->wclass.pin.config & 6014 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6015 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6016 w->enable = 0; 6017 } 6018 i = 0; 6019 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6020 if (ctl->widget == NULL) 6021 continue; 6022 if (ctl->ossmask & SOUND_MASK_DISABLE) 6023 ctl->enable = 0; 6024 w = ctl->widget; 6025 if (w->enable == 0 || 6026 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6027 ctl->enable = 0; 6028 w = ctl->childwidget; 6029 if (w == NULL) 6030 continue; 6031 if (w->enable == 0 || 6032 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6033 ctl->enable = 0; 6034 } 6035 6036 HDA_BOOTVERBOSE( 6037 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6038 ); 6039 hdac_audio_build_tree(devinfo); 6040 6041 i = 0; 6042 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6043 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6044 ctl->ossmask = 0; 6045 } 6046 HDA_BOOTVERBOSE( 6047 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6048 ); 6049 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6050 HDA_BOOTVERBOSE( 6051 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6052 ); 6053 hdac_audio_ctl_commit(devinfo); 6054 6055 HDA_BOOTVERBOSE( 6056 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6057 ); 6058 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6059 HDA_BOOTVERBOSE( 6060 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6061 ); 6062 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6063 6064 hdac_unlock(sc); 6065 HDA_BOOTVERBOSE( 6066 device_printf(sc->dev, 6067 "HDA_DEBUG: OSS mixer initialization...\n"); 6068 ); 6069 6070 /* 6071 * There is no point of return after this. If the driver failed, 6072 * so be it. Let the detach procedure do all the cleanup. 6073 */ 6074 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6075 device_printf(sc->dev, "Can't register mixer\n"); 6076 6077 if (pcnt > 0) 6078 pcnt = 1; 6079 if (rcnt > 0) 6080 rcnt = 1; 6081 6082 HDA_BOOTVERBOSE( 6083 device_printf(sc->dev, 6084 "HDA_DEBUG: Registering PCM channels...\n"); 6085 ); 6086 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6087 device_printf(sc->dev, "Can't register PCM\n"); 6088 6089 sc->registered++; 6090 6091 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6092 hdac_dma_alloc(sc, &sc->pos_dma, 6093 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6094 HDA_BOOTVERBOSE( 6095 device_printf(sc->dev, 6096 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6097 ); 6098 } 6099 6100 for (i = 0; i < pcnt; i++) 6101 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6102 for (i = 0; i < rcnt; i++) 6103 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6104 6105 #ifdef SND_DYNSYSCTL 6106 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6107 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6108 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6109 sysctl_hdac_polling, "I", "Enable polling mode"); 6110 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6111 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6112 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6113 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6114 "Controller/Jack Sense polling interval (1-1000 ms)"); 6115 #ifdef SND_DEBUG 6116 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6117 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6118 "dump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6119 sysctl_hdac_dump, "I", "Dump states"); 6120 #endif 6121 #endif 6122 6123 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6124 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6125 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6126 pcm_setstatus(sc->dev, status); 6127 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6128 HDA_BOOTVERBOSE( 6129 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6130 hdac_codec_id(devinfo)); 6131 ); 6132 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6133 HDA_DRV_TEST_REV); 6134 6135 HDA_BOOTVERBOSE( 6136 if (devinfo->function.audio.quirks != 0) { 6137 device_printf(sc->dev, "\n"); 6138 device_printf(sc->dev, "HDA config/quirks:"); 6139 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6140 if ((devinfo->function.audio.quirks & 6141 hdac_quirks_tab[i].value) == 6142 hdac_quirks_tab[i].value) 6143 printf(" %s", hdac_quirks_tab[i].key); 6144 } 6145 printf("\n"); 6146 } 6147 device_printf(sc->dev, "\n"); 6148 device_printf(sc->dev, "+-------------------+\n"); 6149 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6150 device_printf(sc->dev, "+-------------------+\n"); 6151 hdac_dump_nodes(devinfo); 6152 device_printf(sc->dev, "\n"); 6153 device_printf(sc->dev, "+------------------------+\n"); 6154 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6155 device_printf(sc->dev, "+------------------------+\n"); 6156 device_printf(sc->dev, "\n"); 6157 i = 0; 6158 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6159 device_printf(sc->dev, "%3d: nid=%d", i, 6160 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6161 if (ctl->childwidget != NULL) 6162 printf(" cnid=%d", ctl->childwidget->nid); 6163 printf(" dir=0x%x index=%d " 6164 "ossmask=0x%08x ossdev=%d%s\n", 6165 ctl->dir, ctl->index, 6166 ctl->ossmask, ctl->ossdev, 6167 (ctl->enable == 0) ? " [DISABLED]" : ""); 6168 } 6169 device_printf(sc->dev, "\n"); 6170 device_printf(sc->dev, "+-----------------------------------+\n"); 6171 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6172 device_printf(sc->dev, "+-----------------------------------+\n"); 6173 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6174 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6175 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6176 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6177 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6178 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6179 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6180 hdac_dump_ctls(devinfo, NULL, 0); 6181 hdac_dump_dac(devinfo); 6182 hdac_dump_adc(devinfo); 6183 device_printf(sc->dev, "\n"); 6184 device_printf(sc->dev, "+--------------------------------------+\n"); 6185 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6186 device_printf(sc->dev, "+--------------------------------------+\n"); 6187 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6188 ); 6189 6190 if (sc->polling != 0) { 6191 hdac_lock(sc); 6192 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6193 hdac_unlock(sc); 6194 } 6195 } 6196 6197 /**************************************************************************** 6198 * int hdac_detach(device_t) 6199 * 6200 * Detach and free up resources utilized by the hdac device. 6201 ****************************************************************************/ 6202 static int 6203 hdac_detach(device_t dev) 6204 { 6205 struct hdac_softc *sc = NULL; 6206 struct hdac_devinfo *devinfo = NULL; 6207 int err; 6208 6209 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6210 if (devinfo != NULL && devinfo->codec != NULL) 6211 sc = devinfo->codec->sc; 6212 if (sc == NULL) 6213 return (0); 6214 6215 if (sc->registered > 0) { 6216 err = pcm_unregister(dev); 6217 if (err != 0) 6218 return (err); 6219 } 6220 6221 hdac_release_resources(sc); 6222 6223 return (0); 6224 } 6225 6226 static device_method_t hdac_methods[] = { 6227 /* device interface */ 6228 DEVMETHOD(device_probe, hdac_probe), 6229 DEVMETHOD(device_attach, hdac_attach), 6230 DEVMETHOD(device_detach, hdac_detach), 6231 { 0, 0 } 6232 }; 6233 6234 static driver_t hdac_driver = { 6235 "pcm", 6236 hdac_methods, 6237 PCM_SOFTC_SIZE, 6238 }; 6239 6240 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6241 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6242 MODULE_VERSION(snd_hda, 1); 6243