1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71 #ifdef HAVE_KERNEL_OPTION_HEADERS 72 #include "opt_snd.h" 73 #endif 74 75 #include <dev/sound/pcm/sound.h> 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 79 #include <sys/ctype.h> 80 #include <sys/taskqueue.h> 81 82 #include <dev/sound/pci/hda/hdac_private.h> 83 #include <dev/sound/pci/hda/hdac_reg.h> 84 #include <dev/sound/pci/hda/hda_reg.h> 85 #include <dev/sound/pci/hda/hdac.h> 86 87 #include "mixer_if.h" 88 89 #define HDA_DRV_TEST_REV "20100226_0142" 90 91 SND_DECLARE_FILE("$FreeBSD$"); 92 93 #define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97 } while (0) 98 99 #define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103 } while (0) 104 105 #if 1 106 #undef HDAC_INTR_EXTRA 107 #define HDAC_INTR_EXTRA 1 108 #endif 109 110 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 111 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122 #define HDA_MATCH_ALL 0xffffffff 123 #define HDAC_INVALID 0xffffffff 124 125 /* Default controller / jack sense poll: 250ms */ 126 #define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128 /* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131 #define HDAC_TRIGGER_NONE 0x00000000 132 #define HDAC_TRIGGER_PLAY 0x00000fff 133 #define HDAC_TRIGGER_REC 0x00fff000 134 #define HDAC_TRIGGER_UNSOL 0x80000000 135 136 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139 /* Controller models */ 140 141 /* Intel */ 142 #define INTEL_VENDORID 0x8086 143 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 144 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 145 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 146 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 147 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 148 #define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 149 #define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 150 #define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 151 #define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 152 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 153 154 /* Nvidia */ 155 #define NVIDIA_VENDORID 0x10de 156 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 157 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 158 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 159 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 160 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 161 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 162 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 163 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 164 #define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 165 #define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 166 #define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 167 #define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 168 #define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 169 #define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 170 #define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 171 #define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 172 #define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 173 #define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 174 #define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 175 #define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 176 #define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 177 #define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 178 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 179 180 /* ATI */ 181 #define ATI_VENDORID 0x1002 182 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 183 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 184 #define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 185 #define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 186 #define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 187 #define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 188 #define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 189 #define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 190 #define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 191 #define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 192 #define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 193 #define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 194 #define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 195 #define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 196 #define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 197 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 198 199 /* VIA */ 200 #define VIA_VENDORID 0x1106 201 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 202 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 203 204 /* SiS */ 205 #define SIS_VENDORID 0x1039 206 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 207 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 208 209 /* ULI */ 210 #define ULI_VENDORID 0x10b9 211 #define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 212 #define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 213 214 /* OEM/subvendors */ 215 216 /* Intel */ 217 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 218 219 /* HP/Compaq */ 220 #define HP_VENDORID 0x103c 221 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 222 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 223 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 224 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 225 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 226 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 227 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 228 #define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 229 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 230 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 231 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 232 #define HP_NX6325_SUBVENDORX 0x103c30b0 233 234 /* Dell */ 235 #define DELL_VENDORID 0x1028 236 #define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 237 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 238 #define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 239 #define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 240 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 241 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 242 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 243 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 244 245 /* Clevo */ 246 #define CLEVO_VENDORID 0x1558 247 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 248 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 249 250 /* Acer */ 251 #define ACER_VENDORID 0x1025 252 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 253 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 254 #define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 255 #define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 256 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 257 #define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 258 #define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 259 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 260 261 /* Asus */ 262 #define ASUS_VENDORID 0x1043 263 #define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 264 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 265 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 266 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 267 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 268 #define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 269 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 270 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 271 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 272 #define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 273 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 274 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 275 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 276 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 277 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 278 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 279 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 280 281 /* IBM / Lenovo */ 282 #define IBM_VENDORID 0x1014 283 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 284 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 285 286 /* Lenovo */ 287 #define LENOVO_VENDORID 0x17aa 288 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 289 #define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 290 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 291 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 292 293 /* Samsung */ 294 #define SAMSUNG_VENDORID 0x144d 295 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 296 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 297 298 /* Medion ? */ 299 #define MEDION_VENDORID 0x161f 300 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 301 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 302 303 /* Apple Computer Inc. */ 304 #define APPLE_VENDORID 0x106b 305 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 306 307 /* Sony */ 308 #define SONY_VENDORID 0x104d 309 #define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 310 #define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 311 312 /* 313 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 314 * instead of their own, which is beyond my comprehension 315 * (see HDA_CODEC_STAC9221 below). 316 */ 317 #define APPLE_INTEL_MAC 0x76808384 318 #define APPLE_MACBOOKPRO55 0xcb7910de 319 320 /* LG Electronics */ 321 #define LG_VENDORID 0x1854 322 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 323 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 324 325 /* Fujitsu Siemens */ 326 #define FS_VENDORID 0x1734 327 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 328 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 329 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 330 331 /* Fujitsu Limited */ 332 #define FL_VENDORID 0x10cf 333 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 334 #define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 335 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 336 337 /* Toshiba */ 338 #define TOSHIBA_VENDORID 0x1179 339 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 340 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 341 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 342 343 /* Micro-Star International (MSI) */ 344 #define MSI_VENDORID 0x1462 345 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 346 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 347 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 348 349 /* Giga-Byte Technology */ 350 #define GB_VENDORID 0x1458 351 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 352 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 353 354 /* Uniwill ? */ 355 #define UNIWILL_VENDORID 0x1584 356 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 357 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 358 359 360 /* Misc constants.. */ 361 #define HDA_AMP_VOL_DEFAULT (-1) 362 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 363 #define HDA_AMP_MUTE_NONE (0) 364 #define HDA_AMP_MUTE_LEFT (1 << 0) 365 #define HDA_AMP_MUTE_RIGHT (1 << 1) 366 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 367 368 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 369 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 370 371 #define HDA_ADC_MONITOR (1 << 0) 372 373 #define HDA_CTL_OUT 1 374 #define HDA_CTL_IN 2 375 376 #define HDA_GPIO_MAX 8 377 /* 0 - 7 = GPIO , 8 = Flush */ 378 #define HDA_QUIRK_GPIO0 (1 << 0) 379 #define HDA_QUIRK_GPIO1 (1 << 1) 380 #define HDA_QUIRK_GPIO2 (1 << 2) 381 #define HDA_QUIRK_GPIO3 (1 << 3) 382 #define HDA_QUIRK_GPIO4 (1 << 4) 383 #define HDA_QUIRK_GPIO5 (1 << 5) 384 #define HDA_QUIRK_GPIO6 (1 << 6) 385 #define HDA_QUIRK_GPIO7 (1 << 7) 386 #define HDA_QUIRK_GPIOFLUSH (1 << 8) 387 388 /* 9 - 25 = anything else */ 389 #define HDA_QUIRK_SOFTPCMVOL (1 << 9) 390 #define HDA_QUIRK_FIXEDRATE (1 << 10) 391 #define HDA_QUIRK_FORCESTEREO (1 << 11) 392 #define HDA_QUIRK_EAPDINV (1 << 12) 393 #define HDA_QUIRK_DMAPOS (1 << 13) 394 #define HDA_QUIRK_SENSEINV (1 << 14) 395 396 /* 26 - 31 = vrefs */ 397 #define HDA_QUIRK_IVREF50 (1 << 26) 398 #define HDA_QUIRK_IVREF80 (1 << 27) 399 #define HDA_QUIRK_IVREF100 (1 << 28) 400 #define HDA_QUIRK_OVREF50 (1 << 29) 401 #define HDA_QUIRK_OVREF80 (1 << 30) 402 #define HDA_QUIRK_OVREF100 (1 << 31) 403 404 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 405 HDA_QUIRK_IVREF100) 406 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 407 HDA_QUIRK_OVREF100) 408 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 409 410 #if __FreeBSD_version < 600000 411 #define taskqueue_drain(...) 412 #endif 413 414 static const struct { 415 char *key; 416 uint32_t value; 417 } hdac_quirks_tab[] = { 418 { "gpio0", HDA_QUIRK_GPIO0 }, 419 { "gpio1", HDA_QUIRK_GPIO1 }, 420 { "gpio2", HDA_QUIRK_GPIO2 }, 421 { "gpio3", HDA_QUIRK_GPIO3 }, 422 { "gpio4", HDA_QUIRK_GPIO4 }, 423 { "gpio5", HDA_QUIRK_GPIO5 }, 424 { "gpio6", HDA_QUIRK_GPIO6 }, 425 { "gpio7", HDA_QUIRK_GPIO7 }, 426 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 427 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 428 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 429 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 430 { "eapdinv", HDA_QUIRK_EAPDINV }, 431 { "dmapos", HDA_QUIRK_DMAPOS }, 432 { "senseinv", HDA_QUIRK_SENSEINV }, 433 { "ivref50", HDA_QUIRK_IVREF50 }, 434 { "ivref80", HDA_QUIRK_IVREF80 }, 435 { "ivref100", HDA_QUIRK_IVREF100 }, 436 { "ovref50", HDA_QUIRK_OVREF50 }, 437 { "ovref80", HDA_QUIRK_OVREF80 }, 438 { "ovref100", HDA_QUIRK_OVREF100 }, 439 { "ivref", HDA_QUIRK_IVREF }, 440 { "ovref", HDA_QUIRK_OVREF }, 441 { "vref", HDA_QUIRK_VREF }, 442 }; 443 #define HDAC_QUIRKS_TAB_LEN \ 444 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 445 446 #define HDA_BDL_MIN 2 447 #define HDA_BDL_MAX 256 448 #define HDA_BDL_DEFAULT HDA_BDL_MIN 449 450 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 451 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 452 453 #define HDA_BUFSZ_MIN 4096 454 #define HDA_BUFSZ_MAX 65536 455 #define HDA_BUFSZ_DEFAULT 16384 456 457 #define HDA_PARSE_MAXDEPTH 10 458 459 #define HDAC_UNSOLTAG_EVENT_HP 0x00 460 461 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 462 463 const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 464 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 465 "White", "Other"}; 466 467 const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 468 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 469 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 470 471 const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 472 473 /* Default */ 474 static uint32_t hdac_fmt[] = { 475 SND_FORMAT(AFMT_S16_LE, 2, 0), 476 0 477 }; 478 479 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 480 481 #define HDAC_NO_MSI 1 482 #define HDAC_NO_64BIT 2 483 484 static const struct { 485 uint32_t model; 486 char *desc; 487 char flags; 488 } hdac_devices[] = { 489 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 490 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 491 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 492 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 493 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 494 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 495 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 496 { HDA_INTEL_PCH, "Intel PCH", 0 }, 497 { HDA_INTEL_SCH, "Intel SCH", 0 }, 498 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 499 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 500 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 501 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 502 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 503 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 504 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 505 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 506 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 507 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 508 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 509 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 510 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 511 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 512 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 513 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 514 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 515 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 516 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 517 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 518 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 519 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 520 { HDA_ATI_SB450, "ATI SB450", 0 }, 521 { HDA_ATI_SB600, "ATI SB600", 0 }, 522 { HDA_ATI_RS600, "ATI RS600", 0 }, 523 { HDA_ATI_RS690, "ATI RS690", 0 }, 524 { HDA_ATI_RS780, "ATI RS780", 0 }, 525 { HDA_ATI_R600, "ATI R600", 0 }, 526 { HDA_ATI_RV610, "ATI RV610", 0 }, 527 { HDA_ATI_RV620, "ATI RV620", 0 }, 528 { HDA_ATI_RV630, "ATI RV630", 0 }, 529 { HDA_ATI_RV635, "ATI RV635", 0 }, 530 { HDA_ATI_RV710, "ATI RV710", 0 }, 531 { HDA_ATI_RV730, "ATI RV730", 0 }, 532 { HDA_ATI_RV740, "ATI RV740", 0 }, 533 { HDA_ATI_RV770, "ATI RV770", 0 }, 534 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 535 { HDA_SIS_966, "SiS 966", 0 }, 536 { HDA_ULI_M5461, "ULI M5461", 0 }, 537 /* Unknown */ 538 { HDA_INTEL_ALL, "Intel (Unknown)" }, 539 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 540 { HDA_ATI_ALL, "ATI (Unknown)" }, 541 { HDA_VIA_ALL, "VIA (Unknown)" }, 542 { HDA_SIS_ALL, "SiS (Unknown)" }, 543 { HDA_ULI_ALL, "ULI (Unknown)" }, 544 }; 545 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 546 547 static const struct { 548 uint16_t vendor; 549 uint8_t reg; 550 uint8_t mask; 551 uint8_t enable; 552 } hdac_pcie_snoop[] = { 553 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 554 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 555 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 556 }; 557 #define HDAC_PCIESNOOP_LEN \ 558 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 559 560 static const struct { 561 uint32_t rate; 562 int valid; 563 uint16_t base; 564 uint16_t mul; 565 uint16_t div; 566 } hda_rate_tab[] = { 567 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 568 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 569 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 570 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 571 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 572 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 573 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 574 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 575 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 576 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 577 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 578 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 579 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 580 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 581 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 582 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 583 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 584 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 585 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 586 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 587 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 588 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 589 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 590 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 591 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 592 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 593 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 594 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 595 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 596 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 597 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 598 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 599 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 600 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 601 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 602 }; 603 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 604 605 /* All codecs you can eat... */ 606 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 607 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 608 609 /* Cirrus Logic */ 610 #define CIRRUSLOGIC_VENDORID 0x1013 611 #define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206) 612 #define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207) 613 #define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff) 614 615 /* Realtek */ 616 #define REALTEK_VENDORID 0x10ec 617 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 618 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 619 #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 620 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 621 #define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 622 #define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270) 623 #define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 624 #define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273) 625 #define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275) 626 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 627 #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 628 #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 629 #define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665) 630 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 631 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 632 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 633 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 634 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 635 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 636 #define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) 637 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 638 #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 639 #define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892) 640 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 641 642 /* Analog Devices */ 643 #define ANALOGDEVICES_VENDORID 0x11d4 644 #define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 645 #define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 646 #define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 647 #define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 648 #define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 649 #define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 650 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 651 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 652 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 653 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 654 #define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 655 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 656 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 657 #define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 658 #define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 659 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 660 661 /* CMedia */ 662 #define CMEDIA_VENDORID 0x434d 663 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 664 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 665 666 /* Sigmatel */ 667 #define SIGMATEL_VENDORID 0x8384 668 #define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 669 #define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 670 #define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 671 #define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 672 #define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 673 #define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 674 #define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 675 #define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 676 #define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 677 #define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 678 #define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 679 #define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 680 #define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 681 #define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 682 #define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 683 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 684 #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 685 #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 686 #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 687 #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 688 #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 689 #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 690 #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 691 #define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 692 #define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661) 693 #define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 694 #define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664) 695 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 696 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 697 #define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 698 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 699 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 700 #define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 701 #define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 702 #define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 703 #define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 704 #define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 705 #define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 706 #define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 707 #define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 708 #define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 709 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 710 711 /* IDT */ 712 #define IDT_VENDORID 0x111d 713 #define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 714 #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 715 #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 716 #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 717 #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 718 #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 719 #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 720 #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 721 #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 722 #define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 723 #define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 724 #define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 725 #define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 726 727 /* Silicon Image */ 728 #define SII_VENDORID 0x1095 729 #define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 730 #define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 731 #define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 732 733 /* Lucent/Agere */ 734 #define AGERE_VENDORID 0x11c1 735 #define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 736 737 /* Conexant */ 738 #define CONEXANT_VENDORID 0x14f1 739 #define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 740 #define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 741 #define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 742 #define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066) 743 #define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067) 744 #define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069) 745 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 746 747 /* VIA */ 748 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 749 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 750 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 751 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 752 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 753 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 754 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 755 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 756 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 757 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 758 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 759 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 760 #define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 761 #define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 762 #define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 763 #define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 764 #define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 765 #define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 766 #define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 767 #define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 768 #define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 769 #define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 770 #define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 771 #define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 772 #define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 773 #define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 774 #define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 775 #define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 776 #define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 777 #define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 778 #define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 779 #define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 780 #define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 781 #define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 782 #define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 783 #define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 784 #define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433) 785 #define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721) 786 #define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428) 787 #define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428) 788 #define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448) 789 #define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440) 790 #define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441) 791 #define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438) 792 #define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438) 793 #define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441) 794 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 795 796 /* ATI */ 797 #define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 798 #define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 799 #define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 800 #define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 801 #define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 802 803 /* NVIDIA */ 804 #define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 805 #define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 806 #define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 807 #define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a) 808 #define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b) 809 #define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c) 810 #define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d) 811 #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 812 #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 813 #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 814 815 /* INTEL */ 816 #define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 817 #define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 818 #define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 819 #define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x2804) 820 #define HDA_CODEC_INTELG45_5 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 821 #define HDA_CODEC_INTELQ57 HDA_CODEC_CONSTRUCT(INTEL, 0x0054) 822 #define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 823 824 /* Codecs */ 825 static const struct { 826 uint32_t id; 827 char *name; 828 } hdac_codecs[] = { 829 { HDA_CODEC_CS4206, "Cirrus Logic CS4206" }, 830 { HDA_CODEC_CS4207, "Cirrus Logic CS4207" }, 831 { HDA_CODEC_ALC260, "Realtek ALC260" }, 832 { HDA_CODEC_ALC262, "Realtek ALC262" }, 833 { HDA_CODEC_ALC267, "Realtek ALC267" }, 834 { HDA_CODEC_ALC268, "Realtek ALC268" }, 835 { HDA_CODEC_ALC269, "Realtek ALC269" }, 836 { HDA_CODEC_ALC270, "Realtek ALC270" }, 837 { HDA_CODEC_ALC272, "Realtek ALC272" }, 838 { HDA_CODEC_ALC273, "Realtek ALC273" }, 839 { HDA_CODEC_ALC275, "Realtek ALC275" }, 840 { HDA_CODEC_ALC660, "Realtek ALC660" }, 841 { HDA_CODEC_ALC662, "Realtek ALC662" }, 842 { HDA_CODEC_ALC663, "Realtek ALC663" }, 843 { HDA_CODEC_ALC665, "Realtek ALC665" }, 844 { HDA_CODEC_ALC861, "Realtek ALC861" }, 845 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 846 { HDA_CODEC_ALC880, "Realtek ALC880" }, 847 { HDA_CODEC_ALC882, "Realtek ALC882" }, 848 { HDA_CODEC_ALC883, "Realtek ALC883" }, 849 { HDA_CODEC_ALC885, "Realtek ALC885" }, 850 { HDA_CODEC_ALC887, "Realtek ALC887" }, 851 { HDA_CODEC_ALC888, "Realtek ALC888" }, 852 { HDA_CODEC_ALC889, "Realtek ALC889" }, 853 { HDA_CODEC_ALC892, "Realtek ALC892" }, 854 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 855 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 856 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 857 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 858 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 859 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 860 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 861 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 862 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 863 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 864 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 865 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 866 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 867 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 868 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 869 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 870 { HDA_CODEC_CXD9872RDK, "Sigmatel CXD9872RD/K" }, 871 { HDA_CODEC_CXD9872AKD, "Sigmatel CXD9872AKD" }, 872 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 873 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 874 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 875 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 876 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 877 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 878 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 879 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 880 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 881 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 882 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 883 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 884 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 885 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 886 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 887 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 888 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 889 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 890 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 891 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 892 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 893 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 894 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 895 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 896 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 897 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 898 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 899 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 900 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 901 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 902 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 903 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 904 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 905 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 906 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 907 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 908 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 909 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 910 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 911 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 912 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 913 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 914 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 915 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 916 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 917 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 918 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 919 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 920 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 921 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 922 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 923 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 924 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 925 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 926 { HDA_CODEC_CX20582, "Conexant CX20582 (Pebble)" }, 927 { HDA_CODEC_CX20583, "Conexant CX20583 (Pebble HSF)" }, 928 { HDA_CODEC_CX20585, "Conexant CX20585" }, 929 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 930 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 931 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 932 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 933 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 934 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 935 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 936 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 937 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 938 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 939 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 940 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 941 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 942 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 943 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 944 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 945 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 946 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 947 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 948 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 949 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 950 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 951 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 952 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 953 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 954 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 955 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 956 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 957 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 958 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 959 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 960 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 961 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 962 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 963 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 964 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 965 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" }, 966 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" }, 967 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" }, 968 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" }, 969 { HDA_CODEC_VT1812, "VIA VT1812" }, 970 { HDA_CODEC_VT1818S, "VIA VT1818S" }, 971 { HDA_CODEC_VT1828S, "VIA VT1828S" }, 972 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" }, 973 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" }, 974 { HDA_CODEC_VT2020, "VIA VT2020" }, 975 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 976 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 977 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 978 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 979 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 980 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 981 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 982 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 983 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 984 { HDA_CODEC_NVIDIAGT220, "NVidia GT220 HDMI" }, 985 { HDA_CODEC_NVIDIAGT21X, "NVidia GT21x HDMI" }, 986 { HDA_CODEC_NVIDIAMCP89, "NVidia MCP89 HDMI" }, 987 { HDA_CODEC_NVIDIAGT240, "NVidia GT240 HDMI" }, 988 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 989 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 990 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 991 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 992 { HDA_CODEC_INTELG45_5, "Intel G45 HDMI" }, 993 { HDA_CODEC_INTELQ57, "Intel Q57 HDMI" }, 994 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 995 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 996 /* Unknown codec */ 997 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 998 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 999 { HDA_CODEC_CSXXXX, "Cirrus Logic (Unknown)" }, 1000 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 1001 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 1002 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 1003 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 1004 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 1005 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 1006 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 1007 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 1008 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 1009 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 1010 }; 1011 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 1012 1013 1014 /**************************************************************************** 1015 * Function prototypes 1016 ****************************************************************************/ 1017 static void hdac_intr_handler(void *); 1018 static int hdac_reset(struct hdac_softc *, int); 1019 static int hdac_get_capabilities(struct hdac_softc *); 1020 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 1021 static int hdac_dma_alloc(struct hdac_softc *, 1022 struct hdac_dma *, bus_size_t); 1023 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 1024 static int hdac_mem_alloc(struct hdac_softc *); 1025 static void hdac_mem_free(struct hdac_softc *); 1026 static int hdac_irq_alloc(struct hdac_softc *); 1027 static void hdac_irq_free(struct hdac_softc *); 1028 static void hdac_corb_init(struct hdac_softc *); 1029 static void hdac_rirb_init(struct hdac_softc *); 1030 static void hdac_corb_start(struct hdac_softc *); 1031 static void hdac_rirb_start(struct hdac_softc *); 1032 static void hdac_scan_codecs(struct hdac_softc *); 1033 static void hdac_probe_codec(struct hdac_codec *); 1034 static void hdac_probe_function(struct hdac_codec *, nid_t); 1035 static int hdac_pcmchannel_setup(struct hdac_chan *); 1036 1037 static void hdac_attach2(void *); 1038 1039 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 1040 uint32_t, int); 1041 static void hdac_command_send_internal(struct hdac_softc *, 1042 struct hdac_command_list *, int); 1043 1044 static int hdac_probe(device_t); 1045 static int hdac_attach(device_t); 1046 static int hdac_detach(device_t); 1047 static int hdac_suspend(device_t); 1048 static int hdac_resume(device_t); 1049 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 1050 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 1051 uint32_t, int, int); 1052 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 1053 nid_t, int, int, int); 1054 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 1055 nid_t, nid_t, int, int, int, int, int, int); 1056 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 1057 1058 static int hdac_rirb_flush(struct hdac_softc *sc); 1059 static int hdac_unsolq_flush(struct hdac_softc *sc); 1060 1061 static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 1062 1063 #define hdac_command(a1, a2, a3) \ 1064 hdac_command_sendone_internal(a1, a2, a3) 1065 1066 #define hdac_codec_id(c) \ 1067 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1068 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1069 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1070 1071 static char * 1072 hdac_codec_name(struct hdac_codec *codec) 1073 { 1074 uint32_t id; 1075 int i; 1076 1077 id = hdac_codec_id(codec); 1078 1079 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1080 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1081 return (hdac_codecs[i].name); 1082 } 1083 1084 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1085 } 1086 1087 static char * 1088 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1089 { 1090 static char *ossname[] = SOUND_DEVICE_NAMES; 1091 int i, first = 1; 1092 1093 bzero(buf, len); 1094 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1095 if (mask & (1 << i)) { 1096 if (first == 0) 1097 strlcat(buf, ", ", len); 1098 strlcat(buf, ossname[i], len); 1099 first = 0; 1100 } 1101 } 1102 return (buf); 1103 } 1104 1105 static struct hdac_audio_ctl * 1106 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1107 { 1108 if (devinfo == NULL || 1109 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1110 index == NULL || devinfo->function.audio.ctl == NULL || 1111 devinfo->function.audio.ctlcnt < 1 || 1112 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1113 return (NULL); 1114 return (&devinfo->function.audio.ctl[(*index)++]); 1115 } 1116 1117 static struct hdac_audio_ctl * 1118 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1119 int index, int cnt) 1120 { 1121 struct hdac_audio_ctl *ctl; 1122 int i, found = 0; 1123 1124 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1125 return (NULL); 1126 1127 i = 0; 1128 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1129 if (ctl->enable == 0) 1130 continue; 1131 if (ctl->widget->nid != nid) 1132 continue; 1133 if (dir && ctl->ndir != dir) 1134 continue; 1135 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1136 ctl->dir == ctl->ndir && ctl->index != index) 1137 continue; 1138 found++; 1139 if (found == cnt || cnt <= 0) 1140 return (ctl); 1141 } 1142 1143 return (NULL); 1144 } 1145 1146 /* 1147 * Jack detection (Speaker/HP redirection) event handler. 1148 */ 1149 static void 1150 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1151 { 1152 struct hdac_audio_as *as; 1153 struct hdac_softc *sc; 1154 struct hdac_widget *w; 1155 struct hdac_audio_ctl *ctl; 1156 uint32_t val, res; 1157 int i, j; 1158 nid_t cad; 1159 1160 if (devinfo == NULL || devinfo->codec == NULL || 1161 devinfo->codec->sc == NULL) 1162 return; 1163 1164 sc = devinfo->codec->sc; 1165 cad = devinfo->codec->cad; 1166 as = devinfo->function.audio.as; 1167 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1168 if (as[i].hpredir < 0) 1169 continue; 1170 1171 w = hdac_widget_get(devinfo, as[i].pins[15]); 1172 if (w == NULL || w->enable == 0 || w->type != 1173 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1174 continue; 1175 1176 res = hdac_command(sc, 1177 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1178 1179 HDA_BOOTVERBOSE( 1180 device_printf(sc->dev, 1181 "Pin sense: nid=%d res=0x%08x\n", 1182 as[i].pins[15], res); 1183 ); 1184 1185 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1186 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1187 res ^= 1; 1188 1189 /* (Un)Mute headphone pin. */ 1190 ctl = hdac_audio_ctl_amp_get(devinfo, 1191 as[i].pins[15], HDA_CTL_IN, -1, 1); 1192 if (ctl != NULL && ctl->mute) { 1193 /* If pin has muter - use it. */ 1194 val = (res != 0) ? 0 : 1; 1195 if (val != ctl->forcemute) { 1196 ctl->forcemute = val; 1197 hdac_audio_ctl_amp_set(ctl, 1198 HDA_AMP_MUTE_DEFAULT, 1199 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1200 } 1201 } else { 1202 /* If there is no muter - disable pin output. */ 1203 w = hdac_widget_get(devinfo, as[i].pins[15]); 1204 if (w != NULL && w->type == 1205 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1206 if (res != 0) 1207 val = w->wclass.pin.ctrl | 1208 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1209 else 1210 val = w->wclass.pin.ctrl & 1211 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1212 if (val != w->wclass.pin.ctrl) { 1213 w->wclass.pin.ctrl = val; 1214 hdac_command(sc, 1215 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1216 w->nid, w->wclass.pin.ctrl), cad); 1217 } 1218 } 1219 } 1220 /* (Un)Mute other pins. */ 1221 for (j = 0; j < 15; j++) { 1222 if (as[i].pins[j] <= 0) 1223 continue; 1224 ctl = hdac_audio_ctl_amp_get(devinfo, 1225 as[i].pins[j], HDA_CTL_IN, -1, 1); 1226 if (ctl != NULL && ctl->mute) { 1227 /* If pin has muter - use it. */ 1228 val = (res != 0) ? 1 : 0; 1229 if (val == ctl->forcemute) 1230 continue; 1231 ctl->forcemute = val; 1232 hdac_audio_ctl_amp_set(ctl, 1233 HDA_AMP_MUTE_DEFAULT, 1234 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1235 continue; 1236 } 1237 /* If there is no muter - disable pin output. */ 1238 w = hdac_widget_get(devinfo, as[i].pins[j]); 1239 if (w != NULL && w->type == 1240 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1241 if (res != 0) 1242 val = w->wclass.pin.ctrl & 1243 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1244 else 1245 val = w->wclass.pin.ctrl | 1246 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1247 if (val != w->wclass.pin.ctrl) { 1248 w->wclass.pin.ctrl = val; 1249 hdac_command(sc, 1250 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1251 w->nid, w->wclass.pin.ctrl), cad); 1252 } 1253 } 1254 } 1255 } 1256 } 1257 1258 /* 1259 * Callback for poll based jack detection. 1260 */ 1261 static void 1262 hdac_jack_poll_callback(void *arg) 1263 { 1264 struct hdac_devinfo *devinfo = arg; 1265 struct hdac_softc *sc; 1266 1267 if (devinfo == NULL || devinfo->codec == NULL || 1268 devinfo->codec->sc == NULL) 1269 return; 1270 sc = devinfo->codec->sc; 1271 hdac_lock(sc); 1272 if (sc->poll_ival == 0) { 1273 hdac_unlock(sc); 1274 return; 1275 } 1276 hdac_hp_switch_handler(devinfo); 1277 callout_reset(&sc->poll_jack, sc->poll_ival, 1278 hdac_jack_poll_callback, devinfo); 1279 hdac_unlock(sc); 1280 } 1281 1282 /* 1283 * Jack detection initializer. 1284 */ 1285 static void 1286 hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1287 { 1288 struct hdac_softc *sc = devinfo->codec->sc; 1289 struct hdac_audio_as *as = devinfo->function.audio.as; 1290 struct hdac_widget *w; 1291 uint32_t id; 1292 int i, enable = 0, poll = 0; 1293 nid_t cad; 1294 1295 id = hdac_codec_id(devinfo->codec); 1296 cad = devinfo->codec->cad; 1297 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1298 if (as[i].hpredir < 0) 1299 continue; 1300 1301 w = hdac_widget_get(devinfo, as[i].pins[15]); 1302 if (w == NULL || w->enable == 0 || w->type != 1303 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1304 continue; 1305 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1306 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1307 device_printf(sc->dev, 1308 "No jack detection support at pin %d\n", 1309 as[i].pins[15]); 1310 continue; 1311 } 1312 enable = 1; 1313 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1314 hdac_command(sc, 1315 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1316 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1317 HDAC_UNSOLTAG_EVENT_HP), cad); 1318 } else 1319 poll = 1; 1320 HDA_BOOTVERBOSE( 1321 device_printf(sc->dev, 1322 "Enabling headphone/speaker " 1323 "audio routing switching:\n"); 1324 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1325 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1326 ); 1327 } 1328 if (enable) { 1329 hdac_hp_switch_handler(devinfo); 1330 if (poll) { 1331 callout_reset(&sc->poll_jack, 1, 1332 hdac_jack_poll_callback, devinfo); 1333 } 1334 } 1335 } 1336 1337 /* 1338 * Unsolicited messages handler. 1339 */ 1340 static void 1341 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1342 { 1343 struct hdac_softc *sc; 1344 struct hdac_devinfo *devinfo = NULL; 1345 int i; 1346 1347 if (codec == NULL || codec->sc == NULL) 1348 return; 1349 1350 sc = codec->sc; 1351 1352 HDA_BOOTVERBOSE( 1353 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1354 ); 1355 1356 for (i = 0; i < codec->num_fgs; i++) { 1357 if (codec->fgs[i].node_type == 1358 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1359 devinfo = &codec->fgs[i]; 1360 break; 1361 } 1362 } 1363 1364 if (devinfo == NULL) 1365 return; 1366 1367 switch (tag) { 1368 case HDAC_UNSOLTAG_EVENT_HP: 1369 hdac_hp_switch_handler(devinfo); 1370 break; 1371 default: 1372 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1373 break; 1374 } 1375 } 1376 1377 static int 1378 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1379 { 1380 /* XXX to be removed */ 1381 #ifdef HDAC_INTR_EXTRA 1382 uint32_t res; 1383 #endif 1384 1385 if (!(ch->flags & HDAC_CHN_RUNNING)) 1386 return (0); 1387 1388 /* XXX to be removed */ 1389 #ifdef HDAC_INTR_EXTRA 1390 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1391 #endif 1392 1393 /* XXX to be removed */ 1394 #ifdef HDAC_INTR_EXTRA 1395 HDA_BOOTVERBOSE( 1396 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1397 device_printf(ch->pdevinfo->dev, 1398 "PCMDIR_%s intr triggered beyond stream boundary:" 1399 "%08x\n", 1400 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1401 ); 1402 #endif 1403 1404 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1405 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1406 1407 /* XXX to be removed */ 1408 #ifdef HDAC_INTR_EXTRA 1409 if (res & HDAC_SDSTS_BCIS) { 1410 #endif 1411 return (1); 1412 /* XXX to be removed */ 1413 #ifdef HDAC_INTR_EXTRA 1414 } 1415 #endif 1416 1417 return (0); 1418 } 1419 1420 /**************************************************************************** 1421 * void hdac_intr_handler(void *) 1422 * 1423 * Interrupt handler. Processes interrupts received from the hdac. 1424 ****************************************************************************/ 1425 static void 1426 hdac_intr_handler(void *context) 1427 { 1428 struct hdac_softc *sc; 1429 uint32_t intsts; 1430 uint8_t rirbsts; 1431 struct hdac_rirb *rirb_base; 1432 uint32_t trigger; 1433 int i; 1434 1435 sc = (struct hdac_softc *)context; 1436 1437 hdac_lock(sc); 1438 if (sc->polling != 0) { 1439 hdac_unlock(sc); 1440 return; 1441 } 1442 1443 /* Do we have anything to do? */ 1444 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1445 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1446 hdac_unlock(sc); 1447 return; 1448 } 1449 1450 trigger = 0; 1451 1452 /* Was this a controller interrupt? */ 1453 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1454 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1455 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1456 /* Get as many responses that we can */ 1457 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1458 HDAC_WRITE_1(&sc->mem, 1459 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1460 if (hdac_rirb_flush(sc) != 0) 1461 trigger |= HDAC_TRIGGER_UNSOL; 1462 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1463 } 1464 /* XXX to be removed */ 1465 /* Clear interrupt and exit */ 1466 #ifdef HDAC_INTR_EXTRA 1467 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1468 #endif 1469 } 1470 1471 if (intsts & HDAC_INTSTS_SIS_MASK) { 1472 for (i = 0; i < sc->num_chans; i++) { 1473 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1474 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1475 trigger |= (1 << i); 1476 } 1477 /* XXX to be removed */ 1478 #ifdef HDAC_INTR_EXTRA 1479 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1480 HDAC_INTSTS_SIS_MASK); 1481 #endif 1482 } 1483 1484 hdac_unlock(sc); 1485 1486 for (i = 0; i < sc->num_chans; i++) { 1487 if (trigger & (1 << i)) 1488 chn_intr(sc->chans[i].c); 1489 } 1490 if (trigger & HDAC_TRIGGER_UNSOL) 1491 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1492 } 1493 1494 /**************************************************************************** 1495 * int hdac_reset(hdac_softc *, int) 1496 * 1497 * Reset the hdac to a quiescent and known state. 1498 ****************************************************************************/ 1499 static int 1500 hdac_reset(struct hdac_softc *sc, int wakeup) 1501 { 1502 uint32_t gctl; 1503 int count, i; 1504 1505 /* 1506 * Stop all Streams DMA engine 1507 */ 1508 for (i = 0; i < sc->num_iss; i++) 1509 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1510 for (i = 0; i < sc->num_oss; i++) 1511 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1512 for (i = 0; i < sc->num_bss; i++) 1513 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1514 1515 /* 1516 * Stop Control DMA engines. 1517 */ 1518 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1519 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1520 1521 /* 1522 * Reset DMA position buffer. 1523 */ 1524 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1525 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1526 1527 /* 1528 * Reset the controller. The reset must remain asserted for 1529 * a minimum of 100us. 1530 */ 1531 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1532 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1533 count = 10000; 1534 do { 1535 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1536 if (!(gctl & HDAC_GCTL_CRST)) 1537 break; 1538 DELAY(10); 1539 } while (--count); 1540 if (gctl & HDAC_GCTL_CRST) { 1541 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1542 return (ENXIO); 1543 } 1544 1545 /* If wakeup is not requested - leave the controller in reset state. */ 1546 if (!wakeup) 1547 return (0); 1548 1549 DELAY(100); 1550 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1551 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1552 count = 10000; 1553 do { 1554 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1555 if (gctl & HDAC_GCTL_CRST) 1556 break; 1557 DELAY(10); 1558 } while (--count); 1559 if (!(gctl & HDAC_GCTL_CRST)) { 1560 device_printf(sc->dev, "Device stuck in reset\n"); 1561 return (ENXIO); 1562 } 1563 1564 /* 1565 * Wait for codecs to finish their own reset sequence. The delay here 1566 * should be of 250us but for some reasons, on it's not enough on my 1567 * computer. Let's use twice as much as necessary to make sure that 1568 * it's reset properly. 1569 */ 1570 DELAY(1000); 1571 1572 return (0); 1573 } 1574 1575 1576 /**************************************************************************** 1577 * int hdac_get_capabilities(struct hdac_softc *); 1578 * 1579 * Retreive the general capabilities of the hdac; 1580 * Number of Input Streams 1581 * Number of Output Streams 1582 * Number of bidirectional Streams 1583 * 64bit ready 1584 * CORB and RIRB sizes 1585 ****************************************************************************/ 1586 static int 1587 hdac_get_capabilities(struct hdac_softc *sc) 1588 { 1589 uint16_t gcap; 1590 uint8_t corbsize, rirbsize; 1591 1592 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1593 sc->num_iss = HDAC_GCAP_ISS(gcap); 1594 sc->num_oss = HDAC_GCAP_OSS(gcap); 1595 sc->num_bss = HDAC_GCAP_BSS(gcap); 1596 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1597 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1598 1599 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1600 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1601 HDAC_CORBSIZE_CORBSZCAP_256) 1602 sc->corb_size = 256; 1603 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1604 HDAC_CORBSIZE_CORBSZCAP_16) 1605 sc->corb_size = 16; 1606 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1607 HDAC_CORBSIZE_CORBSZCAP_2) 1608 sc->corb_size = 2; 1609 else { 1610 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1611 __func__, corbsize); 1612 return (ENXIO); 1613 } 1614 1615 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1616 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1617 HDAC_RIRBSIZE_RIRBSZCAP_256) 1618 sc->rirb_size = 256; 1619 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1620 HDAC_RIRBSIZE_RIRBSZCAP_16) 1621 sc->rirb_size = 16; 1622 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1623 HDAC_RIRBSIZE_RIRBSZCAP_2) 1624 sc->rirb_size = 2; 1625 else { 1626 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1627 __func__, rirbsize); 1628 return (ENXIO); 1629 } 1630 1631 HDA_BOOTVERBOSE( 1632 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1633 "NSDO %d%s, CORB %d, RIRB %d\n", 1634 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1635 sc->support_64bit ? ", 64bit" : "", 1636 sc->corb_size, sc->rirb_size); 1637 ); 1638 1639 return (0); 1640 } 1641 1642 1643 /**************************************************************************** 1644 * void hdac_dma_cb 1645 * 1646 * This function is called by bus_dmamap_load when the mapping has been 1647 * established. We just record the physical address of the mapping into 1648 * the struct hdac_dma passed in. 1649 ****************************************************************************/ 1650 static void 1651 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1652 { 1653 struct hdac_dma *dma; 1654 1655 if (error == 0) { 1656 dma = (struct hdac_dma *)callback_arg; 1657 dma->dma_paddr = segs[0].ds_addr; 1658 } 1659 } 1660 1661 1662 /**************************************************************************** 1663 * int hdac_dma_alloc 1664 * 1665 * This function allocate and setup a dma region (struct hdac_dma). 1666 * It must be freed by a corresponding hdac_dma_free. 1667 ****************************************************************************/ 1668 static int 1669 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1670 { 1671 bus_size_t roundsz; 1672 int result; 1673 1674 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1675 bzero(dma, sizeof(*dma)); 1676 1677 /* 1678 * Create a DMA tag 1679 */ 1680 result = bus_dma_tag_create( 1681 bus_get_dma_tag(sc->dev), /* parent */ 1682 HDAC_DMA_ALIGNMENT, /* alignment */ 1683 0, /* boundary */ 1684 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1685 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1686 BUS_SPACE_MAXADDR, /* highaddr */ 1687 NULL, /* filtfunc */ 1688 NULL, /* fistfuncarg */ 1689 roundsz, /* maxsize */ 1690 1, /* nsegments */ 1691 roundsz, /* maxsegsz */ 1692 0, /* flags */ 1693 NULL, /* lockfunc */ 1694 NULL, /* lockfuncarg */ 1695 &dma->dma_tag); /* dmat */ 1696 if (result != 0) { 1697 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1698 __func__, result); 1699 goto hdac_dma_alloc_fail; 1700 } 1701 1702 /* 1703 * Allocate DMA memory 1704 */ 1705 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1706 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1707 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1708 &dma->dma_map); 1709 if (result != 0) { 1710 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1711 __func__, result); 1712 goto hdac_dma_alloc_fail; 1713 } 1714 1715 dma->dma_size = roundsz; 1716 1717 /* 1718 * Map the memory 1719 */ 1720 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1721 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1722 if (result != 0 || dma->dma_paddr == 0) { 1723 if (result == 0) 1724 result = ENOMEM; 1725 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1726 __func__, result); 1727 goto hdac_dma_alloc_fail; 1728 } 1729 1730 HDA_BOOTHVERBOSE( 1731 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1732 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1733 ); 1734 1735 return (0); 1736 1737 hdac_dma_alloc_fail: 1738 hdac_dma_free(sc, dma); 1739 1740 return (result); 1741 } 1742 1743 1744 /**************************************************************************** 1745 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1746 * 1747 * Free a struct dhac_dma that has been previously allocated via the 1748 * hdac_dma_alloc function. 1749 ****************************************************************************/ 1750 static void 1751 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1752 { 1753 if (dma->dma_map != NULL) { 1754 #if 0 1755 /* Flush caches */ 1756 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1757 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1758 #endif 1759 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1760 } 1761 if (dma->dma_vaddr != NULL) { 1762 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1763 dma->dma_vaddr = NULL; 1764 } 1765 dma->dma_map = NULL; 1766 if (dma->dma_tag != NULL) { 1767 bus_dma_tag_destroy(dma->dma_tag); 1768 dma->dma_tag = NULL; 1769 } 1770 dma->dma_size = 0; 1771 } 1772 1773 /**************************************************************************** 1774 * int hdac_mem_alloc(struct hdac_softc *) 1775 * 1776 * Allocate all the bus resources necessary to speak with the physical 1777 * controller. 1778 ****************************************************************************/ 1779 static int 1780 hdac_mem_alloc(struct hdac_softc *sc) 1781 { 1782 struct hdac_mem *mem; 1783 1784 mem = &sc->mem; 1785 mem->mem_rid = PCIR_BAR(0); 1786 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1787 &mem->mem_rid, RF_ACTIVE); 1788 if (mem->mem_res == NULL) { 1789 device_printf(sc->dev, 1790 "%s: Unable to allocate memory resource\n", __func__); 1791 return (ENOMEM); 1792 } 1793 mem->mem_tag = rman_get_bustag(mem->mem_res); 1794 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1795 1796 return (0); 1797 } 1798 1799 /**************************************************************************** 1800 * void hdac_mem_free(struct hdac_softc *) 1801 * 1802 * Free up resources previously allocated by hdac_mem_alloc. 1803 ****************************************************************************/ 1804 static void 1805 hdac_mem_free(struct hdac_softc *sc) 1806 { 1807 struct hdac_mem *mem; 1808 1809 mem = &sc->mem; 1810 if (mem->mem_res != NULL) 1811 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1812 mem->mem_res); 1813 mem->mem_res = NULL; 1814 } 1815 1816 /**************************************************************************** 1817 * int hdac_irq_alloc(struct hdac_softc *) 1818 * 1819 * Allocate and setup the resources necessary for interrupt handling. 1820 ****************************************************************************/ 1821 static int 1822 hdac_irq_alloc(struct hdac_softc *sc) 1823 { 1824 struct hdac_irq *irq; 1825 int result; 1826 1827 irq = &sc->irq; 1828 irq->irq_rid = 0x0; 1829 1830 if ((sc->flags & HDAC_F_MSI) && 1831 (result = pci_msi_count(sc->dev)) == 1 && 1832 pci_alloc_msi(sc->dev, &result) == 0) 1833 irq->irq_rid = 0x1; 1834 else 1835 sc->flags &= ~HDAC_F_MSI; 1836 1837 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1838 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1839 if (irq->irq_res == NULL) { 1840 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1841 __func__); 1842 goto hdac_irq_alloc_fail; 1843 } 1844 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1845 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1846 if (result != 0) { 1847 device_printf(sc->dev, 1848 "%s: Unable to setup interrupt handler (%x)\n", 1849 __func__, result); 1850 goto hdac_irq_alloc_fail; 1851 } 1852 1853 return (0); 1854 1855 hdac_irq_alloc_fail: 1856 hdac_irq_free(sc); 1857 1858 return (ENXIO); 1859 } 1860 1861 /**************************************************************************** 1862 * void hdac_irq_free(struct hdac_softc *) 1863 * 1864 * Free up resources previously allocated by hdac_irq_alloc. 1865 ****************************************************************************/ 1866 static void 1867 hdac_irq_free(struct hdac_softc *sc) 1868 { 1869 struct hdac_irq *irq; 1870 1871 irq = &sc->irq; 1872 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1873 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1874 if (irq->irq_res != NULL) 1875 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1876 irq->irq_res); 1877 if (irq->irq_rid == 0x1) 1878 pci_release_msi(sc->dev); 1879 irq->irq_handle = NULL; 1880 irq->irq_res = NULL; 1881 irq->irq_rid = 0x0; 1882 } 1883 1884 /**************************************************************************** 1885 * void hdac_corb_init(struct hdac_softc *) 1886 * 1887 * Initialize the corb registers for operations but do not start it up yet. 1888 * The CORB engine must not be running when this function is called. 1889 ****************************************************************************/ 1890 static void 1891 hdac_corb_init(struct hdac_softc *sc) 1892 { 1893 uint8_t corbsize; 1894 uint64_t corbpaddr; 1895 1896 /* Setup the CORB size. */ 1897 switch (sc->corb_size) { 1898 case 256: 1899 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1900 break; 1901 case 16: 1902 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1903 break; 1904 case 2: 1905 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1906 break; 1907 default: 1908 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1909 } 1910 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1911 1912 /* Setup the CORB Address in the hdac */ 1913 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1914 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1915 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1916 1917 /* Set the WP and RP */ 1918 sc->corb_wp = 0; 1919 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1920 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1921 /* 1922 * The HDA specification indicates that the CORBRPRST bit will always 1923 * read as zero. Unfortunately, it seems that at least the 82801G 1924 * doesn't reset the bit to zero, which stalls the corb engine. 1925 * manually reset the bit to zero before continuing. 1926 */ 1927 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1928 1929 /* Enable CORB error reporting */ 1930 #if 0 1931 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1932 #endif 1933 } 1934 1935 /**************************************************************************** 1936 * void hdac_rirb_init(struct hdac_softc *) 1937 * 1938 * Initialize the rirb registers for operations but do not start it up yet. 1939 * The RIRB engine must not be running when this function is called. 1940 ****************************************************************************/ 1941 static void 1942 hdac_rirb_init(struct hdac_softc *sc) 1943 { 1944 uint8_t rirbsize; 1945 uint64_t rirbpaddr; 1946 1947 /* Setup the RIRB size. */ 1948 switch (sc->rirb_size) { 1949 case 256: 1950 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1951 break; 1952 case 16: 1953 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1954 break; 1955 case 2: 1956 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1957 break; 1958 default: 1959 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1960 } 1961 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1962 1963 /* Setup the RIRB Address in the hdac */ 1964 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1965 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1966 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1967 1968 /* Setup the WP and RP */ 1969 sc->rirb_rp = 0; 1970 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1971 1972 /* Setup the interrupt threshold */ 1973 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1974 1975 /* Enable Overrun and response received reporting */ 1976 #if 0 1977 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1978 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1979 #else 1980 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1981 #endif 1982 1983 #if 0 1984 /* 1985 * Make sure that the Host CPU cache doesn't contain any dirty 1986 * cache lines that falls in the rirb. If I understood correctly, it 1987 * should be sufficient to do this only once as the rirb is purely 1988 * read-only from now on. 1989 */ 1990 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1991 BUS_DMASYNC_PREREAD); 1992 #endif 1993 } 1994 1995 /**************************************************************************** 1996 * void hdac_corb_start(hdac_softc *) 1997 * 1998 * Startup the corb DMA engine 1999 ****************************************************************************/ 2000 static void 2001 hdac_corb_start(struct hdac_softc *sc) 2002 { 2003 uint32_t corbctl; 2004 2005 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 2006 corbctl |= HDAC_CORBCTL_CORBRUN; 2007 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 2008 } 2009 2010 /**************************************************************************** 2011 * void hdac_rirb_start(hdac_softc *) 2012 * 2013 * Startup the rirb DMA engine 2014 ****************************************************************************/ 2015 static void 2016 hdac_rirb_start(struct hdac_softc *sc) 2017 { 2018 uint32_t rirbctl; 2019 2020 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 2021 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 2022 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 2023 } 2024 2025 2026 /**************************************************************************** 2027 * void hdac_scan_codecs(struct hdac_softc *, int) 2028 * 2029 * Scan the bus for available codecs, starting with num. 2030 ****************************************************************************/ 2031 static void 2032 hdac_scan_codecs(struct hdac_softc *sc) 2033 { 2034 struct hdac_codec *codec; 2035 int i; 2036 uint16_t statests; 2037 2038 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 2039 for (i = 0; i < HDAC_CODEC_MAX; i++) { 2040 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 2041 /* We have found a codec. */ 2042 codec = (struct hdac_codec *)malloc(sizeof(*codec), 2043 M_HDAC, M_ZERO | M_NOWAIT); 2044 if (codec == NULL) { 2045 device_printf(sc->dev, 2046 "Unable to allocate memory for codec\n"); 2047 continue; 2048 } 2049 codec->commands = NULL; 2050 codec->responses_received = 0; 2051 codec->verbs_sent = 0; 2052 codec->sc = sc; 2053 codec->cad = i; 2054 sc->codecs[i] = codec; 2055 hdac_probe_codec(codec); 2056 } 2057 } 2058 /* All codecs have been probed, now try to attach drivers to them */ 2059 /* bus_generic_attach(sc->dev); */ 2060 } 2061 2062 /**************************************************************************** 2063 * void hdac_probe_codec(struct hdac_softc *, int) 2064 * 2065 * Probe a the given codec_id for available function groups. 2066 ****************************************************************************/ 2067 static void 2068 hdac_probe_codec(struct hdac_codec *codec) 2069 { 2070 struct hdac_softc *sc = codec->sc; 2071 uint32_t vendorid, revisionid, subnode; 2072 int startnode; 2073 int endnode; 2074 int i; 2075 nid_t cad = codec->cad; 2076 2077 HDA_BOOTVERBOSE( 2078 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2079 ); 2080 vendorid = hdac_command(sc, 2081 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2082 cad); 2083 revisionid = hdac_command(sc, 2084 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2085 cad); 2086 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2087 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2088 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2089 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2090 2091 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2092 device_printf(sc->dev, "Codec #%d is not responding!" 2093 " Probing aborted.\n", cad); 2094 return; 2095 } 2096 2097 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2098 cad, hdac_codec_name(codec)); 2099 HDA_BOOTVERBOSE( 2100 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2101 hdac_codec_id(codec)); 2102 device_printf(sc->dev, " Vendor: 0x%04x\n", 2103 codec->vendor_id); 2104 device_printf(sc->dev, " Device: 0x%04x\n", 2105 codec->device_id); 2106 device_printf(sc->dev, " Revision: 0x%02x\n", 2107 codec->revision_id); 2108 device_printf(sc->dev, " Stepping: 0x%02x\n", 2109 codec->stepping_id); 2110 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2111 sc->pci_subvendor); 2112 ); 2113 subnode = hdac_command(sc, 2114 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2115 cad); 2116 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2117 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2118 2119 HDA_BOOTHVERBOSE( 2120 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2121 startnode, endnode); 2122 ); 2123 2124 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2125 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2126 if (codec->fgs == NULL) { 2127 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2128 __func__); 2129 return; 2130 } 2131 2132 for (i = startnode; i < endnode; i++) 2133 hdac_probe_function(codec, i); 2134 return; 2135 } 2136 2137 /* 2138 * Probe codec function and add it to the list. 2139 */ 2140 static void 2141 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2142 { 2143 struct hdac_softc *sc = codec->sc; 2144 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2145 uint32_t fctgrptype; 2146 uint32_t res; 2147 nid_t cad = codec->cad; 2148 2149 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2150 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2151 2152 devinfo->nid = nid; 2153 devinfo->node_type = fctgrptype; 2154 devinfo->codec = codec; 2155 2156 res = hdac_command(sc, 2157 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2158 2159 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2160 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2161 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2162 2163 HDA_BOOTVERBOSE( 2164 device_printf(sc->dev, 2165 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2166 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2167 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2168 "unknown", nid, devinfo->startnode, devinfo->endnode, 2169 devinfo->nodecnt); 2170 ); 2171 2172 if (devinfo->nodecnt > 0) 2173 devinfo->widget = (struct hdac_widget *)malloc( 2174 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2175 M_NOWAIT | M_ZERO); 2176 else 2177 devinfo->widget = NULL; 2178 2179 if (devinfo->widget == NULL) { 2180 device_printf(sc->dev, "unable to allocate widgets!\n"); 2181 devinfo->endnode = devinfo->startnode; 2182 devinfo->nodecnt = 0; 2183 return; 2184 } 2185 2186 codec->num_fgs++; 2187 } 2188 2189 static void 2190 hdac_widget_connection_parse(struct hdac_widget *w) 2191 { 2192 struct hdac_softc *sc = w->devinfo->codec->sc; 2193 uint32_t res; 2194 int i, j, max, ents, entnum; 2195 nid_t cad = w->devinfo->codec->cad; 2196 nid_t nid = w->nid; 2197 nid_t cnid, addcnid, prevcnid; 2198 2199 w->nconns = 0; 2200 2201 res = hdac_command(sc, 2202 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2203 2204 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2205 2206 if (ents < 1) 2207 return; 2208 2209 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2210 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2211 prevcnid = 0; 2212 2213 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2214 #define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2215 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2216 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2217 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2218 2219 for (i = 0; i < ents; i += entnum) { 2220 res = hdac_command(sc, 2221 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2222 for (j = 0; j < entnum; j++) { 2223 cnid = CONN_CNID(res, entnum, j); 2224 if (cnid == 0) { 2225 if (w->nconns < ents) 2226 device_printf(sc->dev, 2227 "%s: nid=%d WARNING: zero cnid " 2228 "entnum=%d j=%d index=%d " 2229 "entries=%d found=%d res=0x%08x\n", 2230 __func__, nid, entnum, j, i, 2231 ents, w->nconns, res); 2232 else 2233 goto getconns_out; 2234 } 2235 if (cnid < w->devinfo->startnode || 2236 cnid >= w->devinfo->endnode) { 2237 HDA_BOOTVERBOSE( 2238 device_printf(sc->dev, 2239 "GHOST: nid=%d j=%d " 2240 "entnum=%d index=%d res=0x%08x\n", 2241 nid, j, entnum, i, res); 2242 ); 2243 } 2244 if (CONN_RANGE(res, entnum, j) == 0) 2245 addcnid = cnid; 2246 else if (prevcnid == 0 || prevcnid >= cnid) { 2247 device_printf(sc->dev, 2248 "%s: WARNING: Invalid child range " 2249 "nid=%d index=%d j=%d entnum=%d " 2250 "prevcnid=%d cnid=%d res=0x%08x\n", 2251 __func__, nid, i, j, entnum, prevcnid, 2252 cnid, res); 2253 addcnid = cnid; 2254 } else 2255 addcnid = prevcnid + 1; 2256 while (addcnid <= cnid) { 2257 if (w->nconns > max) { 2258 device_printf(sc->dev, 2259 "Adding %d (nid=%d): " 2260 "Max connection reached! max=%d\n", 2261 addcnid, nid, max + 1); 2262 goto getconns_out; 2263 } 2264 w->connsenable[w->nconns] = 1; 2265 w->conns[w->nconns++] = addcnid++; 2266 } 2267 prevcnid = cnid; 2268 } 2269 } 2270 2271 getconns_out: 2272 return; 2273 } 2274 2275 static uint32_t 2276 hdac_widget_pin_patch(uint32_t config, const char *str) 2277 { 2278 char buf[256]; 2279 char *key, *value, *rest, *bad; 2280 int ival, i; 2281 2282 strlcpy(buf, str, sizeof(buf)); 2283 rest = buf; 2284 while ((key = strsep(&rest, "=")) != NULL) { 2285 value = strsep(&rest, " \t"); 2286 if (value == NULL) 2287 break; 2288 ival = strtol(value, &bad, 10); 2289 if (strcmp(key, "seq") == 0) { 2290 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2291 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2292 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2293 } else if (strcmp(key, "as") == 0) { 2294 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2295 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2296 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2297 } else if (strcmp(key, "misc") == 0) { 2298 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2299 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2300 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2301 } else if (strcmp(key, "color") == 0) { 2302 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2303 if (bad[0] == 0) { 2304 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2305 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2306 }; 2307 for (i = 0; i < 16; i++) { 2308 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2309 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2310 break; 2311 } 2312 } 2313 } else if (strcmp(key, "ctype") == 0) { 2314 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2315 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2316 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2317 } else if (strcmp(key, "device") == 0) { 2318 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2319 if (bad[0] == 0) { 2320 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2321 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2322 continue; 2323 }; 2324 for (i = 0; i < 16; i++) { 2325 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2326 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2327 break; 2328 } 2329 } 2330 } else if (strcmp(key, "loc") == 0) { 2331 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2332 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2333 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2334 } else if (strcmp(key, "conn") == 0) { 2335 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2336 if (bad[0] == 0) { 2337 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2338 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2339 continue; 2340 }; 2341 for (i = 0; i < 4; i++) { 2342 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2343 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2344 break; 2345 } 2346 } 2347 } 2348 } 2349 return (config); 2350 } 2351 2352 static uint32_t 2353 hdac_widget_pin_getconfig(struct hdac_widget *w) 2354 { 2355 struct hdac_softc *sc; 2356 uint32_t config, orig, id; 2357 nid_t cad, nid; 2358 char buf[32]; 2359 const char *res = NULL, *patch = NULL; 2360 2361 sc = w->devinfo->codec->sc; 2362 cad = w->devinfo->codec->cad; 2363 nid = w->nid; 2364 id = hdac_codec_id(w->devinfo->codec); 2365 2366 config = hdac_command(sc, 2367 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2368 cad); 2369 orig = config; 2370 2371 HDA_BOOTVERBOSE( 2372 hdac_dump_pin_config(w, orig); 2373 ); 2374 2375 /* XXX: Old patches require complete review. 2376 * Now they may create more problem then solve due to 2377 * incorrect associations. 2378 */ 2379 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2380 switch (nid) { 2381 case 26: 2382 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2383 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2384 break; 2385 case 27: 2386 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2387 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2388 break; 2389 default: 2390 break; 2391 } 2392 } else if (id == HDA_CODEC_ALC880 && 2393 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2394 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2395 /* 2396 * Super broken BIOS 2397 */ 2398 switch (nid) { 2399 case 24: /* MIC1 */ 2400 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2401 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2402 break; 2403 case 25: /* XXX MIC2 */ 2404 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2405 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2406 break; 2407 case 26: /* LINE1 */ 2408 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2409 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2410 break; 2411 case 27: /* XXX LINE2 */ 2412 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2413 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2414 break; 2415 case 28: /* CD */ 2416 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2417 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2418 break; 2419 } 2420 } else if (id == HDA_CODEC_ALC883 && 2421 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2422 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2423 switch (nid) { 2424 case 25: 2425 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2426 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2427 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2428 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2429 break; 2430 case 28: 2431 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2432 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2433 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2434 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2435 break; 2436 } 2437 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2438 HP_V3000_SUBVENDOR) { 2439 switch (nid) { 2440 case 18: 2441 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2442 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2443 break; 2444 case 20: 2445 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2446 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2447 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2448 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2449 break; 2450 case 21: 2451 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2452 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2453 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2454 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2455 break; 2456 } 2457 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2458 HP_DV5000_SUBVENDOR) { 2459 switch (nid) { 2460 case 20: 2461 case 21: 2462 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2463 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2464 break; 2465 } 2466 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2467 ASUS_W6F_SUBVENDOR) { 2468 switch (nid) { 2469 case 11: 2470 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2471 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2472 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2473 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2474 break; 2475 case 12: 2476 case 14: 2477 case 16: 2478 case 31: 2479 case 32: 2480 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2481 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2482 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2483 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2484 break; 2485 case 15: 2486 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2487 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2488 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2489 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2490 break; 2491 } 2492 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2493 UNIWILL_9075_SUBVENDOR) { 2494 switch (nid) { 2495 case 15: 2496 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2497 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2498 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2499 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2500 break; 2501 } 2502 } 2503 2504 /* New patches */ 2505 if (id == HDA_CODEC_AD1986A && 2506 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2507 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2508 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2509 switch (nid) { 2510 case 26: /* Headphones with redirection */ 2511 patch = "as=1 seq=15"; 2512 break; 2513 case 28: /* 5.1 out => 2.0 out + 1 input */ 2514 patch = "device=Line-in as=8 seq=1"; 2515 break; 2516 case 29: /* Can't use this as input, as the only available mic 2517 * preamplifier is busy by front panel mic (nid 31). 2518 * If you want to use this rear connector as mic input, 2519 * you have to disable the front panel one. */ 2520 patch = "as=0"; 2521 break; 2522 case 31: /* Lot of inputs configured with as=15 and unusable */ 2523 patch = "as=8 seq=3"; 2524 break; 2525 case 32: 2526 patch = "as=8 seq=4"; 2527 break; 2528 case 34: 2529 patch = "as=8 seq=5"; 2530 break; 2531 case 36: 2532 patch = "as=8 seq=6"; 2533 break; 2534 } 2535 } else if (id == HDA_CODEC_ALC260 && 2536 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2537 switch (nid) { 2538 case 16: 2539 patch = "seq=15 device=Headphones"; 2540 break; 2541 } 2542 } else if (id == HDA_CODEC_ALC268) { 2543 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2544 switch (nid) { 2545 case 20: /* Headphones Jack */ 2546 patch = "as=1 seq=15"; 2547 break; 2548 } 2549 } 2550 } 2551 2552 if (patch != NULL) 2553 config = hdac_widget_pin_patch(config, patch); 2554 2555 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2556 if (resource_string_value(device_get_name(sc->dev), 2557 device_get_unit(sc->dev), buf, &res) == 0) { 2558 if (strncmp(res, "0x", 2) == 0) { 2559 config = strtol(res + 2, NULL, 16); 2560 } else { 2561 config = hdac_widget_pin_patch(config, res); 2562 } 2563 } 2564 2565 HDA_BOOTVERBOSE( 2566 if (config != orig) 2567 device_printf(sc->dev, 2568 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2569 nid, orig, config); 2570 ); 2571 2572 return (config); 2573 } 2574 2575 static uint32_t 2576 hdac_widget_pin_getcaps(struct hdac_widget *w) 2577 { 2578 struct hdac_softc *sc; 2579 uint32_t caps, orig, id; 2580 nid_t cad, nid; 2581 2582 sc = w->devinfo->codec->sc; 2583 cad = w->devinfo->codec->cad; 2584 nid = w->nid; 2585 id = hdac_codec_id(w->devinfo->codec); 2586 2587 caps = hdac_command(sc, 2588 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2589 orig = caps; 2590 2591 HDA_BOOTVERBOSE( 2592 if (caps != orig) 2593 device_printf(sc->dev, 2594 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2595 nid, orig, caps); 2596 ); 2597 2598 return (caps); 2599 } 2600 2601 static void 2602 hdac_widget_pin_parse(struct hdac_widget *w) 2603 { 2604 struct hdac_softc *sc = w->devinfo->codec->sc; 2605 uint32_t config, pincap; 2606 const char *devstr; 2607 nid_t cad = w->devinfo->codec->cad; 2608 nid_t nid = w->nid; 2609 int conn, color; 2610 2611 config = hdac_widget_pin_getconfig(w); 2612 w->wclass.pin.config = config; 2613 2614 pincap = hdac_widget_pin_getcaps(w); 2615 w->wclass.pin.cap = pincap; 2616 2617 w->wclass.pin.ctrl = hdac_command(sc, 2618 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2619 2620 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2621 w->param.eapdbtl = hdac_command(sc, 2622 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2623 w->param.eapdbtl &= 0x7; 2624 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2625 } else 2626 w->param.eapdbtl = HDAC_INVALID; 2627 2628 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2629 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2630 2631 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2632 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2633 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2634 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2635 2636 strlcat(w->name, ": ", sizeof(w->name)); 2637 strlcat(w->name, devstr, sizeof(w->name)); 2638 strlcat(w->name, " (", sizeof(w->name)); 2639 if (conn == 0 && color != 0 && color != 15) { 2640 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2641 strlcat(w->name, " ", sizeof(w->name)); 2642 } 2643 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2644 strlcat(w->name, ")", sizeof(w->name)); 2645 } 2646 2647 static uint32_t 2648 hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2649 { 2650 struct hdac_softc *sc; 2651 uint32_t caps, orig, id; 2652 nid_t cad, nid, beeper = -1; 2653 2654 sc = w->devinfo->codec->sc; 2655 cad = w->devinfo->codec->cad; 2656 nid = w->nid; 2657 id = hdac_codec_id(w->devinfo->codec); 2658 2659 caps = hdac_command(sc, 2660 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2661 cad); 2662 orig = caps; 2663 2664 /* On some codecs beeper is an input pin, but it is not recordable 2665 alone. Also most of BIOSes does not declare beeper pin. 2666 Change beeper pin node type to beeper to help parser. */ 2667 *waspin = 0; 2668 switch (id) { 2669 case HDA_CODEC_AD1882: 2670 case HDA_CODEC_AD1883: 2671 case HDA_CODEC_AD1984: 2672 case HDA_CODEC_AD1984A: 2673 case HDA_CODEC_AD1984B: 2674 case HDA_CODEC_AD1987: 2675 case HDA_CODEC_AD1988: 2676 case HDA_CODEC_AD1988B: 2677 case HDA_CODEC_AD1989B: 2678 beeper = 26; 2679 break; 2680 case HDA_CODEC_ALC260: 2681 beeper = 23; 2682 break; 2683 case HDA_CODEC_ALC262: 2684 case HDA_CODEC_ALC268: 2685 case HDA_CODEC_ALC880: 2686 case HDA_CODEC_ALC882: 2687 case HDA_CODEC_ALC883: 2688 case HDA_CODEC_ALC885: 2689 case HDA_CODEC_ALC888: 2690 case HDA_CODEC_ALC889: 2691 beeper = 29; 2692 break; 2693 } 2694 if (nid == beeper) { 2695 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2696 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2697 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2698 *waspin = 1; 2699 } 2700 2701 HDA_BOOTVERBOSE( 2702 if (caps != orig) { 2703 device_printf(sc->dev, 2704 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2705 nid, orig, caps); 2706 } 2707 ); 2708 2709 return (caps); 2710 } 2711 2712 static void 2713 hdac_widget_parse(struct hdac_widget *w) 2714 { 2715 struct hdac_softc *sc = w->devinfo->codec->sc; 2716 uint32_t wcap, cap; 2717 char *typestr; 2718 nid_t cad = w->devinfo->codec->cad; 2719 nid_t nid = w->nid; 2720 2721 wcap = hdac_widget_getcaps(w, &w->waspin); 2722 2723 w->param.widget_cap = wcap; 2724 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2725 2726 switch (w->type) { 2727 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2728 typestr = "audio output"; 2729 break; 2730 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2731 typestr = "audio input"; 2732 break; 2733 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2734 typestr = "audio mixer"; 2735 break; 2736 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2737 typestr = "audio selector"; 2738 break; 2739 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2740 typestr = "pin"; 2741 break; 2742 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2743 typestr = "power widget"; 2744 break; 2745 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2746 typestr = "volume widget"; 2747 break; 2748 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2749 typestr = "beep widget"; 2750 break; 2751 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2752 typestr = "vendor widget"; 2753 break; 2754 default: 2755 typestr = "unknown type"; 2756 break; 2757 } 2758 2759 strlcpy(w->name, typestr, sizeof(w->name)); 2760 2761 hdac_widget_connection_parse(w); 2762 2763 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2764 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2765 w->param.outamp_cap = 2766 hdac_command(sc, 2767 HDA_CMD_GET_PARAMETER(cad, nid, 2768 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2769 else 2770 w->param.outamp_cap = 2771 w->devinfo->function.audio.outamp_cap; 2772 } else 2773 w->param.outamp_cap = 0; 2774 2775 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2776 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2777 w->param.inamp_cap = 2778 hdac_command(sc, 2779 HDA_CMD_GET_PARAMETER(cad, nid, 2780 HDA_PARAM_INPUT_AMP_CAP), cad); 2781 else 2782 w->param.inamp_cap = 2783 w->devinfo->function.audio.inamp_cap; 2784 } else 2785 w->param.inamp_cap = 0; 2786 2787 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2788 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2789 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2790 cap = hdac_command(sc, 2791 HDA_CMD_GET_PARAMETER(cad, nid, 2792 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2793 w->param.supp_stream_formats = (cap != 0) ? cap : 2794 w->devinfo->function.audio.supp_stream_formats; 2795 cap = hdac_command(sc, 2796 HDA_CMD_GET_PARAMETER(cad, nid, 2797 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2798 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2799 w->devinfo->function.audio.supp_pcm_size_rate; 2800 } else { 2801 w->param.supp_stream_formats = 2802 w->devinfo->function.audio.supp_stream_formats; 2803 w->param.supp_pcm_size_rate = 2804 w->devinfo->function.audio.supp_pcm_size_rate; 2805 } 2806 } else { 2807 w->param.supp_stream_formats = 0; 2808 w->param.supp_pcm_size_rate = 0; 2809 } 2810 2811 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2812 hdac_widget_pin_parse(w); 2813 } 2814 2815 static struct hdac_widget * 2816 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2817 { 2818 if (devinfo == NULL || devinfo->widget == NULL || 2819 nid < devinfo->startnode || nid >= devinfo->endnode) 2820 return (NULL); 2821 return (&devinfo->widget[nid - devinfo->startnode]); 2822 } 2823 2824 static __inline int 2825 hda_poll_channel(struct hdac_chan *ch) 2826 { 2827 uint32_t sz, delta; 2828 volatile uint32_t ptr; 2829 2830 if (!(ch->flags & HDAC_CHN_RUNNING)) 2831 return (0); 2832 2833 sz = ch->blksz * ch->blkcnt; 2834 if (ch->dmapos != NULL) 2835 ptr = *(ch->dmapos); 2836 else 2837 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2838 ch->off + HDAC_SDLPIB); 2839 ch->ptr = ptr; 2840 ptr %= sz; 2841 ptr &= ~(ch->blksz - 1); 2842 delta = (sz + ptr - ch->prevptr) % sz; 2843 2844 if (delta < ch->blksz) 2845 return (0); 2846 2847 ch->prevptr = ptr; 2848 2849 return (1); 2850 } 2851 2852 static void 2853 hda_poll_callback(void *arg) 2854 { 2855 struct hdac_softc *sc = arg; 2856 uint32_t trigger; 2857 int i, active = 0; 2858 2859 if (sc == NULL) 2860 return; 2861 2862 hdac_lock(sc); 2863 if (sc->polling == 0) { 2864 hdac_unlock(sc); 2865 return; 2866 } 2867 2868 trigger = 0; 2869 for (i = 0; i < sc->num_chans; i++) { 2870 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2871 continue; 2872 active = 1; 2873 if (hda_poll_channel(&sc->chans[i])) 2874 trigger |= (1 << i); 2875 } 2876 2877 /* XXX */ 2878 if (active) 2879 callout_reset(&sc->poll_hda, sc->poll_ticks, 2880 hda_poll_callback, sc); 2881 2882 hdac_unlock(sc); 2883 2884 for (i = 0; i < sc->num_chans; i++) { 2885 if (trigger & (1 << i)) 2886 chn_intr(sc->chans[i].c); 2887 } 2888 } 2889 2890 static int 2891 hdac_rirb_flush(struct hdac_softc *sc) 2892 { 2893 struct hdac_rirb *rirb_base, *rirb; 2894 struct hdac_codec *codec; 2895 struct hdac_command_list *commands; 2896 nid_t cad; 2897 uint32_t resp; 2898 uint8_t rirbwp; 2899 int ret; 2900 2901 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2902 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2903 #if 0 2904 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2905 BUS_DMASYNC_POSTREAD); 2906 #endif 2907 2908 ret = 0; 2909 2910 while (sc->rirb_rp != rirbwp) { 2911 sc->rirb_rp++; 2912 sc->rirb_rp %= sc->rirb_size; 2913 rirb = &rirb_base[sc->rirb_rp]; 2914 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2915 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2916 sc->codecs[cad] == NULL) 2917 continue; 2918 resp = rirb->response; 2919 codec = sc->codecs[cad]; 2920 commands = codec->commands; 2921 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2922 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2923 ((resp >> 26) & 0xffff); 2924 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2925 } else if (commands != NULL && commands->num_commands > 0 && 2926 codec->responses_received < commands->num_commands) 2927 commands->responses[codec->responses_received++] = 2928 resp; 2929 ret++; 2930 } 2931 2932 return (ret); 2933 } 2934 2935 static int 2936 hdac_unsolq_flush(struct hdac_softc *sc) 2937 { 2938 nid_t cad; 2939 uint32_t tag; 2940 int ret = 0; 2941 2942 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2943 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2944 while (sc->unsolq_rp != sc->unsolq_wp) { 2945 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2946 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2947 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2948 hdac_unsolicited_handler(sc->codecs[cad], tag); 2949 ret++; 2950 } 2951 sc->unsolq_st = HDAC_UNSOLQ_READY; 2952 } 2953 2954 return (ret); 2955 } 2956 2957 static void 2958 hdac_poll_callback(void *arg) 2959 { 2960 struct hdac_softc *sc = arg; 2961 if (sc == NULL) 2962 return; 2963 2964 hdac_lock(sc); 2965 if (sc->polling == 0 || sc->poll_ival == 0) { 2966 hdac_unlock(sc); 2967 return; 2968 } 2969 if (hdac_rirb_flush(sc) != 0) 2970 hdac_unsolq_flush(sc); 2971 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2972 hdac_unlock(sc); 2973 } 2974 2975 static void 2976 hdac_poll_reinit(struct hdac_softc *sc) 2977 { 2978 int i, pollticks, min = 1000000; 2979 struct hdac_chan *ch; 2980 2981 for (i = 0; i < sc->num_chans; i++) { 2982 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2983 continue; 2984 ch = &sc->chans[i]; 2985 pollticks = ((uint64_t)hz * ch->blksz) / 2986 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2987 pollticks >>= 1; 2988 if (pollticks > hz) 2989 pollticks = hz; 2990 if (pollticks < 1) { 2991 HDA_BOOTVERBOSE( 2992 device_printf(sc->dev, 2993 "%s: pollticks=%d < 1 !\n", 2994 __func__, pollticks); 2995 ); 2996 pollticks = 1; 2997 } 2998 if (min > pollticks) 2999 min = pollticks; 3000 } 3001 HDA_BOOTVERBOSE( 3002 device_printf(sc->dev, 3003 "%s: pollticks %d -> %d\n", 3004 __func__, sc->poll_ticks, min); 3005 ); 3006 sc->poll_ticks = min; 3007 if (min == 1000000) 3008 callout_stop(&sc->poll_hda); 3009 else 3010 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 3011 } 3012 3013 static void 3014 hdac_stream_stop(struct hdac_chan *ch) 3015 { 3016 struct hdac_softc *sc = ch->devinfo->codec->sc; 3017 uint32_t ctl; 3018 3019 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3020 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3021 HDAC_SDCTL_RUN); 3022 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3023 3024 ch->flags &= ~HDAC_CHN_RUNNING; 3025 3026 if (sc->polling != 0) 3027 hdac_poll_reinit(sc); 3028 3029 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3030 ctl &= ~(1 << (ch->off >> 5)); 3031 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3032 } 3033 3034 static void 3035 hdac_stream_start(struct hdac_chan *ch) 3036 { 3037 struct hdac_softc *sc = ch->devinfo->codec->sc; 3038 uint32_t ctl; 3039 3040 ch->flags |= HDAC_CHN_RUNNING; 3041 3042 if (sc->polling != 0) 3043 hdac_poll_reinit(sc); 3044 3045 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3046 ctl |= 1 << (ch->off >> 5); 3047 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3048 3049 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3050 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3051 HDAC_SDCTL_RUN; 3052 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3053 } 3054 3055 static void 3056 hdac_stream_reset(struct hdac_chan *ch) 3057 { 3058 struct hdac_softc *sc = ch->devinfo->codec->sc; 3059 int timeout = 1000; 3060 int to = timeout; 3061 uint32_t ctl; 3062 3063 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3064 ctl |= HDAC_SDCTL_SRST; 3065 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3066 do { 3067 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3068 if (ctl & HDAC_SDCTL_SRST) 3069 break; 3070 DELAY(10); 3071 } while (--to); 3072 if (!(ctl & HDAC_SDCTL_SRST)) { 3073 device_printf(sc->dev, "timeout in reset\n"); 3074 } 3075 ctl &= ~HDAC_SDCTL_SRST; 3076 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3077 to = timeout; 3078 do { 3079 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3080 if (!(ctl & HDAC_SDCTL_SRST)) 3081 break; 3082 DELAY(10); 3083 } while (--to); 3084 if (ctl & HDAC_SDCTL_SRST) 3085 device_printf(sc->dev, "can't reset!\n"); 3086 } 3087 3088 static void 3089 hdac_stream_setid(struct hdac_chan *ch) 3090 { 3091 struct hdac_softc *sc = ch->devinfo->codec->sc; 3092 uint32_t ctl; 3093 3094 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3095 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3096 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3097 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3098 } 3099 3100 static void 3101 hdac_bdl_setup(struct hdac_chan *ch) 3102 { 3103 struct hdac_softc *sc = ch->devinfo->codec->sc; 3104 struct hdac_bdle *bdle; 3105 uint64_t addr; 3106 uint32_t blksz, blkcnt; 3107 int i; 3108 3109 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3110 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3111 3112 blksz = ch->blksz; 3113 blkcnt = ch->blkcnt; 3114 3115 for (i = 0; i < blkcnt; i++, bdle++) { 3116 bdle->addrl = (uint32_t)addr; 3117 bdle->addrh = (uint32_t)(addr >> 32); 3118 bdle->len = blksz; 3119 bdle->ioc = 1; 3120 addr += blksz; 3121 } 3122 3123 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3124 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3125 addr = ch->bdl_dma.dma_paddr; 3126 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3127 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3128 if (ch->dmapos != NULL && 3129 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3130 addr = sc->pos_dma.dma_paddr; 3131 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3132 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3133 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3134 } 3135 } 3136 3137 static int 3138 hdac_bdl_alloc(struct hdac_chan *ch) 3139 { 3140 struct hdac_softc *sc = ch->devinfo->codec->sc; 3141 int rc; 3142 3143 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3144 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3145 if (rc) { 3146 device_printf(sc->dev, "can't alloc bdl\n"); 3147 return (rc); 3148 } 3149 3150 return (0); 3151 } 3152 3153 static void 3154 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3155 int index, int lmute, int rmute, 3156 int left, int right, int dir) 3157 { 3158 uint16_t v = 0; 3159 3160 if (sc == NULL) 3161 return; 3162 3163 if (left != right || lmute != rmute) { 3164 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3165 (lmute << 7) | left; 3166 hdac_command(sc, 3167 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3168 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3169 (rmute << 7) | right; 3170 } else 3171 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3172 (lmute << 7) | left; 3173 3174 hdac_command(sc, 3175 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3176 } 3177 3178 static void 3179 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3180 int left, int right) 3181 { 3182 struct hdac_softc *sc; 3183 nid_t nid, cad; 3184 int lmute, rmute; 3185 3186 sc = ctl->widget->devinfo->codec->sc; 3187 cad = ctl->widget->devinfo->codec->cad; 3188 nid = ctl->widget->nid; 3189 3190 /* Save new values if valid. */ 3191 if (mute != HDA_AMP_MUTE_DEFAULT) 3192 ctl->muted = mute; 3193 if (left != HDA_AMP_VOL_DEFAULT) 3194 ctl->left = left; 3195 if (right != HDA_AMP_VOL_DEFAULT) 3196 ctl->right = right; 3197 /* Prepare effective values */ 3198 if (ctl->forcemute) { 3199 lmute = 1; 3200 rmute = 1; 3201 left = 0; 3202 right = 0; 3203 } else { 3204 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3205 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3206 left = ctl->left; 3207 right = ctl->right; 3208 } 3209 /* Apply effective values */ 3210 if (ctl->dir & HDA_CTL_OUT) 3211 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3212 lmute, rmute, left, right, 0); 3213 if (ctl->dir & HDA_CTL_IN) 3214 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3215 lmute, rmute, left, right, 1); 3216 } 3217 3218 static void 3219 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3220 { 3221 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3222 return; 3223 hdac_command(w->devinfo->codec->sc, 3224 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3225 w->nid, index), w->devinfo->codec->cad); 3226 w->selconn = index; 3227 } 3228 3229 3230 /**************************************************************************** 3231 * uint32_t hdac_command_sendone_internal 3232 * 3233 * Wrapper function that sends only one command to a given codec 3234 ****************************************************************************/ 3235 static uint32_t 3236 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3237 { 3238 struct hdac_command_list cl; 3239 uint32_t response = HDAC_INVALID; 3240 3241 if (!hdac_lockowned(sc)) 3242 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3243 cl.num_commands = 1; 3244 cl.verbs = &verb; 3245 cl.responses = &response; 3246 3247 hdac_command_send_internal(sc, &cl, cad); 3248 3249 return (response); 3250 } 3251 3252 /**************************************************************************** 3253 * hdac_command_send_internal 3254 * 3255 * Send a command list to the codec via the corb. We queue as much verbs as 3256 * we can and msleep on the codec. When the interrupt get the responses 3257 * back from the rirb, it will wake us up so we can queue the remaining verbs 3258 * if any. 3259 ****************************************************************************/ 3260 static void 3261 hdac_command_send_internal(struct hdac_softc *sc, 3262 struct hdac_command_list *commands, nid_t cad) 3263 { 3264 struct hdac_codec *codec; 3265 int corbrp; 3266 uint32_t *corb; 3267 int timeout; 3268 int retry = 10; 3269 struct hdac_rirb *rirb_base; 3270 3271 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3272 commands->num_commands < 1) 3273 return; 3274 3275 codec = sc->codecs[cad]; 3276 codec->commands = commands; 3277 codec->responses_received = 0; 3278 codec->verbs_sent = 0; 3279 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3280 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3281 3282 do { 3283 if (codec->verbs_sent != commands->num_commands) { 3284 /* Queue as many verbs as possible */ 3285 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3286 #if 0 3287 bus_dmamap_sync(sc->corb_dma.dma_tag, 3288 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3289 #endif 3290 while (codec->verbs_sent != commands->num_commands && 3291 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3292 sc->corb_wp++; 3293 sc->corb_wp %= sc->corb_size; 3294 corb[sc->corb_wp] = 3295 commands->verbs[codec->verbs_sent++]; 3296 } 3297 3298 /* Send the verbs to the codecs */ 3299 #if 0 3300 bus_dmamap_sync(sc->corb_dma.dma_tag, 3301 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3302 #endif 3303 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3304 } 3305 3306 timeout = 1000; 3307 while (hdac_rirb_flush(sc) == 0 && --timeout) 3308 DELAY(10); 3309 } while ((codec->verbs_sent != commands->num_commands || 3310 codec->responses_received != commands->num_commands) && --retry); 3311 3312 if (retry == 0) 3313 device_printf(sc->dev, 3314 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3315 __func__, commands->num_commands, codec->verbs_sent, 3316 codec->responses_received); 3317 3318 codec->commands = NULL; 3319 codec->responses_received = 0; 3320 codec->verbs_sent = 0; 3321 3322 hdac_unsolq_flush(sc); 3323 } 3324 3325 3326 /**************************************************************************** 3327 * Device Methods 3328 ****************************************************************************/ 3329 3330 /**************************************************************************** 3331 * int hdac_probe(device_t) 3332 * 3333 * Probe for the presence of an hdac. If none is found, check for a generic 3334 * match using the subclass of the device. 3335 ****************************************************************************/ 3336 static int 3337 hdac_probe(device_t dev) 3338 { 3339 int i, result; 3340 uint32_t model; 3341 uint16_t class, subclass; 3342 char desc[64]; 3343 3344 model = (uint32_t)pci_get_device(dev) << 16; 3345 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3346 class = pci_get_class(dev); 3347 subclass = pci_get_subclass(dev); 3348 3349 bzero(desc, sizeof(desc)); 3350 result = ENXIO; 3351 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3352 if (hdac_devices[i].model == model) { 3353 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3354 result = BUS_PROBE_DEFAULT; 3355 break; 3356 } 3357 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3358 class == PCIC_MULTIMEDIA && 3359 subclass == PCIS_MULTIMEDIA_HDA) { 3360 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3361 result = BUS_PROBE_GENERIC; 3362 break; 3363 } 3364 } 3365 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3366 subclass == PCIS_MULTIMEDIA_HDA) { 3367 strlcpy(desc, "Generic", sizeof(desc)); 3368 result = BUS_PROBE_GENERIC; 3369 } 3370 if (result != ENXIO) { 3371 strlcat(desc, " High Definition Audio Controller", 3372 sizeof(desc)); 3373 device_set_desc_copy(dev, desc); 3374 } 3375 3376 return (result); 3377 } 3378 3379 static void * 3380 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3381 struct pcm_channel *c, int dir) 3382 { 3383 struct hdac_pcm_devinfo *pdevinfo = data; 3384 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3385 struct hdac_softc *sc = devinfo->codec->sc; 3386 struct hdac_chan *ch; 3387 int i, ord = 0, chid; 3388 3389 hdac_lock(sc); 3390 3391 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3392 ch = &sc->chans[chid]; 3393 for (i = 0; i < sc->num_chans && i < chid; i++) { 3394 if (ch->dir == sc->chans[i].dir) 3395 ord++; 3396 } 3397 if (dir == PCMDIR_PLAY) { 3398 ch->off = (sc->num_iss + ord) << 5; 3399 } else { 3400 ch->off = ord << 5; 3401 } 3402 3403 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3404 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3405 ch->pcmrates[0] = 48000; 3406 ch->pcmrates[1] = 0; 3407 } 3408 if (sc->pos_dma.dma_vaddr != NULL) 3409 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3410 (sc->streamcnt * 8)); 3411 else 3412 ch->dmapos = NULL; 3413 ch->sid = ++sc->streamcnt; 3414 ch->dir = dir; 3415 ch->b = b; 3416 ch->c = c; 3417 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3418 ch->blkcnt = pdevinfo->chan_blkcnt; 3419 hdac_unlock(sc); 3420 3421 if (hdac_bdl_alloc(ch) != 0) { 3422 ch->blkcnt = 0; 3423 return (NULL); 3424 } 3425 3426 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3427 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3428 pdevinfo->chan_size) != 0) 3429 return (NULL); 3430 3431 return (ch); 3432 } 3433 3434 static int 3435 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3436 { 3437 struct hdac_chan *ch = data; 3438 int i; 3439 3440 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3441 if (format == ch->caps.fmtlist[i]) { 3442 ch->fmt = format; 3443 return (0); 3444 } 3445 } 3446 3447 return (EINVAL); 3448 } 3449 3450 static uint32_t 3451 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3452 { 3453 struct hdac_chan *ch = data; 3454 uint32_t spd = 0, threshold; 3455 int i; 3456 3457 for (i = 0; ch->pcmrates[i] != 0; i++) { 3458 spd = ch->pcmrates[i]; 3459 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3460 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3461 if (speed < threshold) 3462 break; 3463 } 3464 3465 if (spd == 0) /* impossible */ 3466 ch->spd = 48000; 3467 else 3468 ch->spd = spd; 3469 3470 return (ch->spd); 3471 } 3472 3473 static void 3474 hdac_stream_setup(struct hdac_chan *ch) 3475 { 3476 struct hdac_softc *sc = ch->devinfo->codec->sc; 3477 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3478 struct hdac_widget *w; 3479 int i, chn, totalchn, c; 3480 nid_t cad = ch->devinfo->codec->cad; 3481 uint16_t fmt, dfmt; 3482 uint16_t chmap[2][5] = {{ 0x0010, 0x0001, 0x0201, 0x0231, 0x0231 }, /* 5.1 */ 3483 { 0x0010, 0x0001, 0x2001, 0x2031, 0x2431 }};/* 7.1 */ 3484 int map = -1; 3485 3486 totalchn = AFMT_CHANNEL(ch->fmt); 3487 HDA_BOOTHVERBOSE( 3488 device_printf(ch->pdevinfo->dev, 3489 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3490 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3491 ch->fmt, ch->spd); 3492 ); 3493 fmt = 0; 3494 if (ch->fmt & AFMT_S16_LE) 3495 fmt |= ch->bit16 << 4; 3496 else if (ch->fmt & AFMT_S32_LE) 3497 fmt |= ch->bit32 << 4; 3498 else 3499 fmt |= 1 << 4; 3500 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3501 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3502 fmt |= hda_rate_tab[i].base; 3503 fmt |= hda_rate_tab[i].mul; 3504 fmt |= hda_rate_tab[i].div; 3505 break; 3506 } 3507 } 3508 fmt |= (totalchn - 1); 3509 3510 /* Set channel mapping for known speaker setups. */ 3511 if (as->pinset == 0x0007 || as->pinset == 0x0013) /* Standard 5.1 */ 3512 map = 0; 3513 else if (as->pinset == 0x0017) /* Standard 7.1 */ 3514 map = 1; 3515 3516 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3517 3518 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3519 if (ch->fmt & AFMT_AC3) 3520 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3521 3522 chn = 0; 3523 for (i = 0; ch->io[i] != -1; i++) { 3524 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3525 if (w == NULL) 3526 continue; 3527 3528 /* If HP redirection is enabled, but failed to use same 3529 DAC, make last DAC to duplicate first one. */ 3530 if (as->fakeredir && i == (as->pincnt - 1)) { 3531 c = (ch->sid << 4); 3532 } else { 3533 if (map >= 0) /* Map known speaker setups. */ 3534 chn = (((chmap[map][totalchn / 2] >> i * 4) & 3535 0xf) - 1) * 2; 3536 if (chn < 0 || chn >= totalchn) { 3537 c = 0; 3538 } else { 3539 c = (ch->sid << 4) | chn; 3540 } 3541 } 3542 HDA_BOOTHVERBOSE( 3543 device_printf(ch->pdevinfo->dev, 3544 "PCMDIR_%s: Stream setup nid=%d: " 3545 "fmt=0x%04x, dfmt=0x%04x, chan=0x%04x\n", 3546 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3547 ch->io[i], fmt, dfmt, c); 3548 ); 3549 hdac_command(sc, 3550 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3551 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3552 hdac_command(sc, 3553 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3554 cad); 3555 } 3556 hdac_command(sc, 3557 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3558 #if 0 3559 hdac_command(sc, 3560 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3561 hdac_command(sc, 3562 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3563 hdac_command(sc, 3564 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3565 #endif 3566 chn += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 3567 } 3568 } 3569 3570 /* 3571 * Greatest Common Divisor. 3572 */ 3573 static unsigned 3574 gcd(unsigned a, unsigned b) 3575 { 3576 u_int c; 3577 3578 while (b != 0) { 3579 c = a; 3580 a = b; 3581 b = (c % b); 3582 } 3583 return (a); 3584 } 3585 3586 /* 3587 * Least Common Multiple. 3588 */ 3589 static unsigned 3590 lcm(unsigned a, unsigned b) 3591 { 3592 3593 return ((a * b) / gcd(a, b)); 3594 } 3595 3596 static int 3597 hdac_channel_setfragments(kobj_t obj, void *data, 3598 uint32_t blksz, uint32_t blkcnt) 3599 { 3600 struct hdac_chan *ch = data; 3601 struct hdac_softc *sc = ch->devinfo->codec->sc; 3602 3603 blksz -= blksz % lcm(HDAC_DMA_ALIGNMENT, sndbuf_getalign(ch->b)); 3604 3605 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3606 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3607 if (blksz < HDA_BLK_MIN) 3608 blksz = HDA_BLK_MIN; 3609 if (blkcnt > HDA_BDL_MAX) 3610 blkcnt = HDA_BDL_MAX; 3611 if (blkcnt < HDA_BDL_MIN) 3612 blkcnt = HDA_BDL_MIN; 3613 3614 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3615 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3616 blkcnt >>= 1; 3617 else if ((blksz >> 1) >= HDA_BLK_MIN) 3618 blksz >>= 1; 3619 else 3620 break; 3621 } 3622 3623 if ((sndbuf_getblksz(ch->b) != blksz || 3624 sndbuf_getblkcnt(ch->b) != blkcnt) && 3625 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3626 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3627 __func__, blksz, blkcnt); 3628 3629 ch->blksz = sndbuf_getblksz(ch->b); 3630 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3631 3632 return (0); 3633 } 3634 3635 static uint32_t 3636 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3637 { 3638 struct hdac_chan *ch = data; 3639 3640 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3641 3642 return (ch->blksz); 3643 } 3644 3645 static void 3646 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3647 { 3648 struct hdac_devinfo *devinfo = ch->devinfo; 3649 struct hdac_widget *w; 3650 nid_t cad = devinfo->codec->cad; 3651 int i; 3652 3653 hdac_stream_stop(ch); 3654 3655 for (i = 0; ch->io[i] != -1; i++) { 3656 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3657 if (w == NULL) 3658 continue; 3659 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3660 hdac_command(sc, 3661 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3662 cad); 3663 } 3664 hdac_command(sc, 3665 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3666 0), cad); 3667 } 3668 } 3669 3670 static void 3671 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3672 { 3673 ch->ptr = 0; 3674 ch->prevptr = 0; 3675 hdac_stream_stop(ch); 3676 hdac_stream_reset(ch); 3677 hdac_bdl_setup(ch); 3678 hdac_stream_setid(ch); 3679 hdac_stream_setup(ch); 3680 hdac_stream_start(ch); 3681 } 3682 3683 static int 3684 hdac_channel_trigger(kobj_t obj, void *data, int go) 3685 { 3686 struct hdac_chan *ch = data; 3687 struct hdac_softc *sc = ch->devinfo->codec->sc; 3688 3689 if (!PCMTRIG_COMMON(go)) 3690 return (0); 3691 3692 hdac_lock(sc); 3693 switch (go) { 3694 case PCMTRIG_START: 3695 hdac_channel_start(sc, ch); 3696 break; 3697 case PCMTRIG_STOP: 3698 case PCMTRIG_ABORT: 3699 hdac_channel_stop(sc, ch); 3700 break; 3701 default: 3702 break; 3703 } 3704 hdac_unlock(sc); 3705 3706 return (0); 3707 } 3708 3709 static uint32_t 3710 hdac_channel_getptr(kobj_t obj, void *data) 3711 { 3712 struct hdac_chan *ch = data; 3713 struct hdac_softc *sc = ch->devinfo->codec->sc; 3714 uint32_t ptr; 3715 3716 hdac_lock(sc); 3717 if (sc->polling != 0) 3718 ptr = ch->ptr; 3719 else if (ch->dmapos != NULL) 3720 ptr = *(ch->dmapos); 3721 else 3722 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3723 hdac_unlock(sc); 3724 3725 /* 3726 * Round to available space and force 128 bytes aligment. 3727 */ 3728 ptr %= ch->blksz * ch->blkcnt; 3729 ptr &= HDA_BLK_ALIGN; 3730 3731 return (ptr); 3732 } 3733 3734 static struct pcmchan_caps * 3735 hdac_channel_getcaps(kobj_t obj, void *data) 3736 { 3737 return (&((struct hdac_chan *)data)->caps); 3738 } 3739 3740 static kobj_method_t hdac_channel_methods[] = { 3741 KOBJMETHOD(channel_init, hdac_channel_init), 3742 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3743 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3744 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3745 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3746 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3747 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3748 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3749 KOBJMETHOD_END 3750 }; 3751 CHANNEL_DECLARE(hdac_channel); 3752 3753 static int 3754 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3755 { 3756 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3757 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3758 struct hdac_softc *sc = devinfo->codec->sc; 3759 struct hdac_widget *w, *cw; 3760 struct hdac_audio_ctl *ctl; 3761 uint32_t mask, recmask, id; 3762 int i, j, softpcmvol; 3763 3764 hdac_lock(sc); 3765 3766 /* Make sure that in case of soft volume it won't stay muted. */ 3767 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3768 pdevinfo->left[i] = 100; 3769 pdevinfo->right[i] = 100; 3770 } 3771 3772 mask = 0; 3773 recmask = 0; 3774 id = hdac_codec_id(devinfo->codec); 3775 3776 /* Declate EAPD as ogain control. */ 3777 if (pdevinfo->play >= 0) { 3778 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3779 w = hdac_widget_get(devinfo, i); 3780 if (w == NULL || w->enable == 0) 3781 continue; 3782 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3783 w->param.eapdbtl == HDAC_INVALID || 3784 w->bindas != sc->chans[pdevinfo->play].as) 3785 continue; 3786 mask |= SOUND_MASK_OGAIN; 3787 break; 3788 } 3789 } 3790 3791 /* Declare volume controls assigned to this association. */ 3792 i = 0; 3793 ctl = NULL; 3794 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3795 if (ctl->enable == 0) 3796 continue; 3797 if ((pdevinfo->play >= 0 && 3798 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3799 (pdevinfo->rec >= 0 && 3800 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3801 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3802 mask |= ctl->ossmask; 3803 } 3804 3805 /* Declare record sources available to this association. */ 3806 if (pdevinfo->rec >= 0) { 3807 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3808 for (i = 0; ch->io[i] != -1; i++) { 3809 w = hdac_widget_get(devinfo, ch->io[i]); 3810 if (w == NULL || w->enable == 0) 3811 continue; 3812 for (j = 0; j < w->nconns; j++) { 3813 if (w->connsenable[j] == 0) 3814 continue; 3815 cw = hdac_widget_get(devinfo, w->conns[j]); 3816 if (cw == NULL || cw->enable == 0) 3817 continue; 3818 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3819 cw->bindas != -2) 3820 continue; 3821 recmask |= cw->ossmask; 3822 } 3823 } 3824 } 3825 3826 /* Declare soft PCM volume if needed. */ 3827 if (pdevinfo->play >= 0) { 3828 ctl = NULL; 3829 if ((mask & SOUND_MASK_PCM) == 0 || 3830 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3831 softpcmvol = 1; 3832 mask |= SOUND_MASK_PCM; 3833 } else { 3834 softpcmvol = 0; 3835 i = 0; 3836 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3837 if (ctl->enable == 0) 3838 continue; 3839 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3840 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3841 continue; 3842 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3843 continue; 3844 if (ctl->step > 0) 3845 break; 3846 } 3847 } 3848 3849 if (softpcmvol == 1 || ctl == NULL) { 3850 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3851 HDA_BOOTVERBOSE( 3852 device_printf(pdevinfo->dev, 3853 "%s Soft PCM volume\n", 3854 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3855 ); 3856 } 3857 } 3858 3859 /* Declare master volume if needed. */ 3860 if (pdevinfo->play >= 0) { 3861 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3862 SOUND_MASK_PCM) { 3863 mask |= SOUND_MASK_VOLUME; 3864 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3865 SOUND_MASK_PCM); 3866 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3867 SOUND_MIXER_NONE); 3868 HDA_BOOTVERBOSE( 3869 device_printf(pdevinfo->dev, 3870 "Forcing master volume with PCM\n"); 3871 ); 3872 } 3873 } 3874 3875 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3876 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3877 3878 mix_setrecdevs(m, recmask); 3879 mix_setdevs(m, mask); 3880 3881 hdac_unlock(sc); 3882 3883 return (0); 3884 } 3885 3886 static int 3887 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3888 unsigned left, unsigned right) 3889 { 3890 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3891 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3892 struct hdac_softc *sc = devinfo->codec->sc; 3893 struct hdac_widget *w; 3894 struct hdac_audio_ctl *ctl; 3895 uint32_t mute; 3896 int lvol, rvol; 3897 int i, j; 3898 3899 hdac_lock(sc); 3900 /* Save new values. */ 3901 pdevinfo->left[dev] = left; 3902 pdevinfo->right[dev] = right; 3903 3904 /* 'ogain' is the special case implemented with EAPD. */ 3905 if (dev == SOUND_MIXER_OGAIN) { 3906 uint32_t orig; 3907 w = NULL; 3908 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3909 w = hdac_widget_get(devinfo, i); 3910 if (w == NULL || w->enable == 0) 3911 continue; 3912 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3913 w->param.eapdbtl == HDAC_INVALID) 3914 continue; 3915 break; 3916 } 3917 if (i >= devinfo->endnode) { 3918 hdac_unlock(sc); 3919 return (-1); 3920 } 3921 orig = w->param.eapdbtl; 3922 if (left == 0) 3923 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3924 else 3925 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3926 if (orig != w->param.eapdbtl) { 3927 uint32_t val; 3928 3929 val = w->param.eapdbtl; 3930 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3931 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3932 hdac_command(sc, 3933 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3934 w->nid, val), devinfo->codec->cad); 3935 } 3936 hdac_unlock(sc); 3937 return (left | (left << 8)); 3938 } 3939 3940 /* Recalculate all controls related to this OSS device. */ 3941 i = 0; 3942 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3943 if (ctl->enable == 0 || 3944 !(ctl->ossmask & (1 << dev))) 3945 continue; 3946 if (!((pdevinfo->play >= 0 && 3947 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3948 (pdevinfo->rec >= 0 && 3949 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3950 ctl->widget->bindas == -2)) 3951 continue; 3952 3953 lvol = 100; 3954 rvol = 100; 3955 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3956 if (ctl->ossmask & (1 << j)) { 3957 lvol = lvol * pdevinfo->left[j] / 100; 3958 rvol = rvol * pdevinfo->right[j] / 100; 3959 } 3960 } 3961 mute = (lvol == 0) ? HDA_AMP_MUTE_LEFT : 0; 3962 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3963 lvol = (lvol * ctl->step + 50) / 100; 3964 rvol = (rvol * ctl->step + 50) / 100; 3965 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3966 } 3967 hdac_unlock(sc); 3968 3969 return (left | (right << 8)); 3970 } 3971 3972 /* 3973 * Commutate specified record source. 3974 */ 3975 static uint32_t 3976 hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3977 { 3978 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3979 struct hdac_widget *w, *cw; 3980 struct hdac_audio_ctl *ctl; 3981 char buf[64]; 3982 int i, muted; 3983 uint32_t res = 0; 3984 3985 if (depth > HDA_PARSE_MAXDEPTH) 3986 return (0); 3987 3988 w = hdac_widget_get(devinfo, nid); 3989 if (w == NULL || w->enable == 0) 3990 return (0); 3991 3992 for (i = 0; i < w->nconns; i++) { 3993 if (w->connsenable[i] == 0) 3994 continue; 3995 cw = hdac_widget_get(devinfo, w->conns[i]); 3996 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3997 continue; 3998 /* Call recursively to trace signal to it's source if needed. */ 3999 if ((src & cw->ossmask) != 0) { 4000 if (cw->ossdev < 0) { 4001 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 4002 w->conns[i], depth + 1); 4003 } else { 4004 res |= cw->ossmask; 4005 } 4006 } 4007 /* We have two special cases: mixers and others (selectors). */ 4008 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4009 ctl = hdac_audio_ctl_amp_get(devinfo, 4010 w->nid, HDA_CTL_IN, i, 1); 4011 if (ctl == NULL) 4012 continue; 4013 /* If we have input control on this node mute them 4014 * according to requested sources. */ 4015 muted = (src & cw->ossmask) ? 0 : 1; 4016 if (muted != ctl->forcemute) { 4017 ctl->forcemute = muted; 4018 hdac_audio_ctl_amp_set(ctl, 4019 HDA_AMP_MUTE_DEFAULT, 4020 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 4021 } 4022 HDA_BOOTHVERBOSE( 4023 device_printf(pdevinfo->dev, 4024 "Recsel (%s): nid %d source %d %s\n", 4025 hdac_audio_ctl_ossmixer_mask2allname( 4026 src, buf, sizeof(buf)), 4027 nid, i, muted?"mute":"unmute"); 4028 ); 4029 } else { 4030 if (w->nconns == 1) 4031 break; 4032 if ((src & cw->ossmask) == 0) 4033 continue; 4034 /* If we found requested source - select it and exit. */ 4035 hdac_widget_connection_select(w, i); 4036 HDA_BOOTHVERBOSE( 4037 device_printf(pdevinfo->dev, 4038 "Recsel (%s): nid %d source %d select\n", 4039 hdac_audio_ctl_ossmixer_mask2allname( 4040 src, buf, sizeof(buf)), 4041 nid, i); 4042 ); 4043 break; 4044 } 4045 } 4046 return (res); 4047 } 4048 4049 static uint32_t 4050 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 4051 { 4052 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 4053 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 4054 struct hdac_widget *w; 4055 struct hdac_softc *sc = devinfo->codec->sc; 4056 struct hdac_chan *ch; 4057 int i; 4058 uint32_t ret = 0xffffffff; 4059 4060 hdac_lock(sc); 4061 4062 /* Commutate requested recsrc for each ADC. */ 4063 ch = &sc->chans[pdevinfo->rec]; 4064 for (i = 0; ch->io[i] != -1; i++) { 4065 w = hdac_widget_get(devinfo, ch->io[i]); 4066 if (w == NULL || w->enable == 0) 4067 continue; 4068 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 4069 } 4070 4071 hdac_unlock(sc); 4072 4073 return ((ret == 0xffffffff)? 0 : ret); 4074 } 4075 4076 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 4077 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 4078 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 4079 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 4080 KOBJMETHOD_END 4081 }; 4082 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 4083 4084 static void 4085 hdac_unsolq_task(void *context, int pending) 4086 { 4087 struct hdac_softc *sc; 4088 4089 sc = (struct hdac_softc *)context; 4090 4091 hdac_lock(sc); 4092 hdac_unsolq_flush(sc); 4093 hdac_unlock(sc); 4094 } 4095 4096 /**************************************************************************** 4097 * int hdac_attach(device_t) 4098 * 4099 * Attach the device into the kernel. Interrupts usually won't be enabled 4100 * when this function is called. Setup everything that doesn't require 4101 * interrupts and defer probing of codecs until interrupts are enabled. 4102 ****************************************************************************/ 4103 static int 4104 hdac_attach(device_t dev) 4105 { 4106 struct hdac_softc *sc; 4107 int result; 4108 int i, devid = -1; 4109 uint32_t model; 4110 uint16_t class, subclass; 4111 uint16_t vendor; 4112 uint8_t v; 4113 4114 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4115 4116 model = (uint32_t)pci_get_device(dev) << 16; 4117 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4118 class = pci_get_class(dev); 4119 subclass = pci_get_subclass(dev); 4120 4121 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4122 if (hdac_devices[i].model == model) { 4123 devid = i; 4124 break; 4125 } 4126 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4127 class == PCIC_MULTIMEDIA && 4128 subclass == PCIS_MULTIMEDIA_HDA) { 4129 devid = i; 4130 break; 4131 } 4132 } 4133 4134 sc = device_get_softc(dev); 4135 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4136 sc->dev = dev; 4137 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4138 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4139 vendor = pci_get_vendor(dev); 4140 4141 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4142 /* Screw nx6325 - subdevice/subvendor swapped */ 4143 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4144 } 4145 4146 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4147 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4148 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4149 4150 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4151 4152 sc->poll_ticks = 1000000; 4153 sc->poll_ival = HDAC_POLL_INTERVAL; 4154 if (resource_int_value(device_get_name(dev), 4155 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4156 sc->polling = 1; 4157 else 4158 sc->polling = 0; 4159 4160 sc->hdabus = NULL; 4161 for (i = 0; i < HDAC_CODEC_MAX; i++) 4162 sc->codecs[i] = NULL; 4163 4164 pci_enable_busmaster(dev); 4165 4166 if (vendor == INTEL_VENDORID) { 4167 /* TCSEL -> TC0 */ 4168 v = pci_read_config(dev, 0x44, 1); 4169 pci_write_config(dev, 0x44, v & 0xf8, 1); 4170 HDA_BOOTHVERBOSE( 4171 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4172 pci_read_config(dev, 0x44, 1)); 4173 ); 4174 } 4175 4176 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4177 sc->flags &= ~HDAC_F_MSI; 4178 else 4179 sc->flags |= HDAC_F_MSI; 4180 if (resource_int_value(device_get_name(dev), 4181 device_get_unit(dev), "msi", &i) == 0) { 4182 if (i == 0) 4183 sc->flags &= ~HDAC_F_MSI; 4184 else 4185 sc->flags |= HDAC_F_MSI; 4186 } 4187 4188 #if defined(__i386__) || defined(__amd64__) 4189 sc->flags |= HDAC_F_DMA_NOCACHE; 4190 4191 if (resource_int_value(device_get_name(dev), 4192 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4193 #else 4194 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4195 #endif 4196 /* 4197 * Try to enable PCIe snoop to avoid messing around with 4198 * uncacheable DMA attribute. Since PCIe snoop register 4199 * config is pretty much vendor specific, there are no 4200 * general solutions on how to enable it, forcing us (even 4201 * Microsoft) to enable uncacheable or write combined DMA 4202 * by default. 4203 * 4204 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4205 */ 4206 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4207 if (hdac_pcie_snoop[i].vendor != vendor) 4208 continue; 4209 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4210 if (hdac_pcie_snoop[i].reg == 0x00) 4211 break; 4212 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4213 if ((v & hdac_pcie_snoop[i].enable) == 4214 hdac_pcie_snoop[i].enable) 4215 break; 4216 v &= hdac_pcie_snoop[i].mask; 4217 v |= hdac_pcie_snoop[i].enable; 4218 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4219 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4220 if ((v & hdac_pcie_snoop[i].enable) != 4221 hdac_pcie_snoop[i].enable) { 4222 HDA_BOOTVERBOSE( 4223 device_printf(dev, 4224 "WARNING: Failed to enable PCIe " 4225 "snoop!\n"); 4226 ); 4227 #if defined(__i386__) || defined(__amd64__) 4228 sc->flags |= HDAC_F_DMA_NOCACHE; 4229 #endif 4230 } 4231 break; 4232 } 4233 #if defined(__i386__) || defined(__amd64__) 4234 } 4235 #endif 4236 4237 HDA_BOOTHVERBOSE( 4238 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4239 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4240 "Uncacheable" : "PCIe snoop", vendor); 4241 ); 4242 4243 /* Allocate resources */ 4244 result = hdac_mem_alloc(sc); 4245 if (result != 0) 4246 goto hdac_attach_fail; 4247 result = hdac_irq_alloc(sc); 4248 if (result != 0) 4249 goto hdac_attach_fail; 4250 4251 /* Get Capabilities */ 4252 result = hdac_get_capabilities(sc); 4253 if (result != 0) 4254 goto hdac_attach_fail; 4255 4256 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4257 sc->support_64bit = 0; 4258 4259 /* Allocate CORB and RIRB dma memory */ 4260 result = hdac_dma_alloc(sc, &sc->corb_dma, 4261 sc->corb_size * sizeof(uint32_t)); 4262 if (result != 0) 4263 goto hdac_attach_fail; 4264 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4265 sc->rirb_size * sizeof(struct hdac_rirb)); 4266 if (result != 0) 4267 goto hdac_attach_fail; 4268 4269 result = bus_dma_tag_create( 4270 bus_get_dma_tag(sc->dev), /* parent */ 4271 HDAC_DMA_ALIGNMENT, /* alignment */ 4272 0, /* boundary */ 4273 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4274 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4275 BUS_SPACE_MAXADDR, /* highaddr */ 4276 NULL, /* filtfunc */ 4277 NULL, /* fistfuncarg */ 4278 HDA_BUFSZ_MAX, /* maxsize */ 4279 1, /* nsegments */ 4280 HDA_BUFSZ_MAX, /* maxsegsz */ 4281 0, /* flags */ 4282 NULL, /* lockfunc */ 4283 NULL, /* lockfuncarg */ 4284 &sc->chan_dmat); /* dmat */ 4285 if (result != 0) { 4286 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4287 __func__, result); 4288 goto hdac_attach_fail; 4289 } 4290 4291 /* Quiesce everything */ 4292 HDA_BOOTHVERBOSE( 4293 device_printf(dev, "Reset controller...\n"); 4294 ); 4295 hdac_reset(sc, 1); 4296 4297 /* Initialize the CORB and RIRB */ 4298 hdac_corb_init(sc); 4299 hdac_rirb_init(sc); 4300 4301 /* Defer remaining of initialization until interrupts are enabled */ 4302 sc->intrhook.ich_func = hdac_attach2; 4303 sc->intrhook.ich_arg = (void *)sc; 4304 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4305 sc->intrhook.ich_func = NULL; 4306 hdac_attach2((void *)sc); 4307 } 4308 4309 return (0); 4310 4311 hdac_attach_fail: 4312 hdac_irq_free(sc); 4313 hdac_dma_free(sc, &sc->rirb_dma); 4314 hdac_dma_free(sc, &sc->corb_dma); 4315 hdac_mem_free(sc); 4316 snd_mtxfree(sc->lock); 4317 free(sc, M_DEVBUF); 4318 4319 return (ENXIO); 4320 } 4321 4322 static void 4323 hdac_audio_parse(struct hdac_devinfo *devinfo) 4324 { 4325 struct hdac_codec *codec = devinfo->codec; 4326 struct hdac_softc *sc = codec->sc; 4327 struct hdac_widget *w; 4328 uint32_t res; 4329 int i; 4330 nid_t cad, nid; 4331 4332 cad = devinfo->codec->cad; 4333 nid = devinfo->nid; 4334 4335 res = hdac_command(sc, 4336 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4337 devinfo->function.audio.gpio = res; 4338 4339 HDA_BOOTVERBOSE( 4340 device_printf(sc->dev, "GPIO: 0x%08x " 4341 "NumGPIO=%d NumGPO=%d " 4342 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4343 devinfo->function.audio.gpio, 4344 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4345 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4346 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4347 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4348 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4349 ); 4350 4351 res = hdac_command(sc, 4352 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4353 cad); 4354 devinfo->function.audio.supp_stream_formats = res; 4355 4356 res = hdac_command(sc, 4357 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4358 cad); 4359 devinfo->function.audio.supp_pcm_size_rate = res; 4360 4361 res = hdac_command(sc, 4362 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4363 cad); 4364 devinfo->function.audio.outamp_cap = res; 4365 4366 res = hdac_command(sc, 4367 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4368 cad); 4369 devinfo->function.audio.inamp_cap = res; 4370 4371 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4372 w = hdac_widget_get(devinfo, i); 4373 if (w == NULL) 4374 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4375 else { 4376 w->devinfo = devinfo; 4377 w->nid = i; 4378 w->enable = 1; 4379 w->selconn = -1; 4380 w->pflags = 0; 4381 w->ossdev = -1; 4382 w->bindas = -1; 4383 w->param.eapdbtl = HDAC_INVALID; 4384 hdac_widget_parse(w); 4385 } 4386 } 4387 } 4388 4389 static void 4390 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4391 { 4392 struct hdac_softc *sc = devinfo->codec->sc; 4393 struct hdac_audio_ctl *ctls; 4394 struct hdac_widget *w, *cw; 4395 int i, j, cnt, max, ocap, icap; 4396 int mute, offset, step, size; 4397 4398 /* XXX This is redundant */ 4399 max = 0; 4400 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4401 w = hdac_widget_get(devinfo, i); 4402 if (w == NULL || w->enable == 0) 4403 continue; 4404 if (w->param.outamp_cap != 0) 4405 max++; 4406 if (w->param.inamp_cap != 0) { 4407 switch (w->type) { 4408 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4409 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4410 for (j = 0; j < w->nconns; j++) { 4411 cw = hdac_widget_get(devinfo, 4412 w->conns[j]); 4413 if (cw == NULL || cw->enable == 0) 4414 continue; 4415 max++; 4416 } 4417 break; 4418 default: 4419 max++; 4420 break; 4421 } 4422 } 4423 } 4424 4425 devinfo->function.audio.ctlcnt = max; 4426 4427 if (max < 1) 4428 return; 4429 4430 ctls = (struct hdac_audio_ctl *)malloc( 4431 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4432 4433 if (ctls == NULL) { 4434 /* Blekh! */ 4435 device_printf(sc->dev, "unable to allocate ctls!\n"); 4436 devinfo->function.audio.ctlcnt = 0; 4437 return; 4438 } 4439 4440 cnt = 0; 4441 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4442 if (cnt >= max) { 4443 device_printf(sc->dev, "%s: Ctl overflow!\n", 4444 __func__); 4445 break; 4446 } 4447 w = hdac_widget_get(devinfo, i); 4448 if (w == NULL || w->enable == 0) 4449 continue; 4450 ocap = w->param.outamp_cap; 4451 icap = w->param.inamp_cap; 4452 if (ocap != 0) { 4453 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4454 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4455 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4456 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4457 /*if (offset > step) { 4458 HDA_BOOTVERBOSE( 4459 device_printf(sc->dev, 4460 "BUGGY outamp: nid=%d " 4461 "[offset=%d > step=%d]\n", 4462 w->nid, offset, step); 4463 ); 4464 offset = step; 4465 }*/ 4466 ctls[cnt].enable = 1; 4467 ctls[cnt].widget = w; 4468 ctls[cnt].mute = mute; 4469 ctls[cnt].step = step; 4470 ctls[cnt].size = size; 4471 ctls[cnt].offset = offset; 4472 ctls[cnt].left = offset; 4473 ctls[cnt].right = offset; 4474 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4475 w->waspin) 4476 ctls[cnt].ndir = HDA_CTL_IN; 4477 else 4478 ctls[cnt].ndir = HDA_CTL_OUT; 4479 ctls[cnt++].dir = HDA_CTL_OUT; 4480 } 4481 4482 if (icap != 0) { 4483 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4484 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4485 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4486 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4487 /*if (offset > step) { 4488 HDA_BOOTVERBOSE( 4489 device_printf(sc->dev, 4490 "BUGGY inamp: nid=%d " 4491 "[offset=%d > step=%d]\n", 4492 w->nid, offset, step); 4493 ); 4494 offset = step; 4495 }*/ 4496 switch (w->type) { 4497 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4498 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4499 for (j = 0; j < w->nconns; j++) { 4500 if (cnt >= max) { 4501 device_printf(sc->dev, 4502 "%s: Ctl overflow!\n", 4503 __func__); 4504 break; 4505 } 4506 cw = hdac_widget_get(devinfo, 4507 w->conns[j]); 4508 if (cw == NULL || cw->enable == 0) 4509 continue; 4510 ctls[cnt].enable = 1; 4511 ctls[cnt].widget = w; 4512 ctls[cnt].childwidget = cw; 4513 ctls[cnt].index = j; 4514 ctls[cnt].mute = mute; 4515 ctls[cnt].step = step; 4516 ctls[cnt].size = size; 4517 ctls[cnt].offset = offset; 4518 ctls[cnt].left = offset; 4519 ctls[cnt].right = offset; 4520 ctls[cnt].ndir = HDA_CTL_IN; 4521 ctls[cnt++].dir = HDA_CTL_IN; 4522 } 4523 break; 4524 default: 4525 if (cnt >= max) { 4526 device_printf(sc->dev, 4527 "%s: Ctl overflow!\n", 4528 __func__); 4529 break; 4530 } 4531 ctls[cnt].enable = 1; 4532 ctls[cnt].widget = w; 4533 ctls[cnt].mute = mute; 4534 ctls[cnt].step = step; 4535 ctls[cnt].size = size; 4536 ctls[cnt].offset = offset; 4537 ctls[cnt].left = offset; 4538 ctls[cnt].right = offset; 4539 if (w->type == 4540 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4541 ctls[cnt].ndir = HDA_CTL_OUT; 4542 else 4543 ctls[cnt].ndir = HDA_CTL_IN; 4544 ctls[cnt++].dir = HDA_CTL_IN; 4545 break; 4546 } 4547 } 4548 } 4549 4550 devinfo->function.audio.ctl = ctls; 4551 } 4552 4553 static void 4554 hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4555 { 4556 struct hdac_softc *sc = devinfo->codec->sc; 4557 struct hdac_audio_as *as; 4558 struct hdac_widget *w; 4559 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4560 4561 /* Count present associations */ 4562 max = 0; 4563 for (j = 1; j < 16; j++) { 4564 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4565 w = hdac_widget_get(devinfo, i); 4566 if (w == NULL || w->enable == 0) 4567 continue; 4568 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4569 continue; 4570 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4571 != j) 4572 continue; 4573 max++; 4574 if (j != 15) /* There could be many 1-pin assocs #15 */ 4575 break; 4576 } 4577 } 4578 4579 devinfo->function.audio.ascnt = max; 4580 4581 if (max < 1) 4582 return; 4583 4584 as = (struct hdac_audio_as *)malloc( 4585 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4586 4587 if (as == NULL) { 4588 /* Blekh! */ 4589 device_printf(sc->dev, "unable to allocate assocs!\n"); 4590 devinfo->function.audio.ascnt = 0; 4591 return; 4592 } 4593 4594 for (i = 0; i < max; i++) { 4595 as[i].hpredir = -1; 4596 as[i].chan = -1; 4597 as[i].digital = 0; 4598 } 4599 4600 /* Scan associations skipping as=0. */ 4601 cnt = 0; 4602 for (j = 1; j < 16; j++) { 4603 first = 16; 4604 hpredir = 0; 4605 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4606 w = hdac_widget_get(devinfo, i); 4607 if (w == NULL || w->enable == 0) 4608 continue; 4609 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4610 continue; 4611 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4612 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4613 if (assoc != j) { 4614 continue; 4615 } 4616 KASSERT(cnt < max, 4617 ("%s: Associations owerflow (%d of %d)", 4618 __func__, cnt, max)); 4619 type = w->wclass.pin.config & 4620 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4621 /* Get pin direction. */ 4622 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4623 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4624 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4625 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4626 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4627 dir = HDA_CTL_OUT; 4628 else 4629 dir = HDA_CTL_IN; 4630 /* If this is a first pin - create new association. */ 4631 if (as[cnt].pincnt == 0) { 4632 as[cnt].enable = 1; 4633 as[cnt].index = j; 4634 as[cnt].dir = dir; 4635 } 4636 if (seq < first) 4637 first = seq; 4638 /* Check association correctness. */ 4639 if (as[cnt].pins[seq] != 0) { 4640 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4641 "in association %d! Disabling association.\n", 4642 __func__, seq, w->nid, j); 4643 as[cnt].enable = 0; 4644 } 4645 if (dir != as[cnt].dir) { 4646 device_printf(sc->dev, "%s: Pin %d has wrong " 4647 "direction for association %d! Disabling " 4648 "association.\n", 4649 __func__, w->nid, j); 4650 as[cnt].enable = 0; 4651 } 4652 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4653 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4654 as[cnt].digital = 3; 4655 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4656 as[cnt].digital = 2; 4657 else 4658 as[cnt].digital = 1; 4659 } 4660 /* Headphones with seq=15 may mean redirection. */ 4661 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4662 seq == 15) 4663 hpredir = 1; 4664 as[cnt].pins[seq] = w->nid; 4665 as[cnt].pincnt++; 4666 /* Association 15 is a multiple unassociated pins. */ 4667 if (j == 15) 4668 cnt++; 4669 } 4670 if (j != 15 && as[cnt].pincnt > 0) { 4671 if (hpredir && as[cnt].pincnt > 1) 4672 as[cnt].hpredir = first; 4673 cnt++; 4674 } 4675 } 4676 HDA_BOOTVERBOSE( 4677 device_printf(sc->dev, 4678 "%d associations found:\n", max); 4679 for (i = 0; i < max; i++) { 4680 device_printf(sc->dev, 4681 "Association %d (%d) %s%s:\n", 4682 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4683 as[i].enable?"":" (disabled)"); 4684 for (j = 0; j < 16; j++) { 4685 if (as[i].pins[j] == 0) 4686 continue; 4687 device_printf(sc->dev, 4688 " Pin nid=%d seq=%d\n", 4689 as[i].pins[j], j); 4690 } 4691 } 4692 ); 4693 4694 devinfo->function.audio.as = as; 4695 } 4696 4697 static const struct { 4698 uint32_t model; 4699 uint32_t id; 4700 uint32_t set, unset; 4701 } hdac_quirks[] = { 4702 /* 4703 * XXX Force stereo quirk. Monoural recording / playback 4704 * on few codecs (especially ALC880) seems broken or 4705 * perhaps unsupported. 4706 */ 4707 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4708 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4709 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4710 HDA_QUIRK_GPIO0, 0 }, 4711 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4712 HDA_QUIRK_GPIO0, 0 }, 4713 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4714 HDA_QUIRK_GPIO0, 0 }, 4715 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4716 HDA_QUIRK_GPIO0, 0 }, 4717 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4718 HDA_QUIRK_GPIO0, 0 }, 4719 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4720 HDA_QUIRK_GPIO0, 0 }, 4721 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4722 HDA_QUIRK_EAPDINV, 0 }, 4723 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4724 HDA_QUIRK_EAPDINV, 0 }, 4725 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4726 HDA_QUIRK_OVREF, 0 }, 4727 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4728 HDA_QUIRK_OVREF, 0 }, 4729 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4730 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4731 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4732 HDA_QUIRK_GPIO1, 0 }, 4733 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4734 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4735 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4736 HDA_QUIRK_EAPDINV, 0 }, 4737 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4738 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4739 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4740 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4741 { APPLE_MACBOOKPRO55, HDA_CODEC_CS4206, 4742 HDA_QUIRK_GPIO1 | HDA_QUIRK_GPIO3, 0 }, 4743 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4744 HDA_QUIRK_GPIO0, 0 }, 4745 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4746 HDA_QUIRK_GPIO2, 0 }, 4747 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4748 HDA_QUIRK_GPIO0, 0 }, 4749 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4750 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4751 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4752 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4753 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4754 0, HDA_QUIRK_FORCESTEREO } 4755 }; 4756 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4757 4758 static void 4759 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4760 { 4761 struct hdac_widget *w; 4762 uint32_t id, subvendor; 4763 int i; 4764 4765 id = hdac_codec_id(devinfo->codec); 4766 subvendor = devinfo->codec->sc->pci_subvendor; 4767 4768 /* 4769 * Quirks 4770 */ 4771 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4772 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4773 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4774 continue; 4775 if (hdac_quirks[i].set != 0) 4776 devinfo->function.audio.quirks |= 4777 hdac_quirks[i].set; 4778 if (hdac_quirks[i].unset != 0) 4779 devinfo->function.audio.quirks &= 4780 ~(hdac_quirks[i].unset); 4781 } 4782 4783 switch (id) { 4784 case HDA_CODEC_AD1983: 4785 /* 4786 * This codec has several possible usages, but none 4787 * fit the parser best. Help parser to choose better. 4788 */ 4789 /* Disable direct unmixed playback to get pcm volume. */ 4790 w = hdac_widget_get(devinfo, 5); 4791 if (w != NULL) 4792 w->connsenable[0] = 0; 4793 w = hdac_widget_get(devinfo, 6); 4794 if (w != NULL) 4795 w->connsenable[0] = 0; 4796 w = hdac_widget_get(devinfo, 11); 4797 if (w != NULL) 4798 w->connsenable[0] = 0; 4799 /* Disable mic and line selectors. */ 4800 w = hdac_widget_get(devinfo, 12); 4801 if (w != NULL) 4802 w->connsenable[1] = 0; 4803 w = hdac_widget_get(devinfo, 13); 4804 if (w != NULL) 4805 w->connsenable[1] = 0; 4806 /* Disable recording from mono playback mix. */ 4807 w = hdac_widget_get(devinfo, 20); 4808 if (w != NULL) 4809 w->connsenable[3] = 0; 4810 break; 4811 case HDA_CODEC_AD1986A: 4812 /* 4813 * This codec has overcomplicated input mixing. 4814 * Make some cleaning there. 4815 */ 4816 /* Disable input mono mixer. Not needed and not supported. */ 4817 w = hdac_widget_get(devinfo, 43); 4818 if (w != NULL) 4819 w->enable = 0; 4820 /* Disable any with any input mixing mesh. Use separately. */ 4821 w = hdac_widget_get(devinfo, 39); 4822 if (w != NULL) 4823 w->enable = 0; 4824 w = hdac_widget_get(devinfo, 40); 4825 if (w != NULL) 4826 w->enable = 0; 4827 w = hdac_widget_get(devinfo, 41); 4828 if (w != NULL) 4829 w->enable = 0; 4830 w = hdac_widget_get(devinfo, 42); 4831 if (w != NULL) 4832 w->enable = 0; 4833 /* Disable duplicate mixer node connector. */ 4834 w = hdac_widget_get(devinfo, 15); 4835 if (w != NULL) 4836 w->connsenable[3] = 0; 4837 /* There is only one mic preamplifier, use it effectively. */ 4838 w = hdac_widget_get(devinfo, 31); 4839 if (w != NULL) { 4840 if ((w->wclass.pin.config & 4841 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4842 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4843 w = hdac_widget_get(devinfo, 16); 4844 if (w != NULL) 4845 w->connsenable[2] = 0; 4846 } else { 4847 w = hdac_widget_get(devinfo, 15); 4848 if (w != NULL) 4849 w->connsenable[0] = 0; 4850 } 4851 } 4852 w = hdac_widget_get(devinfo, 32); 4853 if (w != NULL) { 4854 if ((w->wclass.pin.config & 4855 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4856 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4857 w = hdac_widget_get(devinfo, 16); 4858 if (w != NULL) 4859 w->connsenable[0] = 0; 4860 } else { 4861 w = hdac_widget_get(devinfo, 15); 4862 if (w != NULL) 4863 w->connsenable[1] = 0; 4864 } 4865 } 4866 4867 if (subvendor == ASUS_A8X_SUBVENDOR) { 4868 /* 4869 * This is just plain ridiculous.. There 4870 * are several A8 series that share the same 4871 * pci id but works differently (EAPD). 4872 */ 4873 w = hdac_widget_get(devinfo, 26); 4874 if (w != NULL && w->type == 4875 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4876 (w->wclass.pin.config & 4877 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4878 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4879 devinfo->function.audio.quirks &= 4880 ~HDA_QUIRK_EAPDINV; 4881 } 4882 break; 4883 case HDA_CODEC_AD1981HD: 4884 /* 4885 * This codec has very unusual design with several 4886 * points inappropriate for the present parser. 4887 */ 4888 /* Disable recording from mono playback mix. */ 4889 w = hdac_widget_get(devinfo, 21); 4890 if (w != NULL) 4891 w->connsenable[3] = 0; 4892 /* Disable rear to front mic mixer, use separately. */ 4893 w = hdac_widget_get(devinfo, 31); 4894 if (w != NULL) 4895 w->enable = 0; 4896 /* Disable direct playback, use mixer. */ 4897 w = hdac_widget_get(devinfo, 5); 4898 if (w != NULL) 4899 w->connsenable[0] = 0; 4900 w = hdac_widget_get(devinfo, 6); 4901 if (w != NULL) 4902 w->connsenable[0] = 0; 4903 w = hdac_widget_get(devinfo, 9); 4904 if (w != NULL) 4905 w->connsenable[0] = 0; 4906 w = hdac_widget_get(devinfo, 24); 4907 if (w != NULL) 4908 w->connsenable[0] = 0; 4909 break; 4910 } 4911 } 4912 4913 /* 4914 * Trace path from DAC to pin. 4915 */ 4916 static nid_t 4917 hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4918 int dupseq, int min, int only, int depth) 4919 { 4920 struct hdac_widget *w; 4921 int i, im = -1; 4922 nid_t m = 0, ret; 4923 4924 if (depth > HDA_PARSE_MAXDEPTH) 4925 return (0); 4926 w = hdac_widget_get(devinfo, nid); 4927 if (w == NULL || w->enable == 0) 4928 return (0); 4929 HDA_BOOTHVERBOSE( 4930 if (!only) { 4931 device_printf(devinfo->codec->sc->dev, 4932 " %*stracing via nid %d\n", 4933 depth + 1, "", w->nid); 4934 } 4935 ); 4936 /* Use only unused widgets */ 4937 if (w->bindas >= 0 && w->bindas != as) { 4938 HDA_BOOTHVERBOSE( 4939 if (!only) { 4940 device_printf(devinfo->codec->sc->dev, 4941 " %*snid %d busy by association %d\n", 4942 depth + 1, "", w->nid, w->bindas); 4943 } 4944 ); 4945 return (0); 4946 } 4947 if (dupseq < 0) { 4948 if (w->bindseqmask != 0) { 4949 HDA_BOOTHVERBOSE( 4950 if (!only) { 4951 device_printf(devinfo->codec->sc->dev, 4952 " %*snid %d busy by seqmask %x\n", 4953 depth + 1, "", w->nid, w->bindseqmask); 4954 } 4955 ); 4956 return (0); 4957 } 4958 } else { 4959 /* If this is headphones - allow duplicate first pin. */ 4960 if (w->bindseqmask != 0 && 4961 (w->bindseqmask & (1 << dupseq)) == 0) { 4962 HDA_BOOTHVERBOSE( 4963 device_printf(devinfo->codec->sc->dev, 4964 " %*snid %d busy by seqmask %x\n", 4965 depth + 1, "", w->nid, w->bindseqmask); 4966 ); 4967 return (0); 4968 } 4969 } 4970 4971 switch (w->type) { 4972 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4973 /* Do not traverse input. AD1988 has digital monitor 4974 for which we are not ready. */ 4975 break; 4976 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4977 /* If we are tracing HP take only dac of first pin. */ 4978 if ((only == 0 || only == w->nid) && 4979 (w->nid >= min) && (dupseq < 0 || w->nid == 4980 devinfo->function.audio.as[as].dacs[dupseq])) 4981 m = w->nid; 4982 break; 4983 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4984 if (depth > 0) 4985 break; 4986 /* Fall */ 4987 default: 4988 /* Find reachable DACs with smallest nid respecting constraints. */ 4989 for (i = 0; i < w->nconns; i++) { 4990 if (w->connsenable[i] == 0) 4991 continue; 4992 if (w->selconn != -1 && w->selconn != i) 4993 continue; 4994 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4995 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4996 if (m == 0 || ret < m) { 4997 m = ret; 4998 im = i; 4999 } 5000 if (only || dupseq >= 0) 5001 break; 5002 } 5003 } 5004 if (m && only && ((w->nconns > 1 && 5005 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5006 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 5007 w->selconn = im; 5008 break; 5009 } 5010 if (m && only) { 5011 w->bindas = as; 5012 w->bindseqmask |= (1 << seq); 5013 } 5014 HDA_BOOTHVERBOSE( 5015 if (!only) { 5016 device_printf(devinfo->codec->sc->dev, 5017 " %*snid %d returned %d\n", 5018 depth + 1, "", w->nid, m); 5019 } 5020 ); 5021 return (m); 5022 } 5023 5024 /* 5025 * Trace path from widget to ADC. 5026 */ 5027 static nid_t 5028 hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 5029 int only, int depth) 5030 { 5031 struct hdac_widget *w, *wc; 5032 int i, j; 5033 nid_t res = 0; 5034 5035 if (depth > HDA_PARSE_MAXDEPTH) 5036 return (0); 5037 w = hdac_widget_get(devinfo, nid); 5038 if (w == NULL || w->enable == 0) 5039 return (0); 5040 HDA_BOOTHVERBOSE( 5041 device_printf(devinfo->codec->sc->dev, 5042 " %*stracing via nid %d\n", 5043 depth + 1, "", w->nid); 5044 ); 5045 /* Use only unused widgets */ 5046 if (w->bindas >= 0 && w->bindas != as) { 5047 HDA_BOOTHVERBOSE( 5048 device_printf(devinfo->codec->sc->dev, 5049 " %*snid %d busy by association %d\n", 5050 depth + 1, "", w->nid, w->bindas); 5051 ); 5052 return (0); 5053 } 5054 5055 switch (w->type) { 5056 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5057 /* If we are tracing HP take only dac of first pin. */ 5058 if (only == w->nid) 5059 res = 1; 5060 break; 5061 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5062 if (depth > 0) 5063 break; 5064 /* Fall */ 5065 default: 5066 /* Try to find reachable ADCs with specified nid. */ 5067 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5068 wc = hdac_widget_get(devinfo, j); 5069 if (wc == NULL || wc->enable == 0) 5070 continue; 5071 for (i = 0; i < wc->nconns; i++) { 5072 if (wc->connsenable[i] == 0) 5073 continue; 5074 if (wc->conns[i] != nid) 5075 continue; 5076 if (hdac_audio_trace_adc(devinfo, as, seq, 5077 j, only, depth + 1) != 0) { 5078 res = 1; 5079 if (((wc->nconns > 1 && 5080 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5081 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5082 wc->selconn == -1) 5083 wc->selconn = i; 5084 } 5085 } 5086 } 5087 break; 5088 } 5089 if (res) { 5090 w->bindas = as; 5091 w->bindseqmask |= (1 << seq); 5092 } 5093 HDA_BOOTHVERBOSE( 5094 device_printf(devinfo->codec->sc->dev, 5095 " %*snid %d returned %d\n", 5096 depth + 1, "", w->nid, res); 5097 ); 5098 return (res); 5099 } 5100 5101 /* 5102 * Erase trace path of the specified association. 5103 */ 5104 static void 5105 hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5106 { 5107 struct hdac_widget *w; 5108 int i; 5109 5110 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5111 w = hdac_widget_get(devinfo, i); 5112 if (w == NULL || w->enable == 0) 5113 continue; 5114 if (w->bindas == as) { 5115 if (seq >= 0) { 5116 w->bindseqmask &= ~(1 << seq); 5117 if (w->bindseqmask == 0) { 5118 w->bindas = -1; 5119 w->selconn = -1; 5120 } 5121 } else { 5122 w->bindas = -1; 5123 w->bindseqmask = 0; 5124 w->selconn = -1; 5125 } 5126 } 5127 } 5128 } 5129 5130 /* 5131 * Trace association path from DAC to output 5132 */ 5133 static int 5134 hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5135 { 5136 struct hdac_audio_as *ases = devinfo->function.audio.as; 5137 int i, hpredir; 5138 nid_t min, res; 5139 5140 /* Find next pin */ 5141 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5142 ; 5143 /* Check if there is no any left. If so - we succeeded. */ 5144 if (i == 16) 5145 return (1); 5146 5147 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5148 min = 0; 5149 res = 0; 5150 do { 5151 HDA_BOOTHVERBOSE( 5152 device_printf(devinfo->codec->sc->dev, 5153 " Tracing pin %d with min nid %d", 5154 ases[as].pins[i], min); 5155 if (hpredir >= 0) 5156 printf(" and hpredir %d", hpredir); 5157 printf("\n"); 5158 ); 5159 /* Trace this pin taking min nid into account. */ 5160 res = hdac_audio_trace_dac(devinfo, as, i, 5161 ases[as].pins[i], hpredir, min, 0, 0); 5162 if (res == 0) { 5163 /* If we failed - return to previous and redo it. */ 5164 HDA_BOOTVERBOSE( 5165 device_printf(devinfo->codec->sc->dev, 5166 " Unable to trace pin %d seq %d with min " 5167 "nid %d", 5168 ases[as].pins[i], i, min); 5169 if (hpredir >= 0) 5170 printf(" and hpredir %d", hpredir); 5171 printf("\n"); 5172 ); 5173 return (0); 5174 } 5175 HDA_BOOTVERBOSE( 5176 device_printf(devinfo->codec->sc->dev, 5177 " Pin %d traced to DAC %d", 5178 ases[as].pins[i], res); 5179 if (hpredir >= 0) 5180 printf(" and hpredir %d", hpredir); 5181 if (ases[as].fakeredir) 5182 printf(" with fake redirection"); 5183 printf("\n"); 5184 ); 5185 /* Trace again to mark the path */ 5186 hdac_audio_trace_dac(devinfo, as, i, 5187 ases[as].pins[i], hpredir, min, res, 0); 5188 ases[as].dacs[i] = res; 5189 /* We succeeded, so call next. */ 5190 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5191 return (1); 5192 /* If next failed, we should retry with next min */ 5193 hdac_audio_undo_trace(devinfo, as, i); 5194 ases[as].dacs[i] = 0; 5195 min = res + 1; 5196 } while (1); 5197 } 5198 5199 /* 5200 * Trace association path from input to ADC 5201 */ 5202 static int 5203 hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5204 { 5205 struct hdac_audio_as *ases = devinfo->function.audio.as; 5206 struct hdac_widget *w; 5207 int i, j, k; 5208 5209 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5210 w = hdac_widget_get(devinfo, j); 5211 if (w == NULL || w->enable == 0) 5212 continue; 5213 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5214 continue; 5215 if (w->bindas >= 0 && w->bindas != as) 5216 continue; 5217 5218 /* Find next pin */ 5219 for (i = 0; i < 16; i++) { 5220 if (ases[as].pins[i] == 0) 5221 continue; 5222 5223 HDA_BOOTHVERBOSE( 5224 device_printf(devinfo->codec->sc->dev, 5225 " Tracing pin %d to ADC %d\n", 5226 ases[as].pins[i], j); 5227 ); 5228 /* Trace this pin taking goal into account. */ 5229 if (hdac_audio_trace_adc(devinfo, as, i, 5230 ases[as].pins[i], j, 0) == 0) { 5231 /* If we failed - return to previous and redo it. */ 5232 HDA_BOOTVERBOSE( 5233 device_printf(devinfo->codec->sc->dev, 5234 " Unable to trace pin %d to ADC %d, undo traces\n", 5235 ases[as].pins[i], j); 5236 ); 5237 hdac_audio_undo_trace(devinfo, as, -1); 5238 for (k = 0; k < 16; k++) 5239 ases[as].dacs[k] = 0; 5240 break; 5241 } 5242 HDA_BOOTVERBOSE( 5243 device_printf(devinfo->codec->sc->dev, 5244 " Pin %d traced to ADC %d\n", 5245 ases[as].pins[i], j); 5246 ); 5247 ases[as].dacs[i] = j; 5248 } 5249 if (i == 16) 5250 return (1); 5251 } 5252 return (0); 5253 } 5254 5255 /* 5256 * Trace input monitor path from mixer to output association. 5257 */ 5258 static int 5259 hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5260 { 5261 struct hdac_audio_as *ases = devinfo->function.audio.as; 5262 struct hdac_widget *w, *wc; 5263 int i, j; 5264 nid_t res = 0; 5265 5266 if (depth > HDA_PARSE_MAXDEPTH) 5267 return (0); 5268 w = hdac_widget_get(devinfo, nid); 5269 if (w == NULL || w->enable == 0) 5270 return (0); 5271 HDA_BOOTHVERBOSE( 5272 device_printf(devinfo->codec->sc->dev, 5273 " %*stracing via nid %d\n", 5274 depth + 1, "", w->nid); 5275 ); 5276 /* Use only unused widgets */ 5277 if (depth > 0 && w->bindas != -1) { 5278 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5279 HDA_BOOTHVERBOSE( 5280 device_printf(devinfo->codec->sc->dev, 5281 " %*snid %d found output association %d\n", 5282 depth + 1, "", w->nid, w->bindas); 5283 ); 5284 if (w->bindas >= 0) 5285 w->pflags |= HDA_ADC_MONITOR; 5286 return (1); 5287 } else { 5288 HDA_BOOTHVERBOSE( 5289 device_printf(devinfo->codec->sc->dev, 5290 " %*snid %d busy by input association %d\n", 5291 depth + 1, "", w->nid, w->bindas); 5292 ); 5293 return (0); 5294 } 5295 } 5296 5297 switch (w->type) { 5298 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5299 /* Do not traverse input. AD1988 has digital monitor 5300 for which we are not ready. */ 5301 break; 5302 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5303 if (depth > 0) 5304 break; 5305 /* Fall */ 5306 default: 5307 /* Try to find reachable ADCs with specified nid. */ 5308 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5309 wc = hdac_widget_get(devinfo, j); 5310 if (wc == NULL || wc->enable == 0) 5311 continue; 5312 for (i = 0; i < wc->nconns; i++) { 5313 if (wc->connsenable[i] == 0) 5314 continue; 5315 if (wc->conns[i] != nid) 5316 continue; 5317 if (hdac_audio_trace_to_out(devinfo, 5318 j, depth + 1) != 0) { 5319 res = 1; 5320 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5321 wc->selconn == -1) 5322 wc->selconn = i; 5323 } 5324 } 5325 } 5326 break; 5327 } 5328 if (res && w->bindas == -1) 5329 w->bindas = -2; 5330 5331 HDA_BOOTHVERBOSE( 5332 device_printf(devinfo->codec->sc->dev, 5333 " %*snid %d returned %d\n", 5334 depth + 1, "", w->nid, res); 5335 ); 5336 return (res); 5337 } 5338 5339 /* 5340 * Trace extra associations (beeper, monitor) 5341 */ 5342 static void 5343 hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5344 { 5345 struct hdac_audio_as *as = devinfo->function.audio.as; 5346 struct hdac_widget *w; 5347 int j; 5348 5349 /* Input monitor */ 5350 /* Find mixer associated with input, but supplying signal 5351 for output associations. Hope it will be input monitor. */ 5352 HDA_BOOTVERBOSE( 5353 device_printf(devinfo->codec->sc->dev, 5354 "Tracing input monitor\n"); 5355 ); 5356 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5357 w = hdac_widget_get(devinfo, j); 5358 if (w == NULL || w->enable == 0) 5359 continue; 5360 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5361 continue; 5362 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5363 continue; 5364 HDA_BOOTVERBOSE( 5365 device_printf(devinfo->codec->sc->dev, 5366 " Tracing nid %d to out\n", 5367 j); 5368 ); 5369 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5370 HDA_BOOTVERBOSE( 5371 device_printf(devinfo->codec->sc->dev, 5372 " nid %d is input monitor\n", 5373 w->nid); 5374 ); 5375 w->ossdev = SOUND_MIXER_IMIX; 5376 } 5377 } 5378 5379 /* Other inputs monitor */ 5380 /* Find input pins supplying signal for output associations. 5381 Hope it will be input monitoring. */ 5382 HDA_BOOTVERBOSE( 5383 device_printf(devinfo->codec->sc->dev, 5384 "Tracing other input monitors\n"); 5385 ); 5386 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5387 w = hdac_widget_get(devinfo, j); 5388 if (w == NULL || w->enable == 0) 5389 continue; 5390 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5391 continue; 5392 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5393 continue; 5394 HDA_BOOTVERBOSE( 5395 device_printf(devinfo->codec->sc->dev, 5396 " Tracing nid %d to out\n", 5397 j); 5398 ); 5399 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5400 HDA_BOOTVERBOSE( 5401 device_printf(devinfo->codec->sc->dev, 5402 " nid %d is input monitor\n", 5403 w->nid); 5404 ); 5405 } 5406 } 5407 5408 /* Beeper */ 5409 HDA_BOOTVERBOSE( 5410 device_printf(devinfo->codec->sc->dev, 5411 "Tracing beeper\n"); 5412 ); 5413 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5414 w = hdac_widget_get(devinfo, j); 5415 if (w == NULL || w->enable == 0) 5416 continue; 5417 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5418 continue; 5419 HDA_BOOTHVERBOSE( 5420 device_printf(devinfo->codec->sc->dev, 5421 " Tracing nid %d to out\n", 5422 j); 5423 ); 5424 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5425 HDA_BOOTVERBOSE( 5426 device_printf(devinfo->codec->sc->dev, 5427 " nid %d traced to out\n", 5428 j); 5429 ); 5430 } 5431 w->bindas = -2; 5432 } 5433 } 5434 5435 /* 5436 * Bind assotiations to PCM channels 5437 */ 5438 static void 5439 hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5440 { 5441 struct hdac_softc *sc = devinfo->codec->sc; 5442 struct hdac_audio_as *as = devinfo->function.audio.as; 5443 int j, cnt = 0, free; 5444 5445 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5446 if (as[j].enable) 5447 cnt++; 5448 } 5449 if (sc->num_chans == 0) { 5450 sc->chans = (struct hdac_chan *)malloc( 5451 sizeof(struct hdac_chan) * cnt, 5452 M_HDAC, M_ZERO | M_NOWAIT); 5453 if (sc->chans == NULL) { 5454 device_printf(sc->dev, 5455 "Channels memory allocation failed!\n"); 5456 return; 5457 } 5458 } else { 5459 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5460 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5461 M_HDAC, M_ZERO | M_NOWAIT); 5462 if (sc->chans == NULL) { 5463 sc->num_chans = 0; 5464 device_printf(sc->dev, 5465 "Channels memory allocation failed!\n"); 5466 return; 5467 } 5468 /* Fixup relative pointers after realloc */ 5469 for (j = 0; j < sc->num_chans; j++) 5470 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5471 } 5472 free = sc->num_chans; 5473 sc->num_chans += cnt; 5474 5475 for (j = free; j < free + cnt; j++) { 5476 sc->chans[j].devinfo = devinfo; 5477 sc->chans[j].as = -1; 5478 } 5479 5480 /* Assign associations in order of their numbers, */ 5481 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5482 if (as[j].enable == 0) 5483 continue; 5484 5485 as[j].chan = free; 5486 sc->chans[free].as = j; 5487 sc->chans[free].dir = 5488 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5489 hdac_pcmchannel_setup(&sc->chans[free]); 5490 free++; 5491 } 5492 } 5493 5494 static void 5495 hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5496 { 5497 struct hdac_widget *w; 5498 int i; 5499 5500 /* Disable power and volume widgets. */ 5501 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5502 w = hdac_widget_get(devinfo, i); 5503 if (w == NULL || w->enable == 0) 5504 continue; 5505 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5506 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5507 w->enable = 0; 5508 HDA_BOOTHVERBOSE( 5509 device_printf(devinfo->codec->sc->dev, 5510 " Disabling nid %d due to it's" 5511 " non-audio type.\n", 5512 w->nid); 5513 ); 5514 } 5515 } 5516 } 5517 5518 static void 5519 hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5520 { 5521 struct hdac_widget *w, *cw; 5522 struct hdac_audio_ctl *ctl; 5523 int done, found, i, j, k; 5524 5525 /* Disable useless pins. */ 5526 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5527 w = hdac_widget_get(devinfo, i); 5528 if (w == NULL || w->enable == 0) 5529 continue; 5530 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5531 if ((w->wclass.pin.config & 5532 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5533 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5534 w->enable = 0; 5535 HDA_BOOTHVERBOSE( 5536 device_printf(devinfo->codec->sc->dev, 5537 " Disabling pin nid %d due" 5538 " to None connectivity.\n", 5539 w->nid); 5540 ); 5541 } else if ((w->wclass.pin.config & 5542 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5543 w->enable = 0; 5544 HDA_BOOTHVERBOSE( 5545 device_printf(devinfo->codec->sc->dev, 5546 " Disabling unassociated" 5547 " pin nid %d.\n", 5548 w->nid); 5549 ); 5550 } 5551 } 5552 } 5553 do { 5554 done = 1; 5555 /* Disable and mute controls for disabled widgets. */ 5556 i = 0; 5557 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5558 if (ctl->enable == 0) 5559 continue; 5560 if (ctl->widget->enable == 0 || 5561 (ctl->childwidget != NULL && 5562 ctl->childwidget->enable == 0)) { 5563 ctl->forcemute = 1; 5564 ctl->muted = HDA_AMP_MUTE_ALL; 5565 ctl->left = 0; 5566 ctl->right = 0; 5567 ctl->enable = 0; 5568 if (ctl->ndir == HDA_CTL_IN) 5569 ctl->widget->connsenable[ctl->index] = 0; 5570 done = 0; 5571 HDA_BOOTHVERBOSE( 5572 device_printf(devinfo->codec->sc->dev, 5573 " Disabling ctl %d nid %d cnid %d due" 5574 " to disabled widget.\n", i, 5575 ctl->widget->nid, 5576 (ctl->childwidget != NULL)? 5577 ctl->childwidget->nid:-1); 5578 ); 5579 } 5580 } 5581 /* Disable useless widgets. */ 5582 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5583 w = hdac_widget_get(devinfo, i); 5584 if (w == NULL || w->enable == 0) 5585 continue; 5586 /* Disable inputs with disabled child widgets. */ 5587 for (j = 0; j < w->nconns; j++) { 5588 if (w->connsenable[j]) { 5589 cw = hdac_widget_get(devinfo, w->conns[j]); 5590 if (cw == NULL || cw->enable == 0) { 5591 w->connsenable[j] = 0; 5592 HDA_BOOTHVERBOSE( 5593 device_printf(devinfo->codec->sc->dev, 5594 " Disabling nid %d connection %d due" 5595 " to disabled child widget.\n", 5596 i, j); 5597 ); 5598 } 5599 } 5600 } 5601 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5602 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5603 continue; 5604 /* Disable mixers and selectors without inputs. */ 5605 found = 0; 5606 for (j = 0; j < w->nconns; j++) { 5607 if (w->connsenable[j]) { 5608 found = 1; 5609 break; 5610 } 5611 } 5612 if (found == 0) { 5613 w->enable = 0; 5614 done = 0; 5615 HDA_BOOTHVERBOSE( 5616 device_printf(devinfo->codec->sc->dev, 5617 " Disabling nid %d due to all it's" 5618 " inputs disabled.\n", w->nid); 5619 ); 5620 } 5621 /* Disable nodes without consumers. */ 5622 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5623 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5624 continue; 5625 found = 0; 5626 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5627 cw = hdac_widget_get(devinfo, k); 5628 if (cw == NULL || cw->enable == 0) 5629 continue; 5630 for (j = 0; j < cw->nconns; j++) { 5631 if (cw->connsenable[j] && cw->conns[j] == i) { 5632 found = 1; 5633 break; 5634 } 5635 } 5636 } 5637 if (found == 0) { 5638 w->enable = 0; 5639 done = 0; 5640 HDA_BOOTHVERBOSE( 5641 device_printf(devinfo->codec->sc->dev, 5642 " Disabling nid %d due to all it's" 5643 " consumers disabled.\n", w->nid); 5644 ); 5645 } 5646 } 5647 } while (done == 0); 5648 5649 } 5650 5651 static void 5652 hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5653 { 5654 struct hdac_audio_as *as = devinfo->function.audio.as; 5655 struct hdac_widget *w, *cw; 5656 struct hdac_audio_ctl *ctl; 5657 int i, j, k; 5658 5659 /* Disable unassosiated widgets. */ 5660 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5661 w = hdac_widget_get(devinfo, i); 5662 if (w == NULL || w->enable == 0) 5663 continue; 5664 if (w->bindas == -1) { 5665 w->enable = 0; 5666 HDA_BOOTHVERBOSE( 5667 device_printf(devinfo->codec->sc->dev, 5668 " Disabling unassociated nid %d.\n", 5669 w->nid); 5670 ); 5671 } 5672 } 5673 /* Disable input connections on input pin and 5674 * output on output. */ 5675 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5676 w = hdac_widget_get(devinfo, i); 5677 if (w == NULL || w->enable == 0) 5678 continue; 5679 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5680 continue; 5681 if (w->bindas < 0) 5682 continue; 5683 if (as[w->bindas].dir == HDA_CTL_IN) { 5684 for (j = 0; j < w->nconns; j++) { 5685 if (w->connsenable[j] == 0) 5686 continue; 5687 w->connsenable[j] = 0; 5688 HDA_BOOTHVERBOSE( 5689 device_printf(devinfo->codec->sc->dev, 5690 " Disabling connection to input pin " 5691 "nid %d conn %d.\n", 5692 i, j); 5693 ); 5694 } 5695 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5696 HDA_CTL_IN, -1, 1); 5697 if (ctl && ctl->enable) { 5698 ctl->forcemute = 1; 5699 ctl->muted = HDA_AMP_MUTE_ALL; 5700 ctl->left = 0; 5701 ctl->right = 0; 5702 ctl->enable = 0; 5703 } 5704 } else { 5705 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5706 HDA_CTL_OUT, -1, 1); 5707 if (ctl && ctl->enable) { 5708 ctl->forcemute = 1; 5709 ctl->muted = HDA_AMP_MUTE_ALL; 5710 ctl->left = 0; 5711 ctl->right = 0; 5712 ctl->enable = 0; 5713 } 5714 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5715 cw = hdac_widget_get(devinfo, k); 5716 if (cw == NULL || cw->enable == 0) 5717 continue; 5718 for (j = 0; j < cw->nconns; j++) { 5719 if (cw->connsenable[j] && cw->conns[j] == i) { 5720 cw->connsenable[j] = 0; 5721 HDA_BOOTHVERBOSE( 5722 device_printf(devinfo->codec->sc->dev, 5723 " Disabling connection from output pin " 5724 "nid %d conn %d cnid %d.\n", 5725 k, j, i); 5726 ); 5727 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5728 cw->nconns > 1) 5729 continue; 5730 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5731 HDA_CTL_IN, j, 1); 5732 if (ctl && ctl->enable) { 5733 ctl->forcemute = 1; 5734 ctl->muted = HDA_AMP_MUTE_ALL; 5735 ctl->left = 0; 5736 ctl->right = 0; 5737 ctl->enable = 0; 5738 } 5739 } 5740 } 5741 } 5742 } 5743 } 5744 } 5745 5746 static void 5747 hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5748 { 5749 struct hdac_audio_as *as = devinfo->function.audio.as; 5750 struct hdac_widget *w; 5751 int i, j; 5752 5753 /* On playback path we can safely disable all unseleted inputs. */ 5754 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5755 w = hdac_widget_get(devinfo, i); 5756 if (w == NULL || w->enable == 0) 5757 continue; 5758 if (w->nconns <= 1) 5759 continue; 5760 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5761 continue; 5762 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5763 continue; 5764 for (j = 0; j < w->nconns; j++) { 5765 if (w->connsenable[j] == 0) 5766 continue; 5767 if (w->selconn < 0 || w->selconn == j) 5768 continue; 5769 w->connsenable[j] = 0; 5770 HDA_BOOTHVERBOSE( 5771 device_printf(devinfo->codec->sc->dev, 5772 " Disabling unselected connection " 5773 "nid %d conn %d.\n", 5774 i, j); 5775 ); 5776 } 5777 } 5778 } 5779 5780 static void 5781 hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5782 { 5783 struct hdac_audio_as *ases = devinfo->function.audio.as; 5784 struct hdac_widget *w, *cw; 5785 struct hdac_audio_ctl *ctl; 5786 int i, j; 5787 5788 /* Disable crossassociatement and unwanted crosschannel connections. */ 5789 /* ... using selectors */ 5790 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5791 w = hdac_widget_get(devinfo, i); 5792 if (w == NULL || w->enable == 0) 5793 continue; 5794 if (w->nconns <= 1) 5795 continue; 5796 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5797 continue; 5798 if (w->bindas == -2) 5799 continue; 5800 for (j = 0; j < w->nconns; j++) { 5801 if (w->connsenable[j] == 0) 5802 continue; 5803 cw = hdac_widget_get(devinfo, w->conns[j]); 5804 if (cw == NULL || w->enable == 0) 5805 continue; 5806 if (cw->bindas == -2 || 5807 ((w->pflags & HDA_ADC_MONITOR) && 5808 cw->bindas >= 0 && 5809 ases[cw->bindas].dir == HDA_CTL_IN)) 5810 continue; 5811 if (w->bindas == cw->bindas && 5812 (w->bindseqmask & cw->bindseqmask) != 0) 5813 continue; 5814 w->connsenable[j] = 0; 5815 HDA_BOOTHVERBOSE( 5816 device_printf(devinfo->codec->sc->dev, 5817 " Disabling crossassociatement connection " 5818 "nid %d conn %d cnid %d.\n", 5819 i, j, cw->nid); 5820 ); 5821 } 5822 } 5823 /* ... using controls */ 5824 i = 0; 5825 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5826 if (ctl->enable == 0 || ctl->childwidget == NULL) 5827 continue; 5828 if (ctl->widget->bindas == -2) 5829 continue; 5830 if (ctl->childwidget->bindas == -2 || 5831 ((ctl->widget->pflags & HDA_ADC_MONITOR) && 5832 ctl->childwidget->bindas >= 0 && 5833 ases[ctl->childwidget->bindas].dir == HDA_CTL_IN)) 5834 continue; 5835 if (ctl->widget->bindas != ctl->childwidget->bindas || 5836 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5837 ctl->forcemute = 1; 5838 ctl->muted = HDA_AMP_MUTE_ALL; 5839 ctl->left = 0; 5840 ctl->right = 0; 5841 ctl->enable = 0; 5842 if (ctl->ndir == HDA_CTL_IN) 5843 ctl->widget->connsenable[ctl->index] = 0; 5844 HDA_BOOTHVERBOSE( 5845 device_printf(devinfo->codec->sc->dev, 5846 " Disabling crossassociatement connection " 5847 "ctl %d nid %d cnid %d.\n", i, 5848 ctl->widget->nid, 5849 ctl->childwidget->nid); 5850 ); 5851 } 5852 } 5853 5854 } 5855 5856 #define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5857 5858 /* 5859 * Find controls to control amplification for source. 5860 */ 5861 static int 5862 hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5863 int ossdev, int ctlable, int depth, int need) 5864 { 5865 struct hdac_widget *w, *wc; 5866 struct hdac_audio_ctl *ctl; 5867 int i, j, conns = 0, rneed; 5868 5869 if (depth > HDA_PARSE_MAXDEPTH) 5870 return (need); 5871 5872 w = hdac_widget_get(devinfo, nid); 5873 if (w == NULL || w->enable == 0) 5874 return (need); 5875 5876 /* Count number of active inputs. */ 5877 if (depth > 0) { 5878 for (j = 0; j < w->nconns; j++) { 5879 if (w->connsenable[j]) 5880 conns++; 5881 } 5882 } 5883 5884 /* If this is not a first step - use input mixer. 5885 Pins have common input ctl so care must be taken. */ 5886 if (depth > 0 && ctlable && (conns == 1 || 5887 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5888 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5889 index, 1); 5890 if (ctl) { 5891 if (HDA_CTL_GIVE(ctl) & need) 5892 ctl->ossmask |= (1 << ossdev); 5893 else 5894 ctl->possmask |= (1 << ossdev); 5895 need &= ~HDA_CTL_GIVE(ctl); 5896 } 5897 } 5898 5899 /* If widget has own ossdev - not traverse it. 5900 It will be traversed on it's own. */ 5901 if (w->ossdev >= 0 && depth > 0) 5902 return (need); 5903 5904 /* We must not traverse pin */ 5905 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5906 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5907 depth > 0) 5908 return (need); 5909 5910 /* record that this widget exports such signal, */ 5911 w->ossmask |= (1 << ossdev); 5912 5913 /* If signals mixed, we can't assign controls farther. 5914 * Ignore this on depth zero. Caller must knows why. 5915 * Ignore this for static selectors if this input selected. 5916 */ 5917 if (conns > 1) 5918 ctlable = 0; 5919 5920 if (ctlable) { 5921 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5922 if (ctl) { 5923 if (HDA_CTL_GIVE(ctl) & need) 5924 ctl->ossmask |= (1 << ossdev); 5925 else 5926 ctl->possmask |= (1 << ossdev); 5927 need &= ~HDA_CTL_GIVE(ctl); 5928 } 5929 } 5930 5931 rneed = 0; 5932 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5933 wc = hdac_widget_get(devinfo, i); 5934 if (wc == NULL || wc->enable == 0) 5935 continue; 5936 for (j = 0; j < wc->nconns; j++) { 5937 if (wc->connsenable[j] && wc->conns[j] == nid) { 5938 rneed |= hdac_audio_ctl_source_amp(devinfo, 5939 wc->nid, j, ossdev, ctlable, depth + 1, need); 5940 } 5941 } 5942 } 5943 rneed &= need; 5944 5945 return (rneed); 5946 } 5947 5948 /* 5949 * Find controls to control amplification for destination. 5950 */ 5951 static void 5952 hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5953 int ossdev, int depth, int need) 5954 { 5955 struct hdac_audio_as *as = devinfo->function.audio.as; 5956 struct hdac_widget *w, *wc; 5957 struct hdac_audio_ctl *ctl; 5958 int i, j, consumers; 5959 5960 if (depth > HDA_PARSE_MAXDEPTH) 5961 return; 5962 5963 w = hdac_widget_get(devinfo, nid); 5964 if (w == NULL || w->enable == 0) 5965 return; 5966 5967 if (depth > 0) { 5968 /* If this node produce output for several consumers, 5969 we can't touch it. */ 5970 consumers = 0; 5971 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5972 wc = hdac_widget_get(devinfo, i); 5973 if (wc == NULL || wc->enable == 0) 5974 continue; 5975 for (j = 0; j < wc->nconns; j++) { 5976 if (wc->connsenable[j] && wc->conns[j] == nid) 5977 consumers++; 5978 } 5979 } 5980 /* The only exception is if real HP redirection is configured 5981 and this is a duplication point. 5982 XXX: Actually exception is not completely correct. 5983 XXX: Duplication point check is not perfect. */ 5984 if ((consumers == 2 && (w->bindas < 0 || 5985 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5986 (w->bindseqmask & (1 << 15)) == 0)) || 5987 consumers > 2) 5988 return; 5989 5990 /* Else use it's output mixer. */ 5991 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5992 HDA_CTL_OUT, -1, 1); 5993 if (ctl) { 5994 if (HDA_CTL_GIVE(ctl) & need) 5995 ctl->ossmask |= (1 << ossdev); 5996 else 5997 ctl->possmask |= (1 << ossdev); 5998 need &= ~HDA_CTL_GIVE(ctl); 5999 } 6000 } 6001 6002 /* We must not traverse pin */ 6003 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6004 depth > 0) 6005 return; 6006 6007 for (i = 0; i < w->nconns; i++) { 6008 int tneed = need; 6009 if (w->connsenable[i] == 0) 6010 continue; 6011 if (index >= 0 && i != index) 6012 continue; 6013 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 6014 HDA_CTL_IN, i, 1); 6015 if (ctl) { 6016 if (HDA_CTL_GIVE(ctl) & tneed) 6017 ctl->ossmask |= (1 << ossdev); 6018 else 6019 ctl->possmask |= (1 << ossdev); 6020 tneed &= ~HDA_CTL_GIVE(ctl); 6021 } 6022 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], -1, ossdev, 6023 depth + 1, tneed); 6024 } 6025 } 6026 6027 /* 6028 * Assign OSS names to sound sources 6029 */ 6030 static void 6031 hdac_audio_assign_names(struct hdac_devinfo *devinfo) 6032 { 6033 struct hdac_audio_as *as = devinfo->function.audio.as; 6034 struct hdac_widget *w; 6035 int i, j; 6036 int type = -1, use, used = 0; 6037 static const int types[7][13] = { 6038 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6039 SOUND_MIXER_LINE3, -1 }, /* line */ 6040 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 6041 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 6042 { SOUND_MIXER_CD, -1 }, /* cd */ 6043 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 6044 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 6045 -1 }, /* digital */ 6046 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6047 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 6048 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 6049 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 6050 -1 } /* others */ 6051 }; 6052 6053 /* Surely known names */ 6054 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6055 w = hdac_widget_get(devinfo, i); 6056 if (w == NULL || w->enable == 0) 6057 continue; 6058 if (w->bindas == -1) 6059 continue; 6060 use = -1; 6061 switch (w->type) { 6062 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 6063 if (as[w->bindas].dir == HDA_CTL_OUT) 6064 break; 6065 type = -1; 6066 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6067 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 6068 type = 0; 6069 break; 6070 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6071 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 6072 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 6073 break; 6074 type = 1; 6075 break; 6076 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 6077 type = 3; 6078 break; 6079 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6080 type = 4; 6081 break; 6082 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 6083 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 6084 type = 5; 6085 break; 6086 } 6087 if (type == -1) 6088 break; 6089 j = 0; 6090 while (types[type][j] >= 0 && 6091 (used & (1 << types[type][j])) != 0) { 6092 j++; 6093 } 6094 if (types[type][j] >= 0) 6095 use = types[type][j]; 6096 break; 6097 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 6098 use = SOUND_MIXER_PCM; 6099 break; 6100 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 6101 use = SOUND_MIXER_SPEAKER; 6102 break; 6103 default: 6104 break; 6105 } 6106 if (use >= 0) { 6107 w->ossdev = use; 6108 used |= (1 << use); 6109 } 6110 } 6111 /* Semi-known names */ 6112 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6113 w = hdac_widget_get(devinfo, i); 6114 if (w == NULL || w->enable == 0) 6115 continue; 6116 if (w->ossdev >= 0) 6117 continue; 6118 if (w->bindas == -1) 6119 continue; 6120 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6121 continue; 6122 if (as[w->bindas].dir == HDA_CTL_OUT) 6123 continue; 6124 type = -1; 6125 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6126 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6127 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6128 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6129 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6130 type = 0; 6131 break; 6132 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6133 type = 2; 6134 break; 6135 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6136 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6137 type = 5; 6138 break; 6139 } 6140 if (type == -1) 6141 break; 6142 j = 0; 6143 while (types[type][j] >= 0 && 6144 (used & (1 << types[type][j])) != 0) { 6145 j++; 6146 } 6147 if (types[type][j] >= 0) { 6148 w->ossdev = types[type][j]; 6149 used |= (1 << types[type][j]); 6150 } 6151 } 6152 /* Others */ 6153 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6154 w = hdac_widget_get(devinfo, i); 6155 if (w == NULL || w->enable == 0) 6156 continue; 6157 if (w->ossdev >= 0) 6158 continue; 6159 if (w->bindas == -1) 6160 continue; 6161 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6162 continue; 6163 if (as[w->bindas].dir == HDA_CTL_OUT) 6164 continue; 6165 j = 0; 6166 while (types[6][j] >= 0 && 6167 (used & (1 << types[6][j])) != 0) { 6168 j++; 6169 } 6170 if (types[6][j] >= 0) { 6171 w->ossdev = types[6][j]; 6172 used |= (1 << types[6][j]); 6173 } 6174 } 6175 } 6176 6177 static void 6178 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6179 { 6180 struct hdac_audio_as *as = devinfo->function.audio.as; 6181 int j, res; 6182 6183 /* Trace all associations in order of their numbers, */ 6184 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6185 if (as[j].enable == 0) 6186 continue; 6187 HDA_BOOTVERBOSE( 6188 device_printf(devinfo->codec->sc->dev, 6189 "Tracing association %d (%d)\n", j, as[j].index); 6190 ); 6191 if (as[j].dir == HDA_CTL_OUT) { 6192 retry: 6193 res = hdac_audio_trace_as_out(devinfo, j, 0); 6194 if (res == 0 && as[j].hpredir >= 0 && 6195 as[j].fakeredir == 0) { 6196 /* If codec can't do analog HP redirection 6197 try to make it using one more DAC. */ 6198 as[j].fakeredir = 1; 6199 goto retry; 6200 } 6201 } else { 6202 res = hdac_audio_trace_as_in(devinfo, j); 6203 } 6204 if (res) { 6205 HDA_BOOTVERBOSE( 6206 device_printf(devinfo->codec->sc->dev, 6207 "Association %d (%d) trace succeeded\n", 6208 j, as[j].index); 6209 ); 6210 } else { 6211 HDA_BOOTVERBOSE( 6212 device_printf(devinfo->codec->sc->dev, 6213 "Association %d (%d) trace failed\n", 6214 j, as[j].index); 6215 ); 6216 as[j].enable = 0; 6217 } 6218 } 6219 6220 /* Trace mixer and beeper pseudo associations. */ 6221 hdac_audio_trace_as_extra(devinfo); 6222 } 6223 6224 static void 6225 hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6226 { 6227 struct hdac_audio_as *as = devinfo->function.audio.as; 6228 struct hdac_audio_ctl *ctl; 6229 struct hdac_widget *w, *cw; 6230 int i, j; 6231 6232 /* Assign mixers to the tree. */ 6233 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6234 w = hdac_widget_get(devinfo, i); 6235 if (w == NULL || w->enable == 0) 6236 continue; 6237 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6238 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6239 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6240 as[w->bindas].dir == HDA_CTL_IN)) { 6241 if (w->ossdev < 0) 6242 continue; 6243 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6244 w->ossdev, 1, 0, 1); 6245 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6246 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6247 SOUND_MIXER_RECLEV, 0, 1); 6248 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6249 as[w->bindas].dir == HDA_CTL_OUT) { 6250 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6251 SOUND_MIXER_VOLUME, 0, 1); 6252 } 6253 if (w->ossdev == SOUND_MIXER_IMIX) { 6254 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6255 w->ossdev, 1, 0, 1)) { 6256 /* If we are unable to control input monitor 6257 as source - try to control it as destination. */ 6258 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6259 w->ossdev, 0, 1); 6260 } 6261 } 6262 if (w->pflags & HDA_ADC_MONITOR) { 6263 for (j = 0; j < w->nconns; j++) { 6264 if (!w->connsenable[j]) 6265 continue; 6266 cw = hdac_widget_get(devinfo, w->conns[j]); 6267 if (cw == NULL || cw->enable == 0) 6268 continue; 6269 if (cw->bindas == -1) 6270 continue; 6271 if (cw->bindas >= 0 && 6272 as[cw->bindas].dir != HDA_CTL_IN) 6273 continue; 6274 hdac_audio_ctl_dest_amp(devinfo, 6275 w->nid, j, SOUND_MIXER_IGAIN, 0, 1); 6276 } 6277 } 6278 } 6279 /* Treat unrequired as possible. */ 6280 i = 0; 6281 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6282 if (ctl->ossmask == 0) 6283 ctl->ossmask = ctl->possmask; 6284 } 6285 } 6286 6287 static void 6288 hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6289 { 6290 struct hdac_audio_as *as = devinfo->function.audio.as; 6291 struct hdac_widget *w; 6292 uint32_t pincap; 6293 int i; 6294 6295 for (i = 0; i < devinfo->nodecnt; i++) { 6296 w = &devinfo->widget[i]; 6297 if (w == NULL) 6298 continue; 6299 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6300 continue; 6301 6302 pincap = w->wclass.pin.cap; 6303 6304 /* Disable everything. */ 6305 w->wclass.pin.ctrl &= ~( 6306 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6307 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6308 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6309 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6310 6311 if (w->enable == 0 || 6312 w->bindas < 0 || as[w->bindas].enable == 0) { 6313 /* Pin is unused so left it disabled. */ 6314 continue; 6315 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6316 /* Input pin, configure for input. */ 6317 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6318 w->wclass.pin.ctrl |= 6319 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6320 6321 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6322 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6323 w->wclass.pin.ctrl |= 6324 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6325 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6326 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6327 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6328 w->wclass.pin.ctrl |= 6329 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6330 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6331 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6332 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6333 w->wclass.pin.ctrl |= 6334 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6335 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6336 } else { 6337 /* Output pin, configure for output. */ 6338 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6339 w->wclass.pin.ctrl |= 6340 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6341 6342 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6343 (w->wclass.pin.config & 6344 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6345 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6346 w->wclass.pin.ctrl |= 6347 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6348 6349 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6350 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6351 w->wclass.pin.ctrl |= 6352 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6353 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6354 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6355 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6356 w->wclass.pin.ctrl |= 6357 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6358 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6359 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6360 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6361 w->wclass.pin.ctrl |= 6362 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6363 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6364 } 6365 } 6366 } 6367 6368 static void 6369 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6370 { 6371 struct hdac_audio_ctl *ctl; 6372 int i, z; 6373 6374 i = 0; 6375 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6376 if (ctl->enable == 0 || ctl->ossmask != 0) { 6377 /* Mute disabled and mixer controllable controls. 6378 * Last will be initialized by mixer_init(). 6379 * This expected to reduce click on startup. */ 6380 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6381 continue; 6382 } 6383 /* Init fixed controls to 0dB amplification. */ 6384 z = ctl->offset; 6385 if (z > ctl->step) 6386 z = ctl->step; 6387 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6388 } 6389 } 6390 6391 static void 6392 hdac_audio_commit(struct hdac_devinfo *devinfo) 6393 { 6394 struct hdac_softc *sc = devinfo->codec->sc; 6395 struct hdac_widget *w; 6396 nid_t cad; 6397 uint32_t gdata, gmask, gdir; 6398 int commitgpio, numgpio; 6399 int i; 6400 6401 cad = devinfo->codec->cad; 6402 6403 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6404 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6405 0x7e7, 0), cad); 6406 6407 /* Commit controls. */ 6408 hdac_audio_ctl_commit(devinfo); 6409 6410 /* Commit selectors, pins and EAPD. */ 6411 for (i = 0; i < devinfo->nodecnt; i++) { 6412 w = &devinfo->widget[i]; 6413 if (w == NULL) 6414 continue; 6415 if (w->selconn == -1) 6416 w->selconn = 0; 6417 if (w->nconns > 0) 6418 hdac_widget_connection_select(w, w->selconn); 6419 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6420 hdac_command(sc, 6421 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6422 w->wclass.pin.ctrl), cad); 6423 } 6424 if (w->param.eapdbtl != HDAC_INVALID) { 6425 uint32_t val; 6426 6427 val = w->param.eapdbtl; 6428 if (devinfo->function.audio.quirks & 6429 HDA_QUIRK_EAPDINV) 6430 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6431 hdac_command(sc, 6432 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6433 val), cad); 6434 } 6435 } 6436 6437 /* Commit GPIOs. */ 6438 gdata = 0; 6439 gmask = 0; 6440 gdir = 0; 6441 commitgpio = 0; 6442 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6443 devinfo->function.audio.gpio); 6444 6445 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6446 commitgpio = (numgpio > 0) ? 1 : 0; 6447 else { 6448 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6449 if (!(devinfo->function.audio.quirks & 6450 (1 << i))) 6451 continue; 6452 if (commitgpio == 0) { 6453 commitgpio = 1; 6454 HDA_BOOTVERBOSE( 6455 gdata = hdac_command(sc, 6456 HDA_CMD_GET_GPIO_DATA(cad, 6457 devinfo->nid), cad); 6458 gmask = hdac_command(sc, 6459 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6460 devinfo->nid), cad); 6461 gdir = hdac_command(sc, 6462 HDA_CMD_GET_GPIO_DIRECTION(cad, 6463 devinfo->nid), cad); 6464 device_printf(sc->dev, 6465 "GPIO init: data=0x%08x " 6466 "mask=0x%08x dir=0x%08x\n", 6467 gdata, gmask, gdir); 6468 gdata = 0; 6469 gmask = 0; 6470 gdir = 0; 6471 ); 6472 } 6473 gdata |= 1 << i; 6474 gmask |= 1 << i; 6475 gdir |= 1 << i; 6476 } 6477 } 6478 6479 if (commitgpio != 0) { 6480 HDA_BOOTVERBOSE( 6481 device_printf(sc->dev, 6482 "GPIO commit: data=0x%08x mask=0x%08x " 6483 "dir=0x%08x\n", 6484 gdata, gmask, gdir); 6485 ); 6486 hdac_command(sc, 6487 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6488 gmask), cad); 6489 hdac_command(sc, 6490 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6491 gdir), cad); 6492 hdac_command(sc, 6493 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6494 gdata), cad); 6495 } 6496 } 6497 6498 static void 6499 hdac_powerup(struct hdac_devinfo *devinfo) 6500 { 6501 struct hdac_softc *sc = devinfo->codec->sc; 6502 nid_t cad = devinfo->codec->cad; 6503 int i; 6504 6505 hdac_command(sc, 6506 HDA_CMD_SET_POWER_STATE(cad, 6507 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6508 cad); 6509 DELAY(100); 6510 6511 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6512 hdac_command(sc, 6513 HDA_CMD_SET_POWER_STATE(cad, 6514 i, HDA_CMD_POWER_STATE_D0), 6515 cad); 6516 } 6517 DELAY(1000); 6518 } 6519 6520 static int 6521 hdac_pcmchannel_setup(struct hdac_chan *ch) 6522 { 6523 struct hdac_devinfo *devinfo = ch->devinfo; 6524 struct hdac_audio_as *as = devinfo->function.audio.as; 6525 struct hdac_widget *w; 6526 uint32_t cap, fmtcap, pcmcap; 6527 int i, j, ret, channels, onlystereo; 6528 uint16_t pinset; 6529 6530 ch->caps = hdac_caps; 6531 ch->caps.fmtlist = ch->fmtlist; 6532 ch->bit16 = 1; 6533 ch->bit32 = 0; 6534 ch->pcmrates[0] = 48000; 6535 ch->pcmrates[1] = 0; 6536 6537 ret = 0; 6538 channels = 0; 6539 onlystereo = 1; 6540 pinset = 0; 6541 fmtcap = devinfo->function.audio.supp_stream_formats; 6542 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6543 6544 for (i = 0; i < 16; i++) { 6545 /* Check as is correct */ 6546 if (ch->as < 0) 6547 break; 6548 /* Cound only present DACs */ 6549 if (as[ch->as].dacs[i] <= 0) 6550 continue; 6551 /* Ignore duplicates */ 6552 for (j = 0; j < ret; j++) { 6553 if (ch->io[j] == as[ch->as].dacs[i]) 6554 break; 6555 } 6556 if (j < ret) 6557 continue; 6558 6559 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6560 if (w == NULL || w->enable == 0) 6561 continue; 6562 cap = w->param.supp_stream_formats; 6563 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6564 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6565 continue; 6566 /* Many CODECs does not declare AC3 support on SPDIF. 6567 I don't beleave that they doesn't support it! */ 6568 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6569 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6570 if (ret == 0) { 6571 fmtcap = cap; 6572 pcmcap = w->param.supp_pcm_size_rate; 6573 } else { 6574 fmtcap &= cap; 6575 pcmcap &= w->param.supp_pcm_size_rate; 6576 } 6577 ch->io[ret++] = as[ch->as].dacs[i]; 6578 /* Do not count redirection pin/dac channels. */ 6579 if (i == 15 && as[ch->as].hpredir >= 0) 6580 continue; 6581 channels += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 6582 if (HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) != 1) 6583 onlystereo = 0; 6584 pinset |= (1 << i); 6585 } 6586 ch->io[ret] = -1; 6587 6588 if (as[ch->as].fakeredir) 6589 ret--; 6590 /* Standard speaks only about stereo pins and playback, ... */ 6591 if ((!onlystereo) || as[ch->as].dir != HDA_CTL_OUT) 6592 pinset = 0; 6593 /* ..., but there it gives us info about speakers layout. */ 6594 as[ch->as].pinset = pinset; 6595 6596 ch->supp_stream_formats = fmtcap; 6597 ch->supp_pcm_size_rate = pcmcap; 6598 6599 /* 6600 * 8bit = 0 6601 * 16bit = 1 6602 * 20bit = 2 6603 * 24bit = 3 6604 * 32bit = 4 6605 */ 6606 if (ret > 0) { 6607 i = 0; 6608 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6609 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6610 ch->bit16 = 1; 6611 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6612 ch->bit16 = 0; 6613 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6614 ch->bit32 = 4; 6615 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6616 ch->bit32 = 3; 6617 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6618 ch->bit32 = 2; 6619 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) { 6620 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 1, 0); 6621 if (ch->bit32) 6622 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 1, 0); 6623 } 6624 if (channels >= 2) { 6625 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6626 if (ch->bit32) 6627 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 2, 0); 6628 } 6629 if (channels == 4 || /* Any 4-channel */ 6630 pinset == 0x0007 || /* 5.1 */ 6631 pinset == 0x0013 || /* 5.1 */ 6632 pinset == 0x0017) { /* 7.1 */ 6633 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 4, 0); 6634 if (ch->bit32) 6635 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 4, 0); 6636 } 6637 if (channels == 6 || /* Any 6-channel */ 6638 pinset == 0x0017) { /* 7.1 */ 6639 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 6, 1); 6640 if (ch->bit32) 6641 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 6, 1); 6642 } 6643 if (channels == 8) { /* Any 8-channel */ 6644 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 8, 1); 6645 if (ch->bit32) 6646 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 8, 1); 6647 } 6648 } 6649 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6650 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6651 } 6652 ch->fmtlist[i] = 0; 6653 i = 0; 6654 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6655 ch->pcmrates[i++] = 8000; 6656 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6657 ch->pcmrates[i++] = 11025; 6658 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6659 ch->pcmrates[i++] = 16000; 6660 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6661 ch->pcmrates[i++] = 22050; 6662 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6663 ch->pcmrates[i++] = 32000; 6664 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6665 ch->pcmrates[i++] = 44100; 6666 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6667 ch->pcmrates[i++] = 48000; 6668 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6669 ch->pcmrates[i++] = 88200; 6670 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6671 ch->pcmrates[i++] = 96000; 6672 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6673 ch->pcmrates[i++] = 176400; 6674 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6675 ch->pcmrates[i++] = 192000; 6676 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6677 ch->pcmrates[i] = 0; 6678 if (i > 0) { 6679 ch->caps.minspeed = ch->pcmrates[0]; 6680 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6681 } 6682 } 6683 6684 return (ret); 6685 } 6686 6687 static void 6688 hdac_create_pcms(struct hdac_devinfo *devinfo) 6689 { 6690 struct hdac_softc *sc = devinfo->codec->sc; 6691 struct hdac_audio_as *as = devinfo->function.audio.as; 6692 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6693 6694 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6695 if (as[i].enable == 0) 6696 continue; 6697 if (as[i].dir == HDA_CTL_IN) { 6698 if (as[i].digital) 6699 drdev++; 6700 else 6701 ardev++; 6702 } else { 6703 if (as[i].digital) 6704 dpdev++; 6705 else 6706 apdev++; 6707 } 6708 } 6709 devinfo->function.audio.num_devs = 6710 max(ardev, apdev) + max(drdev, dpdev); 6711 devinfo->function.audio.devs = 6712 (struct hdac_pcm_devinfo *)malloc( 6713 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6714 M_HDAC, M_ZERO | M_NOWAIT); 6715 if (devinfo->function.audio.devs == NULL) { 6716 device_printf(sc->dev, 6717 "Unable to allocate memory for devices\n"); 6718 return; 6719 } 6720 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6721 devinfo->function.audio.devs[i].index = i; 6722 devinfo->function.audio.devs[i].devinfo = devinfo; 6723 devinfo->function.audio.devs[i].play = -1; 6724 devinfo->function.audio.devs[i].rec = -1; 6725 devinfo->function.audio.devs[i].digital = 255; 6726 } 6727 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6728 if (as[i].enable == 0) 6729 continue; 6730 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6731 if (devinfo->function.audio.devs[j].digital != 255 && 6732 (!devinfo->function.audio.devs[j].digital) != 6733 (!as[i].digital)) 6734 continue; 6735 if (as[i].dir == HDA_CTL_IN) { 6736 if (devinfo->function.audio.devs[j].rec >= 0) 6737 continue; 6738 devinfo->function.audio.devs[j].rec 6739 = as[i].chan; 6740 } else { 6741 if (devinfo->function.audio.devs[j].play >= 0) 6742 continue; 6743 devinfo->function.audio.devs[j].play 6744 = as[i].chan; 6745 } 6746 sc->chans[as[i].chan].pdevinfo = 6747 &devinfo->function.audio.devs[j]; 6748 devinfo->function.audio.devs[j].digital = 6749 as[i].digital; 6750 break; 6751 } 6752 } 6753 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6754 struct hdac_pcm_devinfo *pdevinfo = 6755 &devinfo->function.audio.devs[i]; 6756 pdevinfo->dev = 6757 device_add_child(sc->dev, "pcm", -1); 6758 device_set_ivars(pdevinfo->dev, 6759 (void *)pdevinfo); 6760 } 6761 } 6762 6763 static void 6764 hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6765 { 6766 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6767 struct hdac_audio_ctl *ctl; 6768 struct hdac_softc *sc = devinfo->codec->sc; 6769 char buf[64]; 6770 int i, j, printed; 6771 6772 if (flag == 0) { 6773 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6774 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6775 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_IGAIN | 6776 SOUND_MASK_OGAIN | SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6777 } 6778 6779 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6780 if ((flag & (1 << j)) == 0) 6781 continue; 6782 i = 0; 6783 printed = 0; 6784 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6785 if (ctl->enable == 0 || 6786 ctl->widget->enable == 0) 6787 continue; 6788 if (!((pdevinfo->play >= 0 && 6789 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6790 (pdevinfo->rec >= 0 && 6791 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6792 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6793 continue; 6794 if ((ctl->ossmask & (1 << j)) == 0) 6795 continue; 6796 6797 if (printed == 0) { 6798 device_printf(pdevinfo->dev, "\n"); 6799 if (banner != NULL) { 6800 device_printf(pdevinfo->dev, "%s", banner); 6801 } else { 6802 device_printf(pdevinfo->dev, "Unknown Ctl"); 6803 } 6804 printf(" (OSS: %s)\n", 6805 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6806 buf, sizeof(buf))); 6807 device_printf(pdevinfo->dev, " |\n"); 6808 printed = 1; 6809 } 6810 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6811 ctl->widget->nid, 6812 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6813 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6814 printf(" %2d): ", ctl->index); 6815 else 6816 printf("): "); 6817 if (ctl->step > 0) { 6818 printf("%+d/%+ddB (%d steps)%s\n", 6819 (0 - ctl->offset) * (ctl->size + 1) / 4, 6820 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6821 ctl->step + 1, 6822 ctl->mute?" + mute":""); 6823 } else 6824 printf("%s\n", ctl->mute?"mute":""); 6825 } 6826 } 6827 } 6828 6829 static void 6830 hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6831 { 6832 uint32_t cap; 6833 6834 cap = fcap; 6835 if (cap != 0) { 6836 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6837 device_printf(dev, " "); 6838 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6839 printf(" AC3"); 6840 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6841 printf(" FLOAT32"); 6842 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6843 printf(" PCM"); 6844 printf("\n"); 6845 } 6846 cap = pcmcap; 6847 if (cap != 0) { 6848 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6849 device_printf(dev, " "); 6850 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6851 printf(" 8"); 6852 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6853 printf(" 16"); 6854 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6855 printf(" 20"); 6856 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6857 printf(" 24"); 6858 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6859 printf(" 32"); 6860 printf(" bits,"); 6861 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6862 printf(" 8"); 6863 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6864 printf(" 11"); 6865 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6866 printf(" 16"); 6867 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6868 printf(" 22"); 6869 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6870 printf(" 32"); 6871 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6872 printf(" 44"); 6873 printf(" 48"); 6874 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6875 printf(" 88"); 6876 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6877 printf(" 96"); 6878 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6879 printf(" 176"); 6880 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6881 printf(" 192"); 6882 printf(" KHz\n"); 6883 } 6884 } 6885 6886 static void 6887 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6888 { 6889 uint32_t pincap; 6890 6891 pincap = w->wclass.pin.cap; 6892 6893 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6894 device_printf(sc->dev, " "); 6895 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6896 printf(" ISC"); 6897 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6898 printf(" TRQD"); 6899 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6900 printf(" PDC"); 6901 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6902 printf(" HP"); 6903 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6904 printf(" OUT"); 6905 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6906 printf(" IN"); 6907 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6908 printf(" BAL"); 6909 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6910 printf(" HDMI"); 6911 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6912 printf(" VREF["); 6913 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6914 printf(" 50"); 6915 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6916 printf(" 80"); 6917 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6918 printf(" 100"); 6919 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6920 printf(" GROUND"); 6921 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6922 printf(" HIZ"); 6923 printf(" ]"); 6924 } 6925 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6926 printf(" EAPD"); 6927 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6928 printf(" DP"); 6929 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6930 printf(" HBR"); 6931 printf("\n"); 6932 device_printf(sc->dev, " Pin config: 0x%08x\n", 6933 w->wclass.pin.config); 6934 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6935 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6936 printf(" HP"); 6937 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6938 printf(" IN"); 6939 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6940 printf(" OUT"); 6941 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6942 printf(" VREFs"); 6943 printf("\n"); 6944 } 6945 6946 static void 6947 hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6948 { 6949 struct hdac_softc *sc = w->devinfo->codec->sc; 6950 6951 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6952 "jack %2d loc %2d color %7s misc %d%s\n", 6953 w->nid, conf, 6954 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6955 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6956 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6957 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6958 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6959 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6960 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6961 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6962 (w->enable == 0)?" [DISABLED]":""); 6963 } 6964 6965 static void 6966 hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6967 { 6968 struct hdac_widget *w; 6969 int i; 6970 6971 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6972 w = hdac_widget_get(devinfo, i); 6973 if (w == NULL) 6974 continue; 6975 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6976 continue; 6977 hdac_dump_pin_config(w, w->wclass.pin.config); 6978 } 6979 } 6980 6981 static void 6982 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6983 { 6984 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6985 device_printf(sc->dev, " " 6986 "mute=%d step=%d size=%d offset=%d\n", 6987 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6988 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6989 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6990 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6991 } 6992 6993 static void 6994 hdac_dump_nodes(struct hdac_devinfo *devinfo) 6995 { 6996 struct hdac_softc *sc = devinfo->codec->sc; 6997 static char *ossname[] = SOUND_DEVICE_NAMES; 6998 struct hdac_widget *w, *cw; 6999 char buf[64]; 7000 int i, j; 7001 7002 device_printf(sc->dev, "\n"); 7003 device_printf(sc->dev, "Default Parameter\n"); 7004 device_printf(sc->dev, "-----------------\n"); 7005 hdac_dump_audio_formats(sc->dev, 7006 devinfo->function.audio.supp_stream_formats, 7007 devinfo->function.audio.supp_pcm_size_rate); 7008 device_printf(sc->dev, " IN amp: 0x%08x\n", 7009 devinfo->function.audio.inamp_cap); 7010 device_printf(sc->dev, " OUT amp: 0x%08x\n", 7011 devinfo->function.audio.outamp_cap); 7012 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7013 w = hdac_widget_get(devinfo, i); 7014 if (w == NULL) { 7015 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 7016 continue; 7017 } 7018 device_printf(sc->dev, "\n"); 7019 device_printf(sc->dev, " nid: %d%s\n", w->nid, 7020 (w->enable == 0) ? " [DISABLED]" : ""); 7021 device_printf(sc->dev, " Name: %s\n", w->name); 7022 device_printf(sc->dev, " Widget cap: 0x%08x\n", 7023 w->param.widget_cap); 7024 if (w->param.widget_cap & 0x0ee1) { 7025 device_printf(sc->dev, " "); 7026 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 7027 printf(" LRSWAP"); 7028 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 7029 printf(" PWR"); 7030 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 7031 printf(" DIGITAL"); 7032 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 7033 printf(" UNSOL"); 7034 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 7035 printf(" PROC"); 7036 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 7037 printf(" STRIPE"); 7038 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 7039 if (j == 1) 7040 printf(" STEREO"); 7041 else if (j > 1) 7042 printf(" %dCH", j + 1); 7043 printf("\n"); 7044 } 7045 if (w->bindas != -1) { 7046 device_printf(sc->dev, " Association: %d (0x%08x)\n", 7047 w->bindas, w->bindseqmask); 7048 } 7049 if (w->ossmask != 0 || w->ossdev >= 0) { 7050 device_printf(sc->dev, " OSS: %s", 7051 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 7052 if (w->ossdev >= 0) 7053 printf(" (%s)", ossname[w->ossdev]); 7054 printf("\n"); 7055 } 7056 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 7057 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 7058 hdac_dump_audio_formats(sc->dev, 7059 w->param.supp_stream_formats, 7060 w->param.supp_pcm_size_rate); 7061 } else if (w->type == 7062 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7063 hdac_dump_pin(sc, w); 7064 if (w->param.eapdbtl != HDAC_INVALID) 7065 device_printf(sc->dev, " EAPD: 0x%08x\n", 7066 w->param.eapdbtl); 7067 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 7068 w->param.outamp_cap != 0) 7069 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 7070 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 7071 w->param.inamp_cap != 0) 7072 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 7073 if (w->nconns > 0) { 7074 device_printf(sc->dev, " connections: %d\n", w->nconns); 7075 device_printf(sc->dev, " |\n"); 7076 } 7077 for (j = 0; j < w->nconns; j++) { 7078 cw = hdac_widget_get(devinfo, w->conns[j]); 7079 device_printf(sc->dev, " + %s<- nid=%d [%s]", 7080 (w->connsenable[j] == 0)?"[DISABLED] ":"", 7081 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 7082 if (cw == NULL) 7083 printf(" [UNKNOWN]"); 7084 else if (cw->enable == 0) 7085 printf(" [DISABLED]"); 7086 if (w->nconns > 1 && w->selconn == j && w->type != 7087 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 7088 printf(" (selected)"); 7089 printf("\n"); 7090 } 7091 } 7092 7093 } 7094 7095 static void 7096 hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 7097 { 7098 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7099 struct hdac_widget *w, *cw; 7100 char buf[64]; 7101 int i, printed = 0; 7102 7103 if (depth > HDA_PARSE_MAXDEPTH) 7104 return; 7105 7106 w = hdac_widget_get(devinfo, nid); 7107 if (w == NULL || w->enable == 0) 7108 return; 7109 7110 if (depth == 0) 7111 device_printf(pdevinfo->dev, "%*s", 4, ""); 7112 else 7113 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 7114 printf("nid=%d [%s]", w->nid, w->name); 7115 7116 if (depth > 0) { 7117 if (w->ossmask == 0) { 7118 printf("\n"); 7119 return; 7120 } 7121 printf(" [src: %s]", 7122 hdac_audio_ctl_ossmixer_mask2allname( 7123 w->ossmask, buf, sizeof(buf))); 7124 if (w->ossdev >= 0) { 7125 printf("\n"); 7126 return; 7127 } 7128 } 7129 printf("\n"); 7130 7131 for (i = 0; i < w->nconns; i++) { 7132 if (w->connsenable[i] == 0) 7133 continue; 7134 cw = hdac_widget_get(devinfo, w->conns[i]); 7135 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 7136 continue; 7137 if (printed == 0) { 7138 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 7139 printed = 1; 7140 } 7141 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 7142 } 7143 7144 } 7145 7146 static void 7147 hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 7148 { 7149 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7150 struct hdac_softc *sc = devinfo->codec->sc; 7151 struct hdac_audio_as *as; 7152 struct hdac_widget *w; 7153 int i, printed = 0; 7154 7155 if (pdevinfo->play < 0) 7156 return; 7157 7158 as = &devinfo->function.audio.as[sc->chans[pdevinfo->play].as]; 7159 for (i = 0; i < 16; i++) { 7160 if (as->pins[i] <= 0) 7161 continue; 7162 w = hdac_widget_get(devinfo, as->pins[i]); 7163 if (w == NULL || w->enable == 0) 7164 continue; 7165 if (printed == 0) { 7166 printed = 1; 7167 device_printf(pdevinfo->dev, "\n"); 7168 device_printf(pdevinfo->dev, "Playback:\n"); 7169 } 7170 device_printf(pdevinfo->dev, "\n"); 7171 hdac_dump_dst_nid(pdevinfo, as->pins[i], 0); 7172 } 7173 } 7174 7175 static void 7176 hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7177 { 7178 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7179 struct hdac_softc *sc = devinfo->codec->sc; 7180 struct hdac_widget *w; 7181 int i; 7182 int printed = 0; 7183 7184 if (pdevinfo->rec < 0) 7185 return; 7186 7187 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7188 w = hdac_widget_get(devinfo, i); 7189 if (w == NULL || w->enable == 0) 7190 continue; 7191 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7192 continue; 7193 if (w->bindas != sc->chans[pdevinfo->rec].as) 7194 continue; 7195 if (printed == 0) { 7196 printed = 1; 7197 device_printf(pdevinfo->dev, "\n"); 7198 device_printf(pdevinfo->dev, "Record:\n"); 7199 } 7200 device_printf(pdevinfo->dev, "\n"); 7201 hdac_dump_dst_nid(pdevinfo, i, 0); 7202 } 7203 } 7204 7205 static void 7206 hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7207 { 7208 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7209 struct hdac_widget *w; 7210 int i; 7211 int printed = 0; 7212 7213 if (pdevinfo->index != 0) 7214 return; 7215 7216 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7217 w = hdac_widget_get(devinfo, i); 7218 if (w == NULL || w->enable == 0) 7219 continue; 7220 if (w->ossdev != SOUND_MIXER_IMIX) 7221 continue; 7222 if (printed == 0) { 7223 printed = 1; 7224 device_printf(pdevinfo->dev, "\n"); 7225 device_printf(pdevinfo->dev, "Input Mix:\n"); 7226 } 7227 device_printf(pdevinfo->dev, "\n"); 7228 hdac_dump_dst_nid(pdevinfo, i, 0); 7229 } 7230 } 7231 7232 static void 7233 hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7234 { 7235 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7236 nid_t *nids; 7237 int i; 7238 7239 if (pdevinfo->play >= 0) { 7240 i = pdevinfo->play; 7241 device_printf(pdevinfo->dev, "\n"); 7242 device_printf(pdevinfo->dev, "Playback:\n"); 7243 device_printf(pdevinfo->dev, "\n"); 7244 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7245 sc->chans[i].supp_pcm_size_rate); 7246 device_printf(pdevinfo->dev, " DAC:"); 7247 for (nids = sc->chans[i].io; *nids != -1; nids++) 7248 printf(" %d", *nids); 7249 printf("\n"); 7250 } 7251 if (pdevinfo->rec >= 0) { 7252 i = pdevinfo->rec; 7253 device_printf(pdevinfo->dev, "\n"); 7254 device_printf(pdevinfo->dev, "Record:\n"); 7255 device_printf(pdevinfo->dev, "\n"); 7256 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7257 sc->chans[i].supp_pcm_size_rate); 7258 device_printf(pdevinfo->dev, " ADC:"); 7259 for (nids = sc->chans[i].io; *nids != -1; nids++) 7260 printf(" %d", *nids); 7261 printf("\n"); 7262 } 7263 } 7264 7265 static void 7266 hdac_release_resources(struct hdac_softc *sc) 7267 { 7268 int i, j; 7269 7270 if (sc == NULL) 7271 return; 7272 7273 hdac_lock(sc); 7274 sc->polling = 0; 7275 sc->poll_ival = 0; 7276 callout_stop(&sc->poll_hda); 7277 callout_stop(&sc->poll_hdac); 7278 callout_stop(&sc->poll_jack); 7279 hdac_reset(sc, 0); 7280 hdac_unlock(sc); 7281 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7282 callout_drain(&sc->poll_hda); 7283 callout_drain(&sc->poll_hdac); 7284 callout_drain(&sc->poll_jack); 7285 7286 hdac_irq_free(sc); 7287 7288 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7289 if (sc->codecs[i] == NULL) 7290 continue; 7291 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7292 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7293 if (sc->codecs[i]->fgs[j].node_type == 7294 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7295 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7296 M_HDAC); 7297 free(sc->codecs[i]->fgs[j].function.audio.as, 7298 M_HDAC); 7299 free(sc->codecs[i]->fgs[j].function.audio.devs, 7300 M_HDAC); 7301 } 7302 } 7303 free(sc->codecs[i]->fgs, M_HDAC); 7304 free(sc->codecs[i], M_HDAC); 7305 sc->codecs[i] = NULL; 7306 } 7307 7308 hdac_dma_free(sc, &sc->pos_dma); 7309 hdac_dma_free(sc, &sc->rirb_dma); 7310 hdac_dma_free(sc, &sc->corb_dma); 7311 for (i = 0; i < sc->num_chans; i++) { 7312 if (sc->chans[i].blkcnt > 0) 7313 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7314 } 7315 free(sc->chans, M_HDAC); 7316 if (sc->chan_dmat != NULL) { 7317 bus_dma_tag_destroy(sc->chan_dmat); 7318 sc->chan_dmat = NULL; 7319 } 7320 hdac_mem_free(sc); 7321 snd_mtxfree(sc->lock); 7322 } 7323 7324 /* This function surely going to make its way into upper level someday. */ 7325 static void 7326 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7327 { 7328 const char *res = NULL; 7329 int i = 0, j, k, len, inv; 7330 7331 if (on != NULL) 7332 *on = 0; 7333 if (off != NULL) 7334 *off = 0; 7335 if (sc == NULL) 7336 return; 7337 if (resource_string_value(device_get_name(sc->dev), 7338 device_get_unit(sc->dev), "config", &res) != 0) 7339 return; 7340 if (!(res != NULL && strlen(res) > 0)) 7341 return; 7342 HDA_BOOTVERBOSE( 7343 device_printf(sc->dev, "HDA Config:"); 7344 ); 7345 for (;;) { 7346 while (res[i] != '\0' && 7347 (res[i] == ',' || isspace(res[i]) != 0)) 7348 i++; 7349 if (res[i] == '\0') { 7350 HDA_BOOTVERBOSE( 7351 printf("\n"); 7352 ); 7353 return; 7354 } 7355 j = i; 7356 while (res[j] != '\0' && 7357 !(res[j] == ',' || isspace(res[j]) != 0)) 7358 j++; 7359 len = j - i; 7360 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7361 inv = 2; 7362 else 7363 inv = 0; 7364 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7365 if (strncmp(res + i + inv, 7366 hdac_quirks_tab[k].key, len - inv) != 0) 7367 continue; 7368 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7369 continue; 7370 HDA_BOOTVERBOSE( 7371 printf(" %s%s", (inv != 0) ? "no" : "", 7372 hdac_quirks_tab[k].key); 7373 ); 7374 if (inv == 0 && on != NULL) 7375 *on |= hdac_quirks_tab[k].value; 7376 else if (inv != 0 && off != NULL) 7377 *off |= hdac_quirks_tab[k].value; 7378 break; 7379 } 7380 i = j; 7381 } 7382 } 7383 7384 static int 7385 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7386 { 7387 struct hdac_softc *sc; 7388 device_t dev; 7389 uint32_t ctl; 7390 int err, val; 7391 7392 dev = oidp->oid_arg1; 7393 sc = device_get_softc(dev); 7394 if (sc == NULL) 7395 return (EINVAL); 7396 hdac_lock(sc); 7397 val = sc->polling; 7398 hdac_unlock(sc); 7399 err = sysctl_handle_int(oidp, &val, 0, req); 7400 7401 if (err != 0 || req->newptr == NULL) 7402 return (err); 7403 if (val < 0 || val > 1) 7404 return (EINVAL); 7405 7406 hdac_lock(sc); 7407 if (val != sc->polling) { 7408 if (val == 0) { 7409 callout_stop(&sc->poll_hda); 7410 callout_stop(&sc->poll_hdac); 7411 hdac_unlock(sc); 7412 callout_drain(&sc->poll_hda); 7413 callout_drain(&sc->poll_hdac); 7414 hdac_lock(sc); 7415 sc->polling = 0; 7416 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7417 ctl |= HDAC_INTCTL_GIE; 7418 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7419 } else { 7420 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7421 ctl &= ~HDAC_INTCTL_GIE; 7422 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7423 hdac_unlock(sc); 7424 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7425 hdac_lock(sc); 7426 sc->polling = 1; 7427 hdac_poll_reinit(sc); 7428 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7429 } 7430 } 7431 hdac_unlock(sc); 7432 7433 return (err); 7434 } 7435 7436 static int 7437 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7438 { 7439 struct hdac_softc *sc; 7440 device_t dev; 7441 int err, val; 7442 7443 dev = oidp->oid_arg1; 7444 sc = device_get_softc(dev); 7445 if (sc == NULL) 7446 return (EINVAL); 7447 hdac_lock(sc); 7448 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7449 hdac_unlock(sc); 7450 err = sysctl_handle_int(oidp, &val, 0, req); 7451 7452 if (err != 0 || req->newptr == NULL) 7453 return (err); 7454 7455 if (val < 1) 7456 val = 1; 7457 if (val > 5000) 7458 val = 5000; 7459 val = ((uint64_t)val * hz) / 1000; 7460 if (val < 1) 7461 val = 1; 7462 if (val > (hz * 5)) 7463 val = hz * 5; 7464 7465 hdac_lock(sc); 7466 sc->poll_ival = val; 7467 hdac_unlock(sc); 7468 7469 return (err); 7470 } 7471 7472 static int 7473 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7474 { 7475 struct hdac_softc *sc; 7476 struct hdac_codec *codec; 7477 struct hdac_devinfo *devinfo; 7478 struct hdac_widget *w; 7479 device_t dev; 7480 uint32_t res, pincap, delay; 7481 int codec_index, fg_index; 7482 int i, err, val; 7483 nid_t cad; 7484 7485 dev = oidp->oid_arg1; 7486 sc = device_get_softc(dev); 7487 if (sc == NULL) 7488 return (EINVAL); 7489 val = 0; 7490 err = sysctl_handle_int(oidp, &val, 0, req); 7491 if (err != 0 || req->newptr == NULL || val == 0) 7492 return (err); 7493 7494 /* XXX: Temporary. For debugging. */ 7495 if (val == 100) { 7496 hdac_suspend(dev); 7497 return (0); 7498 } else if (val == 101) { 7499 hdac_resume(dev); 7500 return (0); 7501 } 7502 7503 hdac_lock(sc); 7504 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7505 codec = sc->codecs[codec_index]; 7506 if (codec == NULL) 7507 continue; 7508 cad = codec->cad; 7509 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7510 devinfo = &codec->fgs[fg_index]; 7511 if (devinfo->node_type != 7512 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7513 continue; 7514 7515 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7516 codec_index, devinfo->nid); 7517 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7518 w = hdac_widget_get(devinfo, i); 7519 if (w == NULL || w->type != 7520 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7521 continue; 7522 hdac_dump_pin_config(w, w->wclass.pin.config); 7523 pincap = w->wclass.pin.cap; 7524 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7525 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7526 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7527 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7528 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7529 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7530 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7531 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7532 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7533 delay = 0; 7534 hdac_command(sc, 7535 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7536 do { 7537 res = hdac_command(sc, 7538 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7539 if (res != 0x7fffffff && res != 0xffffffff) 7540 break; 7541 DELAY(10); 7542 } while (++delay < 10000); 7543 } else { 7544 delay = 0; 7545 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7546 w->nid), cad); 7547 } 7548 printf(" Sense: 0x%08x", res); 7549 if (delay > 0) 7550 printf(" delay %dus", delay * 10); 7551 } 7552 printf("\n"); 7553 } 7554 device_printf(dev, 7555 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7556 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7557 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7558 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7559 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7560 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7561 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7562 device_printf(dev, " GPI:"); 7563 res = hdac_command(sc, 7564 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7565 printf(" data=0x%08x", res); 7566 res = hdac_command(sc, 7567 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7568 cad); 7569 printf(" wake=0x%08x", res); 7570 res = hdac_command(sc, 7571 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7572 cad); 7573 printf(" unsol=0x%08x", res); 7574 res = hdac_command(sc, 7575 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7576 printf(" sticky=0x%08x\n", res); 7577 } 7578 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7579 device_printf(dev, " GPO:"); 7580 res = hdac_command(sc, 7581 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7582 printf(" data=0x%08x\n", res); 7583 } 7584 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7585 device_printf(dev, "GPIO:"); 7586 res = hdac_command(sc, 7587 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7588 printf(" data=0x%08x", res); 7589 res = hdac_command(sc, 7590 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7591 printf(" enable=0x%08x", res); 7592 res = hdac_command(sc, 7593 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7594 printf(" direction=0x%08x\n", res); 7595 res = hdac_command(sc, 7596 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7597 device_printf(dev, " wake=0x%08x", res); 7598 res = hdac_command(sc, 7599 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7600 cad); 7601 printf(" unsol=0x%08x", res); 7602 res = hdac_command(sc, 7603 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7604 printf(" sticky=0x%08x\n", res); 7605 } 7606 } 7607 } 7608 hdac_unlock(sc); 7609 return (0); 7610 } 7611 7612 static void 7613 hdac_attach2(void *arg) 7614 { 7615 struct hdac_codec *codec; 7616 struct hdac_softc *sc; 7617 struct hdac_audio_ctl *ctl; 7618 uint32_t quirks_on, quirks_off; 7619 int codec_index, fg_index; 7620 int i, dmaalloc = 0; 7621 struct hdac_devinfo *devinfo; 7622 7623 sc = (struct hdac_softc *)arg; 7624 7625 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7626 7627 HDA_BOOTHVERBOSE( 7628 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7629 quirks_on, quirks_off); 7630 ); 7631 7632 hdac_lock(sc); 7633 7634 /* Remove ourselves from the config hooks */ 7635 if (sc->intrhook.ich_func != NULL) { 7636 config_intrhook_disestablish(&sc->intrhook); 7637 sc->intrhook.ich_func = NULL; 7638 } 7639 7640 /* Start the corb and rirb engines */ 7641 HDA_BOOTHVERBOSE( 7642 device_printf(sc->dev, "Starting CORB Engine...\n"); 7643 ); 7644 hdac_corb_start(sc); 7645 HDA_BOOTHVERBOSE( 7646 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7647 ); 7648 hdac_rirb_start(sc); 7649 7650 HDA_BOOTHVERBOSE( 7651 device_printf(sc->dev, 7652 "Enabling controller interrupt...\n"); 7653 ); 7654 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7655 HDAC_GCTL_UNSOL); 7656 if (sc->polling == 0) { 7657 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7658 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7659 } else { 7660 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7661 } 7662 DELAY(1000); 7663 7664 HDA_BOOTHVERBOSE( 7665 device_printf(sc->dev, 7666 "Scanning HDA codecs ...\n"); 7667 ); 7668 hdac_scan_codecs(sc); 7669 7670 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7671 codec = sc->codecs[codec_index]; 7672 if (codec == NULL) 7673 continue; 7674 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7675 devinfo = &codec->fgs[fg_index]; 7676 HDA_BOOTVERBOSE( 7677 device_printf(sc->dev, "\n"); 7678 device_printf(sc->dev, 7679 "Processing %s FG cad=%d nid=%d...\n", 7680 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7681 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7682 "unknown", 7683 devinfo->codec->cad, devinfo->nid); 7684 ); 7685 if (devinfo->node_type != 7686 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7687 HDA_BOOTHVERBOSE( 7688 device_printf(sc->dev, 7689 "Powering down...\n"); 7690 ); 7691 hdac_command(sc, 7692 HDA_CMD_SET_POWER_STATE(codec->cad, 7693 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7694 codec->cad); 7695 continue; 7696 } 7697 7698 HDA_BOOTHVERBOSE( 7699 device_printf(sc->dev, "Powering up...\n"); 7700 ); 7701 hdac_powerup(devinfo); 7702 HDA_BOOTHVERBOSE( 7703 device_printf(sc->dev, "Parsing audio FG...\n"); 7704 ); 7705 hdac_audio_parse(devinfo); 7706 HDA_BOOTHVERBOSE( 7707 device_printf(sc->dev, "Parsing Ctls...\n"); 7708 ); 7709 hdac_audio_ctl_parse(devinfo); 7710 HDA_BOOTHVERBOSE( 7711 device_printf(sc->dev, "Parsing vendor patch...\n"); 7712 ); 7713 hdac_vendor_patch_parse(devinfo); 7714 devinfo->function.audio.quirks |= quirks_on; 7715 devinfo->function.audio.quirks &= ~quirks_off; 7716 7717 HDA_BOOTHVERBOSE( 7718 device_printf(sc->dev, "Disabling nonaudio...\n"); 7719 ); 7720 hdac_audio_disable_nonaudio(devinfo); 7721 HDA_BOOTHVERBOSE( 7722 device_printf(sc->dev, "Disabling useless...\n"); 7723 ); 7724 hdac_audio_disable_useless(devinfo); 7725 HDA_BOOTVERBOSE( 7726 device_printf(sc->dev, "Patched pins configuration:\n"); 7727 hdac_dump_pin_configs(devinfo); 7728 ); 7729 HDA_BOOTHVERBOSE( 7730 device_printf(sc->dev, "Parsing pin associations...\n"); 7731 ); 7732 hdac_audio_as_parse(devinfo); 7733 HDA_BOOTHVERBOSE( 7734 device_printf(sc->dev, "Building AFG tree...\n"); 7735 ); 7736 hdac_audio_build_tree(devinfo); 7737 HDA_BOOTHVERBOSE( 7738 device_printf(sc->dev, "Disabling unassociated " 7739 "widgets...\n"); 7740 ); 7741 hdac_audio_disable_unas(devinfo); 7742 HDA_BOOTHVERBOSE( 7743 device_printf(sc->dev, "Disabling nonselected " 7744 "inputs...\n"); 7745 ); 7746 hdac_audio_disable_notselected(devinfo); 7747 HDA_BOOTHVERBOSE( 7748 device_printf(sc->dev, "Disabling useless...\n"); 7749 ); 7750 hdac_audio_disable_useless(devinfo); 7751 HDA_BOOTHVERBOSE( 7752 device_printf(sc->dev, "Disabling " 7753 "crossassociatement connections...\n"); 7754 ); 7755 hdac_audio_disable_crossas(devinfo); 7756 HDA_BOOTHVERBOSE( 7757 device_printf(sc->dev, "Disabling useless...\n"); 7758 ); 7759 hdac_audio_disable_useless(devinfo); 7760 HDA_BOOTHVERBOSE( 7761 device_printf(sc->dev, "Binding associations to channels...\n"); 7762 ); 7763 hdac_audio_bind_as(devinfo); 7764 HDA_BOOTHVERBOSE( 7765 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7766 ); 7767 hdac_audio_assign_names(devinfo); 7768 HDA_BOOTHVERBOSE( 7769 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7770 ); 7771 hdac_audio_assign_mixers(devinfo); 7772 HDA_BOOTHVERBOSE( 7773 device_printf(sc->dev, "Preparing pin controls...\n"); 7774 ); 7775 hdac_audio_prepare_pin_ctrl(devinfo); 7776 HDA_BOOTHVERBOSE( 7777 device_printf(sc->dev, "AFG commit...\n"); 7778 ); 7779 hdac_audio_commit(devinfo); 7780 HDA_BOOTHVERBOSE( 7781 device_printf(sc->dev, "HP switch init...\n"); 7782 ); 7783 hdac_hp_switch_init(devinfo); 7784 7785 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7786 dmaalloc == 0) { 7787 if (hdac_dma_alloc(sc, &sc->pos_dma, 7788 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7789 HDA_BOOTVERBOSE( 7790 device_printf(sc->dev, "Failed to " 7791 "allocate DMA pos buffer " 7792 "(non-fatal)\n"); 7793 ); 7794 } else 7795 dmaalloc = 1; 7796 } 7797 7798 HDA_BOOTHVERBOSE( 7799 device_printf(sc->dev, "Creating PCM devices...\n"); 7800 ); 7801 hdac_create_pcms(devinfo); 7802 7803 HDA_BOOTVERBOSE( 7804 if (devinfo->function.audio.quirks != 0) { 7805 device_printf(sc->dev, "FG config/quirks:"); 7806 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7807 if ((devinfo->function.audio.quirks & 7808 hdac_quirks_tab[i].value) == 7809 hdac_quirks_tab[i].value) 7810 printf(" %s", hdac_quirks_tab[i].key); 7811 } 7812 printf("\n"); 7813 } 7814 7815 device_printf(sc->dev, "\n"); 7816 device_printf(sc->dev, "+-------------------+\n"); 7817 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7818 device_printf(sc->dev, "+-------------------+\n"); 7819 hdac_dump_nodes(devinfo); 7820 ); 7821 7822 HDA_BOOTHVERBOSE( 7823 device_printf(sc->dev, "\n"); 7824 device_printf(sc->dev, "+------------------------+\n"); 7825 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7826 device_printf(sc->dev, "+------------------------+\n"); 7827 device_printf(sc->dev, "\n"); 7828 i = 0; 7829 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7830 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7831 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7832 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7833 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7834 ctl->index); 7835 if (ctl->childwidget != NULL) 7836 printf(" cnid %3d", ctl->childwidget->nid); 7837 else 7838 printf(" "); 7839 printf(" ossmask=0x%08x\n", 7840 ctl->ossmask); 7841 device_printf(sc->dev, 7842 " mute: %d step: %3d size: %3d off: %3d%s\n", 7843 ctl->mute, ctl->step, ctl->size, ctl->offset, 7844 (ctl->enable == 0) ? " [DISABLED]" : 7845 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7846 } 7847 ); 7848 } 7849 } 7850 hdac_unlock(sc); 7851 7852 HDA_BOOTVERBOSE( 7853 device_printf(sc->dev, "\n"); 7854 ); 7855 7856 bus_generic_attach(sc->dev); 7857 7858 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7859 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7860 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7861 sysctl_hdac_polling, "I", "Enable polling mode"); 7862 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7863 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7864 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7865 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7866 "Controller/Jack Sense polling interval (1-1000 ms)"); 7867 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7868 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7869 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7870 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7871 } 7872 7873 /**************************************************************************** 7874 * int hdac_suspend(device_t) 7875 * 7876 * Suspend and power down HDA bus and codecs. 7877 ****************************************************************************/ 7878 static int 7879 hdac_suspend(device_t dev) 7880 { 7881 struct hdac_softc *sc; 7882 struct hdac_codec *codec; 7883 struct hdac_devinfo *devinfo; 7884 int codec_index, fg_index, i; 7885 7886 HDA_BOOTHVERBOSE( 7887 device_printf(dev, "Suspend...\n"); 7888 ); 7889 7890 sc = device_get_softc(dev); 7891 hdac_lock(sc); 7892 7893 HDA_BOOTHVERBOSE( 7894 device_printf(dev, "Stop streams...\n"); 7895 ); 7896 for (i = 0; i < sc->num_chans; i++) { 7897 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7898 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7899 hdac_channel_stop(sc, &sc->chans[i]); 7900 } 7901 } 7902 7903 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7904 codec = sc->codecs[codec_index]; 7905 if (codec == NULL) 7906 continue; 7907 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7908 devinfo = &codec->fgs[fg_index]; 7909 HDA_BOOTHVERBOSE( 7910 device_printf(dev, 7911 "Power down FG" 7912 " cad=%d nid=%d to the D3 state...\n", 7913 codec->cad, devinfo->nid); 7914 ); 7915 hdac_command(sc, 7916 HDA_CMD_SET_POWER_STATE(codec->cad, 7917 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7918 codec->cad); 7919 } 7920 } 7921 7922 HDA_BOOTHVERBOSE( 7923 device_printf(dev, "Reset controller...\n"); 7924 ); 7925 callout_stop(&sc->poll_hda); 7926 callout_stop(&sc->poll_hdac); 7927 callout_stop(&sc->poll_jack); 7928 hdac_reset(sc, 0); 7929 hdac_unlock(sc); 7930 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7931 callout_drain(&sc->poll_hda); 7932 callout_drain(&sc->poll_hdac); 7933 callout_drain(&sc->poll_jack); 7934 7935 HDA_BOOTHVERBOSE( 7936 device_printf(dev, "Suspend done\n"); 7937 ); 7938 7939 return (0); 7940 } 7941 7942 /**************************************************************************** 7943 * int hdac_resume(device_t) 7944 * 7945 * Powerup and restore HDA bus and codecs state. 7946 ****************************************************************************/ 7947 static int 7948 hdac_resume(device_t dev) 7949 { 7950 struct hdac_softc *sc; 7951 struct hdac_codec *codec; 7952 struct hdac_devinfo *devinfo; 7953 int codec_index, fg_index, i; 7954 7955 HDA_BOOTHVERBOSE( 7956 device_printf(dev, "Resume...\n"); 7957 ); 7958 7959 sc = device_get_softc(dev); 7960 hdac_lock(sc); 7961 7962 /* Quiesce everything */ 7963 HDA_BOOTHVERBOSE( 7964 device_printf(dev, "Reset controller...\n"); 7965 ); 7966 hdac_reset(sc, 1); 7967 7968 /* Initialize the CORB and RIRB */ 7969 hdac_corb_init(sc); 7970 hdac_rirb_init(sc); 7971 7972 /* Start the corb and rirb engines */ 7973 HDA_BOOTHVERBOSE( 7974 device_printf(dev, "Starting CORB Engine...\n"); 7975 ); 7976 hdac_corb_start(sc); 7977 HDA_BOOTHVERBOSE( 7978 device_printf(dev, "Starting RIRB Engine...\n"); 7979 ); 7980 hdac_rirb_start(sc); 7981 7982 HDA_BOOTHVERBOSE( 7983 device_printf(dev, 7984 "Enabling controller interrupt...\n"); 7985 ); 7986 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7987 HDAC_GCTL_UNSOL); 7988 if (sc->polling == 0) { 7989 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7990 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7991 } else { 7992 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7993 } 7994 DELAY(1000); 7995 7996 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7997 codec = sc->codecs[codec_index]; 7998 if (codec == NULL) 7999 continue; 8000 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 8001 devinfo = &codec->fgs[fg_index]; 8002 if (devinfo->node_type != 8003 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 8004 HDA_BOOTHVERBOSE( 8005 device_printf(dev, 8006 "Power down unsupported non-audio FG" 8007 " cad=%d nid=%d to the D3 state...\n", 8008 codec->cad, devinfo->nid); 8009 ); 8010 hdac_command(sc, 8011 HDA_CMD_SET_POWER_STATE(codec->cad, 8012 devinfo->nid, HDA_CMD_POWER_STATE_D3), 8013 codec->cad); 8014 continue; 8015 } 8016 8017 HDA_BOOTHVERBOSE( 8018 device_printf(dev, 8019 "Power up audio FG cad=%d nid=%d...\n", 8020 devinfo->codec->cad, devinfo->nid); 8021 ); 8022 hdac_powerup(devinfo); 8023 HDA_BOOTHVERBOSE( 8024 device_printf(dev, "AFG commit...\n"); 8025 ); 8026 hdac_audio_commit(devinfo); 8027 HDA_BOOTHVERBOSE( 8028 device_printf(dev, "HP switch init...\n"); 8029 ); 8030 hdac_hp_switch_init(devinfo); 8031 8032 hdac_unlock(sc); 8033 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 8034 struct hdac_pcm_devinfo *pdevinfo = 8035 &devinfo->function.audio.devs[i]; 8036 HDA_BOOTHVERBOSE( 8037 device_printf(pdevinfo->dev, 8038 "OSS mixer reinitialization...\n"); 8039 ); 8040 if (mixer_reinit(pdevinfo->dev) == -1) 8041 device_printf(pdevinfo->dev, 8042 "unable to reinitialize the mixer\n"); 8043 } 8044 hdac_lock(sc); 8045 } 8046 } 8047 8048 HDA_BOOTHVERBOSE( 8049 device_printf(dev, "Start streams...\n"); 8050 ); 8051 for (i = 0; i < sc->num_chans; i++) { 8052 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 8053 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 8054 hdac_channel_start(sc, &sc->chans[i]); 8055 } 8056 } 8057 8058 hdac_unlock(sc); 8059 8060 HDA_BOOTHVERBOSE( 8061 device_printf(dev, "Resume done\n"); 8062 ); 8063 8064 return (0); 8065 } 8066 /**************************************************************************** 8067 * int hdac_detach(device_t) 8068 * 8069 * Detach and free up resources utilized by the hdac device. 8070 ****************************************************************************/ 8071 static int 8072 hdac_detach(device_t dev) 8073 { 8074 struct hdac_softc *sc; 8075 device_t *devlist; 8076 int i, devcount, error; 8077 8078 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 8079 return (error); 8080 for (i = 0; i < devcount; i++) { 8081 if ((error = device_delete_child(dev, devlist[i])) != 0) { 8082 free(devlist, M_TEMP); 8083 return (error); 8084 } 8085 } 8086 free(devlist, M_TEMP); 8087 8088 sc = device_get_softc(dev); 8089 hdac_release_resources(sc); 8090 8091 return (0); 8092 } 8093 8094 static int 8095 hdac_print_child(device_t dev, device_t child) 8096 { 8097 struct hdac_pcm_devinfo *pdevinfo = 8098 (struct hdac_pcm_devinfo *)device_get_ivars(child); 8099 int retval; 8100 8101 retval = bus_print_child_header(dev, child); 8102 retval += printf(" at cad %d nid %d", 8103 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 8104 retval += bus_print_child_footer(dev, child); 8105 8106 return (retval); 8107 } 8108 8109 static device_method_t hdac_methods[] = { 8110 /* device interface */ 8111 DEVMETHOD(device_probe, hdac_probe), 8112 DEVMETHOD(device_attach, hdac_attach), 8113 DEVMETHOD(device_detach, hdac_detach), 8114 DEVMETHOD(device_suspend, hdac_suspend), 8115 DEVMETHOD(device_resume, hdac_resume), 8116 /* Bus interface */ 8117 DEVMETHOD(bus_print_child, hdac_print_child), 8118 { 0, 0 } 8119 }; 8120 8121 static driver_t hdac_driver = { 8122 "hdac", 8123 hdac_methods, 8124 sizeof(struct hdac_softc), 8125 }; 8126 8127 static devclass_t hdac_devclass; 8128 8129 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 8130 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 8131 MODULE_VERSION(snd_hda, 1); 8132 8133 static int 8134 hdac_pcm_probe(device_t dev) 8135 { 8136 struct hdac_pcm_devinfo *pdevinfo = 8137 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8138 char buf[128]; 8139 8140 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 8141 hdac_codec_name(pdevinfo->devinfo->codec), 8142 pdevinfo->index, 8143 (pdevinfo->digital == 3)?"DisplayPort": 8144 ((pdevinfo->digital == 2)?"HDMI": 8145 ((pdevinfo->digital)?"Digital":"Analog"))); 8146 device_set_desc_copy(dev, buf); 8147 return (0); 8148 } 8149 8150 static int 8151 hdac_pcm_attach(device_t dev) 8152 { 8153 struct hdac_pcm_devinfo *pdevinfo = 8154 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8155 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 8156 char status[SND_STATUSLEN]; 8157 int i; 8158 8159 pdevinfo->chan_size = pcm_getbuffersize(dev, 8160 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8161 8162 HDA_BOOTVERBOSE( 8163 device_printf(dev, "+--------------------------------------+\n"); 8164 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8165 device_printf(dev, "+--------------------------------------+\n"); 8166 hdac_dump_pcmchannels(pdevinfo); 8167 device_printf(dev, "\n"); 8168 device_printf(dev, "+-------------------------------+\n"); 8169 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8170 device_printf(dev, "+-------------------------------+\n"); 8171 hdac_dump_dac(pdevinfo); 8172 hdac_dump_adc(pdevinfo); 8173 hdac_dump_mix(pdevinfo); 8174 device_printf(dev, "\n"); 8175 device_printf(dev, "+-------------------------+\n"); 8176 device_printf(dev, "| DUMPING Volume Controls |\n"); 8177 device_printf(dev, "+-------------------------+\n"); 8178 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8179 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8180 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8181 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8182 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8183 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8184 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8185 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8186 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8187 hdac_dump_ctls(pdevinfo, "Input Monitoring Level", SOUND_MASK_IGAIN); 8188 hdac_dump_ctls(pdevinfo, NULL, 0); 8189 device_printf(dev, "\n"); 8190 ); 8191 8192 if (resource_int_value(device_get_name(dev), 8193 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8194 i &= HDA_BLK_ALIGN; 8195 if (i < HDA_BLK_MIN) 8196 i = HDA_BLK_MIN; 8197 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8198 i = 0; 8199 while (pdevinfo->chan_blkcnt >> i) 8200 i++; 8201 pdevinfo->chan_blkcnt = 1 << (i - 1); 8202 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8203 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8204 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8205 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8206 } else 8207 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8208 8209 /* 8210 * We don't register interrupt handler with snd_setup_intr 8211 * in pcm device. Mark pcm device as MPSAFE manually. 8212 */ 8213 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8214 8215 HDA_BOOTHVERBOSE( 8216 device_printf(dev, "OSS mixer initialization...\n"); 8217 ); 8218 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8219 device_printf(dev, "Can't register mixer\n"); 8220 8221 HDA_BOOTHVERBOSE( 8222 device_printf(dev, "Registering PCM channels...\n"); 8223 ); 8224 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8225 (pdevinfo->rec >= 0)?1:0) != 0) 8226 device_printf(dev, "Can't register PCM\n"); 8227 8228 pdevinfo->registered++; 8229 8230 if (pdevinfo->play >= 0) 8231 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8232 if (pdevinfo->rec >= 0) 8233 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8234 8235 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8236 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8237 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8238 pcm_setstatus(dev, status); 8239 8240 return (0); 8241 } 8242 8243 static int 8244 hdac_pcm_detach(device_t dev) 8245 { 8246 struct hdac_pcm_devinfo *pdevinfo = 8247 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8248 int err; 8249 8250 if (pdevinfo->registered > 0) { 8251 err = pcm_unregister(dev); 8252 if (err != 0) 8253 return (err); 8254 } 8255 8256 return (0); 8257 } 8258 8259 static device_method_t hdac_pcm_methods[] = { 8260 /* device interface */ 8261 DEVMETHOD(device_probe, hdac_pcm_probe), 8262 DEVMETHOD(device_attach, hdac_pcm_attach), 8263 DEVMETHOD(device_detach, hdac_pcm_detach), 8264 { 0, 0 } 8265 }; 8266 8267 static driver_t hdac_pcm_driver = { 8268 "pcm", 8269 hdac_pcm_methods, 8270 PCM_SOFTC_SIZE, 8271 }; 8272 8273 DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8274 8275