1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71 #ifdef HAVE_KERNEL_OPTION_HEADERS 72 #include "opt_snd.h" 73 #endif 74 75 #include <dev/sound/pcm/sound.h> 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 79 #include <sys/ctype.h> 80 #include <sys/taskqueue.h> 81 82 #include <dev/sound/pci/hda/hdac_private.h> 83 #include <dev/sound/pci/hda/hdac_reg.h> 84 #include <dev/sound/pci/hda/hda_reg.h> 85 #include <dev/sound/pci/hda/hdac.h> 86 87 #include "mixer_if.h" 88 89 #define HDA_DRV_TEST_REV "20100226_0142" 90 91 SND_DECLARE_FILE("$FreeBSD$"); 92 93 #define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97 } while (0) 98 99 #define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103 } while (0) 104 105 #if 1 106 #undef HDAC_INTR_EXTRA 107 #define HDAC_INTR_EXTRA 1 108 #endif 109 110 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 111 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122 #define HDA_MATCH_ALL 0xffffffff 123 #define HDAC_INVALID 0xffffffff 124 125 /* Default controller / jack sense poll: 250ms */ 126 #define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128 /* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131 #define HDAC_TRIGGER_NONE 0x00000000 132 #define HDAC_TRIGGER_PLAY 0x00000fff 133 #define HDAC_TRIGGER_REC 0x00fff000 134 #define HDAC_TRIGGER_UNSOL 0x80000000 135 136 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139 /* Controller models */ 140 141 /* Intel */ 142 #define INTEL_VENDORID 0x8086 143 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 144 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 145 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 146 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 147 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 148 #define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 149 #define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 150 #define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 151 #define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 152 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 153 154 /* Nvidia */ 155 #define NVIDIA_VENDORID 0x10de 156 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 157 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 158 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 159 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 160 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 161 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 162 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 163 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 164 #define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 165 #define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 166 #define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 167 #define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 168 #define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 169 #define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 170 #define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 171 #define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 172 #define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 173 #define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 174 #define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 175 #define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 176 #define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 177 #define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 178 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 179 180 /* ATI */ 181 #define ATI_VENDORID 0x1002 182 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 183 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 184 #define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 185 #define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 186 #define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 187 #define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 188 #define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 189 #define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 190 #define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 191 #define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 192 #define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 193 #define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 194 #define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 195 #define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 196 #define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 197 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 198 199 /* VIA */ 200 #define VIA_VENDORID 0x1106 201 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 202 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 203 204 /* SiS */ 205 #define SIS_VENDORID 0x1039 206 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 207 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 208 209 /* ULI */ 210 #define ULI_VENDORID 0x10b9 211 #define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 212 #define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 213 214 /* OEM/subvendors */ 215 216 /* Intel */ 217 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 218 219 /* HP/Compaq */ 220 #define HP_VENDORID 0x103c 221 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 222 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 223 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 224 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 225 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 226 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 227 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 228 #define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 229 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 230 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 231 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 232 #define HP_NX6325_SUBVENDORX 0x103c30b0 233 234 /* Dell */ 235 #define DELL_VENDORID 0x1028 236 #define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 237 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 238 #define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 239 #define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 240 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 241 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 242 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 243 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 244 245 /* Clevo */ 246 #define CLEVO_VENDORID 0x1558 247 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 248 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 249 250 /* Acer */ 251 #define ACER_VENDORID 0x1025 252 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 253 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 254 #define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 255 #define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 256 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 257 #define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 258 #define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 259 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 260 261 /* Asus */ 262 #define ASUS_VENDORID 0x1043 263 #define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 264 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 265 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 266 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 267 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 268 #define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 269 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 270 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 271 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 272 #define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 273 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 274 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 275 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 276 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 277 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 278 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 279 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 280 281 /* IBM / Lenovo */ 282 #define IBM_VENDORID 0x1014 283 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 284 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 285 286 /* Lenovo */ 287 #define LENOVO_VENDORID 0x17aa 288 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 289 #define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 290 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 291 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 292 293 /* Samsung */ 294 #define SAMSUNG_VENDORID 0x144d 295 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 296 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 297 298 /* Medion ? */ 299 #define MEDION_VENDORID 0x161f 300 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 301 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 302 303 /* Apple Computer Inc. */ 304 #define APPLE_VENDORID 0x106b 305 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 306 307 /* Sony */ 308 #define SONY_VENDORID 0x104d 309 #define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 310 #define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 311 312 /* 313 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 314 * instead of their own, which is beyond my comprehension 315 * (see HDA_CODEC_STAC9221 below). 316 */ 317 #define APPLE_INTEL_MAC 0x76808384 318 #define APPLE_MACBOOKPRO55 0xcb7910de 319 320 /* LG Electronics */ 321 #define LG_VENDORID 0x1854 322 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 323 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 324 325 /* Fujitsu Siemens */ 326 #define FS_VENDORID 0x1734 327 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 328 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 329 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 330 331 /* Fujitsu Limited */ 332 #define FL_VENDORID 0x10cf 333 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 334 #define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 335 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 336 337 /* Toshiba */ 338 #define TOSHIBA_VENDORID 0x1179 339 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 340 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 341 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 342 343 /* Micro-Star International (MSI) */ 344 #define MSI_VENDORID 0x1462 345 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 346 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 347 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 348 349 /* Giga-Byte Technology */ 350 #define GB_VENDORID 0x1458 351 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 352 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 353 354 /* Uniwill ? */ 355 #define UNIWILL_VENDORID 0x1584 356 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 357 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 358 359 360 /* Misc constants.. */ 361 #define HDA_AMP_VOL_DEFAULT (-1) 362 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 363 #define HDA_AMP_MUTE_NONE (0) 364 #define HDA_AMP_MUTE_LEFT (1 << 0) 365 #define HDA_AMP_MUTE_RIGHT (1 << 1) 366 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 367 368 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 369 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 370 371 #define HDA_ADC_MONITOR (1 << 0) 372 373 #define HDA_CTL_OUT 1 374 #define HDA_CTL_IN 2 375 376 #define HDA_GPIO_MAX 8 377 /* 0 - 7 = GPIO , 8 = Flush */ 378 #define HDA_QUIRK_GPIO0 (1 << 0) 379 #define HDA_QUIRK_GPIO1 (1 << 1) 380 #define HDA_QUIRK_GPIO2 (1 << 2) 381 #define HDA_QUIRK_GPIO3 (1 << 3) 382 #define HDA_QUIRK_GPIO4 (1 << 4) 383 #define HDA_QUIRK_GPIO5 (1 << 5) 384 #define HDA_QUIRK_GPIO6 (1 << 6) 385 #define HDA_QUIRK_GPIO7 (1 << 7) 386 #define HDA_QUIRK_GPIOFLUSH (1 << 8) 387 388 /* 9 - 25 = anything else */ 389 #define HDA_QUIRK_SOFTPCMVOL (1 << 9) 390 #define HDA_QUIRK_FIXEDRATE (1 << 10) 391 #define HDA_QUIRK_FORCESTEREO (1 << 11) 392 #define HDA_QUIRK_EAPDINV (1 << 12) 393 #define HDA_QUIRK_DMAPOS (1 << 13) 394 #define HDA_QUIRK_SENSEINV (1 << 14) 395 396 /* 26 - 31 = vrefs */ 397 #define HDA_QUIRK_IVREF50 (1 << 26) 398 #define HDA_QUIRK_IVREF80 (1 << 27) 399 #define HDA_QUIRK_IVREF100 (1 << 28) 400 #define HDA_QUIRK_OVREF50 (1 << 29) 401 #define HDA_QUIRK_OVREF80 (1 << 30) 402 #define HDA_QUIRK_OVREF100 (1 << 31) 403 404 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 405 HDA_QUIRK_IVREF100) 406 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 407 HDA_QUIRK_OVREF100) 408 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 409 410 #if __FreeBSD_version < 600000 411 #define taskqueue_drain(...) 412 #endif 413 414 static const struct { 415 char *key; 416 uint32_t value; 417 } hdac_quirks_tab[] = { 418 { "gpio0", HDA_QUIRK_GPIO0 }, 419 { "gpio1", HDA_QUIRK_GPIO1 }, 420 { "gpio2", HDA_QUIRK_GPIO2 }, 421 { "gpio3", HDA_QUIRK_GPIO3 }, 422 { "gpio4", HDA_QUIRK_GPIO4 }, 423 { "gpio5", HDA_QUIRK_GPIO5 }, 424 { "gpio6", HDA_QUIRK_GPIO6 }, 425 { "gpio7", HDA_QUIRK_GPIO7 }, 426 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 427 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 428 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 429 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 430 { "eapdinv", HDA_QUIRK_EAPDINV }, 431 { "dmapos", HDA_QUIRK_DMAPOS }, 432 { "senseinv", HDA_QUIRK_SENSEINV }, 433 { "ivref50", HDA_QUIRK_IVREF50 }, 434 { "ivref80", HDA_QUIRK_IVREF80 }, 435 { "ivref100", HDA_QUIRK_IVREF100 }, 436 { "ovref50", HDA_QUIRK_OVREF50 }, 437 { "ovref80", HDA_QUIRK_OVREF80 }, 438 { "ovref100", HDA_QUIRK_OVREF100 }, 439 { "ivref", HDA_QUIRK_IVREF }, 440 { "ovref", HDA_QUIRK_OVREF }, 441 { "vref", HDA_QUIRK_VREF }, 442 }; 443 #define HDAC_QUIRKS_TAB_LEN \ 444 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 445 446 #define HDA_BDL_MIN 2 447 #define HDA_BDL_MAX 256 448 #define HDA_BDL_DEFAULT HDA_BDL_MIN 449 450 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 451 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 452 453 #define HDA_BUFSZ_MIN 4096 454 #define HDA_BUFSZ_MAX 65536 455 #define HDA_BUFSZ_DEFAULT 16384 456 457 #define HDA_PARSE_MAXDEPTH 10 458 459 #define HDAC_UNSOLTAG_EVENT_HP 0x00 460 461 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 462 463 const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 464 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 465 "White", "Other"}; 466 467 const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 468 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 469 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 470 471 const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 472 473 /* Default */ 474 static uint32_t hdac_fmt[] = { 475 SND_FORMAT(AFMT_S16_LE, 2, 0), 476 0 477 }; 478 479 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 480 481 #define HDAC_NO_MSI 1 482 #define HDAC_NO_64BIT 2 483 484 static const struct { 485 uint32_t model; 486 char *desc; 487 char flags; 488 } hdac_devices[] = { 489 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 490 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 491 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 492 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 493 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 494 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 495 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 496 { HDA_INTEL_PCH, "Intel PCH", 0 }, 497 { HDA_INTEL_SCH, "Intel SCH", 0 }, 498 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 499 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 500 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 501 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 502 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 503 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 504 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 505 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 506 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 507 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 508 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 509 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 510 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 511 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 512 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 513 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 514 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 515 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 516 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 517 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 518 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 519 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 520 { HDA_ATI_SB450, "ATI SB450", 0 }, 521 { HDA_ATI_SB600, "ATI SB600", 0 }, 522 { HDA_ATI_RS600, "ATI RS600", 0 }, 523 { HDA_ATI_RS690, "ATI RS690", 0 }, 524 { HDA_ATI_RS780, "ATI RS780", 0 }, 525 { HDA_ATI_R600, "ATI R600", 0 }, 526 { HDA_ATI_RV610, "ATI RV610", 0 }, 527 { HDA_ATI_RV620, "ATI RV620", 0 }, 528 { HDA_ATI_RV630, "ATI RV630", 0 }, 529 { HDA_ATI_RV635, "ATI RV635", 0 }, 530 { HDA_ATI_RV710, "ATI RV710", 0 }, 531 { HDA_ATI_RV730, "ATI RV730", 0 }, 532 { HDA_ATI_RV740, "ATI RV740", 0 }, 533 { HDA_ATI_RV770, "ATI RV770", 0 }, 534 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 535 { HDA_SIS_966, "SiS 966", 0 }, 536 { HDA_ULI_M5461, "ULI M5461", 0 }, 537 /* Unknown */ 538 { HDA_INTEL_ALL, "Intel (Unknown)" }, 539 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 540 { HDA_ATI_ALL, "ATI (Unknown)" }, 541 { HDA_VIA_ALL, "VIA (Unknown)" }, 542 { HDA_SIS_ALL, "SiS (Unknown)" }, 543 { HDA_ULI_ALL, "ULI (Unknown)" }, 544 }; 545 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 546 547 static const struct { 548 uint16_t vendor; 549 uint8_t reg; 550 uint8_t mask; 551 uint8_t enable; 552 } hdac_pcie_snoop[] = { 553 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 554 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 555 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 556 }; 557 #define HDAC_PCIESNOOP_LEN \ 558 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 559 560 static const struct { 561 uint32_t rate; 562 int valid; 563 uint16_t base; 564 uint16_t mul; 565 uint16_t div; 566 } hda_rate_tab[] = { 567 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 568 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 569 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 570 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 571 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 572 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 573 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 574 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 575 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 576 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 577 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 578 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 579 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 580 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 581 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 582 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 583 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 584 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 585 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 586 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 587 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 588 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 589 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 590 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 591 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 592 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 593 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 594 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 595 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 596 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 597 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 598 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 599 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 600 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 601 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 602 }; 603 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 604 605 /* All codecs you can eat... */ 606 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 607 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 608 609 /* Cirrus Logic */ 610 #define CIRRUSLOGIC_VENDORID 0x1013 611 #define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206) 612 #define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207) 613 #define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff) 614 615 /* Realtek */ 616 #define REALTEK_VENDORID 0x10ec 617 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 618 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 619 #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 620 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 621 #define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 622 #define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270) 623 #define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 624 #define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273) 625 #define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275) 626 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 627 #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 628 #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 629 #define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665) 630 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 631 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 632 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 633 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 634 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 635 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 636 #define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) 637 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 638 #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 639 #define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892) 640 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 641 642 /* Analog Devices */ 643 #define ANALOGDEVICES_VENDORID 0x11d4 644 #define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 645 #define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 646 #define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 647 #define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 648 #define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 649 #define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 650 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 651 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 652 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 653 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 654 #define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 655 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 656 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 657 #define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 658 #define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 659 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 660 661 /* CMedia */ 662 #define CMEDIA_VENDORID 0x434d 663 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 664 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 665 666 /* Sigmatel */ 667 #define SIGMATEL_VENDORID 0x8384 668 #define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 669 #define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 670 #define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 671 #define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 672 #define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 673 #define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 674 #define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 675 #define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 676 #define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 677 #define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 678 #define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 679 #define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 680 #define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 681 #define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 682 #define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 683 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 684 #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 685 #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 686 #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 687 #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 688 #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 689 #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 690 #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 691 #define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 692 #define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661) 693 #define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 694 #define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664) 695 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 696 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 697 #define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 698 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 699 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 700 #define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 701 #define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 702 #define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 703 #define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 704 #define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 705 #define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 706 #define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 707 #define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 708 #define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 709 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 710 711 /* IDT */ 712 #define IDT_VENDORID 0x111d 713 #define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 714 #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 715 #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 716 #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 717 #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 718 #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 719 #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 720 #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 721 #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 722 #define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 723 #define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 724 #define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 725 #define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 726 727 /* Silicon Image */ 728 #define SII_VENDORID 0x1095 729 #define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 730 #define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 731 #define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 732 733 /* Lucent/Agere */ 734 #define AGERE_VENDORID 0x11c1 735 #define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 736 737 /* Conexant */ 738 #define CONEXANT_VENDORID 0x14f1 739 #define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 740 #define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 741 #define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 742 #define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066) 743 #define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067) 744 #define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069) 745 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 746 747 /* VIA */ 748 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 749 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 750 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 751 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 752 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 753 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 754 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 755 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 756 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 757 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 758 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 759 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 760 #define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 761 #define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 762 #define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 763 #define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 764 #define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 765 #define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 766 #define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 767 #define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 768 #define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 769 #define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 770 #define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 771 #define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 772 #define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 773 #define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 774 #define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 775 #define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 776 #define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 777 #define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 778 #define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 779 #define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 780 #define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 781 #define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 782 #define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 783 #define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 784 #define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433) 785 #define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721) 786 #define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428) 787 #define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428) 788 #define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448) 789 #define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440) 790 #define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441) 791 #define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438) 792 #define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438) 793 #define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441) 794 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 795 796 /* ATI */ 797 #define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 798 #define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 799 #define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 800 #define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 801 #define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 802 803 /* NVIDIA */ 804 #define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 805 #define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 806 #define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 807 #define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a) 808 #define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b) 809 #define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c) 810 #define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d) 811 #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 812 #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 813 #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 814 815 /* INTEL */ 816 #define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 817 #define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 818 #define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 819 #define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x2804) 820 #define HDA_CODEC_INTELG45_5 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 821 #define HDA_CODEC_INTELQ57 HDA_CODEC_CONSTRUCT(INTEL, 0x0054) 822 #define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 823 824 /* Codecs */ 825 static const struct { 826 uint32_t id; 827 char *name; 828 } hdac_codecs[] = { 829 { HDA_CODEC_CS4206, "Cirrus Logic CS4206" }, 830 { HDA_CODEC_CS4207, "Cirrus Logic CS4207" }, 831 { HDA_CODEC_ALC260, "Realtek ALC260" }, 832 { HDA_CODEC_ALC262, "Realtek ALC262" }, 833 { HDA_CODEC_ALC267, "Realtek ALC267" }, 834 { HDA_CODEC_ALC268, "Realtek ALC268" }, 835 { HDA_CODEC_ALC269, "Realtek ALC269" }, 836 { HDA_CODEC_ALC270, "Realtek ALC270" }, 837 { HDA_CODEC_ALC272, "Realtek ALC272" }, 838 { HDA_CODEC_ALC273, "Realtek ALC273" }, 839 { HDA_CODEC_ALC275, "Realtek ALC275" }, 840 { HDA_CODEC_ALC660, "Realtek ALC660" }, 841 { HDA_CODEC_ALC662, "Realtek ALC662" }, 842 { HDA_CODEC_ALC663, "Realtek ALC663" }, 843 { HDA_CODEC_ALC665, "Realtek ALC665" }, 844 { HDA_CODEC_ALC861, "Realtek ALC861" }, 845 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 846 { HDA_CODEC_ALC880, "Realtek ALC880" }, 847 { HDA_CODEC_ALC882, "Realtek ALC882" }, 848 { HDA_CODEC_ALC883, "Realtek ALC883" }, 849 { HDA_CODEC_ALC885, "Realtek ALC885" }, 850 { HDA_CODEC_ALC887, "Realtek ALC887" }, 851 { HDA_CODEC_ALC888, "Realtek ALC888" }, 852 { HDA_CODEC_ALC889, "Realtek ALC889" }, 853 { HDA_CODEC_ALC892, "Realtek ALC892" }, 854 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 855 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 856 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 857 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 858 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 859 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 860 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 861 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 862 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 863 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 864 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 865 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 866 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 867 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 868 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 869 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 870 { HDA_CODEC_CXD9872RDK, "Sigmatel CXD9872RD/K" }, 871 { HDA_CODEC_CXD9872AKD, "Sigmatel CXD9872AKD" }, 872 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 873 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 874 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 875 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 876 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 877 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 878 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 879 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 880 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 881 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 882 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 883 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 884 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 885 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 886 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 887 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 888 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 889 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 890 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 891 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 892 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 893 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 894 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 895 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 896 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 897 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 898 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 899 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 900 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 901 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 902 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 903 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 904 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 905 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 906 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 907 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 908 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 909 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 910 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 911 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 912 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 913 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 914 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 915 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 916 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 917 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 918 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 919 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 920 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 921 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 922 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 923 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 924 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 925 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 926 { HDA_CODEC_CX20582, "Conexant CX20582 (Pebble)" }, 927 { HDA_CODEC_CX20583, "Conexant CX20583 (Pebble HSF)" }, 928 { HDA_CODEC_CX20585, "Conexant CX20585" }, 929 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 930 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 931 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 932 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 933 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 934 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 935 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 936 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 937 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 938 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 939 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 940 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 941 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 942 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 943 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 944 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 945 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 946 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 947 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 948 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 949 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 950 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 951 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 952 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 953 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 954 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 955 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 956 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 957 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 958 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 959 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 960 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 961 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 962 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 963 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 964 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 965 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" }, 966 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" }, 967 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" }, 968 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" }, 969 { HDA_CODEC_VT1812, "VIA VT1812" }, 970 { HDA_CODEC_VT1818S, "VIA VT1818S" }, 971 { HDA_CODEC_VT1828S, "VIA VT1828S" }, 972 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" }, 973 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" }, 974 { HDA_CODEC_VT2020, "VIA VT2020" }, 975 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 976 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 977 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 978 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 979 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 980 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 981 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 982 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 983 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 984 { HDA_CODEC_NVIDIAGT220, "NVidia GT220 HDMI" }, 985 { HDA_CODEC_NVIDIAGT21X, "NVidia GT21x HDMI" }, 986 { HDA_CODEC_NVIDIAMCP89, "NVidia MCP89 HDMI" }, 987 { HDA_CODEC_NVIDIAGT240, "NVidia GT240 HDMI" }, 988 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 989 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 990 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 991 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 992 { HDA_CODEC_INTELG45_5, "Intel G45 HDMI" }, 993 { HDA_CODEC_INTELQ57, "Intel Q57 HDMI" }, 994 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 995 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 996 /* Unknown codec */ 997 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 998 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 999 { HDA_CODEC_CSXXXX, "Cirrus Logic (Unknown)" }, 1000 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 1001 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 1002 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 1003 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 1004 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 1005 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 1006 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 1007 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 1008 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 1009 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 1010 }; 1011 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 1012 1013 1014 /**************************************************************************** 1015 * Function prototypes 1016 ****************************************************************************/ 1017 static void hdac_intr_handler(void *); 1018 static int hdac_reset(struct hdac_softc *, int); 1019 static int hdac_get_capabilities(struct hdac_softc *); 1020 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 1021 static int hdac_dma_alloc(struct hdac_softc *, 1022 struct hdac_dma *, bus_size_t); 1023 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 1024 static int hdac_mem_alloc(struct hdac_softc *); 1025 static void hdac_mem_free(struct hdac_softc *); 1026 static int hdac_irq_alloc(struct hdac_softc *); 1027 static void hdac_irq_free(struct hdac_softc *); 1028 static void hdac_corb_init(struct hdac_softc *); 1029 static void hdac_rirb_init(struct hdac_softc *); 1030 static void hdac_corb_start(struct hdac_softc *); 1031 static void hdac_rirb_start(struct hdac_softc *); 1032 static void hdac_scan_codecs(struct hdac_softc *); 1033 static void hdac_probe_codec(struct hdac_codec *); 1034 static void hdac_probe_function(struct hdac_codec *, nid_t); 1035 static int hdac_pcmchannel_setup(struct hdac_chan *); 1036 1037 static void hdac_attach2(void *); 1038 1039 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 1040 uint32_t, int); 1041 static void hdac_command_send_internal(struct hdac_softc *, 1042 struct hdac_command_list *, int); 1043 1044 static int hdac_probe(device_t); 1045 static int hdac_attach(device_t); 1046 static int hdac_detach(device_t); 1047 static int hdac_suspend(device_t); 1048 static int hdac_resume(device_t); 1049 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 1050 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 1051 uint32_t, int, int); 1052 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 1053 nid_t, int, int, int); 1054 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 1055 nid_t, nid_t, int, int, int, int, int, int); 1056 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 1057 1058 static int hdac_rirb_flush(struct hdac_softc *sc); 1059 static int hdac_unsolq_flush(struct hdac_softc *sc); 1060 1061 static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 1062 1063 #define hdac_command(a1, a2, a3) \ 1064 hdac_command_sendone_internal(a1, a2, a3) 1065 1066 #define hdac_codec_id(c) \ 1067 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1068 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1069 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1070 1071 static char * 1072 hdac_codec_name(struct hdac_codec *codec) 1073 { 1074 uint32_t id; 1075 int i; 1076 1077 id = hdac_codec_id(codec); 1078 1079 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1080 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1081 return (hdac_codecs[i].name); 1082 } 1083 1084 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1085 } 1086 1087 static char * 1088 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1089 { 1090 static char *ossname[] = SOUND_DEVICE_NAMES; 1091 int i, first = 1; 1092 1093 bzero(buf, len); 1094 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1095 if (mask & (1 << i)) { 1096 if (first == 0) 1097 strlcat(buf, ", ", len); 1098 strlcat(buf, ossname[i], len); 1099 first = 0; 1100 } 1101 } 1102 return (buf); 1103 } 1104 1105 static struct hdac_audio_ctl * 1106 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1107 { 1108 if (devinfo == NULL || 1109 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1110 index == NULL || devinfo->function.audio.ctl == NULL || 1111 devinfo->function.audio.ctlcnt < 1 || 1112 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1113 return (NULL); 1114 return (&devinfo->function.audio.ctl[(*index)++]); 1115 } 1116 1117 static struct hdac_audio_ctl * 1118 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1119 int index, int cnt) 1120 { 1121 struct hdac_audio_ctl *ctl; 1122 int i, found = 0; 1123 1124 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1125 return (NULL); 1126 1127 i = 0; 1128 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1129 if (ctl->enable == 0) 1130 continue; 1131 if (ctl->widget->nid != nid) 1132 continue; 1133 if (dir && ctl->ndir != dir) 1134 continue; 1135 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1136 ctl->dir == ctl->ndir && ctl->index != index) 1137 continue; 1138 found++; 1139 if (found == cnt || cnt <= 0) 1140 return (ctl); 1141 } 1142 1143 return (NULL); 1144 } 1145 1146 /* 1147 * Jack detection (Speaker/HP redirection) event handler. 1148 */ 1149 static void 1150 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1151 { 1152 struct hdac_audio_as *as; 1153 struct hdac_softc *sc; 1154 struct hdac_widget *w; 1155 struct hdac_audio_ctl *ctl; 1156 uint32_t val, res; 1157 int i, j; 1158 nid_t cad; 1159 1160 if (devinfo == NULL || devinfo->codec == NULL || 1161 devinfo->codec->sc == NULL) 1162 return; 1163 1164 sc = devinfo->codec->sc; 1165 cad = devinfo->codec->cad; 1166 as = devinfo->function.audio.as; 1167 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1168 if (as[i].hpredir < 0) 1169 continue; 1170 1171 w = hdac_widget_get(devinfo, as[i].pins[15]); 1172 if (w == NULL || w->enable == 0 || w->type != 1173 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1174 continue; 1175 1176 res = hdac_command(sc, 1177 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1178 1179 HDA_BOOTVERBOSE( 1180 device_printf(sc->dev, 1181 "Pin sense: nid=%d res=0x%08x\n", 1182 as[i].pins[15], res); 1183 ); 1184 1185 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1186 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1187 res ^= 1; 1188 1189 /* (Un)Mute headphone pin. */ 1190 ctl = hdac_audio_ctl_amp_get(devinfo, 1191 as[i].pins[15], HDA_CTL_IN, -1, 1); 1192 if (ctl != NULL && ctl->mute) { 1193 /* If pin has muter - use it. */ 1194 val = (res != 0) ? 0 : 1; 1195 if (val != ctl->forcemute) { 1196 ctl->forcemute = val; 1197 hdac_audio_ctl_amp_set(ctl, 1198 HDA_AMP_MUTE_DEFAULT, 1199 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1200 } 1201 } else { 1202 /* If there is no muter - disable pin output. */ 1203 w = hdac_widget_get(devinfo, as[i].pins[15]); 1204 if (w != NULL && w->type == 1205 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1206 if (res != 0) 1207 val = w->wclass.pin.ctrl | 1208 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1209 else 1210 val = w->wclass.pin.ctrl & 1211 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1212 if (val != w->wclass.pin.ctrl) { 1213 w->wclass.pin.ctrl = val; 1214 hdac_command(sc, 1215 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1216 w->nid, w->wclass.pin.ctrl), cad); 1217 } 1218 } 1219 } 1220 /* (Un)Mute other pins. */ 1221 for (j = 0; j < 15; j++) { 1222 if (as[i].pins[j] <= 0) 1223 continue; 1224 ctl = hdac_audio_ctl_amp_get(devinfo, 1225 as[i].pins[j], HDA_CTL_IN, -1, 1); 1226 if (ctl != NULL && ctl->mute) { 1227 /* If pin has muter - use it. */ 1228 val = (res != 0) ? 1 : 0; 1229 if (val == ctl->forcemute) 1230 continue; 1231 ctl->forcemute = val; 1232 hdac_audio_ctl_amp_set(ctl, 1233 HDA_AMP_MUTE_DEFAULT, 1234 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1235 continue; 1236 } 1237 /* If there is no muter - disable pin output. */ 1238 w = hdac_widget_get(devinfo, as[i].pins[j]); 1239 if (w != NULL && w->type == 1240 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1241 if (res != 0) 1242 val = w->wclass.pin.ctrl & 1243 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1244 else 1245 val = w->wclass.pin.ctrl | 1246 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1247 if (val != w->wclass.pin.ctrl) { 1248 w->wclass.pin.ctrl = val; 1249 hdac_command(sc, 1250 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1251 w->nid, w->wclass.pin.ctrl), cad); 1252 } 1253 } 1254 } 1255 } 1256 } 1257 1258 /* 1259 * Callback for poll based jack detection. 1260 */ 1261 static void 1262 hdac_jack_poll_callback(void *arg) 1263 { 1264 struct hdac_devinfo *devinfo = arg; 1265 struct hdac_softc *sc; 1266 1267 if (devinfo == NULL || devinfo->codec == NULL || 1268 devinfo->codec->sc == NULL) 1269 return; 1270 sc = devinfo->codec->sc; 1271 hdac_lock(sc); 1272 if (sc->poll_ival == 0) { 1273 hdac_unlock(sc); 1274 return; 1275 } 1276 hdac_hp_switch_handler(devinfo); 1277 callout_reset(&sc->poll_jack, sc->poll_ival, 1278 hdac_jack_poll_callback, devinfo); 1279 hdac_unlock(sc); 1280 } 1281 1282 /* 1283 * Jack detection initializer. 1284 */ 1285 static void 1286 hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1287 { 1288 struct hdac_softc *sc = devinfo->codec->sc; 1289 struct hdac_audio_as *as = devinfo->function.audio.as; 1290 struct hdac_widget *w; 1291 uint32_t id; 1292 int i, enable = 0, poll = 0; 1293 nid_t cad; 1294 1295 id = hdac_codec_id(devinfo->codec); 1296 cad = devinfo->codec->cad; 1297 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1298 if (as[i].hpredir < 0) 1299 continue; 1300 1301 w = hdac_widget_get(devinfo, as[i].pins[15]); 1302 if (w == NULL || w->enable == 0 || w->type != 1303 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1304 continue; 1305 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1306 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1307 device_printf(sc->dev, 1308 "No jack detection support at pin %d\n", 1309 as[i].pins[15]); 1310 continue; 1311 } 1312 enable = 1; 1313 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1314 hdac_command(sc, 1315 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1316 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1317 HDAC_UNSOLTAG_EVENT_HP), cad); 1318 } else 1319 poll = 1; 1320 HDA_BOOTVERBOSE( 1321 device_printf(sc->dev, 1322 "Enabling headphone/speaker " 1323 "audio routing switching:\n"); 1324 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1325 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1326 ); 1327 } 1328 if (enable) { 1329 hdac_hp_switch_handler(devinfo); 1330 if (poll) { 1331 callout_reset(&sc->poll_jack, 1, 1332 hdac_jack_poll_callback, devinfo); 1333 } 1334 } 1335 } 1336 1337 /* 1338 * Unsolicited messages handler. 1339 */ 1340 static void 1341 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1342 { 1343 struct hdac_softc *sc; 1344 struct hdac_devinfo *devinfo = NULL; 1345 int i; 1346 1347 if (codec == NULL || codec->sc == NULL) 1348 return; 1349 1350 sc = codec->sc; 1351 1352 HDA_BOOTVERBOSE( 1353 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1354 ); 1355 1356 for (i = 0; i < codec->num_fgs; i++) { 1357 if (codec->fgs[i].node_type == 1358 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1359 devinfo = &codec->fgs[i]; 1360 break; 1361 } 1362 } 1363 1364 if (devinfo == NULL) 1365 return; 1366 1367 switch (tag) { 1368 case HDAC_UNSOLTAG_EVENT_HP: 1369 hdac_hp_switch_handler(devinfo); 1370 break; 1371 default: 1372 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1373 break; 1374 } 1375 } 1376 1377 static int 1378 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1379 { 1380 /* XXX to be removed */ 1381 #ifdef HDAC_INTR_EXTRA 1382 uint32_t res; 1383 #endif 1384 1385 if (!(ch->flags & HDAC_CHN_RUNNING)) 1386 return (0); 1387 1388 /* XXX to be removed */ 1389 #ifdef HDAC_INTR_EXTRA 1390 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1391 #endif 1392 1393 /* XXX to be removed */ 1394 #ifdef HDAC_INTR_EXTRA 1395 HDA_BOOTVERBOSE( 1396 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1397 device_printf(ch->pdevinfo->dev, 1398 "PCMDIR_%s intr triggered beyond stream boundary:" 1399 "%08x\n", 1400 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1401 ); 1402 #endif 1403 1404 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1405 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1406 1407 /* XXX to be removed */ 1408 #ifdef HDAC_INTR_EXTRA 1409 if (res & HDAC_SDSTS_BCIS) { 1410 #endif 1411 return (1); 1412 /* XXX to be removed */ 1413 #ifdef HDAC_INTR_EXTRA 1414 } 1415 #endif 1416 1417 return (0); 1418 } 1419 1420 /**************************************************************************** 1421 * void hdac_intr_handler(void *) 1422 * 1423 * Interrupt handler. Processes interrupts received from the hdac. 1424 ****************************************************************************/ 1425 static void 1426 hdac_intr_handler(void *context) 1427 { 1428 struct hdac_softc *sc; 1429 uint32_t intsts; 1430 uint8_t rirbsts; 1431 struct hdac_rirb *rirb_base; 1432 uint32_t trigger; 1433 int i; 1434 1435 sc = (struct hdac_softc *)context; 1436 1437 hdac_lock(sc); 1438 if (sc->polling != 0) { 1439 hdac_unlock(sc); 1440 return; 1441 } 1442 1443 /* Do we have anything to do? */ 1444 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1445 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1446 hdac_unlock(sc); 1447 return; 1448 } 1449 1450 trigger = 0; 1451 1452 /* Was this a controller interrupt? */ 1453 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1454 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1455 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1456 /* Get as many responses that we can */ 1457 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1458 HDAC_WRITE_1(&sc->mem, 1459 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1460 if (hdac_rirb_flush(sc) != 0) 1461 trigger |= HDAC_TRIGGER_UNSOL; 1462 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1463 } 1464 /* XXX to be removed */ 1465 /* Clear interrupt and exit */ 1466 #ifdef HDAC_INTR_EXTRA 1467 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1468 #endif 1469 } 1470 1471 if (intsts & HDAC_INTSTS_SIS_MASK) { 1472 for (i = 0; i < sc->num_chans; i++) { 1473 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1474 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1475 trigger |= (1 << i); 1476 } 1477 /* XXX to be removed */ 1478 #ifdef HDAC_INTR_EXTRA 1479 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1480 HDAC_INTSTS_SIS_MASK); 1481 #endif 1482 } 1483 1484 hdac_unlock(sc); 1485 1486 for (i = 0; i < sc->num_chans; i++) { 1487 if (trigger & (1 << i)) 1488 chn_intr(sc->chans[i].c); 1489 } 1490 if (trigger & HDAC_TRIGGER_UNSOL) 1491 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1492 } 1493 1494 /**************************************************************************** 1495 * int hdac_reset(hdac_softc *, int) 1496 * 1497 * Reset the hdac to a quiescent and known state. 1498 ****************************************************************************/ 1499 static int 1500 hdac_reset(struct hdac_softc *sc, int wakeup) 1501 { 1502 uint32_t gctl; 1503 int count, i; 1504 1505 /* 1506 * Stop all Streams DMA engine 1507 */ 1508 for (i = 0; i < sc->num_iss; i++) 1509 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1510 for (i = 0; i < sc->num_oss; i++) 1511 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1512 for (i = 0; i < sc->num_bss; i++) 1513 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1514 1515 /* 1516 * Stop Control DMA engines. 1517 */ 1518 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1519 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1520 1521 /* 1522 * Reset DMA position buffer. 1523 */ 1524 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1525 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1526 1527 /* 1528 * Reset the controller. The reset must remain asserted for 1529 * a minimum of 100us. 1530 */ 1531 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1532 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1533 count = 10000; 1534 do { 1535 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1536 if (!(gctl & HDAC_GCTL_CRST)) 1537 break; 1538 DELAY(10); 1539 } while (--count); 1540 if (gctl & HDAC_GCTL_CRST) { 1541 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1542 return (ENXIO); 1543 } 1544 1545 /* If wakeup is not requested - leave the controller in reset state. */ 1546 if (!wakeup) 1547 return (0); 1548 1549 DELAY(100); 1550 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1551 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1552 count = 10000; 1553 do { 1554 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1555 if (gctl & HDAC_GCTL_CRST) 1556 break; 1557 DELAY(10); 1558 } while (--count); 1559 if (!(gctl & HDAC_GCTL_CRST)) { 1560 device_printf(sc->dev, "Device stuck in reset\n"); 1561 return (ENXIO); 1562 } 1563 1564 /* 1565 * Wait for codecs to finish their own reset sequence. The delay here 1566 * should be of 250us but for some reasons, on it's not enough on my 1567 * computer. Let's use twice as much as necessary to make sure that 1568 * it's reset properly. 1569 */ 1570 DELAY(1000); 1571 1572 return (0); 1573 } 1574 1575 1576 /**************************************************************************** 1577 * int hdac_get_capabilities(struct hdac_softc *); 1578 * 1579 * Retreive the general capabilities of the hdac; 1580 * Number of Input Streams 1581 * Number of Output Streams 1582 * Number of bidirectional Streams 1583 * 64bit ready 1584 * CORB and RIRB sizes 1585 ****************************************************************************/ 1586 static int 1587 hdac_get_capabilities(struct hdac_softc *sc) 1588 { 1589 uint16_t gcap; 1590 uint8_t corbsize, rirbsize; 1591 1592 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1593 sc->num_iss = HDAC_GCAP_ISS(gcap); 1594 sc->num_oss = HDAC_GCAP_OSS(gcap); 1595 sc->num_bss = HDAC_GCAP_BSS(gcap); 1596 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1597 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1598 1599 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1600 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1601 HDAC_CORBSIZE_CORBSZCAP_256) 1602 sc->corb_size = 256; 1603 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1604 HDAC_CORBSIZE_CORBSZCAP_16) 1605 sc->corb_size = 16; 1606 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1607 HDAC_CORBSIZE_CORBSZCAP_2) 1608 sc->corb_size = 2; 1609 else { 1610 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1611 __func__, corbsize); 1612 return (ENXIO); 1613 } 1614 1615 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1616 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1617 HDAC_RIRBSIZE_RIRBSZCAP_256) 1618 sc->rirb_size = 256; 1619 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1620 HDAC_RIRBSIZE_RIRBSZCAP_16) 1621 sc->rirb_size = 16; 1622 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1623 HDAC_RIRBSIZE_RIRBSZCAP_2) 1624 sc->rirb_size = 2; 1625 else { 1626 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1627 __func__, rirbsize); 1628 return (ENXIO); 1629 } 1630 1631 HDA_BOOTVERBOSE( 1632 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1633 "NSDO %d%s, CORB %d, RIRB %d\n", 1634 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1635 sc->support_64bit ? ", 64bit" : "", 1636 sc->corb_size, sc->rirb_size); 1637 ); 1638 1639 return (0); 1640 } 1641 1642 1643 /**************************************************************************** 1644 * void hdac_dma_cb 1645 * 1646 * This function is called by bus_dmamap_load when the mapping has been 1647 * established. We just record the physical address of the mapping into 1648 * the struct hdac_dma passed in. 1649 ****************************************************************************/ 1650 static void 1651 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1652 { 1653 struct hdac_dma *dma; 1654 1655 if (error == 0) { 1656 dma = (struct hdac_dma *)callback_arg; 1657 dma->dma_paddr = segs[0].ds_addr; 1658 } 1659 } 1660 1661 1662 /**************************************************************************** 1663 * int hdac_dma_alloc 1664 * 1665 * This function allocate and setup a dma region (struct hdac_dma). 1666 * It must be freed by a corresponding hdac_dma_free. 1667 ****************************************************************************/ 1668 static int 1669 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1670 { 1671 bus_size_t roundsz; 1672 int result; 1673 1674 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1675 bzero(dma, sizeof(*dma)); 1676 1677 /* 1678 * Create a DMA tag 1679 */ 1680 result = bus_dma_tag_create( 1681 bus_get_dma_tag(sc->dev), /* parent */ 1682 HDAC_DMA_ALIGNMENT, /* alignment */ 1683 0, /* boundary */ 1684 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1685 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1686 BUS_SPACE_MAXADDR, /* highaddr */ 1687 NULL, /* filtfunc */ 1688 NULL, /* fistfuncarg */ 1689 roundsz, /* maxsize */ 1690 1, /* nsegments */ 1691 roundsz, /* maxsegsz */ 1692 0, /* flags */ 1693 NULL, /* lockfunc */ 1694 NULL, /* lockfuncarg */ 1695 &dma->dma_tag); /* dmat */ 1696 if (result != 0) { 1697 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1698 __func__, result); 1699 goto hdac_dma_alloc_fail; 1700 } 1701 1702 /* 1703 * Allocate DMA memory 1704 */ 1705 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1706 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1707 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1708 &dma->dma_map); 1709 if (result != 0) { 1710 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1711 __func__, result); 1712 goto hdac_dma_alloc_fail; 1713 } 1714 1715 dma->dma_size = roundsz; 1716 1717 /* 1718 * Map the memory 1719 */ 1720 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1721 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1722 if (result != 0 || dma->dma_paddr == 0) { 1723 if (result == 0) 1724 result = ENOMEM; 1725 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1726 __func__, result); 1727 goto hdac_dma_alloc_fail; 1728 } 1729 1730 HDA_BOOTHVERBOSE( 1731 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1732 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1733 ); 1734 1735 return (0); 1736 1737 hdac_dma_alloc_fail: 1738 hdac_dma_free(sc, dma); 1739 1740 return (result); 1741 } 1742 1743 1744 /**************************************************************************** 1745 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1746 * 1747 * Free a struct dhac_dma that has been previously allocated via the 1748 * hdac_dma_alloc function. 1749 ****************************************************************************/ 1750 static void 1751 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1752 { 1753 if (dma->dma_map != NULL) { 1754 #if 0 1755 /* Flush caches */ 1756 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1757 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1758 #endif 1759 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1760 } 1761 if (dma->dma_vaddr != NULL) { 1762 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1763 dma->dma_vaddr = NULL; 1764 } 1765 dma->dma_map = NULL; 1766 if (dma->dma_tag != NULL) { 1767 bus_dma_tag_destroy(dma->dma_tag); 1768 dma->dma_tag = NULL; 1769 } 1770 dma->dma_size = 0; 1771 } 1772 1773 /**************************************************************************** 1774 * int hdac_mem_alloc(struct hdac_softc *) 1775 * 1776 * Allocate all the bus resources necessary to speak with the physical 1777 * controller. 1778 ****************************************************************************/ 1779 static int 1780 hdac_mem_alloc(struct hdac_softc *sc) 1781 { 1782 struct hdac_mem *mem; 1783 1784 mem = &sc->mem; 1785 mem->mem_rid = PCIR_BAR(0); 1786 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1787 &mem->mem_rid, RF_ACTIVE); 1788 if (mem->mem_res == NULL) { 1789 device_printf(sc->dev, 1790 "%s: Unable to allocate memory resource\n", __func__); 1791 return (ENOMEM); 1792 } 1793 mem->mem_tag = rman_get_bustag(mem->mem_res); 1794 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1795 1796 return (0); 1797 } 1798 1799 /**************************************************************************** 1800 * void hdac_mem_free(struct hdac_softc *) 1801 * 1802 * Free up resources previously allocated by hdac_mem_alloc. 1803 ****************************************************************************/ 1804 static void 1805 hdac_mem_free(struct hdac_softc *sc) 1806 { 1807 struct hdac_mem *mem; 1808 1809 mem = &sc->mem; 1810 if (mem->mem_res != NULL) 1811 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1812 mem->mem_res); 1813 mem->mem_res = NULL; 1814 } 1815 1816 /**************************************************************************** 1817 * int hdac_irq_alloc(struct hdac_softc *) 1818 * 1819 * Allocate and setup the resources necessary for interrupt handling. 1820 ****************************************************************************/ 1821 static int 1822 hdac_irq_alloc(struct hdac_softc *sc) 1823 { 1824 struct hdac_irq *irq; 1825 int result; 1826 1827 irq = &sc->irq; 1828 irq->irq_rid = 0x0; 1829 1830 if ((sc->flags & HDAC_F_MSI) && 1831 (result = pci_msi_count(sc->dev)) == 1 && 1832 pci_alloc_msi(sc->dev, &result) == 0) 1833 irq->irq_rid = 0x1; 1834 else 1835 sc->flags &= ~HDAC_F_MSI; 1836 1837 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1838 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1839 if (irq->irq_res == NULL) { 1840 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1841 __func__); 1842 goto hdac_irq_alloc_fail; 1843 } 1844 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1845 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1846 if (result != 0) { 1847 device_printf(sc->dev, 1848 "%s: Unable to setup interrupt handler (%x)\n", 1849 __func__, result); 1850 goto hdac_irq_alloc_fail; 1851 } 1852 1853 return (0); 1854 1855 hdac_irq_alloc_fail: 1856 hdac_irq_free(sc); 1857 1858 return (ENXIO); 1859 } 1860 1861 /**************************************************************************** 1862 * void hdac_irq_free(struct hdac_softc *) 1863 * 1864 * Free up resources previously allocated by hdac_irq_alloc. 1865 ****************************************************************************/ 1866 static void 1867 hdac_irq_free(struct hdac_softc *sc) 1868 { 1869 struct hdac_irq *irq; 1870 1871 irq = &sc->irq; 1872 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1873 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1874 if (irq->irq_res != NULL) 1875 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1876 irq->irq_res); 1877 if (irq->irq_rid == 0x1) 1878 pci_release_msi(sc->dev); 1879 irq->irq_handle = NULL; 1880 irq->irq_res = NULL; 1881 irq->irq_rid = 0x0; 1882 } 1883 1884 /**************************************************************************** 1885 * void hdac_corb_init(struct hdac_softc *) 1886 * 1887 * Initialize the corb registers for operations but do not start it up yet. 1888 * The CORB engine must not be running when this function is called. 1889 ****************************************************************************/ 1890 static void 1891 hdac_corb_init(struct hdac_softc *sc) 1892 { 1893 uint8_t corbsize; 1894 uint64_t corbpaddr; 1895 1896 /* Setup the CORB size. */ 1897 switch (sc->corb_size) { 1898 case 256: 1899 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1900 break; 1901 case 16: 1902 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1903 break; 1904 case 2: 1905 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1906 break; 1907 default: 1908 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1909 } 1910 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1911 1912 /* Setup the CORB Address in the hdac */ 1913 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1914 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1915 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1916 1917 /* Set the WP and RP */ 1918 sc->corb_wp = 0; 1919 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1920 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1921 /* 1922 * The HDA specification indicates that the CORBRPRST bit will always 1923 * read as zero. Unfortunately, it seems that at least the 82801G 1924 * doesn't reset the bit to zero, which stalls the corb engine. 1925 * manually reset the bit to zero before continuing. 1926 */ 1927 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1928 1929 /* Enable CORB error reporting */ 1930 #if 0 1931 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1932 #endif 1933 } 1934 1935 /**************************************************************************** 1936 * void hdac_rirb_init(struct hdac_softc *) 1937 * 1938 * Initialize the rirb registers for operations but do not start it up yet. 1939 * The RIRB engine must not be running when this function is called. 1940 ****************************************************************************/ 1941 static void 1942 hdac_rirb_init(struct hdac_softc *sc) 1943 { 1944 uint8_t rirbsize; 1945 uint64_t rirbpaddr; 1946 1947 /* Setup the RIRB size. */ 1948 switch (sc->rirb_size) { 1949 case 256: 1950 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1951 break; 1952 case 16: 1953 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1954 break; 1955 case 2: 1956 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1957 break; 1958 default: 1959 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1960 } 1961 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1962 1963 /* Setup the RIRB Address in the hdac */ 1964 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1965 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1966 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1967 1968 /* Setup the WP and RP */ 1969 sc->rirb_rp = 0; 1970 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1971 1972 /* Setup the interrupt threshold */ 1973 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1974 1975 /* Enable Overrun and response received reporting */ 1976 #if 0 1977 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1978 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1979 #else 1980 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1981 #endif 1982 1983 #if 0 1984 /* 1985 * Make sure that the Host CPU cache doesn't contain any dirty 1986 * cache lines that falls in the rirb. If I understood correctly, it 1987 * should be sufficient to do this only once as the rirb is purely 1988 * read-only from now on. 1989 */ 1990 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1991 BUS_DMASYNC_PREREAD); 1992 #endif 1993 } 1994 1995 /**************************************************************************** 1996 * void hdac_corb_start(hdac_softc *) 1997 * 1998 * Startup the corb DMA engine 1999 ****************************************************************************/ 2000 static void 2001 hdac_corb_start(struct hdac_softc *sc) 2002 { 2003 uint32_t corbctl; 2004 2005 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 2006 corbctl |= HDAC_CORBCTL_CORBRUN; 2007 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 2008 } 2009 2010 /**************************************************************************** 2011 * void hdac_rirb_start(hdac_softc *) 2012 * 2013 * Startup the rirb DMA engine 2014 ****************************************************************************/ 2015 static void 2016 hdac_rirb_start(struct hdac_softc *sc) 2017 { 2018 uint32_t rirbctl; 2019 2020 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 2021 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 2022 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 2023 } 2024 2025 2026 /**************************************************************************** 2027 * void hdac_scan_codecs(struct hdac_softc *, int) 2028 * 2029 * Scan the bus for available codecs, starting with num. 2030 ****************************************************************************/ 2031 static void 2032 hdac_scan_codecs(struct hdac_softc *sc) 2033 { 2034 struct hdac_codec *codec; 2035 int i; 2036 uint16_t statests; 2037 2038 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 2039 for (i = 0; i < HDAC_CODEC_MAX; i++) { 2040 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 2041 /* We have found a codec. */ 2042 codec = (struct hdac_codec *)malloc(sizeof(*codec), 2043 M_HDAC, M_ZERO | M_NOWAIT); 2044 if (codec == NULL) { 2045 device_printf(sc->dev, 2046 "Unable to allocate memory for codec\n"); 2047 continue; 2048 } 2049 codec->commands = NULL; 2050 codec->responses_received = 0; 2051 codec->verbs_sent = 0; 2052 codec->sc = sc; 2053 codec->cad = i; 2054 sc->codecs[i] = codec; 2055 hdac_probe_codec(codec); 2056 } 2057 } 2058 /* All codecs have been probed, now try to attach drivers to them */ 2059 /* bus_generic_attach(sc->dev); */ 2060 } 2061 2062 /**************************************************************************** 2063 * void hdac_probe_codec(struct hdac_softc *, int) 2064 * 2065 * Probe a the given codec_id for available function groups. 2066 ****************************************************************************/ 2067 static void 2068 hdac_probe_codec(struct hdac_codec *codec) 2069 { 2070 struct hdac_softc *sc = codec->sc; 2071 uint32_t vendorid, revisionid, subnode; 2072 int startnode; 2073 int endnode; 2074 int i; 2075 nid_t cad = codec->cad; 2076 2077 HDA_BOOTVERBOSE( 2078 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2079 ); 2080 vendorid = hdac_command(sc, 2081 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2082 cad); 2083 revisionid = hdac_command(sc, 2084 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2085 cad); 2086 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2087 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2088 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2089 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2090 2091 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2092 device_printf(sc->dev, "Codec #%d is not responding!" 2093 " Probing aborted.\n", cad); 2094 return; 2095 } 2096 2097 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2098 cad, hdac_codec_name(codec)); 2099 HDA_BOOTVERBOSE( 2100 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2101 hdac_codec_id(codec)); 2102 device_printf(sc->dev, " Vendor: 0x%04x\n", 2103 codec->vendor_id); 2104 device_printf(sc->dev, " Device: 0x%04x\n", 2105 codec->device_id); 2106 device_printf(sc->dev, " Revision: 0x%02x\n", 2107 codec->revision_id); 2108 device_printf(sc->dev, " Stepping: 0x%02x\n", 2109 codec->stepping_id); 2110 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2111 sc->pci_subvendor); 2112 ); 2113 subnode = hdac_command(sc, 2114 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2115 cad); 2116 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2117 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2118 2119 HDA_BOOTHVERBOSE( 2120 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2121 startnode, endnode); 2122 ); 2123 2124 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2125 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2126 if (codec->fgs == NULL) { 2127 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2128 __func__); 2129 return; 2130 } 2131 2132 for (i = startnode; i < endnode; i++) 2133 hdac_probe_function(codec, i); 2134 return; 2135 } 2136 2137 /* 2138 * Probe codec function and add it to the list. 2139 */ 2140 static void 2141 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2142 { 2143 struct hdac_softc *sc = codec->sc; 2144 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2145 uint32_t fctgrptype; 2146 uint32_t res; 2147 nid_t cad = codec->cad; 2148 2149 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2150 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2151 2152 devinfo->nid = nid; 2153 devinfo->node_type = fctgrptype; 2154 devinfo->codec = codec; 2155 2156 res = hdac_command(sc, 2157 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2158 2159 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2160 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2161 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2162 2163 HDA_BOOTVERBOSE( 2164 device_printf(sc->dev, 2165 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2166 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2167 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2168 "unknown", nid, devinfo->startnode, devinfo->endnode, 2169 devinfo->nodecnt); 2170 ); 2171 2172 if (devinfo->nodecnt > 0) 2173 devinfo->widget = (struct hdac_widget *)malloc( 2174 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2175 M_NOWAIT | M_ZERO); 2176 else 2177 devinfo->widget = NULL; 2178 2179 if (devinfo->widget == NULL) { 2180 device_printf(sc->dev, "unable to allocate widgets!\n"); 2181 devinfo->endnode = devinfo->startnode; 2182 devinfo->nodecnt = 0; 2183 return; 2184 } 2185 2186 codec->num_fgs++; 2187 } 2188 2189 static void 2190 hdac_widget_connection_parse(struct hdac_widget *w) 2191 { 2192 struct hdac_softc *sc = w->devinfo->codec->sc; 2193 uint32_t res; 2194 int i, j, max, ents, entnum; 2195 nid_t cad = w->devinfo->codec->cad; 2196 nid_t nid = w->nid; 2197 nid_t cnid, addcnid, prevcnid; 2198 2199 w->nconns = 0; 2200 2201 res = hdac_command(sc, 2202 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2203 2204 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2205 2206 if (ents < 1) 2207 return; 2208 2209 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2210 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2211 prevcnid = 0; 2212 2213 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2214 #define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2215 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2216 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2217 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2218 2219 for (i = 0; i < ents; i += entnum) { 2220 res = hdac_command(sc, 2221 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2222 for (j = 0; j < entnum; j++) { 2223 cnid = CONN_CNID(res, entnum, j); 2224 if (cnid == 0) { 2225 if (w->nconns < ents) 2226 device_printf(sc->dev, 2227 "%s: nid=%d WARNING: zero cnid " 2228 "entnum=%d j=%d index=%d " 2229 "entries=%d found=%d res=0x%08x\n", 2230 __func__, nid, entnum, j, i, 2231 ents, w->nconns, res); 2232 else 2233 goto getconns_out; 2234 } 2235 if (cnid < w->devinfo->startnode || 2236 cnid >= w->devinfo->endnode) { 2237 HDA_BOOTVERBOSE( 2238 device_printf(sc->dev, 2239 "GHOST: nid=%d j=%d " 2240 "entnum=%d index=%d res=0x%08x\n", 2241 nid, j, entnum, i, res); 2242 ); 2243 } 2244 if (CONN_RANGE(res, entnum, j) == 0) 2245 addcnid = cnid; 2246 else if (prevcnid == 0 || prevcnid >= cnid) { 2247 device_printf(sc->dev, 2248 "%s: WARNING: Invalid child range " 2249 "nid=%d index=%d j=%d entnum=%d " 2250 "prevcnid=%d cnid=%d res=0x%08x\n", 2251 __func__, nid, i, j, entnum, prevcnid, 2252 cnid, res); 2253 addcnid = cnid; 2254 } else 2255 addcnid = prevcnid + 1; 2256 while (addcnid <= cnid) { 2257 if (w->nconns > max) { 2258 device_printf(sc->dev, 2259 "Adding %d (nid=%d): " 2260 "Max connection reached! max=%d\n", 2261 addcnid, nid, max + 1); 2262 goto getconns_out; 2263 } 2264 w->connsenable[w->nconns] = 1; 2265 w->conns[w->nconns++] = addcnid++; 2266 } 2267 prevcnid = cnid; 2268 } 2269 } 2270 2271 getconns_out: 2272 return; 2273 } 2274 2275 static uint32_t 2276 hdac_widget_pin_patch(uint32_t config, const char *str) 2277 { 2278 char buf[256]; 2279 char *key, *value, *rest, *bad; 2280 int ival, i; 2281 2282 strlcpy(buf, str, sizeof(buf)); 2283 rest = buf; 2284 while ((key = strsep(&rest, "=")) != NULL) { 2285 value = strsep(&rest, " \t"); 2286 if (value == NULL) 2287 break; 2288 ival = strtol(value, &bad, 10); 2289 if (strcmp(key, "seq") == 0) { 2290 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2291 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2292 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2293 } else if (strcmp(key, "as") == 0) { 2294 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2295 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2296 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2297 } else if (strcmp(key, "misc") == 0) { 2298 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2299 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2300 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2301 } else if (strcmp(key, "color") == 0) { 2302 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2303 if (bad[0] == 0) { 2304 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2305 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2306 }; 2307 for (i = 0; i < 16; i++) { 2308 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2309 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2310 break; 2311 } 2312 } 2313 } else if (strcmp(key, "ctype") == 0) { 2314 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2315 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2316 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2317 } else if (strcmp(key, "device") == 0) { 2318 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2319 if (bad[0] == 0) { 2320 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2321 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2322 continue; 2323 }; 2324 for (i = 0; i < 16; i++) { 2325 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2326 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2327 break; 2328 } 2329 } 2330 } else if (strcmp(key, "loc") == 0) { 2331 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2332 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2333 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2334 } else if (strcmp(key, "conn") == 0) { 2335 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2336 if (bad[0] == 0) { 2337 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2338 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2339 continue; 2340 }; 2341 for (i = 0; i < 4; i++) { 2342 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2343 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2344 break; 2345 } 2346 } 2347 } 2348 } 2349 return (config); 2350 } 2351 2352 static uint32_t 2353 hdac_widget_pin_getconfig(struct hdac_widget *w) 2354 { 2355 struct hdac_softc *sc; 2356 uint32_t config, orig, id; 2357 nid_t cad, nid; 2358 char buf[32]; 2359 const char *res = NULL, *patch = NULL; 2360 2361 sc = w->devinfo->codec->sc; 2362 cad = w->devinfo->codec->cad; 2363 nid = w->nid; 2364 id = hdac_codec_id(w->devinfo->codec); 2365 2366 config = hdac_command(sc, 2367 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2368 cad); 2369 orig = config; 2370 2371 HDA_BOOTVERBOSE( 2372 hdac_dump_pin_config(w, orig); 2373 ); 2374 2375 /* XXX: Old patches require complete review. 2376 * Now they may create more problem then solve due to 2377 * incorrect associations. 2378 */ 2379 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2380 switch (nid) { 2381 case 26: 2382 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2383 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2384 break; 2385 case 27: 2386 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2387 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2388 break; 2389 default: 2390 break; 2391 } 2392 } else if (id == HDA_CODEC_ALC880 && 2393 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2394 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2395 /* 2396 * Super broken BIOS 2397 */ 2398 switch (nid) { 2399 case 24: /* MIC1 */ 2400 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2401 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2402 break; 2403 case 25: /* XXX MIC2 */ 2404 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2405 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2406 break; 2407 case 26: /* LINE1 */ 2408 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2409 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2410 break; 2411 case 27: /* XXX LINE2 */ 2412 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2413 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2414 break; 2415 case 28: /* CD */ 2416 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2417 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2418 break; 2419 } 2420 } else if (id == HDA_CODEC_ALC883 && 2421 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2422 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2423 switch (nid) { 2424 case 25: 2425 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2426 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2427 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2428 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2429 break; 2430 case 28: 2431 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2432 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2433 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2434 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2435 break; 2436 } 2437 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2438 HP_V3000_SUBVENDOR) { 2439 switch (nid) { 2440 case 18: 2441 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2442 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2443 break; 2444 case 20: 2445 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2446 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2447 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2448 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2449 break; 2450 case 21: 2451 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2452 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2453 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2454 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2455 break; 2456 } 2457 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2458 HP_DV5000_SUBVENDOR) { 2459 switch (nid) { 2460 case 20: 2461 case 21: 2462 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2463 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2464 break; 2465 } 2466 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2467 ASUS_W6F_SUBVENDOR) { 2468 switch (nid) { 2469 case 11: 2470 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2471 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2472 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2473 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2474 break; 2475 case 12: 2476 case 14: 2477 case 16: 2478 case 31: 2479 case 32: 2480 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2481 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2482 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2483 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2484 break; 2485 case 15: 2486 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2487 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2488 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2489 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2490 break; 2491 } 2492 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2493 UNIWILL_9075_SUBVENDOR) { 2494 switch (nid) { 2495 case 15: 2496 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2497 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2498 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2499 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2500 break; 2501 } 2502 } 2503 2504 /* New patches */ 2505 if (id == HDA_CODEC_AD1986A && 2506 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2507 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2508 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2509 switch (nid) { 2510 case 26: /* Headphones with redirection */ 2511 patch = "as=1 seq=15"; 2512 break; 2513 case 28: /* 5.1 out => 2.0 out + 1 input */ 2514 patch = "device=Line-in as=8 seq=1"; 2515 break; 2516 case 29: /* Can't use this as input, as the only available mic 2517 * preamplifier is busy by front panel mic (nid 31). 2518 * If you want to use this rear connector as mic input, 2519 * you have to disable the front panel one. */ 2520 patch = "as=0"; 2521 break; 2522 case 31: /* Lot of inputs configured with as=15 and unusable */ 2523 patch = "as=8 seq=3"; 2524 break; 2525 case 32: 2526 patch = "as=8 seq=4"; 2527 break; 2528 case 34: 2529 patch = "as=8 seq=5"; 2530 break; 2531 case 36: 2532 patch = "as=8 seq=6"; 2533 break; 2534 } 2535 } else if (id == HDA_CODEC_ALC260 && 2536 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2537 switch (nid) { 2538 case 16: 2539 patch = "seq=15 device=Headphones"; 2540 break; 2541 } 2542 } else if (id == HDA_CODEC_ALC268) { 2543 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2544 switch (nid) { 2545 case 20: /* Headphones Jack */ 2546 patch = "as=1 seq=15"; 2547 break; 2548 } 2549 } 2550 } 2551 2552 if (patch != NULL) 2553 config = hdac_widget_pin_patch(config, patch); 2554 2555 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2556 if (resource_string_value(device_get_name(sc->dev), 2557 device_get_unit(sc->dev), buf, &res) == 0) { 2558 if (strncmp(res, "0x", 2) == 0) { 2559 config = strtol(res + 2, NULL, 16); 2560 } else { 2561 config = hdac_widget_pin_patch(config, res); 2562 } 2563 } 2564 2565 HDA_BOOTVERBOSE( 2566 if (config != orig) 2567 device_printf(sc->dev, 2568 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2569 nid, orig, config); 2570 ); 2571 2572 return (config); 2573 } 2574 2575 static uint32_t 2576 hdac_widget_pin_getcaps(struct hdac_widget *w) 2577 { 2578 struct hdac_softc *sc; 2579 uint32_t caps, orig, id; 2580 nid_t cad, nid; 2581 2582 sc = w->devinfo->codec->sc; 2583 cad = w->devinfo->codec->cad; 2584 nid = w->nid; 2585 id = hdac_codec_id(w->devinfo->codec); 2586 2587 caps = hdac_command(sc, 2588 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2589 orig = caps; 2590 2591 HDA_BOOTVERBOSE( 2592 if (caps != orig) 2593 device_printf(sc->dev, 2594 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2595 nid, orig, caps); 2596 ); 2597 2598 return (caps); 2599 } 2600 2601 static void 2602 hdac_widget_pin_parse(struct hdac_widget *w) 2603 { 2604 struct hdac_softc *sc = w->devinfo->codec->sc; 2605 uint32_t config, pincap; 2606 const char *devstr; 2607 nid_t cad = w->devinfo->codec->cad; 2608 nid_t nid = w->nid; 2609 int conn, color; 2610 2611 config = hdac_widget_pin_getconfig(w); 2612 w->wclass.pin.config = config; 2613 2614 pincap = hdac_widget_pin_getcaps(w); 2615 w->wclass.pin.cap = pincap; 2616 2617 w->wclass.pin.ctrl = hdac_command(sc, 2618 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2619 2620 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2621 w->param.eapdbtl = hdac_command(sc, 2622 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2623 w->param.eapdbtl &= 0x7; 2624 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2625 } else 2626 w->param.eapdbtl = HDAC_INVALID; 2627 2628 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2629 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2630 2631 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2632 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2633 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2634 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2635 2636 strlcat(w->name, ": ", sizeof(w->name)); 2637 strlcat(w->name, devstr, sizeof(w->name)); 2638 strlcat(w->name, " (", sizeof(w->name)); 2639 if (conn == 0 && color != 0 && color != 15) { 2640 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2641 strlcat(w->name, " ", sizeof(w->name)); 2642 } 2643 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2644 strlcat(w->name, ")", sizeof(w->name)); 2645 } 2646 2647 static uint32_t 2648 hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2649 { 2650 struct hdac_softc *sc; 2651 uint32_t caps, orig, id; 2652 nid_t cad, nid, beeper = -1; 2653 2654 sc = w->devinfo->codec->sc; 2655 cad = w->devinfo->codec->cad; 2656 nid = w->nid; 2657 id = hdac_codec_id(w->devinfo->codec); 2658 2659 caps = hdac_command(sc, 2660 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2661 cad); 2662 orig = caps; 2663 2664 /* On some codecs beeper is an input pin, but it is not recordable 2665 alone. Also most of BIOSes does not declare beeper pin. 2666 Change beeper pin node type to beeper to help parser. */ 2667 *waspin = 0; 2668 switch (id) { 2669 case HDA_CODEC_AD1882: 2670 case HDA_CODEC_AD1883: 2671 case HDA_CODEC_AD1984: 2672 case HDA_CODEC_AD1984A: 2673 case HDA_CODEC_AD1984B: 2674 case HDA_CODEC_AD1987: 2675 case HDA_CODEC_AD1988: 2676 case HDA_CODEC_AD1988B: 2677 case HDA_CODEC_AD1989B: 2678 beeper = 26; 2679 break; 2680 case HDA_CODEC_ALC260: 2681 beeper = 23; 2682 break; 2683 case HDA_CODEC_ALC262: 2684 case HDA_CODEC_ALC268: 2685 case HDA_CODEC_ALC880: 2686 case HDA_CODEC_ALC882: 2687 case HDA_CODEC_ALC883: 2688 case HDA_CODEC_ALC885: 2689 case HDA_CODEC_ALC888: 2690 case HDA_CODEC_ALC889: 2691 beeper = 29; 2692 break; 2693 } 2694 if (nid == beeper) { 2695 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2696 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2697 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2698 *waspin = 1; 2699 } 2700 2701 HDA_BOOTVERBOSE( 2702 if (caps != orig) { 2703 device_printf(sc->dev, 2704 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2705 nid, orig, caps); 2706 } 2707 ); 2708 2709 return (caps); 2710 } 2711 2712 static void 2713 hdac_widget_parse(struct hdac_widget *w) 2714 { 2715 struct hdac_softc *sc = w->devinfo->codec->sc; 2716 uint32_t wcap, cap; 2717 char *typestr; 2718 nid_t cad = w->devinfo->codec->cad; 2719 nid_t nid = w->nid; 2720 2721 wcap = hdac_widget_getcaps(w, &w->waspin); 2722 2723 w->param.widget_cap = wcap; 2724 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2725 2726 switch (w->type) { 2727 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2728 typestr = "audio output"; 2729 break; 2730 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2731 typestr = "audio input"; 2732 break; 2733 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2734 typestr = "audio mixer"; 2735 break; 2736 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2737 typestr = "audio selector"; 2738 break; 2739 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2740 typestr = "pin"; 2741 break; 2742 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2743 typestr = "power widget"; 2744 break; 2745 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2746 typestr = "volume widget"; 2747 break; 2748 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2749 typestr = "beep widget"; 2750 break; 2751 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2752 typestr = "vendor widget"; 2753 break; 2754 default: 2755 typestr = "unknown type"; 2756 break; 2757 } 2758 2759 strlcpy(w->name, typestr, sizeof(w->name)); 2760 2761 hdac_widget_connection_parse(w); 2762 2763 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2764 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2765 w->param.outamp_cap = 2766 hdac_command(sc, 2767 HDA_CMD_GET_PARAMETER(cad, nid, 2768 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2769 else 2770 w->param.outamp_cap = 2771 w->devinfo->function.audio.outamp_cap; 2772 } else 2773 w->param.outamp_cap = 0; 2774 2775 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2776 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2777 w->param.inamp_cap = 2778 hdac_command(sc, 2779 HDA_CMD_GET_PARAMETER(cad, nid, 2780 HDA_PARAM_INPUT_AMP_CAP), cad); 2781 else 2782 w->param.inamp_cap = 2783 w->devinfo->function.audio.inamp_cap; 2784 } else 2785 w->param.inamp_cap = 0; 2786 2787 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2788 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2789 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2790 cap = hdac_command(sc, 2791 HDA_CMD_GET_PARAMETER(cad, nid, 2792 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2793 w->param.supp_stream_formats = (cap != 0) ? cap : 2794 w->devinfo->function.audio.supp_stream_formats; 2795 cap = hdac_command(sc, 2796 HDA_CMD_GET_PARAMETER(cad, nid, 2797 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2798 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2799 w->devinfo->function.audio.supp_pcm_size_rate; 2800 } else { 2801 w->param.supp_stream_formats = 2802 w->devinfo->function.audio.supp_stream_formats; 2803 w->param.supp_pcm_size_rate = 2804 w->devinfo->function.audio.supp_pcm_size_rate; 2805 } 2806 } else { 2807 w->param.supp_stream_formats = 0; 2808 w->param.supp_pcm_size_rate = 0; 2809 } 2810 2811 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2812 hdac_widget_pin_parse(w); 2813 } 2814 2815 static struct hdac_widget * 2816 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2817 { 2818 if (devinfo == NULL || devinfo->widget == NULL || 2819 nid < devinfo->startnode || nid >= devinfo->endnode) 2820 return (NULL); 2821 return (&devinfo->widget[nid - devinfo->startnode]); 2822 } 2823 2824 static __inline int 2825 hda_poll_channel(struct hdac_chan *ch) 2826 { 2827 uint32_t sz, delta; 2828 volatile uint32_t ptr; 2829 2830 if (!(ch->flags & HDAC_CHN_RUNNING)) 2831 return (0); 2832 2833 sz = ch->blksz * ch->blkcnt; 2834 if (ch->dmapos != NULL) 2835 ptr = *(ch->dmapos); 2836 else 2837 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2838 ch->off + HDAC_SDLPIB); 2839 ch->ptr = ptr; 2840 ptr %= sz; 2841 ptr &= ~(ch->blksz - 1); 2842 delta = (sz + ptr - ch->prevptr) % sz; 2843 2844 if (delta < ch->blksz) 2845 return (0); 2846 2847 ch->prevptr = ptr; 2848 2849 return (1); 2850 } 2851 2852 static void 2853 hda_poll_callback(void *arg) 2854 { 2855 struct hdac_softc *sc = arg; 2856 uint32_t trigger; 2857 int i, active = 0; 2858 2859 if (sc == NULL) 2860 return; 2861 2862 hdac_lock(sc); 2863 if (sc->polling == 0) { 2864 hdac_unlock(sc); 2865 return; 2866 } 2867 2868 trigger = 0; 2869 for (i = 0; i < sc->num_chans; i++) { 2870 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2871 continue; 2872 active = 1; 2873 if (hda_poll_channel(&sc->chans[i])) 2874 trigger |= (1 << i); 2875 } 2876 2877 /* XXX */ 2878 if (active) 2879 callout_reset(&sc->poll_hda, sc->poll_ticks, 2880 hda_poll_callback, sc); 2881 2882 hdac_unlock(sc); 2883 2884 for (i = 0; i < sc->num_chans; i++) { 2885 if (trigger & (1 << i)) 2886 chn_intr(sc->chans[i].c); 2887 } 2888 } 2889 2890 static int 2891 hdac_rirb_flush(struct hdac_softc *sc) 2892 { 2893 struct hdac_rirb *rirb_base, *rirb; 2894 struct hdac_codec *codec; 2895 struct hdac_command_list *commands; 2896 nid_t cad; 2897 uint32_t resp; 2898 uint8_t rirbwp; 2899 int ret; 2900 2901 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2902 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2903 #if 0 2904 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2905 BUS_DMASYNC_POSTREAD); 2906 #endif 2907 2908 ret = 0; 2909 2910 while (sc->rirb_rp != rirbwp) { 2911 sc->rirb_rp++; 2912 sc->rirb_rp %= sc->rirb_size; 2913 rirb = &rirb_base[sc->rirb_rp]; 2914 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2915 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2916 sc->codecs[cad] == NULL) 2917 continue; 2918 resp = rirb->response; 2919 codec = sc->codecs[cad]; 2920 commands = codec->commands; 2921 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2922 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2923 ((resp >> 26) & 0xffff); 2924 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2925 } else if (commands != NULL && commands->num_commands > 0 && 2926 codec->responses_received < commands->num_commands) 2927 commands->responses[codec->responses_received++] = 2928 resp; 2929 ret++; 2930 } 2931 2932 return (ret); 2933 } 2934 2935 static int 2936 hdac_unsolq_flush(struct hdac_softc *sc) 2937 { 2938 nid_t cad; 2939 uint32_t tag; 2940 int ret = 0; 2941 2942 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2943 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2944 while (sc->unsolq_rp != sc->unsolq_wp) { 2945 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2946 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2947 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2948 hdac_unsolicited_handler(sc->codecs[cad], tag); 2949 ret++; 2950 } 2951 sc->unsolq_st = HDAC_UNSOLQ_READY; 2952 } 2953 2954 return (ret); 2955 } 2956 2957 static void 2958 hdac_poll_callback(void *arg) 2959 { 2960 struct hdac_softc *sc = arg; 2961 if (sc == NULL) 2962 return; 2963 2964 hdac_lock(sc); 2965 if (sc->polling == 0 || sc->poll_ival == 0) { 2966 hdac_unlock(sc); 2967 return; 2968 } 2969 if (hdac_rirb_flush(sc) != 0) 2970 hdac_unsolq_flush(sc); 2971 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2972 hdac_unlock(sc); 2973 } 2974 2975 static void 2976 hdac_poll_reinit(struct hdac_softc *sc) 2977 { 2978 int i, pollticks, min = 1000000; 2979 struct hdac_chan *ch; 2980 2981 for (i = 0; i < sc->num_chans; i++) { 2982 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2983 continue; 2984 ch = &sc->chans[i]; 2985 pollticks = ((uint64_t)hz * ch->blksz) / 2986 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2987 pollticks >>= 1; 2988 if (pollticks > hz) 2989 pollticks = hz; 2990 if (pollticks < 1) { 2991 HDA_BOOTVERBOSE( 2992 device_printf(sc->dev, 2993 "%s: pollticks=%d < 1 !\n", 2994 __func__, pollticks); 2995 ); 2996 pollticks = 1; 2997 } 2998 if (min > pollticks) 2999 min = pollticks; 3000 } 3001 HDA_BOOTVERBOSE( 3002 device_printf(sc->dev, 3003 "%s: pollticks %d -> %d\n", 3004 __func__, sc->poll_ticks, min); 3005 ); 3006 sc->poll_ticks = min; 3007 if (min == 1000000) 3008 callout_stop(&sc->poll_hda); 3009 else 3010 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 3011 } 3012 3013 static void 3014 hdac_stream_stop(struct hdac_chan *ch) 3015 { 3016 struct hdac_softc *sc = ch->devinfo->codec->sc; 3017 uint32_t ctl; 3018 3019 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3020 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3021 HDAC_SDCTL_RUN); 3022 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3023 3024 ch->flags &= ~HDAC_CHN_RUNNING; 3025 3026 if (sc->polling != 0) 3027 hdac_poll_reinit(sc); 3028 3029 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3030 ctl &= ~(1 << (ch->off >> 5)); 3031 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3032 } 3033 3034 static void 3035 hdac_stream_start(struct hdac_chan *ch) 3036 { 3037 struct hdac_softc *sc = ch->devinfo->codec->sc; 3038 uint32_t ctl; 3039 3040 ch->flags |= HDAC_CHN_RUNNING; 3041 3042 if (sc->polling != 0) 3043 hdac_poll_reinit(sc); 3044 3045 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3046 ctl |= 1 << (ch->off >> 5); 3047 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3048 3049 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3050 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3051 HDAC_SDCTL_RUN; 3052 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3053 } 3054 3055 static void 3056 hdac_stream_reset(struct hdac_chan *ch) 3057 { 3058 struct hdac_softc *sc = ch->devinfo->codec->sc; 3059 int timeout = 1000; 3060 int to = timeout; 3061 uint32_t ctl; 3062 3063 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3064 ctl |= HDAC_SDCTL_SRST; 3065 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3066 do { 3067 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3068 if (ctl & HDAC_SDCTL_SRST) 3069 break; 3070 DELAY(10); 3071 } while (--to); 3072 if (!(ctl & HDAC_SDCTL_SRST)) { 3073 device_printf(sc->dev, "timeout in reset\n"); 3074 } 3075 ctl &= ~HDAC_SDCTL_SRST; 3076 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3077 to = timeout; 3078 do { 3079 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3080 if (!(ctl & HDAC_SDCTL_SRST)) 3081 break; 3082 DELAY(10); 3083 } while (--to); 3084 if (ctl & HDAC_SDCTL_SRST) 3085 device_printf(sc->dev, "can't reset!\n"); 3086 } 3087 3088 static void 3089 hdac_stream_setid(struct hdac_chan *ch) 3090 { 3091 struct hdac_softc *sc = ch->devinfo->codec->sc; 3092 uint32_t ctl; 3093 3094 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3095 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3096 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3097 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3098 } 3099 3100 static void 3101 hdac_bdl_setup(struct hdac_chan *ch) 3102 { 3103 struct hdac_softc *sc = ch->devinfo->codec->sc; 3104 struct hdac_bdle *bdle; 3105 uint64_t addr; 3106 uint32_t blksz, blkcnt; 3107 int i; 3108 3109 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3110 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3111 3112 blksz = ch->blksz; 3113 blkcnt = ch->blkcnt; 3114 3115 for (i = 0; i < blkcnt; i++, bdle++) { 3116 bdle->addrl = (uint32_t)addr; 3117 bdle->addrh = (uint32_t)(addr >> 32); 3118 bdle->len = blksz; 3119 bdle->ioc = 1; 3120 addr += blksz; 3121 } 3122 3123 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3124 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3125 addr = ch->bdl_dma.dma_paddr; 3126 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3127 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3128 if (ch->dmapos != NULL && 3129 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3130 addr = sc->pos_dma.dma_paddr; 3131 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3132 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3133 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3134 } 3135 } 3136 3137 static int 3138 hdac_bdl_alloc(struct hdac_chan *ch) 3139 { 3140 struct hdac_softc *sc = ch->devinfo->codec->sc; 3141 int rc; 3142 3143 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3144 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3145 if (rc) { 3146 device_printf(sc->dev, "can't alloc bdl\n"); 3147 return (rc); 3148 } 3149 3150 return (0); 3151 } 3152 3153 static void 3154 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3155 int index, int lmute, int rmute, 3156 int left, int right, int dir) 3157 { 3158 uint16_t v = 0; 3159 3160 if (sc == NULL) 3161 return; 3162 3163 if (left != right || lmute != rmute) { 3164 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3165 (lmute << 7) | left; 3166 hdac_command(sc, 3167 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3168 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3169 (rmute << 7) | right; 3170 } else 3171 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3172 (lmute << 7) | left; 3173 3174 hdac_command(sc, 3175 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3176 } 3177 3178 static void 3179 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3180 int left, int right) 3181 { 3182 struct hdac_softc *sc; 3183 nid_t nid, cad; 3184 int lmute, rmute; 3185 3186 sc = ctl->widget->devinfo->codec->sc; 3187 cad = ctl->widget->devinfo->codec->cad; 3188 nid = ctl->widget->nid; 3189 3190 /* Save new values if valid. */ 3191 if (mute != HDA_AMP_MUTE_DEFAULT) 3192 ctl->muted = mute; 3193 if (left != HDA_AMP_VOL_DEFAULT) 3194 ctl->left = left; 3195 if (right != HDA_AMP_VOL_DEFAULT) 3196 ctl->right = right; 3197 /* Prepare effective values */ 3198 if (ctl->forcemute) { 3199 lmute = 1; 3200 rmute = 1; 3201 left = 0; 3202 right = 0; 3203 } else { 3204 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3205 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3206 left = ctl->left; 3207 right = ctl->right; 3208 } 3209 /* Apply effective values */ 3210 if (ctl->dir & HDA_CTL_OUT) 3211 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3212 lmute, rmute, left, right, 0); 3213 if (ctl->dir & HDA_CTL_IN) 3214 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3215 lmute, rmute, left, right, 1); 3216 } 3217 3218 static void 3219 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3220 { 3221 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3222 return; 3223 hdac_command(w->devinfo->codec->sc, 3224 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3225 w->nid, index), w->devinfo->codec->cad); 3226 w->selconn = index; 3227 } 3228 3229 3230 /**************************************************************************** 3231 * uint32_t hdac_command_sendone_internal 3232 * 3233 * Wrapper function that sends only one command to a given codec 3234 ****************************************************************************/ 3235 static uint32_t 3236 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3237 { 3238 struct hdac_command_list cl; 3239 uint32_t response = HDAC_INVALID; 3240 3241 if (!hdac_lockowned(sc)) 3242 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3243 cl.num_commands = 1; 3244 cl.verbs = &verb; 3245 cl.responses = &response; 3246 3247 hdac_command_send_internal(sc, &cl, cad); 3248 3249 return (response); 3250 } 3251 3252 /**************************************************************************** 3253 * hdac_command_send_internal 3254 * 3255 * Send a command list to the codec via the corb. We queue as much verbs as 3256 * we can and msleep on the codec. When the interrupt get the responses 3257 * back from the rirb, it will wake us up so we can queue the remaining verbs 3258 * if any. 3259 ****************************************************************************/ 3260 static void 3261 hdac_command_send_internal(struct hdac_softc *sc, 3262 struct hdac_command_list *commands, nid_t cad) 3263 { 3264 struct hdac_codec *codec; 3265 int corbrp; 3266 uint32_t *corb; 3267 int timeout; 3268 int retry = 10; 3269 struct hdac_rirb *rirb_base; 3270 3271 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3272 commands->num_commands < 1) 3273 return; 3274 3275 codec = sc->codecs[cad]; 3276 codec->commands = commands; 3277 codec->responses_received = 0; 3278 codec->verbs_sent = 0; 3279 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3280 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3281 3282 do { 3283 if (codec->verbs_sent != commands->num_commands) { 3284 /* Queue as many verbs as possible */ 3285 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3286 #if 0 3287 bus_dmamap_sync(sc->corb_dma.dma_tag, 3288 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3289 #endif 3290 while (codec->verbs_sent != commands->num_commands && 3291 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3292 sc->corb_wp++; 3293 sc->corb_wp %= sc->corb_size; 3294 corb[sc->corb_wp] = 3295 commands->verbs[codec->verbs_sent++]; 3296 } 3297 3298 /* Send the verbs to the codecs */ 3299 #if 0 3300 bus_dmamap_sync(sc->corb_dma.dma_tag, 3301 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3302 #endif 3303 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3304 } 3305 3306 timeout = 1000; 3307 while (hdac_rirb_flush(sc) == 0 && --timeout) 3308 DELAY(10); 3309 } while ((codec->verbs_sent != commands->num_commands || 3310 codec->responses_received != commands->num_commands) && --retry); 3311 3312 if (retry == 0) 3313 device_printf(sc->dev, 3314 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3315 __func__, commands->num_commands, codec->verbs_sent, 3316 codec->responses_received); 3317 3318 codec->commands = NULL; 3319 codec->responses_received = 0; 3320 codec->verbs_sent = 0; 3321 3322 hdac_unsolq_flush(sc); 3323 } 3324 3325 3326 /**************************************************************************** 3327 * Device Methods 3328 ****************************************************************************/ 3329 3330 /**************************************************************************** 3331 * int hdac_probe(device_t) 3332 * 3333 * Probe for the presence of an hdac. If none is found, check for a generic 3334 * match using the subclass of the device. 3335 ****************************************************************************/ 3336 static int 3337 hdac_probe(device_t dev) 3338 { 3339 int i, result; 3340 uint32_t model; 3341 uint16_t class, subclass; 3342 char desc[64]; 3343 3344 model = (uint32_t)pci_get_device(dev) << 16; 3345 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3346 class = pci_get_class(dev); 3347 subclass = pci_get_subclass(dev); 3348 3349 bzero(desc, sizeof(desc)); 3350 result = ENXIO; 3351 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3352 if (hdac_devices[i].model == model) { 3353 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3354 result = BUS_PROBE_DEFAULT; 3355 break; 3356 } 3357 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3358 class == PCIC_MULTIMEDIA && 3359 subclass == PCIS_MULTIMEDIA_HDA) { 3360 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3361 result = BUS_PROBE_GENERIC; 3362 break; 3363 } 3364 } 3365 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3366 subclass == PCIS_MULTIMEDIA_HDA) { 3367 strlcpy(desc, "Generic", sizeof(desc)); 3368 result = BUS_PROBE_GENERIC; 3369 } 3370 if (result != ENXIO) { 3371 strlcat(desc, " High Definition Audio Controller", 3372 sizeof(desc)); 3373 device_set_desc_copy(dev, desc); 3374 } 3375 3376 return (result); 3377 } 3378 3379 static void * 3380 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3381 struct pcm_channel *c, int dir) 3382 { 3383 struct hdac_pcm_devinfo *pdevinfo = data; 3384 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3385 struct hdac_softc *sc = devinfo->codec->sc; 3386 struct hdac_chan *ch; 3387 int i, ord = 0, chid; 3388 3389 hdac_lock(sc); 3390 3391 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3392 ch = &sc->chans[chid]; 3393 for (i = 0; i < sc->num_chans && i < chid; i++) { 3394 if (ch->dir == sc->chans[i].dir) 3395 ord++; 3396 } 3397 if (dir == PCMDIR_PLAY) { 3398 ch->off = (sc->num_iss + ord) << 5; 3399 } else { 3400 ch->off = ord << 5; 3401 } 3402 3403 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3404 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3405 ch->pcmrates[0] = 48000; 3406 ch->pcmrates[1] = 0; 3407 } 3408 if (sc->pos_dma.dma_vaddr != NULL) 3409 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3410 (sc->streamcnt * 8)); 3411 else 3412 ch->dmapos = NULL; 3413 ch->sid = ++sc->streamcnt; 3414 ch->dir = dir; 3415 ch->b = b; 3416 ch->c = c; 3417 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3418 ch->blkcnt = pdevinfo->chan_blkcnt; 3419 hdac_unlock(sc); 3420 3421 if (hdac_bdl_alloc(ch) != 0) { 3422 ch->blkcnt = 0; 3423 return (NULL); 3424 } 3425 3426 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3427 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3428 pdevinfo->chan_size) != 0) 3429 return (NULL); 3430 3431 return (ch); 3432 } 3433 3434 static int 3435 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3436 { 3437 struct hdac_chan *ch = data; 3438 int i; 3439 3440 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3441 if (format == ch->caps.fmtlist[i]) { 3442 ch->fmt = format; 3443 return (0); 3444 } 3445 } 3446 3447 return (EINVAL); 3448 } 3449 3450 static uint32_t 3451 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3452 { 3453 struct hdac_chan *ch = data; 3454 uint32_t spd = 0, threshold; 3455 int i; 3456 3457 for (i = 0; ch->pcmrates[i] != 0; i++) { 3458 spd = ch->pcmrates[i]; 3459 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3460 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3461 if (speed < threshold) 3462 break; 3463 } 3464 3465 if (spd == 0) /* impossible */ 3466 ch->spd = 48000; 3467 else 3468 ch->spd = spd; 3469 3470 return (ch->spd); 3471 } 3472 3473 static void 3474 hdac_stream_setup(struct hdac_chan *ch) 3475 { 3476 struct hdac_softc *sc = ch->devinfo->codec->sc; 3477 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3478 struct hdac_widget *w; 3479 int i, chn, totalchn, c; 3480 nid_t cad = ch->devinfo->codec->cad; 3481 uint16_t fmt, dfmt; 3482 uint16_t chmap[2][5] = {{ 0x0010, 0x0001, 0x0201, 0x0231, 0x0231 }, /* 5.1 */ 3483 { 0x0010, 0x0001, 0x2001, 0x2031, 0x2431 }};/* 7.1 */ 3484 int map = -1; 3485 3486 totalchn = AFMT_CHANNEL(ch->fmt); 3487 HDA_BOOTHVERBOSE( 3488 device_printf(ch->pdevinfo->dev, 3489 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3490 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3491 ch->fmt, ch->spd); 3492 ); 3493 fmt = 0; 3494 if (ch->fmt & AFMT_S16_LE) 3495 fmt |= ch->bit16 << 4; 3496 else if (ch->fmt & AFMT_S32_LE) 3497 fmt |= ch->bit32 << 4; 3498 else 3499 fmt |= 1 << 4; 3500 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3501 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3502 fmt |= hda_rate_tab[i].base; 3503 fmt |= hda_rate_tab[i].mul; 3504 fmt |= hda_rate_tab[i].div; 3505 break; 3506 } 3507 } 3508 fmt |= (totalchn - 1); 3509 3510 /* Set channel mapping for known speaker setups. */ 3511 if (as->pinset == 0x0007 || as->pinset == 0x0013) /* Standard 5.1 */ 3512 map = 0; 3513 else if (as->pinset == 0x0017) /* Standard 7.1 */ 3514 map = 1; 3515 3516 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3517 3518 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3519 if (ch->fmt & AFMT_AC3) 3520 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3521 3522 chn = 0; 3523 for (i = 0; ch->io[i] != -1; i++) { 3524 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3525 if (w == NULL) 3526 continue; 3527 3528 /* If HP redirection is enabled, but failed to use same 3529 DAC, make last DAC to duplicate first one. */ 3530 if (as->fakeredir && i == (as->pincnt - 1)) { 3531 c = (ch->sid << 4); 3532 } else { 3533 if (map >= 0) /* Map known speaker setups. */ 3534 chn = (((chmap[map][totalchn / 2] >> i * 4) & 3535 0xf) - 1) * 2; 3536 if (chn < 0 || chn >= totalchn) { 3537 c = 0; 3538 } else { 3539 c = (ch->sid << 4) | chn; 3540 } 3541 } 3542 HDA_BOOTHVERBOSE( 3543 device_printf(ch->pdevinfo->dev, 3544 "PCMDIR_%s: Stream setup nid=%d: " 3545 "fmt=0x%04x, dfmt=0x%04x, chan=0x%04x\n", 3546 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3547 ch->io[i], fmt, dfmt, c); 3548 ); 3549 hdac_command(sc, 3550 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3551 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3552 hdac_command(sc, 3553 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3554 cad); 3555 } 3556 hdac_command(sc, 3557 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3558 #if 0 3559 hdac_command(sc, 3560 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3561 hdac_command(sc, 3562 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3563 hdac_command(sc, 3564 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3565 #endif 3566 chn += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 3567 } 3568 } 3569 3570 /* 3571 * Greatest Common Divisor. 3572 */ 3573 static unsigned 3574 gcd(unsigned a, unsigned b) 3575 { 3576 u_int c; 3577 3578 while (b != 0) { 3579 c = a; 3580 a = b; 3581 b = (c % b); 3582 } 3583 return (a); 3584 } 3585 3586 /* 3587 * Least Common Multiple. 3588 */ 3589 static unsigned 3590 lcm(unsigned a, unsigned b) 3591 { 3592 3593 return ((a * b) / gcd(a, b)); 3594 } 3595 3596 static int 3597 hdac_channel_setfragments(kobj_t obj, void *data, 3598 uint32_t blksz, uint32_t blkcnt) 3599 { 3600 struct hdac_chan *ch = data; 3601 struct hdac_softc *sc = ch->devinfo->codec->sc; 3602 3603 blksz -= blksz % lcm(HDAC_DMA_ALIGNMENT, sndbuf_getalign(ch->b)); 3604 3605 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3606 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3607 if (blksz < HDA_BLK_MIN) 3608 blksz = HDA_BLK_MIN; 3609 if (blkcnt > HDA_BDL_MAX) 3610 blkcnt = HDA_BDL_MAX; 3611 if (blkcnt < HDA_BDL_MIN) 3612 blkcnt = HDA_BDL_MIN; 3613 3614 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3615 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3616 blkcnt >>= 1; 3617 else if ((blksz >> 1) >= HDA_BLK_MIN) 3618 blksz >>= 1; 3619 else 3620 break; 3621 } 3622 3623 if ((sndbuf_getblksz(ch->b) != blksz || 3624 sndbuf_getblkcnt(ch->b) != blkcnt) && 3625 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3626 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3627 __func__, blksz, blkcnt); 3628 3629 ch->blksz = sndbuf_getblksz(ch->b); 3630 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3631 3632 return (0); 3633 } 3634 3635 static uint32_t 3636 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3637 { 3638 struct hdac_chan *ch = data; 3639 3640 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3641 3642 return (ch->blksz); 3643 } 3644 3645 static void 3646 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3647 { 3648 struct hdac_devinfo *devinfo = ch->devinfo; 3649 struct hdac_widget *w; 3650 nid_t cad = devinfo->codec->cad; 3651 int i; 3652 3653 hdac_stream_stop(ch); 3654 3655 for (i = 0; ch->io[i] != -1; i++) { 3656 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3657 if (w == NULL) 3658 continue; 3659 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3660 hdac_command(sc, 3661 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3662 cad); 3663 } 3664 hdac_command(sc, 3665 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3666 0), cad); 3667 } 3668 } 3669 3670 static void 3671 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3672 { 3673 ch->ptr = 0; 3674 ch->prevptr = 0; 3675 hdac_stream_stop(ch); 3676 hdac_stream_reset(ch); 3677 hdac_bdl_setup(ch); 3678 hdac_stream_setid(ch); 3679 hdac_stream_setup(ch); 3680 hdac_stream_start(ch); 3681 } 3682 3683 static int 3684 hdac_channel_trigger(kobj_t obj, void *data, int go) 3685 { 3686 struct hdac_chan *ch = data; 3687 struct hdac_softc *sc = ch->devinfo->codec->sc; 3688 3689 if (!PCMTRIG_COMMON(go)) 3690 return (0); 3691 3692 hdac_lock(sc); 3693 switch (go) { 3694 case PCMTRIG_START: 3695 hdac_channel_start(sc, ch); 3696 break; 3697 case PCMTRIG_STOP: 3698 case PCMTRIG_ABORT: 3699 hdac_channel_stop(sc, ch); 3700 break; 3701 default: 3702 break; 3703 } 3704 hdac_unlock(sc); 3705 3706 return (0); 3707 } 3708 3709 static uint32_t 3710 hdac_channel_getptr(kobj_t obj, void *data) 3711 { 3712 struct hdac_chan *ch = data; 3713 struct hdac_softc *sc = ch->devinfo->codec->sc; 3714 uint32_t ptr; 3715 3716 hdac_lock(sc); 3717 if (sc->polling != 0) 3718 ptr = ch->ptr; 3719 else if (ch->dmapos != NULL) 3720 ptr = *(ch->dmapos); 3721 else 3722 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3723 hdac_unlock(sc); 3724 3725 /* 3726 * Round to available space and force 128 bytes aligment. 3727 */ 3728 ptr %= ch->blksz * ch->blkcnt; 3729 ptr &= HDA_BLK_ALIGN; 3730 3731 return (ptr); 3732 } 3733 3734 static struct pcmchan_caps * 3735 hdac_channel_getcaps(kobj_t obj, void *data) 3736 { 3737 return (&((struct hdac_chan *)data)->caps); 3738 } 3739 3740 static kobj_method_t hdac_channel_methods[] = { 3741 KOBJMETHOD(channel_init, hdac_channel_init), 3742 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3743 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3744 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3745 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3746 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3747 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3748 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3749 KOBJMETHOD_END 3750 }; 3751 CHANNEL_DECLARE(hdac_channel); 3752 3753 static int 3754 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3755 { 3756 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3757 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3758 struct hdac_softc *sc = devinfo->codec->sc; 3759 struct hdac_widget *w, *cw; 3760 struct hdac_audio_ctl *ctl; 3761 uint32_t mask, recmask, id; 3762 int i, j, softpcmvol; 3763 3764 hdac_lock(sc); 3765 3766 /* Make sure that in case of soft volume it won't stay muted. */ 3767 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3768 pdevinfo->left[i] = 100; 3769 pdevinfo->right[i] = 100; 3770 } 3771 3772 mask = 0; 3773 recmask = 0; 3774 id = hdac_codec_id(devinfo->codec); 3775 3776 /* Declate EAPD as ogain control. */ 3777 if (pdevinfo->play >= 0) { 3778 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3779 w = hdac_widget_get(devinfo, i); 3780 if (w == NULL || w->enable == 0) 3781 continue; 3782 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3783 w->param.eapdbtl == HDAC_INVALID || 3784 w->bindas != sc->chans[pdevinfo->play].as) 3785 continue; 3786 mask |= SOUND_MASK_OGAIN; 3787 break; 3788 } 3789 } 3790 3791 /* Declare volume controls assigned to this association. */ 3792 i = 0; 3793 ctl = NULL; 3794 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3795 if (ctl->enable == 0) 3796 continue; 3797 if ((pdevinfo->play >= 0 && 3798 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3799 (pdevinfo->rec >= 0 && 3800 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3801 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3802 mask |= ctl->ossmask; 3803 } 3804 3805 /* Declare record sources available to this association. */ 3806 if (pdevinfo->rec >= 0) { 3807 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3808 for (i = 0; ch->io[i] != -1; i++) { 3809 w = hdac_widget_get(devinfo, ch->io[i]); 3810 if (w == NULL || w->enable == 0) 3811 continue; 3812 for (j = 0; j < w->nconns; j++) { 3813 if (w->connsenable[j] == 0) 3814 continue; 3815 cw = hdac_widget_get(devinfo, w->conns[j]); 3816 if (cw == NULL || cw->enable == 0) 3817 continue; 3818 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3819 cw->bindas != -2) 3820 continue; 3821 recmask |= cw->ossmask; 3822 } 3823 } 3824 } 3825 3826 /* Declare soft PCM volume if needed. */ 3827 if (pdevinfo->play >= 0) { 3828 ctl = NULL; 3829 if ((mask & SOUND_MASK_PCM) == 0 || 3830 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3831 softpcmvol = 1; 3832 mask |= SOUND_MASK_PCM; 3833 } else { 3834 softpcmvol = 0; 3835 i = 0; 3836 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3837 if (ctl->enable == 0) 3838 continue; 3839 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3840 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3841 continue; 3842 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3843 continue; 3844 if (ctl->step > 0) 3845 break; 3846 } 3847 } 3848 3849 if (softpcmvol == 1 || ctl == NULL) { 3850 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3851 HDA_BOOTVERBOSE( 3852 device_printf(pdevinfo->dev, 3853 "%s Soft PCM volume\n", 3854 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3855 ); 3856 } 3857 } 3858 3859 /* Declare master volume if needed. */ 3860 if (pdevinfo->play >= 0) { 3861 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3862 SOUND_MASK_PCM) { 3863 mask |= SOUND_MASK_VOLUME; 3864 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3865 SOUND_MASK_PCM); 3866 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3867 SOUND_MIXER_NONE); 3868 HDA_BOOTVERBOSE( 3869 device_printf(pdevinfo->dev, 3870 "Forcing master volume with PCM\n"); 3871 ); 3872 } 3873 } 3874 3875 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3876 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3877 3878 mix_setrecdevs(m, recmask); 3879 mix_setdevs(m, mask); 3880 3881 hdac_unlock(sc); 3882 3883 return (0); 3884 } 3885 3886 static int 3887 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3888 unsigned left, unsigned right) 3889 { 3890 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3891 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3892 struct hdac_softc *sc = devinfo->codec->sc; 3893 struct hdac_widget *w; 3894 struct hdac_audio_ctl *ctl; 3895 uint32_t mute; 3896 int lvol, rvol; 3897 int i, j; 3898 3899 hdac_lock(sc); 3900 /* Save new values. */ 3901 pdevinfo->left[dev] = left; 3902 pdevinfo->right[dev] = right; 3903 3904 /* 'ogain' is the special case implemented with EAPD. */ 3905 if (dev == SOUND_MIXER_OGAIN) { 3906 uint32_t orig; 3907 w = NULL; 3908 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3909 w = hdac_widget_get(devinfo, i); 3910 if (w == NULL || w->enable == 0) 3911 continue; 3912 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3913 w->param.eapdbtl == HDAC_INVALID) 3914 continue; 3915 break; 3916 } 3917 if (i >= devinfo->endnode) { 3918 hdac_unlock(sc); 3919 return (-1); 3920 } 3921 orig = w->param.eapdbtl; 3922 if (left == 0) 3923 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3924 else 3925 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3926 if (orig != w->param.eapdbtl) { 3927 uint32_t val; 3928 3929 val = w->param.eapdbtl; 3930 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3931 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3932 hdac_command(sc, 3933 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3934 w->nid, val), devinfo->codec->cad); 3935 } 3936 hdac_unlock(sc); 3937 return (left | (left << 8)); 3938 } 3939 3940 /* Recalculate all controls related to this OSS device. */ 3941 i = 0; 3942 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3943 if (ctl->enable == 0 || 3944 !(ctl->ossmask & (1 << dev))) 3945 continue; 3946 if (!((pdevinfo->play >= 0 && 3947 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3948 (pdevinfo->rec >= 0 && 3949 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3950 ctl->widget->bindas == -2)) 3951 continue; 3952 3953 lvol = 100; 3954 rvol = 100; 3955 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3956 if (ctl->ossmask & (1 << j)) { 3957 lvol = lvol * pdevinfo->left[j] / 100; 3958 rvol = rvol * pdevinfo->right[j] / 100; 3959 } 3960 } 3961 mute = (lvol == 0) ? HDA_AMP_MUTE_LEFT : 0; 3962 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3963 lvol = (lvol * ctl->step + 50) / 100; 3964 rvol = (rvol * ctl->step + 50) / 100; 3965 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3966 } 3967 hdac_unlock(sc); 3968 3969 return (left | (right << 8)); 3970 } 3971 3972 /* 3973 * Commutate specified record source. 3974 */ 3975 static uint32_t 3976 hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3977 { 3978 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3979 struct hdac_widget *w, *cw; 3980 struct hdac_audio_ctl *ctl; 3981 char buf[64]; 3982 int i, muted; 3983 uint32_t res = 0; 3984 3985 if (depth > HDA_PARSE_MAXDEPTH) 3986 return (0); 3987 3988 w = hdac_widget_get(devinfo, nid); 3989 if (w == NULL || w->enable == 0) 3990 return (0); 3991 3992 for (i = 0; i < w->nconns; i++) { 3993 if (w->connsenable[i] == 0) 3994 continue; 3995 cw = hdac_widget_get(devinfo, w->conns[i]); 3996 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3997 continue; 3998 /* Call recursively to trace signal to it's source if needed. */ 3999 if ((src & cw->ossmask) != 0) { 4000 if (cw->ossdev < 0) { 4001 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 4002 w->conns[i], depth + 1); 4003 } else { 4004 res |= cw->ossmask; 4005 } 4006 } 4007 /* We have two special cases: mixers and others (selectors). */ 4008 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4009 ctl = hdac_audio_ctl_amp_get(devinfo, 4010 w->nid, HDA_CTL_IN, i, 1); 4011 if (ctl == NULL) 4012 continue; 4013 /* If we have input control on this node mute them 4014 * according to requested sources. */ 4015 muted = (src & cw->ossmask) ? 0 : 1; 4016 if (muted != ctl->forcemute) { 4017 ctl->forcemute = muted; 4018 hdac_audio_ctl_amp_set(ctl, 4019 HDA_AMP_MUTE_DEFAULT, 4020 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 4021 } 4022 HDA_BOOTHVERBOSE( 4023 device_printf(pdevinfo->dev, 4024 "Recsel (%s): nid %d source %d %s\n", 4025 hdac_audio_ctl_ossmixer_mask2allname( 4026 src, buf, sizeof(buf)), 4027 nid, i, muted?"mute":"unmute"); 4028 ); 4029 } else { 4030 if (w->nconns == 1) 4031 break; 4032 if ((src & cw->ossmask) == 0) 4033 continue; 4034 /* If we found requested source - select it and exit. */ 4035 hdac_widget_connection_select(w, i); 4036 HDA_BOOTHVERBOSE( 4037 device_printf(pdevinfo->dev, 4038 "Recsel (%s): nid %d source %d select\n", 4039 hdac_audio_ctl_ossmixer_mask2allname( 4040 src, buf, sizeof(buf)), 4041 nid, i); 4042 ); 4043 break; 4044 } 4045 } 4046 return (res); 4047 } 4048 4049 static uint32_t 4050 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 4051 { 4052 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 4053 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 4054 struct hdac_widget *w; 4055 struct hdac_softc *sc = devinfo->codec->sc; 4056 struct hdac_chan *ch; 4057 int i; 4058 uint32_t ret = 0xffffffff; 4059 4060 hdac_lock(sc); 4061 4062 /* Commutate requested recsrc for each ADC. */ 4063 ch = &sc->chans[pdevinfo->rec]; 4064 for (i = 0; ch->io[i] != -1; i++) { 4065 w = hdac_widget_get(devinfo, ch->io[i]); 4066 if (w == NULL || w->enable == 0) 4067 continue; 4068 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 4069 } 4070 4071 hdac_unlock(sc); 4072 4073 return ((ret == 0xffffffff)? 0 : ret); 4074 } 4075 4076 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 4077 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 4078 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 4079 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 4080 KOBJMETHOD_END 4081 }; 4082 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 4083 4084 static void 4085 hdac_unsolq_task(void *context, int pending) 4086 { 4087 struct hdac_softc *sc; 4088 4089 sc = (struct hdac_softc *)context; 4090 4091 hdac_lock(sc); 4092 hdac_unsolq_flush(sc); 4093 hdac_unlock(sc); 4094 } 4095 4096 /**************************************************************************** 4097 * int hdac_attach(device_t) 4098 * 4099 * Attach the device into the kernel. Interrupts usually won't be enabled 4100 * when this function is called. Setup everything that doesn't require 4101 * interrupts and defer probing of codecs until interrupts are enabled. 4102 ****************************************************************************/ 4103 static int 4104 hdac_attach(device_t dev) 4105 { 4106 struct hdac_softc *sc; 4107 int result; 4108 int i, devid = -1; 4109 uint32_t model; 4110 uint16_t class, subclass; 4111 uint16_t vendor; 4112 uint8_t v; 4113 4114 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4115 4116 model = (uint32_t)pci_get_device(dev) << 16; 4117 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4118 class = pci_get_class(dev); 4119 subclass = pci_get_subclass(dev); 4120 4121 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4122 if (hdac_devices[i].model == model) { 4123 devid = i; 4124 break; 4125 } 4126 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4127 class == PCIC_MULTIMEDIA && 4128 subclass == PCIS_MULTIMEDIA_HDA) { 4129 devid = i; 4130 break; 4131 } 4132 } 4133 4134 sc = device_get_softc(dev); 4135 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4136 sc->dev = dev; 4137 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4138 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4139 vendor = pci_get_vendor(dev); 4140 4141 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4142 /* Screw nx6325 - subdevice/subvendor swapped */ 4143 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4144 } 4145 4146 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4147 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4148 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4149 4150 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4151 4152 sc->poll_ticks = 1000000; 4153 sc->poll_ival = HDAC_POLL_INTERVAL; 4154 if (resource_int_value(device_get_name(dev), 4155 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4156 sc->polling = 1; 4157 else 4158 sc->polling = 0; 4159 4160 sc->hdabus = NULL; 4161 for (i = 0; i < HDAC_CODEC_MAX; i++) 4162 sc->codecs[i] = NULL; 4163 4164 pci_enable_busmaster(dev); 4165 4166 if (vendor == INTEL_VENDORID) { 4167 /* TCSEL -> TC0 */ 4168 v = pci_read_config(dev, 0x44, 1); 4169 pci_write_config(dev, 0x44, v & 0xf8, 1); 4170 HDA_BOOTHVERBOSE( 4171 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4172 pci_read_config(dev, 0x44, 1)); 4173 ); 4174 } 4175 4176 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4177 sc->flags &= ~HDAC_F_MSI; 4178 else 4179 sc->flags |= HDAC_F_MSI; 4180 if (resource_int_value(device_get_name(dev), 4181 device_get_unit(dev), "msi", &i) == 0) { 4182 if (i == 0) 4183 sc->flags &= ~HDAC_F_MSI; 4184 else 4185 sc->flags |= HDAC_F_MSI; 4186 } 4187 4188 #if defined(__i386__) || defined(__amd64__) 4189 sc->flags |= HDAC_F_DMA_NOCACHE; 4190 4191 if (resource_int_value(device_get_name(dev), 4192 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4193 #else 4194 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4195 #endif 4196 /* 4197 * Try to enable PCIe snoop to avoid messing around with 4198 * uncacheable DMA attribute. Since PCIe snoop register 4199 * config is pretty much vendor specific, there are no 4200 * general solutions on how to enable it, forcing us (even 4201 * Microsoft) to enable uncacheable or write combined DMA 4202 * by default. 4203 * 4204 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4205 */ 4206 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4207 if (hdac_pcie_snoop[i].vendor != vendor) 4208 continue; 4209 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4210 if (hdac_pcie_snoop[i].reg == 0x00) 4211 break; 4212 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4213 if ((v & hdac_pcie_snoop[i].enable) == 4214 hdac_pcie_snoop[i].enable) 4215 break; 4216 v &= hdac_pcie_snoop[i].mask; 4217 v |= hdac_pcie_snoop[i].enable; 4218 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4219 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4220 if ((v & hdac_pcie_snoop[i].enable) != 4221 hdac_pcie_snoop[i].enable) { 4222 HDA_BOOTVERBOSE( 4223 device_printf(dev, 4224 "WARNING: Failed to enable PCIe " 4225 "snoop!\n"); 4226 ); 4227 #if defined(__i386__) || defined(__amd64__) 4228 sc->flags |= HDAC_F_DMA_NOCACHE; 4229 #endif 4230 } 4231 break; 4232 } 4233 #if defined(__i386__) || defined(__amd64__) 4234 } 4235 #endif 4236 4237 HDA_BOOTHVERBOSE( 4238 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4239 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4240 "Uncacheable" : "PCIe snoop", vendor); 4241 ); 4242 4243 /* Allocate resources */ 4244 result = hdac_mem_alloc(sc); 4245 if (result != 0) 4246 goto hdac_attach_fail; 4247 result = hdac_irq_alloc(sc); 4248 if (result != 0) 4249 goto hdac_attach_fail; 4250 4251 /* Get Capabilities */ 4252 result = hdac_get_capabilities(sc); 4253 if (result != 0) 4254 goto hdac_attach_fail; 4255 4256 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4257 sc->support_64bit = 0; 4258 4259 /* Allocate CORB and RIRB dma memory */ 4260 result = hdac_dma_alloc(sc, &sc->corb_dma, 4261 sc->corb_size * sizeof(uint32_t)); 4262 if (result != 0) 4263 goto hdac_attach_fail; 4264 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4265 sc->rirb_size * sizeof(struct hdac_rirb)); 4266 if (result != 0) 4267 goto hdac_attach_fail; 4268 4269 result = bus_dma_tag_create( 4270 bus_get_dma_tag(sc->dev), /* parent */ 4271 HDAC_DMA_ALIGNMENT, /* alignment */ 4272 0, /* boundary */ 4273 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4274 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4275 BUS_SPACE_MAXADDR, /* highaddr */ 4276 NULL, /* filtfunc */ 4277 NULL, /* fistfuncarg */ 4278 HDA_BUFSZ_MAX, /* maxsize */ 4279 1, /* nsegments */ 4280 HDA_BUFSZ_MAX, /* maxsegsz */ 4281 0, /* flags */ 4282 NULL, /* lockfunc */ 4283 NULL, /* lockfuncarg */ 4284 &sc->chan_dmat); /* dmat */ 4285 if (result != 0) { 4286 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4287 __func__, result); 4288 goto hdac_attach_fail; 4289 } 4290 4291 /* Quiesce everything */ 4292 HDA_BOOTHVERBOSE( 4293 device_printf(dev, "Reset controller...\n"); 4294 ); 4295 hdac_reset(sc, 1); 4296 4297 /* Initialize the CORB and RIRB */ 4298 hdac_corb_init(sc); 4299 hdac_rirb_init(sc); 4300 4301 /* Defer remaining of initialization until interrupts are enabled */ 4302 sc->intrhook.ich_func = hdac_attach2; 4303 sc->intrhook.ich_arg = (void *)sc; 4304 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4305 sc->intrhook.ich_func = NULL; 4306 hdac_attach2((void *)sc); 4307 } 4308 4309 return (0); 4310 4311 hdac_attach_fail: 4312 hdac_irq_free(sc); 4313 hdac_dma_free(sc, &sc->rirb_dma); 4314 hdac_dma_free(sc, &sc->corb_dma); 4315 hdac_mem_free(sc); 4316 snd_mtxfree(sc->lock); 4317 4318 return (ENXIO); 4319 } 4320 4321 static void 4322 hdac_audio_parse(struct hdac_devinfo *devinfo) 4323 { 4324 struct hdac_codec *codec = devinfo->codec; 4325 struct hdac_softc *sc = codec->sc; 4326 struct hdac_widget *w; 4327 uint32_t res; 4328 int i; 4329 nid_t cad, nid; 4330 4331 cad = devinfo->codec->cad; 4332 nid = devinfo->nid; 4333 4334 res = hdac_command(sc, 4335 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4336 devinfo->function.audio.gpio = res; 4337 4338 HDA_BOOTVERBOSE( 4339 device_printf(sc->dev, "GPIO: 0x%08x " 4340 "NumGPIO=%d NumGPO=%d " 4341 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4342 devinfo->function.audio.gpio, 4343 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4344 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4345 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4346 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4347 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4348 ); 4349 4350 res = hdac_command(sc, 4351 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4352 cad); 4353 devinfo->function.audio.supp_stream_formats = res; 4354 4355 res = hdac_command(sc, 4356 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4357 cad); 4358 devinfo->function.audio.supp_pcm_size_rate = res; 4359 4360 res = hdac_command(sc, 4361 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4362 cad); 4363 devinfo->function.audio.outamp_cap = res; 4364 4365 res = hdac_command(sc, 4366 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4367 cad); 4368 devinfo->function.audio.inamp_cap = res; 4369 4370 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4371 w = hdac_widget_get(devinfo, i); 4372 if (w == NULL) 4373 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4374 else { 4375 w->devinfo = devinfo; 4376 w->nid = i; 4377 w->enable = 1; 4378 w->selconn = -1; 4379 w->pflags = 0; 4380 w->ossdev = -1; 4381 w->bindas = -1; 4382 w->param.eapdbtl = HDAC_INVALID; 4383 hdac_widget_parse(w); 4384 } 4385 } 4386 } 4387 4388 static void 4389 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4390 { 4391 struct hdac_softc *sc = devinfo->codec->sc; 4392 struct hdac_audio_ctl *ctls; 4393 struct hdac_widget *w, *cw; 4394 int i, j, cnt, max, ocap, icap; 4395 int mute, offset, step, size; 4396 4397 /* XXX This is redundant */ 4398 max = 0; 4399 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4400 w = hdac_widget_get(devinfo, i); 4401 if (w == NULL || w->enable == 0) 4402 continue; 4403 if (w->param.outamp_cap != 0) 4404 max++; 4405 if (w->param.inamp_cap != 0) { 4406 switch (w->type) { 4407 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4408 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4409 for (j = 0; j < w->nconns; j++) { 4410 cw = hdac_widget_get(devinfo, 4411 w->conns[j]); 4412 if (cw == NULL || cw->enable == 0) 4413 continue; 4414 max++; 4415 } 4416 break; 4417 default: 4418 max++; 4419 break; 4420 } 4421 } 4422 } 4423 4424 devinfo->function.audio.ctlcnt = max; 4425 4426 if (max < 1) 4427 return; 4428 4429 ctls = (struct hdac_audio_ctl *)malloc( 4430 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4431 4432 if (ctls == NULL) { 4433 /* Blekh! */ 4434 device_printf(sc->dev, "unable to allocate ctls!\n"); 4435 devinfo->function.audio.ctlcnt = 0; 4436 return; 4437 } 4438 4439 cnt = 0; 4440 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4441 if (cnt >= max) { 4442 device_printf(sc->dev, "%s: Ctl overflow!\n", 4443 __func__); 4444 break; 4445 } 4446 w = hdac_widget_get(devinfo, i); 4447 if (w == NULL || w->enable == 0) 4448 continue; 4449 ocap = w->param.outamp_cap; 4450 icap = w->param.inamp_cap; 4451 if (ocap != 0) { 4452 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4453 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4454 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4455 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4456 /*if (offset > step) { 4457 HDA_BOOTVERBOSE( 4458 device_printf(sc->dev, 4459 "BUGGY outamp: nid=%d " 4460 "[offset=%d > step=%d]\n", 4461 w->nid, offset, step); 4462 ); 4463 offset = step; 4464 }*/ 4465 ctls[cnt].enable = 1; 4466 ctls[cnt].widget = w; 4467 ctls[cnt].mute = mute; 4468 ctls[cnt].step = step; 4469 ctls[cnt].size = size; 4470 ctls[cnt].offset = offset; 4471 ctls[cnt].left = offset; 4472 ctls[cnt].right = offset; 4473 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4474 w->waspin) 4475 ctls[cnt].ndir = HDA_CTL_IN; 4476 else 4477 ctls[cnt].ndir = HDA_CTL_OUT; 4478 ctls[cnt++].dir = HDA_CTL_OUT; 4479 } 4480 4481 if (icap != 0) { 4482 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4483 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4484 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4485 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4486 /*if (offset > step) { 4487 HDA_BOOTVERBOSE( 4488 device_printf(sc->dev, 4489 "BUGGY inamp: nid=%d " 4490 "[offset=%d > step=%d]\n", 4491 w->nid, offset, step); 4492 ); 4493 offset = step; 4494 }*/ 4495 switch (w->type) { 4496 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4497 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4498 for (j = 0; j < w->nconns; j++) { 4499 if (cnt >= max) { 4500 device_printf(sc->dev, 4501 "%s: Ctl overflow!\n", 4502 __func__); 4503 break; 4504 } 4505 cw = hdac_widget_get(devinfo, 4506 w->conns[j]); 4507 if (cw == NULL || cw->enable == 0) 4508 continue; 4509 ctls[cnt].enable = 1; 4510 ctls[cnt].widget = w; 4511 ctls[cnt].childwidget = cw; 4512 ctls[cnt].index = j; 4513 ctls[cnt].mute = mute; 4514 ctls[cnt].step = step; 4515 ctls[cnt].size = size; 4516 ctls[cnt].offset = offset; 4517 ctls[cnt].left = offset; 4518 ctls[cnt].right = offset; 4519 ctls[cnt].ndir = HDA_CTL_IN; 4520 ctls[cnt++].dir = HDA_CTL_IN; 4521 } 4522 break; 4523 default: 4524 if (cnt >= max) { 4525 device_printf(sc->dev, 4526 "%s: Ctl overflow!\n", 4527 __func__); 4528 break; 4529 } 4530 ctls[cnt].enable = 1; 4531 ctls[cnt].widget = w; 4532 ctls[cnt].mute = mute; 4533 ctls[cnt].step = step; 4534 ctls[cnt].size = size; 4535 ctls[cnt].offset = offset; 4536 ctls[cnt].left = offset; 4537 ctls[cnt].right = offset; 4538 if (w->type == 4539 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4540 ctls[cnt].ndir = HDA_CTL_OUT; 4541 else 4542 ctls[cnt].ndir = HDA_CTL_IN; 4543 ctls[cnt++].dir = HDA_CTL_IN; 4544 break; 4545 } 4546 } 4547 } 4548 4549 devinfo->function.audio.ctl = ctls; 4550 } 4551 4552 static void 4553 hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4554 { 4555 struct hdac_softc *sc = devinfo->codec->sc; 4556 struct hdac_audio_as *as; 4557 struct hdac_widget *w; 4558 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4559 4560 /* Count present associations */ 4561 max = 0; 4562 for (j = 1; j < 16; j++) { 4563 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4564 w = hdac_widget_get(devinfo, i); 4565 if (w == NULL || w->enable == 0) 4566 continue; 4567 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4568 continue; 4569 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4570 != j) 4571 continue; 4572 max++; 4573 if (j != 15) /* There could be many 1-pin assocs #15 */ 4574 break; 4575 } 4576 } 4577 4578 devinfo->function.audio.ascnt = max; 4579 4580 if (max < 1) 4581 return; 4582 4583 as = (struct hdac_audio_as *)malloc( 4584 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4585 4586 if (as == NULL) { 4587 /* Blekh! */ 4588 device_printf(sc->dev, "unable to allocate assocs!\n"); 4589 devinfo->function.audio.ascnt = 0; 4590 return; 4591 } 4592 4593 for (i = 0; i < max; i++) { 4594 as[i].hpredir = -1; 4595 as[i].chan = -1; 4596 as[i].digital = 0; 4597 } 4598 4599 /* Scan associations skipping as=0. */ 4600 cnt = 0; 4601 for (j = 1; j < 16; j++) { 4602 first = 16; 4603 hpredir = 0; 4604 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4605 w = hdac_widget_get(devinfo, i); 4606 if (w == NULL || w->enable == 0) 4607 continue; 4608 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4609 continue; 4610 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4611 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4612 if (assoc != j) { 4613 continue; 4614 } 4615 KASSERT(cnt < max, 4616 ("%s: Associations owerflow (%d of %d)", 4617 __func__, cnt, max)); 4618 type = w->wclass.pin.config & 4619 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4620 /* Get pin direction. */ 4621 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4622 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4623 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4624 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4625 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4626 dir = HDA_CTL_OUT; 4627 else 4628 dir = HDA_CTL_IN; 4629 /* If this is a first pin - create new association. */ 4630 if (as[cnt].pincnt == 0) { 4631 as[cnt].enable = 1; 4632 as[cnt].index = j; 4633 as[cnt].dir = dir; 4634 } 4635 if (seq < first) 4636 first = seq; 4637 /* Check association correctness. */ 4638 if (as[cnt].pins[seq] != 0) { 4639 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4640 "in association %d! Disabling association.\n", 4641 __func__, seq, w->nid, j); 4642 as[cnt].enable = 0; 4643 } 4644 if (dir != as[cnt].dir) { 4645 device_printf(sc->dev, "%s: Pin %d has wrong " 4646 "direction for association %d! Disabling " 4647 "association.\n", 4648 __func__, w->nid, j); 4649 as[cnt].enable = 0; 4650 } 4651 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4652 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4653 as[cnt].digital = 3; 4654 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4655 as[cnt].digital = 2; 4656 else 4657 as[cnt].digital = 1; 4658 } 4659 /* Headphones with seq=15 may mean redirection. */ 4660 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4661 seq == 15) 4662 hpredir = 1; 4663 as[cnt].pins[seq] = w->nid; 4664 as[cnt].pincnt++; 4665 /* Association 15 is a multiple unassociated pins. */ 4666 if (j == 15) 4667 cnt++; 4668 } 4669 if (j != 15 && as[cnt].pincnt > 0) { 4670 if (hpredir && as[cnt].pincnt > 1) 4671 as[cnt].hpredir = first; 4672 cnt++; 4673 } 4674 } 4675 HDA_BOOTVERBOSE( 4676 device_printf(sc->dev, 4677 "%d associations found:\n", max); 4678 for (i = 0; i < max; i++) { 4679 device_printf(sc->dev, 4680 "Association %d (%d) %s%s:\n", 4681 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4682 as[i].enable?"":" (disabled)"); 4683 for (j = 0; j < 16; j++) { 4684 if (as[i].pins[j] == 0) 4685 continue; 4686 device_printf(sc->dev, 4687 " Pin nid=%d seq=%d\n", 4688 as[i].pins[j], j); 4689 } 4690 } 4691 ); 4692 4693 devinfo->function.audio.as = as; 4694 } 4695 4696 static const struct { 4697 uint32_t model; 4698 uint32_t id; 4699 uint32_t set, unset; 4700 } hdac_quirks[] = { 4701 /* 4702 * XXX Force stereo quirk. Monoural recording / playback 4703 * on few codecs (especially ALC880) seems broken or 4704 * perhaps unsupported. 4705 */ 4706 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4707 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4708 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4709 HDA_QUIRK_GPIO0, 0 }, 4710 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4711 HDA_QUIRK_GPIO0, 0 }, 4712 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4713 HDA_QUIRK_GPIO0, 0 }, 4714 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4715 HDA_QUIRK_GPIO0, 0 }, 4716 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4717 HDA_QUIRK_GPIO0, 0 }, 4718 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4719 HDA_QUIRK_GPIO0, 0 }, 4720 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4721 HDA_QUIRK_EAPDINV, 0 }, 4722 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4723 HDA_QUIRK_EAPDINV, 0 }, 4724 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4725 HDA_QUIRK_OVREF, 0 }, 4726 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4727 HDA_QUIRK_OVREF, 0 }, 4728 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4729 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4730 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4731 HDA_QUIRK_GPIO1, 0 }, 4732 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4733 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4734 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4735 HDA_QUIRK_EAPDINV, 0 }, 4736 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4737 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4738 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4739 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4740 { APPLE_MACBOOKPRO55, HDA_CODEC_CS4206, 4741 HDA_QUIRK_GPIO1 | HDA_QUIRK_GPIO3, 0 }, 4742 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4743 HDA_QUIRK_GPIO0, 0 }, 4744 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4745 HDA_QUIRK_GPIO2, 0 }, 4746 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4747 HDA_QUIRK_GPIO0, 0 }, 4748 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4749 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4750 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4751 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4752 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4753 0, HDA_QUIRK_FORCESTEREO } 4754 }; 4755 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4756 4757 static void 4758 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4759 { 4760 struct hdac_widget *w; 4761 uint32_t id, subvendor; 4762 int i; 4763 4764 id = hdac_codec_id(devinfo->codec); 4765 subvendor = devinfo->codec->sc->pci_subvendor; 4766 4767 /* 4768 * Quirks 4769 */ 4770 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4771 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4772 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4773 continue; 4774 if (hdac_quirks[i].set != 0) 4775 devinfo->function.audio.quirks |= 4776 hdac_quirks[i].set; 4777 if (hdac_quirks[i].unset != 0) 4778 devinfo->function.audio.quirks &= 4779 ~(hdac_quirks[i].unset); 4780 } 4781 4782 switch (id) { 4783 case HDA_CODEC_AD1983: 4784 /* 4785 * This codec has several possible usages, but none 4786 * fit the parser best. Help parser to choose better. 4787 */ 4788 /* Disable direct unmixed playback to get pcm volume. */ 4789 w = hdac_widget_get(devinfo, 5); 4790 if (w != NULL) 4791 w->connsenable[0] = 0; 4792 w = hdac_widget_get(devinfo, 6); 4793 if (w != NULL) 4794 w->connsenable[0] = 0; 4795 w = hdac_widget_get(devinfo, 11); 4796 if (w != NULL) 4797 w->connsenable[0] = 0; 4798 /* Disable mic and line selectors. */ 4799 w = hdac_widget_get(devinfo, 12); 4800 if (w != NULL) 4801 w->connsenable[1] = 0; 4802 w = hdac_widget_get(devinfo, 13); 4803 if (w != NULL) 4804 w->connsenable[1] = 0; 4805 /* Disable recording from mono playback mix. */ 4806 w = hdac_widget_get(devinfo, 20); 4807 if (w != NULL) 4808 w->connsenable[3] = 0; 4809 break; 4810 case HDA_CODEC_AD1986A: 4811 /* 4812 * This codec has overcomplicated input mixing. 4813 * Make some cleaning there. 4814 */ 4815 /* Disable input mono mixer. Not needed and not supported. */ 4816 w = hdac_widget_get(devinfo, 43); 4817 if (w != NULL) 4818 w->enable = 0; 4819 /* Disable any with any input mixing mesh. Use separately. */ 4820 w = hdac_widget_get(devinfo, 39); 4821 if (w != NULL) 4822 w->enable = 0; 4823 w = hdac_widget_get(devinfo, 40); 4824 if (w != NULL) 4825 w->enable = 0; 4826 w = hdac_widget_get(devinfo, 41); 4827 if (w != NULL) 4828 w->enable = 0; 4829 w = hdac_widget_get(devinfo, 42); 4830 if (w != NULL) 4831 w->enable = 0; 4832 /* Disable duplicate mixer node connector. */ 4833 w = hdac_widget_get(devinfo, 15); 4834 if (w != NULL) 4835 w->connsenable[3] = 0; 4836 /* There is only one mic preamplifier, use it effectively. */ 4837 w = hdac_widget_get(devinfo, 31); 4838 if (w != NULL) { 4839 if ((w->wclass.pin.config & 4840 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4841 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4842 w = hdac_widget_get(devinfo, 16); 4843 if (w != NULL) 4844 w->connsenable[2] = 0; 4845 } else { 4846 w = hdac_widget_get(devinfo, 15); 4847 if (w != NULL) 4848 w->connsenable[0] = 0; 4849 } 4850 } 4851 w = hdac_widget_get(devinfo, 32); 4852 if (w != NULL) { 4853 if ((w->wclass.pin.config & 4854 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4855 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4856 w = hdac_widget_get(devinfo, 16); 4857 if (w != NULL) 4858 w->connsenable[0] = 0; 4859 } else { 4860 w = hdac_widget_get(devinfo, 15); 4861 if (w != NULL) 4862 w->connsenable[1] = 0; 4863 } 4864 } 4865 4866 if (subvendor == ASUS_A8X_SUBVENDOR) { 4867 /* 4868 * This is just plain ridiculous.. There 4869 * are several A8 series that share the same 4870 * pci id but works differently (EAPD). 4871 */ 4872 w = hdac_widget_get(devinfo, 26); 4873 if (w != NULL && w->type == 4874 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4875 (w->wclass.pin.config & 4876 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4877 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4878 devinfo->function.audio.quirks &= 4879 ~HDA_QUIRK_EAPDINV; 4880 } 4881 break; 4882 case HDA_CODEC_AD1981HD: 4883 /* 4884 * This codec has very unusual design with several 4885 * points inappropriate for the present parser. 4886 */ 4887 /* Disable recording from mono playback mix. */ 4888 w = hdac_widget_get(devinfo, 21); 4889 if (w != NULL) 4890 w->connsenable[3] = 0; 4891 /* Disable rear to front mic mixer, use separately. */ 4892 w = hdac_widget_get(devinfo, 31); 4893 if (w != NULL) 4894 w->enable = 0; 4895 /* Disable direct playback, use mixer. */ 4896 w = hdac_widget_get(devinfo, 5); 4897 if (w != NULL) 4898 w->connsenable[0] = 0; 4899 w = hdac_widget_get(devinfo, 6); 4900 if (w != NULL) 4901 w->connsenable[0] = 0; 4902 w = hdac_widget_get(devinfo, 9); 4903 if (w != NULL) 4904 w->connsenable[0] = 0; 4905 w = hdac_widget_get(devinfo, 24); 4906 if (w != NULL) 4907 w->connsenable[0] = 0; 4908 break; 4909 } 4910 } 4911 4912 /* 4913 * Trace path from DAC to pin. 4914 */ 4915 static nid_t 4916 hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4917 int dupseq, int min, int only, int depth) 4918 { 4919 struct hdac_widget *w; 4920 int i, im = -1; 4921 nid_t m = 0, ret; 4922 4923 if (depth > HDA_PARSE_MAXDEPTH) 4924 return (0); 4925 w = hdac_widget_get(devinfo, nid); 4926 if (w == NULL || w->enable == 0) 4927 return (0); 4928 HDA_BOOTHVERBOSE( 4929 if (!only) { 4930 device_printf(devinfo->codec->sc->dev, 4931 " %*stracing via nid %d\n", 4932 depth + 1, "", w->nid); 4933 } 4934 ); 4935 /* Use only unused widgets */ 4936 if (w->bindas >= 0 && w->bindas != as) { 4937 HDA_BOOTHVERBOSE( 4938 if (!only) { 4939 device_printf(devinfo->codec->sc->dev, 4940 " %*snid %d busy by association %d\n", 4941 depth + 1, "", w->nid, w->bindas); 4942 } 4943 ); 4944 return (0); 4945 } 4946 if (dupseq < 0) { 4947 if (w->bindseqmask != 0) { 4948 HDA_BOOTHVERBOSE( 4949 if (!only) { 4950 device_printf(devinfo->codec->sc->dev, 4951 " %*snid %d busy by seqmask %x\n", 4952 depth + 1, "", w->nid, w->bindseqmask); 4953 } 4954 ); 4955 return (0); 4956 } 4957 } else { 4958 /* If this is headphones - allow duplicate first pin. */ 4959 if (w->bindseqmask != 0 && 4960 (w->bindseqmask & (1 << dupseq)) == 0) { 4961 HDA_BOOTHVERBOSE( 4962 device_printf(devinfo->codec->sc->dev, 4963 " %*snid %d busy by seqmask %x\n", 4964 depth + 1, "", w->nid, w->bindseqmask); 4965 ); 4966 return (0); 4967 } 4968 } 4969 4970 switch (w->type) { 4971 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4972 /* Do not traverse input. AD1988 has digital monitor 4973 for which we are not ready. */ 4974 break; 4975 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4976 /* If we are tracing HP take only dac of first pin. */ 4977 if ((only == 0 || only == w->nid) && 4978 (w->nid >= min) && (dupseq < 0 || w->nid == 4979 devinfo->function.audio.as[as].dacs[dupseq])) 4980 m = w->nid; 4981 break; 4982 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4983 if (depth > 0) 4984 break; 4985 /* Fall */ 4986 default: 4987 /* Find reachable DACs with smallest nid respecting constraints. */ 4988 for (i = 0; i < w->nconns; i++) { 4989 if (w->connsenable[i] == 0) 4990 continue; 4991 if (w->selconn != -1 && w->selconn != i) 4992 continue; 4993 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4994 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4995 if (m == 0 || ret < m) { 4996 m = ret; 4997 im = i; 4998 } 4999 if (only || dupseq >= 0) 5000 break; 5001 } 5002 } 5003 if (m && only && ((w->nconns > 1 && 5004 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5005 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 5006 w->selconn = im; 5007 break; 5008 } 5009 if (m && only) { 5010 w->bindas = as; 5011 w->bindseqmask |= (1 << seq); 5012 } 5013 HDA_BOOTHVERBOSE( 5014 if (!only) { 5015 device_printf(devinfo->codec->sc->dev, 5016 " %*snid %d returned %d\n", 5017 depth + 1, "", w->nid, m); 5018 } 5019 ); 5020 return (m); 5021 } 5022 5023 /* 5024 * Trace path from widget to ADC. 5025 */ 5026 static nid_t 5027 hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 5028 int only, int depth) 5029 { 5030 struct hdac_widget *w, *wc; 5031 int i, j; 5032 nid_t res = 0; 5033 5034 if (depth > HDA_PARSE_MAXDEPTH) 5035 return (0); 5036 w = hdac_widget_get(devinfo, nid); 5037 if (w == NULL || w->enable == 0) 5038 return (0); 5039 HDA_BOOTHVERBOSE( 5040 device_printf(devinfo->codec->sc->dev, 5041 " %*stracing via nid %d\n", 5042 depth + 1, "", w->nid); 5043 ); 5044 /* Use only unused widgets */ 5045 if (w->bindas >= 0 && w->bindas != as) { 5046 HDA_BOOTHVERBOSE( 5047 device_printf(devinfo->codec->sc->dev, 5048 " %*snid %d busy by association %d\n", 5049 depth + 1, "", w->nid, w->bindas); 5050 ); 5051 return (0); 5052 } 5053 5054 switch (w->type) { 5055 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5056 /* If we are tracing HP take only dac of first pin. */ 5057 if (only == w->nid) 5058 res = 1; 5059 break; 5060 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5061 if (depth > 0) 5062 break; 5063 /* Fall */ 5064 default: 5065 /* Try to find reachable ADCs with specified nid. */ 5066 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5067 wc = hdac_widget_get(devinfo, j); 5068 if (wc == NULL || wc->enable == 0) 5069 continue; 5070 for (i = 0; i < wc->nconns; i++) { 5071 if (wc->connsenable[i] == 0) 5072 continue; 5073 if (wc->conns[i] != nid) 5074 continue; 5075 if (hdac_audio_trace_adc(devinfo, as, seq, 5076 j, only, depth + 1) != 0) { 5077 res = 1; 5078 if (((wc->nconns > 1 && 5079 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5080 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5081 wc->selconn == -1) 5082 wc->selconn = i; 5083 } 5084 } 5085 } 5086 break; 5087 } 5088 if (res) { 5089 w->bindas = as; 5090 w->bindseqmask |= (1 << seq); 5091 } 5092 HDA_BOOTHVERBOSE( 5093 device_printf(devinfo->codec->sc->dev, 5094 " %*snid %d returned %d\n", 5095 depth + 1, "", w->nid, res); 5096 ); 5097 return (res); 5098 } 5099 5100 /* 5101 * Erase trace path of the specified association. 5102 */ 5103 static void 5104 hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5105 { 5106 struct hdac_widget *w; 5107 int i; 5108 5109 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5110 w = hdac_widget_get(devinfo, i); 5111 if (w == NULL || w->enable == 0) 5112 continue; 5113 if (w->bindas == as) { 5114 if (seq >= 0) { 5115 w->bindseqmask &= ~(1 << seq); 5116 if (w->bindseqmask == 0) { 5117 w->bindas = -1; 5118 w->selconn = -1; 5119 } 5120 } else { 5121 w->bindas = -1; 5122 w->bindseqmask = 0; 5123 w->selconn = -1; 5124 } 5125 } 5126 } 5127 } 5128 5129 /* 5130 * Trace association path from DAC to output 5131 */ 5132 static int 5133 hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5134 { 5135 struct hdac_audio_as *ases = devinfo->function.audio.as; 5136 int i, hpredir; 5137 nid_t min, res; 5138 5139 /* Find next pin */ 5140 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5141 ; 5142 /* Check if there is no any left. If so - we succeeded. */ 5143 if (i == 16) 5144 return (1); 5145 5146 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5147 min = 0; 5148 res = 0; 5149 do { 5150 HDA_BOOTHVERBOSE( 5151 device_printf(devinfo->codec->sc->dev, 5152 " Tracing pin %d with min nid %d", 5153 ases[as].pins[i], min); 5154 if (hpredir >= 0) 5155 printf(" and hpredir %d", hpredir); 5156 printf("\n"); 5157 ); 5158 /* Trace this pin taking min nid into account. */ 5159 res = hdac_audio_trace_dac(devinfo, as, i, 5160 ases[as].pins[i], hpredir, min, 0, 0); 5161 if (res == 0) { 5162 /* If we failed - return to previous and redo it. */ 5163 HDA_BOOTVERBOSE( 5164 device_printf(devinfo->codec->sc->dev, 5165 " Unable to trace pin %d seq %d with min " 5166 "nid %d", 5167 ases[as].pins[i], i, min); 5168 if (hpredir >= 0) 5169 printf(" and hpredir %d", hpredir); 5170 printf("\n"); 5171 ); 5172 return (0); 5173 } 5174 HDA_BOOTVERBOSE( 5175 device_printf(devinfo->codec->sc->dev, 5176 " Pin %d traced to DAC %d", 5177 ases[as].pins[i], res); 5178 if (hpredir >= 0) 5179 printf(" and hpredir %d", hpredir); 5180 if (ases[as].fakeredir) 5181 printf(" with fake redirection"); 5182 printf("\n"); 5183 ); 5184 /* Trace again to mark the path */ 5185 hdac_audio_trace_dac(devinfo, as, i, 5186 ases[as].pins[i], hpredir, min, res, 0); 5187 ases[as].dacs[i] = res; 5188 /* We succeeded, so call next. */ 5189 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5190 return (1); 5191 /* If next failed, we should retry with next min */ 5192 hdac_audio_undo_trace(devinfo, as, i); 5193 ases[as].dacs[i] = 0; 5194 min = res + 1; 5195 } while (1); 5196 } 5197 5198 /* 5199 * Trace association path from input to ADC 5200 */ 5201 static int 5202 hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5203 { 5204 struct hdac_audio_as *ases = devinfo->function.audio.as; 5205 struct hdac_widget *w; 5206 int i, j, k; 5207 5208 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5209 w = hdac_widget_get(devinfo, j); 5210 if (w == NULL || w->enable == 0) 5211 continue; 5212 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5213 continue; 5214 if (w->bindas >= 0 && w->bindas != as) 5215 continue; 5216 5217 /* Find next pin */ 5218 for (i = 0; i < 16; i++) { 5219 if (ases[as].pins[i] == 0) 5220 continue; 5221 5222 HDA_BOOTHVERBOSE( 5223 device_printf(devinfo->codec->sc->dev, 5224 " Tracing pin %d to ADC %d\n", 5225 ases[as].pins[i], j); 5226 ); 5227 /* Trace this pin taking goal into account. */ 5228 if (hdac_audio_trace_adc(devinfo, as, i, 5229 ases[as].pins[i], j, 0) == 0) { 5230 /* If we failed - return to previous and redo it. */ 5231 HDA_BOOTVERBOSE( 5232 device_printf(devinfo->codec->sc->dev, 5233 " Unable to trace pin %d to ADC %d, undo traces\n", 5234 ases[as].pins[i], j); 5235 ); 5236 hdac_audio_undo_trace(devinfo, as, -1); 5237 for (k = 0; k < 16; k++) 5238 ases[as].dacs[k] = 0; 5239 break; 5240 } 5241 HDA_BOOTVERBOSE( 5242 device_printf(devinfo->codec->sc->dev, 5243 " Pin %d traced to ADC %d\n", 5244 ases[as].pins[i], j); 5245 ); 5246 ases[as].dacs[i] = j; 5247 } 5248 if (i == 16) 5249 return (1); 5250 } 5251 return (0); 5252 } 5253 5254 /* 5255 * Trace input monitor path from mixer to output association. 5256 */ 5257 static int 5258 hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5259 { 5260 struct hdac_audio_as *ases = devinfo->function.audio.as; 5261 struct hdac_widget *w, *wc; 5262 int i, j; 5263 nid_t res = 0; 5264 5265 if (depth > HDA_PARSE_MAXDEPTH) 5266 return (0); 5267 w = hdac_widget_get(devinfo, nid); 5268 if (w == NULL || w->enable == 0) 5269 return (0); 5270 HDA_BOOTHVERBOSE( 5271 device_printf(devinfo->codec->sc->dev, 5272 " %*stracing via nid %d\n", 5273 depth + 1, "", w->nid); 5274 ); 5275 /* Use only unused widgets */ 5276 if (depth > 0 && w->bindas != -1) { 5277 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5278 HDA_BOOTHVERBOSE( 5279 device_printf(devinfo->codec->sc->dev, 5280 " %*snid %d found output association %d\n", 5281 depth + 1, "", w->nid, w->bindas); 5282 ); 5283 if (w->bindas >= 0) 5284 w->pflags |= HDA_ADC_MONITOR; 5285 return (1); 5286 } else { 5287 HDA_BOOTHVERBOSE( 5288 device_printf(devinfo->codec->sc->dev, 5289 " %*snid %d busy by input association %d\n", 5290 depth + 1, "", w->nid, w->bindas); 5291 ); 5292 return (0); 5293 } 5294 } 5295 5296 switch (w->type) { 5297 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5298 /* Do not traverse input. AD1988 has digital monitor 5299 for which we are not ready. */ 5300 break; 5301 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5302 if (depth > 0) 5303 break; 5304 /* Fall */ 5305 default: 5306 /* Try to find reachable ADCs with specified nid. */ 5307 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5308 wc = hdac_widget_get(devinfo, j); 5309 if (wc == NULL || wc->enable == 0) 5310 continue; 5311 for (i = 0; i < wc->nconns; i++) { 5312 if (wc->connsenable[i] == 0) 5313 continue; 5314 if (wc->conns[i] != nid) 5315 continue; 5316 if (hdac_audio_trace_to_out(devinfo, 5317 j, depth + 1) != 0) { 5318 res = 1; 5319 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5320 wc->selconn == -1) 5321 wc->selconn = i; 5322 } 5323 } 5324 } 5325 break; 5326 } 5327 if (res && w->bindas == -1) 5328 w->bindas = -2; 5329 5330 HDA_BOOTHVERBOSE( 5331 device_printf(devinfo->codec->sc->dev, 5332 " %*snid %d returned %d\n", 5333 depth + 1, "", w->nid, res); 5334 ); 5335 return (res); 5336 } 5337 5338 /* 5339 * Trace extra associations (beeper, monitor) 5340 */ 5341 static void 5342 hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5343 { 5344 struct hdac_audio_as *as = devinfo->function.audio.as; 5345 struct hdac_widget *w; 5346 int j; 5347 5348 /* Input monitor */ 5349 /* Find mixer associated with input, but supplying signal 5350 for output associations. Hope it will be input monitor. */ 5351 HDA_BOOTVERBOSE( 5352 device_printf(devinfo->codec->sc->dev, 5353 "Tracing input monitor\n"); 5354 ); 5355 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5356 w = hdac_widget_get(devinfo, j); 5357 if (w == NULL || w->enable == 0) 5358 continue; 5359 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5360 continue; 5361 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5362 continue; 5363 HDA_BOOTVERBOSE( 5364 device_printf(devinfo->codec->sc->dev, 5365 " Tracing nid %d to out\n", 5366 j); 5367 ); 5368 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5369 HDA_BOOTVERBOSE( 5370 device_printf(devinfo->codec->sc->dev, 5371 " nid %d is input monitor\n", 5372 w->nid); 5373 ); 5374 w->ossdev = SOUND_MIXER_IMIX; 5375 } 5376 } 5377 5378 /* Other inputs monitor */ 5379 /* Find input pins supplying signal for output associations. 5380 Hope it will be input monitoring. */ 5381 HDA_BOOTVERBOSE( 5382 device_printf(devinfo->codec->sc->dev, 5383 "Tracing other input monitors\n"); 5384 ); 5385 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5386 w = hdac_widget_get(devinfo, j); 5387 if (w == NULL || w->enable == 0) 5388 continue; 5389 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5390 continue; 5391 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5392 continue; 5393 HDA_BOOTVERBOSE( 5394 device_printf(devinfo->codec->sc->dev, 5395 " Tracing nid %d to out\n", 5396 j); 5397 ); 5398 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5399 HDA_BOOTVERBOSE( 5400 device_printf(devinfo->codec->sc->dev, 5401 " nid %d is input monitor\n", 5402 w->nid); 5403 ); 5404 } 5405 } 5406 5407 /* Beeper */ 5408 HDA_BOOTVERBOSE( 5409 device_printf(devinfo->codec->sc->dev, 5410 "Tracing beeper\n"); 5411 ); 5412 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5413 w = hdac_widget_get(devinfo, j); 5414 if (w == NULL || w->enable == 0) 5415 continue; 5416 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5417 continue; 5418 HDA_BOOTHVERBOSE( 5419 device_printf(devinfo->codec->sc->dev, 5420 " Tracing nid %d to out\n", 5421 j); 5422 ); 5423 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5424 HDA_BOOTVERBOSE( 5425 device_printf(devinfo->codec->sc->dev, 5426 " nid %d traced to out\n", 5427 j); 5428 ); 5429 } 5430 w->bindas = -2; 5431 } 5432 } 5433 5434 /* 5435 * Bind assotiations to PCM channels 5436 */ 5437 static void 5438 hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5439 { 5440 struct hdac_softc *sc = devinfo->codec->sc; 5441 struct hdac_audio_as *as = devinfo->function.audio.as; 5442 int j, cnt = 0, free; 5443 5444 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5445 if (as[j].enable) 5446 cnt++; 5447 } 5448 if (sc->num_chans == 0) { 5449 sc->chans = (struct hdac_chan *)malloc( 5450 sizeof(struct hdac_chan) * cnt, 5451 M_HDAC, M_ZERO | M_NOWAIT); 5452 if (sc->chans == NULL) { 5453 device_printf(sc->dev, 5454 "Channels memory allocation failed!\n"); 5455 return; 5456 } 5457 } else { 5458 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5459 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5460 M_HDAC, M_ZERO | M_NOWAIT); 5461 if (sc->chans == NULL) { 5462 sc->num_chans = 0; 5463 device_printf(sc->dev, 5464 "Channels memory allocation failed!\n"); 5465 return; 5466 } 5467 /* Fixup relative pointers after realloc */ 5468 for (j = 0; j < sc->num_chans; j++) 5469 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5470 } 5471 free = sc->num_chans; 5472 sc->num_chans += cnt; 5473 5474 for (j = free; j < free + cnt; j++) { 5475 sc->chans[j].devinfo = devinfo; 5476 sc->chans[j].as = -1; 5477 } 5478 5479 /* Assign associations in order of their numbers, */ 5480 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5481 if (as[j].enable == 0) 5482 continue; 5483 5484 as[j].chan = free; 5485 sc->chans[free].as = j; 5486 sc->chans[free].dir = 5487 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5488 hdac_pcmchannel_setup(&sc->chans[free]); 5489 free++; 5490 } 5491 } 5492 5493 static void 5494 hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5495 { 5496 struct hdac_widget *w; 5497 int i; 5498 5499 /* Disable power and volume widgets. */ 5500 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5501 w = hdac_widget_get(devinfo, i); 5502 if (w == NULL || w->enable == 0) 5503 continue; 5504 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5505 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5506 w->enable = 0; 5507 HDA_BOOTHVERBOSE( 5508 device_printf(devinfo->codec->sc->dev, 5509 " Disabling nid %d due to it's" 5510 " non-audio type.\n", 5511 w->nid); 5512 ); 5513 } 5514 } 5515 } 5516 5517 static void 5518 hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5519 { 5520 struct hdac_widget *w, *cw; 5521 struct hdac_audio_ctl *ctl; 5522 int done, found, i, j, k; 5523 5524 /* Disable useless pins. */ 5525 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5526 w = hdac_widget_get(devinfo, i); 5527 if (w == NULL || w->enable == 0) 5528 continue; 5529 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5530 if ((w->wclass.pin.config & 5531 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5532 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5533 w->enable = 0; 5534 HDA_BOOTHVERBOSE( 5535 device_printf(devinfo->codec->sc->dev, 5536 " Disabling pin nid %d due" 5537 " to None connectivity.\n", 5538 w->nid); 5539 ); 5540 } else if ((w->wclass.pin.config & 5541 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5542 w->enable = 0; 5543 HDA_BOOTHVERBOSE( 5544 device_printf(devinfo->codec->sc->dev, 5545 " Disabling unassociated" 5546 " pin nid %d.\n", 5547 w->nid); 5548 ); 5549 } 5550 } 5551 } 5552 do { 5553 done = 1; 5554 /* Disable and mute controls for disabled widgets. */ 5555 i = 0; 5556 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5557 if (ctl->enable == 0) 5558 continue; 5559 if (ctl->widget->enable == 0 || 5560 (ctl->childwidget != NULL && 5561 ctl->childwidget->enable == 0)) { 5562 ctl->forcemute = 1; 5563 ctl->muted = HDA_AMP_MUTE_ALL; 5564 ctl->left = 0; 5565 ctl->right = 0; 5566 ctl->enable = 0; 5567 if (ctl->ndir == HDA_CTL_IN) 5568 ctl->widget->connsenable[ctl->index] = 0; 5569 done = 0; 5570 HDA_BOOTHVERBOSE( 5571 device_printf(devinfo->codec->sc->dev, 5572 " Disabling ctl %d nid %d cnid %d due" 5573 " to disabled widget.\n", i, 5574 ctl->widget->nid, 5575 (ctl->childwidget != NULL)? 5576 ctl->childwidget->nid:-1); 5577 ); 5578 } 5579 } 5580 /* Disable useless widgets. */ 5581 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5582 w = hdac_widget_get(devinfo, i); 5583 if (w == NULL || w->enable == 0) 5584 continue; 5585 /* Disable inputs with disabled child widgets. */ 5586 for (j = 0; j < w->nconns; j++) { 5587 if (w->connsenable[j]) { 5588 cw = hdac_widget_get(devinfo, w->conns[j]); 5589 if (cw == NULL || cw->enable == 0) { 5590 w->connsenable[j] = 0; 5591 HDA_BOOTHVERBOSE( 5592 device_printf(devinfo->codec->sc->dev, 5593 " Disabling nid %d connection %d due" 5594 " to disabled child widget.\n", 5595 i, j); 5596 ); 5597 } 5598 } 5599 } 5600 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5601 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5602 continue; 5603 /* Disable mixers and selectors without inputs. */ 5604 found = 0; 5605 for (j = 0; j < w->nconns; j++) { 5606 if (w->connsenable[j]) { 5607 found = 1; 5608 break; 5609 } 5610 } 5611 if (found == 0) { 5612 w->enable = 0; 5613 done = 0; 5614 HDA_BOOTHVERBOSE( 5615 device_printf(devinfo->codec->sc->dev, 5616 " Disabling nid %d due to all it's" 5617 " inputs disabled.\n", w->nid); 5618 ); 5619 } 5620 /* Disable nodes without consumers. */ 5621 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5622 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5623 continue; 5624 found = 0; 5625 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5626 cw = hdac_widget_get(devinfo, k); 5627 if (cw == NULL || cw->enable == 0) 5628 continue; 5629 for (j = 0; j < cw->nconns; j++) { 5630 if (cw->connsenable[j] && cw->conns[j] == i) { 5631 found = 1; 5632 break; 5633 } 5634 } 5635 } 5636 if (found == 0) { 5637 w->enable = 0; 5638 done = 0; 5639 HDA_BOOTHVERBOSE( 5640 device_printf(devinfo->codec->sc->dev, 5641 " Disabling nid %d due to all it's" 5642 " consumers disabled.\n", w->nid); 5643 ); 5644 } 5645 } 5646 } while (done == 0); 5647 5648 } 5649 5650 static void 5651 hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5652 { 5653 struct hdac_audio_as *as = devinfo->function.audio.as; 5654 struct hdac_widget *w, *cw; 5655 struct hdac_audio_ctl *ctl; 5656 int i, j, k; 5657 5658 /* Disable unassosiated widgets. */ 5659 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5660 w = hdac_widget_get(devinfo, i); 5661 if (w == NULL || w->enable == 0) 5662 continue; 5663 if (w->bindas == -1) { 5664 w->enable = 0; 5665 HDA_BOOTHVERBOSE( 5666 device_printf(devinfo->codec->sc->dev, 5667 " Disabling unassociated nid %d.\n", 5668 w->nid); 5669 ); 5670 } 5671 } 5672 /* Disable input connections on input pin and 5673 * output on output. */ 5674 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5675 w = hdac_widget_get(devinfo, i); 5676 if (w == NULL || w->enable == 0) 5677 continue; 5678 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5679 continue; 5680 if (w->bindas < 0) 5681 continue; 5682 if (as[w->bindas].dir == HDA_CTL_IN) { 5683 for (j = 0; j < w->nconns; j++) { 5684 if (w->connsenable[j] == 0) 5685 continue; 5686 w->connsenable[j] = 0; 5687 HDA_BOOTHVERBOSE( 5688 device_printf(devinfo->codec->sc->dev, 5689 " Disabling connection to input pin " 5690 "nid %d conn %d.\n", 5691 i, j); 5692 ); 5693 } 5694 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5695 HDA_CTL_IN, -1, 1); 5696 if (ctl && ctl->enable) { 5697 ctl->forcemute = 1; 5698 ctl->muted = HDA_AMP_MUTE_ALL; 5699 ctl->left = 0; 5700 ctl->right = 0; 5701 ctl->enable = 0; 5702 } 5703 } else { 5704 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5705 HDA_CTL_OUT, -1, 1); 5706 if (ctl && ctl->enable) { 5707 ctl->forcemute = 1; 5708 ctl->muted = HDA_AMP_MUTE_ALL; 5709 ctl->left = 0; 5710 ctl->right = 0; 5711 ctl->enable = 0; 5712 } 5713 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5714 cw = hdac_widget_get(devinfo, k); 5715 if (cw == NULL || cw->enable == 0) 5716 continue; 5717 for (j = 0; j < cw->nconns; j++) { 5718 if (cw->connsenable[j] && cw->conns[j] == i) { 5719 cw->connsenable[j] = 0; 5720 HDA_BOOTHVERBOSE( 5721 device_printf(devinfo->codec->sc->dev, 5722 " Disabling connection from output pin " 5723 "nid %d conn %d cnid %d.\n", 5724 k, j, i); 5725 ); 5726 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5727 cw->nconns > 1) 5728 continue; 5729 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5730 HDA_CTL_IN, j, 1); 5731 if (ctl && ctl->enable) { 5732 ctl->forcemute = 1; 5733 ctl->muted = HDA_AMP_MUTE_ALL; 5734 ctl->left = 0; 5735 ctl->right = 0; 5736 ctl->enable = 0; 5737 } 5738 } 5739 } 5740 } 5741 } 5742 } 5743 } 5744 5745 static void 5746 hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5747 { 5748 struct hdac_audio_as *as = devinfo->function.audio.as; 5749 struct hdac_widget *w; 5750 int i, j; 5751 5752 /* On playback path we can safely disable all unseleted inputs. */ 5753 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5754 w = hdac_widget_get(devinfo, i); 5755 if (w == NULL || w->enable == 0) 5756 continue; 5757 if (w->nconns <= 1) 5758 continue; 5759 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5760 continue; 5761 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5762 continue; 5763 for (j = 0; j < w->nconns; j++) { 5764 if (w->connsenable[j] == 0) 5765 continue; 5766 if (w->selconn < 0 || w->selconn == j) 5767 continue; 5768 w->connsenable[j] = 0; 5769 HDA_BOOTHVERBOSE( 5770 device_printf(devinfo->codec->sc->dev, 5771 " Disabling unselected connection " 5772 "nid %d conn %d.\n", 5773 i, j); 5774 ); 5775 } 5776 } 5777 } 5778 5779 static void 5780 hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5781 { 5782 struct hdac_audio_as *ases = devinfo->function.audio.as; 5783 struct hdac_widget *w, *cw; 5784 struct hdac_audio_ctl *ctl; 5785 int i, j; 5786 5787 /* Disable crossassociatement and unwanted crosschannel connections. */ 5788 /* ... using selectors */ 5789 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5790 w = hdac_widget_get(devinfo, i); 5791 if (w == NULL || w->enable == 0) 5792 continue; 5793 if (w->nconns <= 1) 5794 continue; 5795 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5796 continue; 5797 if (w->bindas == -2) 5798 continue; 5799 for (j = 0; j < w->nconns; j++) { 5800 if (w->connsenable[j] == 0) 5801 continue; 5802 cw = hdac_widget_get(devinfo, w->conns[j]); 5803 if (cw == NULL || w->enable == 0) 5804 continue; 5805 if (cw->bindas == -2 || 5806 ((w->pflags & HDA_ADC_MONITOR) && 5807 cw->bindas >= 0 && 5808 ases[cw->bindas].dir == HDA_CTL_IN)) 5809 continue; 5810 if (w->bindas == cw->bindas && 5811 (w->bindseqmask & cw->bindseqmask) != 0) 5812 continue; 5813 w->connsenable[j] = 0; 5814 HDA_BOOTHVERBOSE( 5815 device_printf(devinfo->codec->sc->dev, 5816 " Disabling crossassociatement connection " 5817 "nid %d conn %d cnid %d.\n", 5818 i, j, cw->nid); 5819 ); 5820 } 5821 } 5822 /* ... using controls */ 5823 i = 0; 5824 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5825 if (ctl->enable == 0 || ctl->childwidget == NULL) 5826 continue; 5827 if (ctl->widget->bindas == -2) 5828 continue; 5829 if (ctl->childwidget->bindas == -2 || 5830 ((ctl->widget->pflags & HDA_ADC_MONITOR) && 5831 ctl->childwidget->bindas >= 0 && 5832 ases[ctl->childwidget->bindas].dir == HDA_CTL_IN)) 5833 continue; 5834 if (ctl->widget->bindas != ctl->childwidget->bindas || 5835 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5836 ctl->forcemute = 1; 5837 ctl->muted = HDA_AMP_MUTE_ALL; 5838 ctl->left = 0; 5839 ctl->right = 0; 5840 ctl->enable = 0; 5841 if (ctl->ndir == HDA_CTL_IN) 5842 ctl->widget->connsenable[ctl->index] = 0; 5843 HDA_BOOTHVERBOSE( 5844 device_printf(devinfo->codec->sc->dev, 5845 " Disabling crossassociatement connection " 5846 "ctl %d nid %d cnid %d.\n", i, 5847 ctl->widget->nid, 5848 ctl->childwidget->nid); 5849 ); 5850 } 5851 } 5852 5853 } 5854 5855 #define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5856 5857 /* 5858 * Find controls to control amplification for source. 5859 */ 5860 static int 5861 hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5862 int ossdev, int ctlable, int depth, int need) 5863 { 5864 struct hdac_widget *w, *wc; 5865 struct hdac_audio_ctl *ctl; 5866 int i, j, conns = 0, rneed; 5867 5868 if (depth > HDA_PARSE_MAXDEPTH) 5869 return (need); 5870 5871 w = hdac_widget_get(devinfo, nid); 5872 if (w == NULL || w->enable == 0) 5873 return (need); 5874 5875 /* Count number of active inputs. */ 5876 if (depth > 0) { 5877 for (j = 0; j < w->nconns; j++) { 5878 if (w->connsenable[j]) 5879 conns++; 5880 } 5881 } 5882 5883 /* If this is not a first step - use input mixer. 5884 Pins have common input ctl so care must be taken. */ 5885 if (depth > 0 && ctlable && (conns == 1 || 5886 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5887 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5888 index, 1); 5889 if (ctl) { 5890 if (HDA_CTL_GIVE(ctl) & need) 5891 ctl->ossmask |= (1 << ossdev); 5892 else 5893 ctl->possmask |= (1 << ossdev); 5894 need &= ~HDA_CTL_GIVE(ctl); 5895 } 5896 } 5897 5898 /* If widget has own ossdev - not traverse it. 5899 It will be traversed on it's own. */ 5900 if (w->ossdev >= 0 && depth > 0) 5901 return (need); 5902 5903 /* We must not traverse pin */ 5904 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5905 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5906 depth > 0) 5907 return (need); 5908 5909 /* record that this widget exports such signal, */ 5910 w->ossmask |= (1 << ossdev); 5911 5912 /* If signals mixed, we can't assign controls farther. 5913 * Ignore this on depth zero. Caller must knows why. 5914 * Ignore this for static selectors if this input selected. 5915 */ 5916 if (conns > 1) 5917 ctlable = 0; 5918 5919 if (ctlable) { 5920 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5921 if (ctl) { 5922 if (HDA_CTL_GIVE(ctl) & need) 5923 ctl->ossmask |= (1 << ossdev); 5924 else 5925 ctl->possmask |= (1 << ossdev); 5926 need &= ~HDA_CTL_GIVE(ctl); 5927 } 5928 } 5929 5930 rneed = 0; 5931 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5932 wc = hdac_widget_get(devinfo, i); 5933 if (wc == NULL || wc->enable == 0) 5934 continue; 5935 for (j = 0; j < wc->nconns; j++) { 5936 if (wc->connsenable[j] && wc->conns[j] == nid) { 5937 rneed |= hdac_audio_ctl_source_amp(devinfo, 5938 wc->nid, j, ossdev, ctlable, depth + 1, need); 5939 } 5940 } 5941 } 5942 rneed &= need; 5943 5944 return (rneed); 5945 } 5946 5947 /* 5948 * Find controls to control amplification for destination. 5949 */ 5950 static void 5951 hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5952 int ossdev, int depth, int need) 5953 { 5954 struct hdac_audio_as *as = devinfo->function.audio.as; 5955 struct hdac_widget *w, *wc; 5956 struct hdac_audio_ctl *ctl; 5957 int i, j, consumers; 5958 5959 if (depth > HDA_PARSE_MAXDEPTH) 5960 return; 5961 5962 w = hdac_widget_get(devinfo, nid); 5963 if (w == NULL || w->enable == 0) 5964 return; 5965 5966 if (depth > 0) { 5967 /* If this node produce output for several consumers, 5968 we can't touch it. */ 5969 consumers = 0; 5970 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5971 wc = hdac_widget_get(devinfo, i); 5972 if (wc == NULL || wc->enable == 0) 5973 continue; 5974 for (j = 0; j < wc->nconns; j++) { 5975 if (wc->connsenable[j] && wc->conns[j] == nid) 5976 consumers++; 5977 } 5978 } 5979 /* The only exception is if real HP redirection is configured 5980 and this is a duplication point. 5981 XXX: Actually exception is not completely correct. 5982 XXX: Duplication point check is not perfect. */ 5983 if ((consumers == 2 && (w->bindas < 0 || 5984 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5985 (w->bindseqmask & (1 << 15)) == 0)) || 5986 consumers > 2) 5987 return; 5988 5989 /* Else use it's output mixer. */ 5990 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5991 HDA_CTL_OUT, -1, 1); 5992 if (ctl) { 5993 if (HDA_CTL_GIVE(ctl) & need) 5994 ctl->ossmask |= (1 << ossdev); 5995 else 5996 ctl->possmask |= (1 << ossdev); 5997 need &= ~HDA_CTL_GIVE(ctl); 5998 } 5999 } 6000 6001 /* We must not traverse pin */ 6002 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6003 depth > 0) 6004 return; 6005 6006 for (i = 0; i < w->nconns; i++) { 6007 int tneed = need; 6008 if (w->connsenable[i] == 0) 6009 continue; 6010 if (index >= 0 && i != index) 6011 continue; 6012 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 6013 HDA_CTL_IN, i, 1); 6014 if (ctl) { 6015 if (HDA_CTL_GIVE(ctl) & tneed) 6016 ctl->ossmask |= (1 << ossdev); 6017 else 6018 ctl->possmask |= (1 << ossdev); 6019 tneed &= ~HDA_CTL_GIVE(ctl); 6020 } 6021 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], -1, ossdev, 6022 depth + 1, tneed); 6023 } 6024 } 6025 6026 /* 6027 * Assign OSS names to sound sources 6028 */ 6029 static void 6030 hdac_audio_assign_names(struct hdac_devinfo *devinfo) 6031 { 6032 struct hdac_audio_as *as = devinfo->function.audio.as; 6033 struct hdac_widget *w; 6034 int i, j; 6035 int type = -1, use, used = 0; 6036 static const int types[7][13] = { 6037 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6038 SOUND_MIXER_LINE3, -1 }, /* line */ 6039 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 6040 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 6041 { SOUND_MIXER_CD, -1 }, /* cd */ 6042 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 6043 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 6044 -1 }, /* digital */ 6045 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6046 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 6047 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 6048 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 6049 -1 } /* others */ 6050 }; 6051 6052 /* Surely known names */ 6053 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6054 w = hdac_widget_get(devinfo, i); 6055 if (w == NULL || w->enable == 0) 6056 continue; 6057 if (w->bindas == -1) 6058 continue; 6059 use = -1; 6060 switch (w->type) { 6061 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 6062 if (as[w->bindas].dir == HDA_CTL_OUT) 6063 break; 6064 type = -1; 6065 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6066 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 6067 type = 0; 6068 break; 6069 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6070 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 6071 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 6072 break; 6073 type = 1; 6074 break; 6075 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 6076 type = 3; 6077 break; 6078 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6079 type = 4; 6080 break; 6081 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 6082 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 6083 type = 5; 6084 break; 6085 } 6086 if (type == -1) 6087 break; 6088 j = 0; 6089 while (types[type][j] >= 0 && 6090 (used & (1 << types[type][j])) != 0) { 6091 j++; 6092 } 6093 if (types[type][j] >= 0) 6094 use = types[type][j]; 6095 break; 6096 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 6097 use = SOUND_MIXER_PCM; 6098 break; 6099 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 6100 use = SOUND_MIXER_SPEAKER; 6101 break; 6102 default: 6103 break; 6104 } 6105 if (use >= 0) { 6106 w->ossdev = use; 6107 used |= (1 << use); 6108 } 6109 } 6110 /* Semi-known names */ 6111 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6112 w = hdac_widget_get(devinfo, i); 6113 if (w == NULL || w->enable == 0) 6114 continue; 6115 if (w->ossdev >= 0) 6116 continue; 6117 if (w->bindas == -1) 6118 continue; 6119 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6120 continue; 6121 if (as[w->bindas].dir == HDA_CTL_OUT) 6122 continue; 6123 type = -1; 6124 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6125 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6126 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6127 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6128 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6129 type = 0; 6130 break; 6131 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6132 type = 2; 6133 break; 6134 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6135 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6136 type = 5; 6137 break; 6138 } 6139 if (type == -1) 6140 break; 6141 j = 0; 6142 while (types[type][j] >= 0 && 6143 (used & (1 << types[type][j])) != 0) { 6144 j++; 6145 } 6146 if (types[type][j] >= 0) { 6147 w->ossdev = types[type][j]; 6148 used |= (1 << types[type][j]); 6149 } 6150 } 6151 /* Others */ 6152 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6153 w = hdac_widget_get(devinfo, i); 6154 if (w == NULL || w->enable == 0) 6155 continue; 6156 if (w->ossdev >= 0) 6157 continue; 6158 if (w->bindas == -1) 6159 continue; 6160 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6161 continue; 6162 if (as[w->bindas].dir == HDA_CTL_OUT) 6163 continue; 6164 j = 0; 6165 while (types[6][j] >= 0 && 6166 (used & (1 << types[6][j])) != 0) { 6167 j++; 6168 } 6169 if (types[6][j] >= 0) { 6170 w->ossdev = types[6][j]; 6171 used |= (1 << types[6][j]); 6172 } 6173 } 6174 } 6175 6176 static void 6177 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6178 { 6179 struct hdac_audio_as *as = devinfo->function.audio.as; 6180 int j, res; 6181 6182 /* Trace all associations in order of their numbers, */ 6183 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6184 if (as[j].enable == 0) 6185 continue; 6186 HDA_BOOTVERBOSE( 6187 device_printf(devinfo->codec->sc->dev, 6188 "Tracing association %d (%d)\n", j, as[j].index); 6189 ); 6190 if (as[j].dir == HDA_CTL_OUT) { 6191 retry: 6192 res = hdac_audio_trace_as_out(devinfo, j, 0); 6193 if (res == 0 && as[j].hpredir >= 0 && 6194 as[j].fakeredir == 0) { 6195 /* If codec can't do analog HP redirection 6196 try to make it using one more DAC. */ 6197 as[j].fakeredir = 1; 6198 goto retry; 6199 } 6200 } else { 6201 res = hdac_audio_trace_as_in(devinfo, j); 6202 } 6203 if (res) { 6204 HDA_BOOTVERBOSE( 6205 device_printf(devinfo->codec->sc->dev, 6206 "Association %d (%d) trace succeeded\n", 6207 j, as[j].index); 6208 ); 6209 } else { 6210 HDA_BOOTVERBOSE( 6211 device_printf(devinfo->codec->sc->dev, 6212 "Association %d (%d) trace failed\n", 6213 j, as[j].index); 6214 ); 6215 as[j].enable = 0; 6216 } 6217 } 6218 6219 /* Trace mixer and beeper pseudo associations. */ 6220 hdac_audio_trace_as_extra(devinfo); 6221 } 6222 6223 static void 6224 hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6225 { 6226 struct hdac_audio_as *as = devinfo->function.audio.as; 6227 struct hdac_audio_ctl *ctl; 6228 struct hdac_widget *w, *cw; 6229 int i, j; 6230 6231 /* Assign mixers to the tree. */ 6232 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6233 w = hdac_widget_get(devinfo, i); 6234 if (w == NULL || w->enable == 0) 6235 continue; 6236 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6237 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6238 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6239 as[w->bindas].dir == HDA_CTL_IN)) { 6240 if (w->ossdev < 0) 6241 continue; 6242 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6243 w->ossdev, 1, 0, 1); 6244 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6245 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6246 SOUND_MIXER_RECLEV, 0, 1); 6247 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6248 as[w->bindas].dir == HDA_CTL_OUT) { 6249 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6250 SOUND_MIXER_VOLUME, 0, 1); 6251 } 6252 if (w->ossdev == SOUND_MIXER_IMIX) { 6253 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6254 w->ossdev, 1, 0, 1)) { 6255 /* If we are unable to control input monitor 6256 as source - try to control it as destination. */ 6257 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6258 w->ossdev, 0, 1); 6259 } 6260 } 6261 if (w->pflags & HDA_ADC_MONITOR) { 6262 for (j = 0; j < w->nconns; j++) { 6263 if (!w->connsenable[j]) 6264 continue; 6265 cw = hdac_widget_get(devinfo, w->conns[j]); 6266 if (cw == NULL || cw->enable == 0) 6267 continue; 6268 if (cw->bindas == -1) 6269 continue; 6270 if (cw->bindas >= 0 && 6271 as[cw->bindas].dir != HDA_CTL_IN) 6272 continue; 6273 hdac_audio_ctl_dest_amp(devinfo, 6274 w->nid, j, SOUND_MIXER_IGAIN, 0, 1); 6275 } 6276 } 6277 } 6278 /* Treat unrequired as possible. */ 6279 i = 0; 6280 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6281 if (ctl->ossmask == 0) 6282 ctl->ossmask = ctl->possmask; 6283 } 6284 } 6285 6286 static void 6287 hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6288 { 6289 struct hdac_audio_as *as = devinfo->function.audio.as; 6290 struct hdac_widget *w; 6291 uint32_t pincap; 6292 int i; 6293 6294 for (i = 0; i < devinfo->nodecnt; i++) { 6295 w = &devinfo->widget[i]; 6296 if (w == NULL) 6297 continue; 6298 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6299 continue; 6300 6301 pincap = w->wclass.pin.cap; 6302 6303 /* Disable everything. */ 6304 w->wclass.pin.ctrl &= ~( 6305 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6306 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6307 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6308 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6309 6310 if (w->enable == 0 || 6311 w->bindas < 0 || as[w->bindas].enable == 0) { 6312 /* Pin is unused so left it disabled. */ 6313 continue; 6314 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6315 /* Input pin, configure for input. */ 6316 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6317 w->wclass.pin.ctrl |= 6318 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6319 6320 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6321 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6322 w->wclass.pin.ctrl |= 6323 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6324 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6325 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6326 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6327 w->wclass.pin.ctrl |= 6328 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6329 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6330 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6331 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6332 w->wclass.pin.ctrl |= 6333 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6334 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6335 } else { 6336 /* Output pin, configure for output. */ 6337 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6338 w->wclass.pin.ctrl |= 6339 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6340 6341 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6342 (w->wclass.pin.config & 6343 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6344 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6345 w->wclass.pin.ctrl |= 6346 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6347 6348 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6349 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6350 w->wclass.pin.ctrl |= 6351 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6352 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6353 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6354 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6355 w->wclass.pin.ctrl |= 6356 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6357 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6358 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6359 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6360 w->wclass.pin.ctrl |= 6361 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6362 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6363 } 6364 } 6365 } 6366 6367 static void 6368 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6369 { 6370 struct hdac_audio_ctl *ctl; 6371 int i, z; 6372 6373 i = 0; 6374 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6375 if (ctl->enable == 0 || ctl->ossmask != 0) { 6376 /* Mute disabled and mixer controllable controls. 6377 * Last will be initialized by mixer_init(). 6378 * This expected to reduce click on startup. */ 6379 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6380 continue; 6381 } 6382 /* Init fixed controls to 0dB amplification. */ 6383 z = ctl->offset; 6384 if (z > ctl->step) 6385 z = ctl->step; 6386 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6387 } 6388 } 6389 6390 static void 6391 hdac_audio_commit(struct hdac_devinfo *devinfo) 6392 { 6393 struct hdac_softc *sc = devinfo->codec->sc; 6394 struct hdac_widget *w; 6395 nid_t cad; 6396 uint32_t gdata, gmask, gdir; 6397 int commitgpio, numgpio; 6398 int i; 6399 6400 cad = devinfo->codec->cad; 6401 6402 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6403 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6404 0x7e7, 0), cad); 6405 6406 /* Commit controls. */ 6407 hdac_audio_ctl_commit(devinfo); 6408 6409 /* Commit selectors, pins and EAPD. */ 6410 for (i = 0; i < devinfo->nodecnt; i++) { 6411 w = &devinfo->widget[i]; 6412 if (w == NULL) 6413 continue; 6414 if (w->selconn == -1) 6415 w->selconn = 0; 6416 if (w->nconns > 0) 6417 hdac_widget_connection_select(w, w->selconn); 6418 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6419 hdac_command(sc, 6420 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6421 w->wclass.pin.ctrl), cad); 6422 } 6423 if (w->param.eapdbtl != HDAC_INVALID) { 6424 uint32_t val; 6425 6426 val = w->param.eapdbtl; 6427 if (devinfo->function.audio.quirks & 6428 HDA_QUIRK_EAPDINV) 6429 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6430 hdac_command(sc, 6431 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6432 val), cad); 6433 } 6434 } 6435 6436 /* Commit GPIOs. */ 6437 gdata = 0; 6438 gmask = 0; 6439 gdir = 0; 6440 commitgpio = 0; 6441 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6442 devinfo->function.audio.gpio); 6443 6444 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6445 commitgpio = (numgpio > 0) ? 1 : 0; 6446 else { 6447 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6448 if (!(devinfo->function.audio.quirks & 6449 (1 << i))) 6450 continue; 6451 if (commitgpio == 0) { 6452 commitgpio = 1; 6453 HDA_BOOTVERBOSE( 6454 gdata = hdac_command(sc, 6455 HDA_CMD_GET_GPIO_DATA(cad, 6456 devinfo->nid), cad); 6457 gmask = hdac_command(sc, 6458 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6459 devinfo->nid), cad); 6460 gdir = hdac_command(sc, 6461 HDA_CMD_GET_GPIO_DIRECTION(cad, 6462 devinfo->nid), cad); 6463 device_printf(sc->dev, 6464 "GPIO init: data=0x%08x " 6465 "mask=0x%08x dir=0x%08x\n", 6466 gdata, gmask, gdir); 6467 gdata = 0; 6468 gmask = 0; 6469 gdir = 0; 6470 ); 6471 } 6472 gdata |= 1 << i; 6473 gmask |= 1 << i; 6474 gdir |= 1 << i; 6475 } 6476 } 6477 6478 if (commitgpio != 0) { 6479 HDA_BOOTVERBOSE( 6480 device_printf(sc->dev, 6481 "GPIO commit: data=0x%08x mask=0x%08x " 6482 "dir=0x%08x\n", 6483 gdata, gmask, gdir); 6484 ); 6485 hdac_command(sc, 6486 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6487 gmask), cad); 6488 hdac_command(sc, 6489 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6490 gdir), cad); 6491 hdac_command(sc, 6492 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6493 gdata), cad); 6494 } 6495 } 6496 6497 static void 6498 hdac_powerup(struct hdac_devinfo *devinfo) 6499 { 6500 struct hdac_softc *sc = devinfo->codec->sc; 6501 nid_t cad = devinfo->codec->cad; 6502 int i; 6503 6504 hdac_command(sc, 6505 HDA_CMD_SET_POWER_STATE(cad, 6506 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6507 cad); 6508 DELAY(100); 6509 6510 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6511 hdac_command(sc, 6512 HDA_CMD_SET_POWER_STATE(cad, 6513 i, HDA_CMD_POWER_STATE_D0), 6514 cad); 6515 } 6516 DELAY(1000); 6517 } 6518 6519 static int 6520 hdac_pcmchannel_setup(struct hdac_chan *ch) 6521 { 6522 struct hdac_devinfo *devinfo = ch->devinfo; 6523 struct hdac_audio_as *as = devinfo->function.audio.as; 6524 struct hdac_widget *w; 6525 uint32_t cap, fmtcap, pcmcap; 6526 int i, j, ret, channels, onlystereo; 6527 uint16_t pinset; 6528 6529 ch->caps = hdac_caps; 6530 ch->caps.fmtlist = ch->fmtlist; 6531 ch->bit16 = 1; 6532 ch->bit32 = 0; 6533 ch->pcmrates[0] = 48000; 6534 ch->pcmrates[1] = 0; 6535 6536 ret = 0; 6537 channels = 0; 6538 onlystereo = 1; 6539 pinset = 0; 6540 fmtcap = devinfo->function.audio.supp_stream_formats; 6541 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6542 6543 for (i = 0; i < 16; i++) { 6544 /* Check as is correct */ 6545 if (ch->as < 0) 6546 break; 6547 /* Cound only present DACs */ 6548 if (as[ch->as].dacs[i] <= 0) 6549 continue; 6550 /* Ignore duplicates */ 6551 for (j = 0; j < ret; j++) { 6552 if (ch->io[j] == as[ch->as].dacs[i]) 6553 break; 6554 } 6555 if (j < ret) 6556 continue; 6557 6558 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6559 if (w == NULL || w->enable == 0) 6560 continue; 6561 cap = w->param.supp_stream_formats; 6562 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6563 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6564 continue; 6565 /* Many CODECs does not declare AC3 support on SPDIF. 6566 I don't beleave that they doesn't support it! */ 6567 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6568 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6569 if (ret == 0) { 6570 fmtcap = cap; 6571 pcmcap = w->param.supp_pcm_size_rate; 6572 } else { 6573 fmtcap &= cap; 6574 pcmcap &= w->param.supp_pcm_size_rate; 6575 } 6576 ch->io[ret++] = as[ch->as].dacs[i]; 6577 /* Do not count redirection pin/dac channels. */ 6578 if (i == 15 && as[ch->as].hpredir >= 0) 6579 continue; 6580 channels += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 6581 if (HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) != 1) 6582 onlystereo = 0; 6583 pinset |= (1 << i); 6584 } 6585 ch->io[ret] = -1; 6586 6587 if (as[ch->as].fakeredir) 6588 ret--; 6589 /* Standard speaks only about stereo pins and playback, ... */ 6590 if ((!onlystereo) || as[ch->as].dir != HDA_CTL_OUT) 6591 pinset = 0; 6592 /* ..., but there it gives us info about speakers layout. */ 6593 as[ch->as].pinset = pinset; 6594 6595 ch->supp_stream_formats = fmtcap; 6596 ch->supp_pcm_size_rate = pcmcap; 6597 6598 /* 6599 * 8bit = 0 6600 * 16bit = 1 6601 * 20bit = 2 6602 * 24bit = 3 6603 * 32bit = 4 6604 */ 6605 if (ret > 0) { 6606 i = 0; 6607 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6608 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6609 ch->bit16 = 1; 6610 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6611 ch->bit16 = 0; 6612 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6613 ch->bit32 = 4; 6614 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6615 ch->bit32 = 3; 6616 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6617 ch->bit32 = 2; 6618 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) { 6619 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 1, 0); 6620 if (ch->bit32) 6621 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 1, 0); 6622 } 6623 if (channels >= 2) { 6624 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6625 if (ch->bit32) 6626 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 2, 0); 6627 } 6628 if (channels == 4 || /* Any 4-channel */ 6629 pinset == 0x0007 || /* 5.1 */ 6630 pinset == 0x0013 || /* 5.1 */ 6631 pinset == 0x0017) { /* 7.1 */ 6632 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 4, 0); 6633 if (ch->bit32) 6634 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 4, 0); 6635 } 6636 if (channels == 6 || /* Any 6-channel */ 6637 pinset == 0x0017) { /* 7.1 */ 6638 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 6, 1); 6639 if (ch->bit32) 6640 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 6, 1); 6641 } 6642 if (channels == 8) { /* Any 8-channel */ 6643 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 8, 1); 6644 if (ch->bit32) 6645 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 8, 1); 6646 } 6647 } 6648 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6649 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6650 } 6651 ch->fmtlist[i] = 0; 6652 i = 0; 6653 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6654 ch->pcmrates[i++] = 8000; 6655 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6656 ch->pcmrates[i++] = 11025; 6657 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6658 ch->pcmrates[i++] = 16000; 6659 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6660 ch->pcmrates[i++] = 22050; 6661 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6662 ch->pcmrates[i++] = 32000; 6663 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6664 ch->pcmrates[i++] = 44100; 6665 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6666 ch->pcmrates[i++] = 48000; 6667 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6668 ch->pcmrates[i++] = 88200; 6669 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6670 ch->pcmrates[i++] = 96000; 6671 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6672 ch->pcmrates[i++] = 176400; 6673 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6674 ch->pcmrates[i++] = 192000; 6675 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6676 ch->pcmrates[i] = 0; 6677 if (i > 0) { 6678 ch->caps.minspeed = ch->pcmrates[0]; 6679 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6680 } 6681 } 6682 6683 return (ret); 6684 } 6685 6686 static void 6687 hdac_create_pcms(struct hdac_devinfo *devinfo) 6688 { 6689 struct hdac_softc *sc = devinfo->codec->sc; 6690 struct hdac_audio_as *as = devinfo->function.audio.as; 6691 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6692 6693 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6694 if (as[i].enable == 0) 6695 continue; 6696 if (as[i].dir == HDA_CTL_IN) { 6697 if (as[i].digital) 6698 drdev++; 6699 else 6700 ardev++; 6701 } else { 6702 if (as[i].digital) 6703 dpdev++; 6704 else 6705 apdev++; 6706 } 6707 } 6708 devinfo->function.audio.num_devs = 6709 max(ardev, apdev) + max(drdev, dpdev); 6710 devinfo->function.audio.devs = 6711 (struct hdac_pcm_devinfo *)malloc( 6712 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6713 M_HDAC, M_ZERO | M_NOWAIT); 6714 if (devinfo->function.audio.devs == NULL) { 6715 device_printf(sc->dev, 6716 "Unable to allocate memory for devices\n"); 6717 return; 6718 } 6719 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6720 devinfo->function.audio.devs[i].index = i; 6721 devinfo->function.audio.devs[i].devinfo = devinfo; 6722 devinfo->function.audio.devs[i].play = -1; 6723 devinfo->function.audio.devs[i].rec = -1; 6724 devinfo->function.audio.devs[i].digital = 255; 6725 } 6726 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6727 if (as[i].enable == 0) 6728 continue; 6729 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6730 if (devinfo->function.audio.devs[j].digital != 255 && 6731 (!devinfo->function.audio.devs[j].digital) != 6732 (!as[i].digital)) 6733 continue; 6734 if (as[i].dir == HDA_CTL_IN) { 6735 if (devinfo->function.audio.devs[j].rec >= 0) 6736 continue; 6737 devinfo->function.audio.devs[j].rec 6738 = as[i].chan; 6739 } else { 6740 if (devinfo->function.audio.devs[j].play >= 0) 6741 continue; 6742 devinfo->function.audio.devs[j].play 6743 = as[i].chan; 6744 } 6745 sc->chans[as[i].chan].pdevinfo = 6746 &devinfo->function.audio.devs[j]; 6747 devinfo->function.audio.devs[j].digital = 6748 as[i].digital; 6749 break; 6750 } 6751 } 6752 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6753 struct hdac_pcm_devinfo *pdevinfo = 6754 &devinfo->function.audio.devs[i]; 6755 pdevinfo->dev = 6756 device_add_child(sc->dev, "pcm", -1); 6757 device_set_ivars(pdevinfo->dev, 6758 (void *)pdevinfo); 6759 } 6760 } 6761 6762 static void 6763 hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6764 { 6765 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6766 struct hdac_audio_ctl *ctl; 6767 struct hdac_softc *sc = devinfo->codec->sc; 6768 char buf[64]; 6769 int i, j, printed; 6770 6771 if (flag == 0) { 6772 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6773 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6774 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_IGAIN | 6775 SOUND_MASK_OGAIN | SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6776 } 6777 6778 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6779 if ((flag & (1 << j)) == 0) 6780 continue; 6781 i = 0; 6782 printed = 0; 6783 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6784 if (ctl->enable == 0 || 6785 ctl->widget->enable == 0) 6786 continue; 6787 if (!((pdevinfo->play >= 0 && 6788 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6789 (pdevinfo->rec >= 0 && 6790 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6791 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6792 continue; 6793 if ((ctl->ossmask & (1 << j)) == 0) 6794 continue; 6795 6796 if (printed == 0) { 6797 device_printf(pdevinfo->dev, "\n"); 6798 if (banner != NULL) { 6799 device_printf(pdevinfo->dev, "%s", banner); 6800 } else { 6801 device_printf(pdevinfo->dev, "Unknown Ctl"); 6802 } 6803 printf(" (OSS: %s)\n", 6804 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6805 buf, sizeof(buf))); 6806 device_printf(pdevinfo->dev, " |\n"); 6807 printed = 1; 6808 } 6809 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6810 ctl->widget->nid, 6811 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6812 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6813 printf(" %2d): ", ctl->index); 6814 else 6815 printf("): "); 6816 if (ctl->step > 0) { 6817 printf("%+d/%+ddB (%d steps)%s\n", 6818 (0 - ctl->offset) * (ctl->size + 1) / 4, 6819 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6820 ctl->step + 1, 6821 ctl->mute?" + mute":""); 6822 } else 6823 printf("%s\n", ctl->mute?"mute":""); 6824 } 6825 } 6826 } 6827 6828 static void 6829 hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6830 { 6831 uint32_t cap; 6832 6833 cap = fcap; 6834 if (cap != 0) { 6835 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6836 device_printf(dev, " "); 6837 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6838 printf(" AC3"); 6839 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6840 printf(" FLOAT32"); 6841 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6842 printf(" PCM"); 6843 printf("\n"); 6844 } 6845 cap = pcmcap; 6846 if (cap != 0) { 6847 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6848 device_printf(dev, " "); 6849 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6850 printf(" 8"); 6851 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6852 printf(" 16"); 6853 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6854 printf(" 20"); 6855 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6856 printf(" 24"); 6857 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6858 printf(" 32"); 6859 printf(" bits,"); 6860 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6861 printf(" 8"); 6862 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6863 printf(" 11"); 6864 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6865 printf(" 16"); 6866 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6867 printf(" 22"); 6868 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6869 printf(" 32"); 6870 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6871 printf(" 44"); 6872 printf(" 48"); 6873 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6874 printf(" 88"); 6875 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6876 printf(" 96"); 6877 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6878 printf(" 176"); 6879 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6880 printf(" 192"); 6881 printf(" KHz\n"); 6882 } 6883 } 6884 6885 static void 6886 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6887 { 6888 uint32_t pincap; 6889 6890 pincap = w->wclass.pin.cap; 6891 6892 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6893 device_printf(sc->dev, " "); 6894 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6895 printf(" ISC"); 6896 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6897 printf(" TRQD"); 6898 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6899 printf(" PDC"); 6900 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6901 printf(" HP"); 6902 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6903 printf(" OUT"); 6904 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6905 printf(" IN"); 6906 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6907 printf(" BAL"); 6908 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6909 printf(" HDMI"); 6910 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6911 printf(" VREF["); 6912 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6913 printf(" 50"); 6914 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6915 printf(" 80"); 6916 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6917 printf(" 100"); 6918 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6919 printf(" GROUND"); 6920 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6921 printf(" HIZ"); 6922 printf(" ]"); 6923 } 6924 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6925 printf(" EAPD"); 6926 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6927 printf(" DP"); 6928 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6929 printf(" HBR"); 6930 printf("\n"); 6931 device_printf(sc->dev, " Pin config: 0x%08x\n", 6932 w->wclass.pin.config); 6933 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6934 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6935 printf(" HP"); 6936 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6937 printf(" IN"); 6938 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6939 printf(" OUT"); 6940 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6941 printf(" VREFs"); 6942 printf("\n"); 6943 } 6944 6945 static void 6946 hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6947 { 6948 struct hdac_softc *sc = w->devinfo->codec->sc; 6949 6950 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6951 "jack %2d loc %2d color %7s misc %d%s\n", 6952 w->nid, conf, 6953 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6954 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6955 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6956 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6957 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6958 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6959 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6960 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6961 (w->enable == 0)?" [DISABLED]":""); 6962 } 6963 6964 static void 6965 hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6966 { 6967 struct hdac_widget *w; 6968 int i; 6969 6970 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6971 w = hdac_widget_get(devinfo, i); 6972 if (w == NULL) 6973 continue; 6974 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6975 continue; 6976 hdac_dump_pin_config(w, w->wclass.pin.config); 6977 } 6978 } 6979 6980 static void 6981 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6982 { 6983 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6984 device_printf(sc->dev, " " 6985 "mute=%d step=%d size=%d offset=%d\n", 6986 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6987 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6988 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6989 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6990 } 6991 6992 static void 6993 hdac_dump_nodes(struct hdac_devinfo *devinfo) 6994 { 6995 struct hdac_softc *sc = devinfo->codec->sc; 6996 static char *ossname[] = SOUND_DEVICE_NAMES; 6997 struct hdac_widget *w, *cw; 6998 char buf[64]; 6999 int i, j; 7000 7001 device_printf(sc->dev, "\n"); 7002 device_printf(sc->dev, "Default Parameter\n"); 7003 device_printf(sc->dev, "-----------------\n"); 7004 hdac_dump_audio_formats(sc->dev, 7005 devinfo->function.audio.supp_stream_formats, 7006 devinfo->function.audio.supp_pcm_size_rate); 7007 device_printf(sc->dev, " IN amp: 0x%08x\n", 7008 devinfo->function.audio.inamp_cap); 7009 device_printf(sc->dev, " OUT amp: 0x%08x\n", 7010 devinfo->function.audio.outamp_cap); 7011 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7012 w = hdac_widget_get(devinfo, i); 7013 if (w == NULL) { 7014 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 7015 continue; 7016 } 7017 device_printf(sc->dev, "\n"); 7018 device_printf(sc->dev, " nid: %d%s\n", w->nid, 7019 (w->enable == 0) ? " [DISABLED]" : ""); 7020 device_printf(sc->dev, " Name: %s\n", w->name); 7021 device_printf(sc->dev, " Widget cap: 0x%08x\n", 7022 w->param.widget_cap); 7023 if (w->param.widget_cap & 0x0ee1) { 7024 device_printf(sc->dev, " "); 7025 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 7026 printf(" LRSWAP"); 7027 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 7028 printf(" PWR"); 7029 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 7030 printf(" DIGITAL"); 7031 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 7032 printf(" UNSOL"); 7033 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 7034 printf(" PROC"); 7035 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 7036 printf(" STRIPE"); 7037 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 7038 if (j == 1) 7039 printf(" STEREO"); 7040 else if (j > 1) 7041 printf(" %dCH", j + 1); 7042 printf("\n"); 7043 } 7044 if (w->bindas != -1) { 7045 device_printf(sc->dev, " Association: %d (0x%08x)\n", 7046 w->bindas, w->bindseqmask); 7047 } 7048 if (w->ossmask != 0 || w->ossdev >= 0) { 7049 device_printf(sc->dev, " OSS: %s", 7050 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 7051 if (w->ossdev >= 0) 7052 printf(" (%s)", ossname[w->ossdev]); 7053 printf("\n"); 7054 } 7055 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 7056 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 7057 hdac_dump_audio_formats(sc->dev, 7058 w->param.supp_stream_formats, 7059 w->param.supp_pcm_size_rate); 7060 } else if (w->type == 7061 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7062 hdac_dump_pin(sc, w); 7063 if (w->param.eapdbtl != HDAC_INVALID) 7064 device_printf(sc->dev, " EAPD: 0x%08x\n", 7065 w->param.eapdbtl); 7066 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 7067 w->param.outamp_cap != 0) 7068 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 7069 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 7070 w->param.inamp_cap != 0) 7071 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 7072 if (w->nconns > 0) { 7073 device_printf(sc->dev, " connections: %d\n", w->nconns); 7074 device_printf(sc->dev, " |\n"); 7075 } 7076 for (j = 0; j < w->nconns; j++) { 7077 cw = hdac_widget_get(devinfo, w->conns[j]); 7078 device_printf(sc->dev, " + %s<- nid=%d [%s]", 7079 (w->connsenable[j] == 0)?"[DISABLED] ":"", 7080 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 7081 if (cw == NULL) 7082 printf(" [UNKNOWN]"); 7083 else if (cw->enable == 0) 7084 printf(" [DISABLED]"); 7085 if (w->nconns > 1 && w->selconn == j && w->type != 7086 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 7087 printf(" (selected)"); 7088 printf("\n"); 7089 } 7090 } 7091 7092 } 7093 7094 static void 7095 hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 7096 { 7097 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7098 struct hdac_widget *w, *cw; 7099 char buf[64]; 7100 int i, printed = 0; 7101 7102 if (depth > HDA_PARSE_MAXDEPTH) 7103 return; 7104 7105 w = hdac_widget_get(devinfo, nid); 7106 if (w == NULL || w->enable == 0) 7107 return; 7108 7109 if (depth == 0) 7110 device_printf(pdevinfo->dev, "%*s", 4, ""); 7111 else 7112 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 7113 printf("nid=%d [%s]", w->nid, w->name); 7114 7115 if (depth > 0) { 7116 if (w->ossmask == 0) { 7117 printf("\n"); 7118 return; 7119 } 7120 printf(" [src: %s]", 7121 hdac_audio_ctl_ossmixer_mask2allname( 7122 w->ossmask, buf, sizeof(buf))); 7123 if (w->ossdev >= 0) { 7124 printf("\n"); 7125 return; 7126 } 7127 } 7128 printf("\n"); 7129 7130 for (i = 0; i < w->nconns; i++) { 7131 if (w->connsenable[i] == 0) 7132 continue; 7133 cw = hdac_widget_get(devinfo, w->conns[i]); 7134 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 7135 continue; 7136 if (printed == 0) { 7137 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 7138 printed = 1; 7139 } 7140 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 7141 } 7142 7143 } 7144 7145 static void 7146 hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 7147 { 7148 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7149 struct hdac_softc *sc = devinfo->codec->sc; 7150 struct hdac_audio_as *as; 7151 struct hdac_widget *w; 7152 int i, printed = 0; 7153 7154 if (pdevinfo->play < 0) 7155 return; 7156 7157 as = &devinfo->function.audio.as[sc->chans[pdevinfo->play].as]; 7158 for (i = 0; i < 16; i++) { 7159 if (as->pins[i] <= 0) 7160 continue; 7161 w = hdac_widget_get(devinfo, as->pins[i]); 7162 if (w == NULL || w->enable == 0) 7163 continue; 7164 if (printed == 0) { 7165 printed = 1; 7166 device_printf(pdevinfo->dev, "\n"); 7167 device_printf(pdevinfo->dev, "Playback:\n"); 7168 } 7169 device_printf(pdevinfo->dev, "\n"); 7170 hdac_dump_dst_nid(pdevinfo, as->pins[i], 0); 7171 } 7172 } 7173 7174 static void 7175 hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7176 { 7177 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7178 struct hdac_softc *sc = devinfo->codec->sc; 7179 struct hdac_widget *w; 7180 int i; 7181 int printed = 0; 7182 7183 if (pdevinfo->rec < 0) 7184 return; 7185 7186 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7187 w = hdac_widget_get(devinfo, i); 7188 if (w == NULL || w->enable == 0) 7189 continue; 7190 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7191 continue; 7192 if (w->bindas != sc->chans[pdevinfo->rec].as) 7193 continue; 7194 if (printed == 0) { 7195 printed = 1; 7196 device_printf(pdevinfo->dev, "\n"); 7197 device_printf(pdevinfo->dev, "Record:\n"); 7198 } 7199 device_printf(pdevinfo->dev, "\n"); 7200 hdac_dump_dst_nid(pdevinfo, i, 0); 7201 } 7202 } 7203 7204 static void 7205 hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7206 { 7207 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7208 struct hdac_widget *w; 7209 int i; 7210 int printed = 0; 7211 7212 if (pdevinfo->index != 0) 7213 return; 7214 7215 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7216 w = hdac_widget_get(devinfo, i); 7217 if (w == NULL || w->enable == 0) 7218 continue; 7219 if (w->ossdev != SOUND_MIXER_IMIX) 7220 continue; 7221 if (printed == 0) { 7222 printed = 1; 7223 device_printf(pdevinfo->dev, "\n"); 7224 device_printf(pdevinfo->dev, "Input Mix:\n"); 7225 } 7226 device_printf(pdevinfo->dev, "\n"); 7227 hdac_dump_dst_nid(pdevinfo, i, 0); 7228 } 7229 } 7230 7231 static void 7232 hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7233 { 7234 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7235 nid_t *nids; 7236 int i; 7237 7238 if (pdevinfo->play >= 0) { 7239 i = pdevinfo->play; 7240 device_printf(pdevinfo->dev, "\n"); 7241 device_printf(pdevinfo->dev, "Playback:\n"); 7242 device_printf(pdevinfo->dev, "\n"); 7243 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7244 sc->chans[i].supp_pcm_size_rate); 7245 device_printf(pdevinfo->dev, " DAC:"); 7246 for (nids = sc->chans[i].io; *nids != -1; nids++) 7247 printf(" %d", *nids); 7248 printf("\n"); 7249 } 7250 if (pdevinfo->rec >= 0) { 7251 i = pdevinfo->rec; 7252 device_printf(pdevinfo->dev, "\n"); 7253 device_printf(pdevinfo->dev, "Record:\n"); 7254 device_printf(pdevinfo->dev, "\n"); 7255 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7256 sc->chans[i].supp_pcm_size_rate); 7257 device_printf(pdevinfo->dev, " ADC:"); 7258 for (nids = sc->chans[i].io; *nids != -1; nids++) 7259 printf(" %d", *nids); 7260 printf("\n"); 7261 } 7262 } 7263 7264 static void 7265 hdac_release_resources(struct hdac_softc *sc) 7266 { 7267 int i, j; 7268 7269 if (sc == NULL) 7270 return; 7271 7272 hdac_lock(sc); 7273 sc->polling = 0; 7274 sc->poll_ival = 0; 7275 callout_stop(&sc->poll_hda); 7276 callout_stop(&sc->poll_hdac); 7277 callout_stop(&sc->poll_jack); 7278 hdac_reset(sc, 0); 7279 hdac_unlock(sc); 7280 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7281 callout_drain(&sc->poll_hda); 7282 callout_drain(&sc->poll_hdac); 7283 callout_drain(&sc->poll_jack); 7284 7285 hdac_irq_free(sc); 7286 7287 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7288 if (sc->codecs[i] == NULL) 7289 continue; 7290 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7291 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7292 if (sc->codecs[i]->fgs[j].node_type == 7293 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7294 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7295 M_HDAC); 7296 free(sc->codecs[i]->fgs[j].function.audio.as, 7297 M_HDAC); 7298 free(sc->codecs[i]->fgs[j].function.audio.devs, 7299 M_HDAC); 7300 } 7301 } 7302 free(sc->codecs[i]->fgs, M_HDAC); 7303 free(sc->codecs[i], M_HDAC); 7304 sc->codecs[i] = NULL; 7305 } 7306 7307 hdac_dma_free(sc, &sc->pos_dma); 7308 hdac_dma_free(sc, &sc->rirb_dma); 7309 hdac_dma_free(sc, &sc->corb_dma); 7310 for (i = 0; i < sc->num_chans; i++) { 7311 if (sc->chans[i].blkcnt > 0) 7312 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7313 } 7314 free(sc->chans, M_HDAC); 7315 if (sc->chan_dmat != NULL) { 7316 bus_dma_tag_destroy(sc->chan_dmat); 7317 sc->chan_dmat = NULL; 7318 } 7319 hdac_mem_free(sc); 7320 snd_mtxfree(sc->lock); 7321 } 7322 7323 /* This function surely going to make its way into upper level someday. */ 7324 static void 7325 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7326 { 7327 const char *res = NULL; 7328 int i = 0, j, k, len, inv; 7329 7330 if (on != NULL) 7331 *on = 0; 7332 if (off != NULL) 7333 *off = 0; 7334 if (sc == NULL) 7335 return; 7336 if (resource_string_value(device_get_name(sc->dev), 7337 device_get_unit(sc->dev), "config", &res) != 0) 7338 return; 7339 if (!(res != NULL && strlen(res) > 0)) 7340 return; 7341 HDA_BOOTVERBOSE( 7342 device_printf(sc->dev, "HDA Config:"); 7343 ); 7344 for (;;) { 7345 while (res[i] != '\0' && 7346 (res[i] == ',' || isspace(res[i]) != 0)) 7347 i++; 7348 if (res[i] == '\0') { 7349 HDA_BOOTVERBOSE( 7350 printf("\n"); 7351 ); 7352 return; 7353 } 7354 j = i; 7355 while (res[j] != '\0' && 7356 !(res[j] == ',' || isspace(res[j]) != 0)) 7357 j++; 7358 len = j - i; 7359 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7360 inv = 2; 7361 else 7362 inv = 0; 7363 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7364 if (strncmp(res + i + inv, 7365 hdac_quirks_tab[k].key, len - inv) != 0) 7366 continue; 7367 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7368 continue; 7369 HDA_BOOTVERBOSE( 7370 printf(" %s%s", (inv != 0) ? "no" : "", 7371 hdac_quirks_tab[k].key); 7372 ); 7373 if (inv == 0 && on != NULL) 7374 *on |= hdac_quirks_tab[k].value; 7375 else if (inv != 0 && off != NULL) 7376 *off |= hdac_quirks_tab[k].value; 7377 break; 7378 } 7379 i = j; 7380 } 7381 } 7382 7383 static int 7384 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7385 { 7386 struct hdac_softc *sc; 7387 device_t dev; 7388 uint32_t ctl; 7389 int err, val; 7390 7391 dev = oidp->oid_arg1; 7392 sc = device_get_softc(dev); 7393 if (sc == NULL) 7394 return (EINVAL); 7395 hdac_lock(sc); 7396 val = sc->polling; 7397 hdac_unlock(sc); 7398 err = sysctl_handle_int(oidp, &val, 0, req); 7399 7400 if (err != 0 || req->newptr == NULL) 7401 return (err); 7402 if (val < 0 || val > 1) 7403 return (EINVAL); 7404 7405 hdac_lock(sc); 7406 if (val != sc->polling) { 7407 if (val == 0) { 7408 callout_stop(&sc->poll_hda); 7409 callout_stop(&sc->poll_hdac); 7410 hdac_unlock(sc); 7411 callout_drain(&sc->poll_hda); 7412 callout_drain(&sc->poll_hdac); 7413 hdac_lock(sc); 7414 sc->polling = 0; 7415 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7416 ctl |= HDAC_INTCTL_GIE; 7417 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7418 } else { 7419 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7420 ctl &= ~HDAC_INTCTL_GIE; 7421 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7422 hdac_unlock(sc); 7423 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7424 hdac_lock(sc); 7425 sc->polling = 1; 7426 hdac_poll_reinit(sc); 7427 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7428 } 7429 } 7430 hdac_unlock(sc); 7431 7432 return (err); 7433 } 7434 7435 static int 7436 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7437 { 7438 struct hdac_softc *sc; 7439 device_t dev; 7440 int err, val; 7441 7442 dev = oidp->oid_arg1; 7443 sc = device_get_softc(dev); 7444 if (sc == NULL) 7445 return (EINVAL); 7446 hdac_lock(sc); 7447 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7448 hdac_unlock(sc); 7449 err = sysctl_handle_int(oidp, &val, 0, req); 7450 7451 if (err != 0 || req->newptr == NULL) 7452 return (err); 7453 7454 if (val < 1) 7455 val = 1; 7456 if (val > 5000) 7457 val = 5000; 7458 val = ((uint64_t)val * hz) / 1000; 7459 if (val < 1) 7460 val = 1; 7461 if (val > (hz * 5)) 7462 val = hz * 5; 7463 7464 hdac_lock(sc); 7465 sc->poll_ival = val; 7466 hdac_unlock(sc); 7467 7468 return (err); 7469 } 7470 7471 static int 7472 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7473 { 7474 struct hdac_softc *sc; 7475 struct hdac_codec *codec; 7476 struct hdac_devinfo *devinfo; 7477 struct hdac_widget *w; 7478 device_t dev; 7479 uint32_t res, pincap, delay; 7480 int codec_index, fg_index; 7481 int i, err, val; 7482 nid_t cad; 7483 7484 dev = oidp->oid_arg1; 7485 sc = device_get_softc(dev); 7486 if (sc == NULL) 7487 return (EINVAL); 7488 val = 0; 7489 err = sysctl_handle_int(oidp, &val, 0, req); 7490 if (err != 0 || req->newptr == NULL || val == 0) 7491 return (err); 7492 7493 /* XXX: Temporary. For debugging. */ 7494 if (val == 100) { 7495 hdac_suspend(dev); 7496 return (0); 7497 } else if (val == 101) { 7498 hdac_resume(dev); 7499 return (0); 7500 } 7501 7502 hdac_lock(sc); 7503 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7504 codec = sc->codecs[codec_index]; 7505 if (codec == NULL) 7506 continue; 7507 cad = codec->cad; 7508 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7509 devinfo = &codec->fgs[fg_index]; 7510 if (devinfo->node_type != 7511 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7512 continue; 7513 7514 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7515 codec_index, devinfo->nid); 7516 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7517 w = hdac_widget_get(devinfo, i); 7518 if (w == NULL || w->type != 7519 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7520 continue; 7521 hdac_dump_pin_config(w, w->wclass.pin.config); 7522 pincap = w->wclass.pin.cap; 7523 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7524 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7525 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7526 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7527 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7528 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7529 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7530 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7531 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7532 delay = 0; 7533 hdac_command(sc, 7534 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7535 do { 7536 res = hdac_command(sc, 7537 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7538 if (res != 0x7fffffff && res != 0xffffffff) 7539 break; 7540 DELAY(10); 7541 } while (++delay < 10000); 7542 } else { 7543 delay = 0; 7544 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7545 w->nid), cad); 7546 } 7547 printf(" Sense: 0x%08x", res); 7548 if (delay > 0) 7549 printf(" delay %dus", delay * 10); 7550 } 7551 printf("\n"); 7552 } 7553 device_printf(dev, 7554 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7555 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7556 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7557 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7558 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7559 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7560 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7561 device_printf(dev, " GPI:"); 7562 res = hdac_command(sc, 7563 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7564 printf(" data=0x%08x", res); 7565 res = hdac_command(sc, 7566 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7567 cad); 7568 printf(" wake=0x%08x", res); 7569 res = hdac_command(sc, 7570 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7571 cad); 7572 printf(" unsol=0x%08x", res); 7573 res = hdac_command(sc, 7574 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7575 printf(" sticky=0x%08x\n", res); 7576 } 7577 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7578 device_printf(dev, " GPO:"); 7579 res = hdac_command(sc, 7580 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7581 printf(" data=0x%08x\n", res); 7582 } 7583 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7584 device_printf(dev, "GPIO:"); 7585 res = hdac_command(sc, 7586 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7587 printf(" data=0x%08x", res); 7588 res = hdac_command(sc, 7589 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7590 printf(" enable=0x%08x", res); 7591 res = hdac_command(sc, 7592 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7593 printf(" direction=0x%08x\n", res); 7594 res = hdac_command(sc, 7595 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7596 device_printf(dev, " wake=0x%08x", res); 7597 res = hdac_command(sc, 7598 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7599 cad); 7600 printf(" unsol=0x%08x", res); 7601 res = hdac_command(sc, 7602 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7603 printf(" sticky=0x%08x\n", res); 7604 } 7605 } 7606 } 7607 hdac_unlock(sc); 7608 return (0); 7609 } 7610 7611 static void 7612 hdac_attach2(void *arg) 7613 { 7614 struct hdac_codec *codec; 7615 struct hdac_softc *sc; 7616 struct hdac_audio_ctl *ctl; 7617 uint32_t quirks_on, quirks_off; 7618 int codec_index, fg_index; 7619 int i, dmaalloc = 0; 7620 struct hdac_devinfo *devinfo; 7621 7622 sc = (struct hdac_softc *)arg; 7623 7624 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7625 7626 HDA_BOOTHVERBOSE( 7627 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7628 quirks_on, quirks_off); 7629 ); 7630 7631 hdac_lock(sc); 7632 7633 /* Remove ourselves from the config hooks */ 7634 if (sc->intrhook.ich_func != NULL) { 7635 config_intrhook_disestablish(&sc->intrhook); 7636 sc->intrhook.ich_func = NULL; 7637 } 7638 7639 /* Start the corb and rirb engines */ 7640 HDA_BOOTHVERBOSE( 7641 device_printf(sc->dev, "Starting CORB Engine...\n"); 7642 ); 7643 hdac_corb_start(sc); 7644 HDA_BOOTHVERBOSE( 7645 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7646 ); 7647 hdac_rirb_start(sc); 7648 7649 HDA_BOOTHVERBOSE( 7650 device_printf(sc->dev, 7651 "Enabling controller interrupt...\n"); 7652 ); 7653 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7654 HDAC_GCTL_UNSOL); 7655 if (sc->polling == 0) { 7656 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7657 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7658 } else { 7659 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7660 } 7661 DELAY(1000); 7662 7663 HDA_BOOTHVERBOSE( 7664 device_printf(sc->dev, 7665 "Scanning HDA codecs ...\n"); 7666 ); 7667 hdac_scan_codecs(sc); 7668 7669 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7670 codec = sc->codecs[codec_index]; 7671 if (codec == NULL) 7672 continue; 7673 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7674 devinfo = &codec->fgs[fg_index]; 7675 HDA_BOOTVERBOSE( 7676 device_printf(sc->dev, "\n"); 7677 device_printf(sc->dev, 7678 "Processing %s FG cad=%d nid=%d...\n", 7679 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7680 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7681 "unknown", 7682 devinfo->codec->cad, devinfo->nid); 7683 ); 7684 if (devinfo->node_type != 7685 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7686 HDA_BOOTHVERBOSE( 7687 device_printf(sc->dev, 7688 "Powering down...\n"); 7689 ); 7690 hdac_command(sc, 7691 HDA_CMD_SET_POWER_STATE(codec->cad, 7692 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7693 codec->cad); 7694 continue; 7695 } 7696 7697 HDA_BOOTHVERBOSE( 7698 device_printf(sc->dev, "Powering up...\n"); 7699 ); 7700 hdac_powerup(devinfo); 7701 HDA_BOOTHVERBOSE( 7702 device_printf(sc->dev, "Parsing audio FG...\n"); 7703 ); 7704 hdac_audio_parse(devinfo); 7705 HDA_BOOTHVERBOSE( 7706 device_printf(sc->dev, "Parsing Ctls...\n"); 7707 ); 7708 hdac_audio_ctl_parse(devinfo); 7709 HDA_BOOTHVERBOSE( 7710 device_printf(sc->dev, "Parsing vendor patch...\n"); 7711 ); 7712 hdac_vendor_patch_parse(devinfo); 7713 devinfo->function.audio.quirks |= quirks_on; 7714 devinfo->function.audio.quirks &= ~quirks_off; 7715 7716 HDA_BOOTHVERBOSE( 7717 device_printf(sc->dev, "Disabling nonaudio...\n"); 7718 ); 7719 hdac_audio_disable_nonaudio(devinfo); 7720 HDA_BOOTHVERBOSE( 7721 device_printf(sc->dev, "Disabling useless...\n"); 7722 ); 7723 hdac_audio_disable_useless(devinfo); 7724 HDA_BOOTVERBOSE( 7725 device_printf(sc->dev, "Patched pins configuration:\n"); 7726 hdac_dump_pin_configs(devinfo); 7727 ); 7728 HDA_BOOTHVERBOSE( 7729 device_printf(sc->dev, "Parsing pin associations...\n"); 7730 ); 7731 hdac_audio_as_parse(devinfo); 7732 HDA_BOOTHVERBOSE( 7733 device_printf(sc->dev, "Building AFG tree...\n"); 7734 ); 7735 hdac_audio_build_tree(devinfo); 7736 HDA_BOOTHVERBOSE( 7737 device_printf(sc->dev, "Disabling unassociated " 7738 "widgets...\n"); 7739 ); 7740 hdac_audio_disable_unas(devinfo); 7741 HDA_BOOTHVERBOSE( 7742 device_printf(sc->dev, "Disabling nonselected " 7743 "inputs...\n"); 7744 ); 7745 hdac_audio_disable_notselected(devinfo); 7746 HDA_BOOTHVERBOSE( 7747 device_printf(sc->dev, "Disabling useless...\n"); 7748 ); 7749 hdac_audio_disable_useless(devinfo); 7750 HDA_BOOTHVERBOSE( 7751 device_printf(sc->dev, "Disabling " 7752 "crossassociatement connections...\n"); 7753 ); 7754 hdac_audio_disable_crossas(devinfo); 7755 HDA_BOOTHVERBOSE( 7756 device_printf(sc->dev, "Disabling useless...\n"); 7757 ); 7758 hdac_audio_disable_useless(devinfo); 7759 HDA_BOOTHVERBOSE( 7760 device_printf(sc->dev, "Binding associations to channels...\n"); 7761 ); 7762 hdac_audio_bind_as(devinfo); 7763 HDA_BOOTHVERBOSE( 7764 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7765 ); 7766 hdac_audio_assign_names(devinfo); 7767 HDA_BOOTHVERBOSE( 7768 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7769 ); 7770 hdac_audio_assign_mixers(devinfo); 7771 HDA_BOOTHVERBOSE( 7772 device_printf(sc->dev, "Preparing pin controls...\n"); 7773 ); 7774 hdac_audio_prepare_pin_ctrl(devinfo); 7775 HDA_BOOTHVERBOSE( 7776 device_printf(sc->dev, "AFG commit...\n"); 7777 ); 7778 hdac_audio_commit(devinfo); 7779 HDA_BOOTHVERBOSE( 7780 device_printf(sc->dev, "HP switch init...\n"); 7781 ); 7782 hdac_hp_switch_init(devinfo); 7783 7784 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7785 dmaalloc == 0) { 7786 if (hdac_dma_alloc(sc, &sc->pos_dma, 7787 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7788 HDA_BOOTVERBOSE( 7789 device_printf(sc->dev, "Failed to " 7790 "allocate DMA pos buffer " 7791 "(non-fatal)\n"); 7792 ); 7793 } else 7794 dmaalloc = 1; 7795 } 7796 7797 HDA_BOOTHVERBOSE( 7798 device_printf(sc->dev, "Creating PCM devices...\n"); 7799 ); 7800 hdac_create_pcms(devinfo); 7801 7802 HDA_BOOTVERBOSE( 7803 if (devinfo->function.audio.quirks != 0) { 7804 device_printf(sc->dev, "FG config/quirks:"); 7805 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7806 if ((devinfo->function.audio.quirks & 7807 hdac_quirks_tab[i].value) == 7808 hdac_quirks_tab[i].value) 7809 printf(" %s", hdac_quirks_tab[i].key); 7810 } 7811 printf("\n"); 7812 } 7813 7814 device_printf(sc->dev, "\n"); 7815 device_printf(sc->dev, "+-------------------+\n"); 7816 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7817 device_printf(sc->dev, "+-------------------+\n"); 7818 hdac_dump_nodes(devinfo); 7819 ); 7820 7821 HDA_BOOTHVERBOSE( 7822 device_printf(sc->dev, "\n"); 7823 device_printf(sc->dev, "+------------------------+\n"); 7824 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7825 device_printf(sc->dev, "+------------------------+\n"); 7826 device_printf(sc->dev, "\n"); 7827 i = 0; 7828 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7829 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7830 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7831 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7832 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7833 ctl->index); 7834 if (ctl->childwidget != NULL) 7835 printf(" cnid %3d", ctl->childwidget->nid); 7836 else 7837 printf(" "); 7838 printf(" ossmask=0x%08x\n", 7839 ctl->ossmask); 7840 device_printf(sc->dev, 7841 " mute: %d step: %3d size: %3d off: %3d%s\n", 7842 ctl->mute, ctl->step, ctl->size, ctl->offset, 7843 (ctl->enable == 0) ? " [DISABLED]" : 7844 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7845 } 7846 ); 7847 } 7848 } 7849 hdac_unlock(sc); 7850 7851 HDA_BOOTVERBOSE( 7852 device_printf(sc->dev, "\n"); 7853 ); 7854 7855 bus_generic_attach(sc->dev); 7856 7857 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7858 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7859 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7860 sysctl_hdac_polling, "I", "Enable polling mode"); 7861 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7862 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7863 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7864 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7865 "Controller/Jack Sense polling interval (1-1000 ms)"); 7866 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7867 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7868 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7869 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7870 } 7871 7872 /**************************************************************************** 7873 * int hdac_suspend(device_t) 7874 * 7875 * Suspend and power down HDA bus and codecs. 7876 ****************************************************************************/ 7877 static int 7878 hdac_suspend(device_t dev) 7879 { 7880 struct hdac_softc *sc; 7881 struct hdac_codec *codec; 7882 struct hdac_devinfo *devinfo; 7883 int codec_index, fg_index, i; 7884 7885 HDA_BOOTHVERBOSE( 7886 device_printf(dev, "Suspend...\n"); 7887 ); 7888 7889 sc = device_get_softc(dev); 7890 hdac_lock(sc); 7891 7892 HDA_BOOTHVERBOSE( 7893 device_printf(dev, "Stop streams...\n"); 7894 ); 7895 for (i = 0; i < sc->num_chans; i++) { 7896 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7897 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7898 hdac_channel_stop(sc, &sc->chans[i]); 7899 } 7900 } 7901 7902 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7903 codec = sc->codecs[codec_index]; 7904 if (codec == NULL) 7905 continue; 7906 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7907 devinfo = &codec->fgs[fg_index]; 7908 HDA_BOOTHVERBOSE( 7909 device_printf(dev, 7910 "Power down FG" 7911 " cad=%d nid=%d to the D3 state...\n", 7912 codec->cad, devinfo->nid); 7913 ); 7914 hdac_command(sc, 7915 HDA_CMD_SET_POWER_STATE(codec->cad, 7916 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7917 codec->cad); 7918 } 7919 } 7920 7921 HDA_BOOTHVERBOSE( 7922 device_printf(dev, "Reset controller...\n"); 7923 ); 7924 callout_stop(&sc->poll_hda); 7925 callout_stop(&sc->poll_hdac); 7926 callout_stop(&sc->poll_jack); 7927 hdac_reset(sc, 0); 7928 hdac_unlock(sc); 7929 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7930 callout_drain(&sc->poll_hda); 7931 callout_drain(&sc->poll_hdac); 7932 callout_drain(&sc->poll_jack); 7933 7934 HDA_BOOTHVERBOSE( 7935 device_printf(dev, "Suspend done\n"); 7936 ); 7937 7938 return (0); 7939 } 7940 7941 /**************************************************************************** 7942 * int hdac_resume(device_t) 7943 * 7944 * Powerup and restore HDA bus and codecs state. 7945 ****************************************************************************/ 7946 static int 7947 hdac_resume(device_t dev) 7948 { 7949 struct hdac_softc *sc; 7950 struct hdac_codec *codec; 7951 struct hdac_devinfo *devinfo; 7952 int codec_index, fg_index, i; 7953 7954 HDA_BOOTHVERBOSE( 7955 device_printf(dev, "Resume...\n"); 7956 ); 7957 7958 sc = device_get_softc(dev); 7959 hdac_lock(sc); 7960 7961 /* Quiesce everything */ 7962 HDA_BOOTHVERBOSE( 7963 device_printf(dev, "Reset controller...\n"); 7964 ); 7965 hdac_reset(sc, 1); 7966 7967 /* Initialize the CORB and RIRB */ 7968 hdac_corb_init(sc); 7969 hdac_rirb_init(sc); 7970 7971 /* Start the corb and rirb engines */ 7972 HDA_BOOTHVERBOSE( 7973 device_printf(dev, "Starting CORB Engine...\n"); 7974 ); 7975 hdac_corb_start(sc); 7976 HDA_BOOTHVERBOSE( 7977 device_printf(dev, "Starting RIRB Engine...\n"); 7978 ); 7979 hdac_rirb_start(sc); 7980 7981 HDA_BOOTHVERBOSE( 7982 device_printf(dev, 7983 "Enabling controller interrupt...\n"); 7984 ); 7985 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7986 HDAC_GCTL_UNSOL); 7987 if (sc->polling == 0) { 7988 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7989 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7990 } else { 7991 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7992 } 7993 DELAY(1000); 7994 7995 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7996 codec = sc->codecs[codec_index]; 7997 if (codec == NULL) 7998 continue; 7999 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 8000 devinfo = &codec->fgs[fg_index]; 8001 if (devinfo->node_type != 8002 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 8003 HDA_BOOTHVERBOSE( 8004 device_printf(dev, 8005 "Power down unsupported non-audio FG" 8006 " cad=%d nid=%d to the D3 state...\n", 8007 codec->cad, devinfo->nid); 8008 ); 8009 hdac_command(sc, 8010 HDA_CMD_SET_POWER_STATE(codec->cad, 8011 devinfo->nid, HDA_CMD_POWER_STATE_D3), 8012 codec->cad); 8013 continue; 8014 } 8015 8016 HDA_BOOTHVERBOSE( 8017 device_printf(dev, 8018 "Power up audio FG cad=%d nid=%d...\n", 8019 devinfo->codec->cad, devinfo->nid); 8020 ); 8021 hdac_powerup(devinfo); 8022 HDA_BOOTHVERBOSE( 8023 device_printf(dev, "AFG commit...\n"); 8024 ); 8025 hdac_audio_commit(devinfo); 8026 HDA_BOOTHVERBOSE( 8027 device_printf(dev, "HP switch init...\n"); 8028 ); 8029 hdac_hp_switch_init(devinfo); 8030 8031 hdac_unlock(sc); 8032 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 8033 struct hdac_pcm_devinfo *pdevinfo = 8034 &devinfo->function.audio.devs[i]; 8035 HDA_BOOTHVERBOSE( 8036 device_printf(pdevinfo->dev, 8037 "OSS mixer reinitialization...\n"); 8038 ); 8039 if (mixer_reinit(pdevinfo->dev) == -1) 8040 device_printf(pdevinfo->dev, 8041 "unable to reinitialize the mixer\n"); 8042 } 8043 hdac_lock(sc); 8044 } 8045 } 8046 8047 HDA_BOOTHVERBOSE( 8048 device_printf(dev, "Start streams...\n"); 8049 ); 8050 for (i = 0; i < sc->num_chans; i++) { 8051 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 8052 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 8053 hdac_channel_start(sc, &sc->chans[i]); 8054 } 8055 } 8056 8057 hdac_unlock(sc); 8058 8059 HDA_BOOTHVERBOSE( 8060 device_printf(dev, "Resume done\n"); 8061 ); 8062 8063 return (0); 8064 } 8065 /**************************************************************************** 8066 * int hdac_detach(device_t) 8067 * 8068 * Detach and free up resources utilized by the hdac device. 8069 ****************************************************************************/ 8070 static int 8071 hdac_detach(device_t dev) 8072 { 8073 struct hdac_softc *sc; 8074 device_t *devlist; 8075 int i, devcount, error; 8076 8077 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 8078 return (error); 8079 for (i = 0; i < devcount; i++) { 8080 if ((error = device_delete_child(dev, devlist[i])) != 0) { 8081 free(devlist, M_TEMP); 8082 return (error); 8083 } 8084 } 8085 free(devlist, M_TEMP); 8086 8087 sc = device_get_softc(dev); 8088 hdac_release_resources(sc); 8089 8090 return (0); 8091 } 8092 8093 static int 8094 hdac_print_child(device_t dev, device_t child) 8095 { 8096 struct hdac_pcm_devinfo *pdevinfo = 8097 (struct hdac_pcm_devinfo *)device_get_ivars(child); 8098 int retval; 8099 8100 retval = bus_print_child_header(dev, child); 8101 retval += printf(" at cad %d nid %d", 8102 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 8103 retval += bus_print_child_footer(dev, child); 8104 8105 return (retval); 8106 } 8107 8108 static device_method_t hdac_methods[] = { 8109 /* device interface */ 8110 DEVMETHOD(device_probe, hdac_probe), 8111 DEVMETHOD(device_attach, hdac_attach), 8112 DEVMETHOD(device_detach, hdac_detach), 8113 DEVMETHOD(device_suspend, hdac_suspend), 8114 DEVMETHOD(device_resume, hdac_resume), 8115 /* Bus interface */ 8116 DEVMETHOD(bus_print_child, hdac_print_child), 8117 { 0, 0 } 8118 }; 8119 8120 static driver_t hdac_driver = { 8121 "hdac", 8122 hdac_methods, 8123 sizeof(struct hdac_softc), 8124 }; 8125 8126 static devclass_t hdac_devclass; 8127 8128 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 8129 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 8130 MODULE_VERSION(snd_hda, 1); 8131 8132 static int 8133 hdac_pcm_probe(device_t dev) 8134 { 8135 struct hdac_pcm_devinfo *pdevinfo = 8136 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8137 char buf[128]; 8138 8139 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 8140 hdac_codec_name(pdevinfo->devinfo->codec), 8141 pdevinfo->index, 8142 (pdevinfo->digital == 3)?"DisplayPort": 8143 ((pdevinfo->digital == 2)?"HDMI": 8144 ((pdevinfo->digital)?"Digital":"Analog"))); 8145 device_set_desc_copy(dev, buf); 8146 return (0); 8147 } 8148 8149 static int 8150 hdac_pcm_attach(device_t dev) 8151 { 8152 struct hdac_pcm_devinfo *pdevinfo = 8153 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8154 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 8155 char status[SND_STATUSLEN]; 8156 int i; 8157 8158 pdevinfo->chan_size = pcm_getbuffersize(dev, 8159 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8160 8161 HDA_BOOTVERBOSE( 8162 device_printf(dev, "+--------------------------------------+\n"); 8163 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8164 device_printf(dev, "+--------------------------------------+\n"); 8165 hdac_dump_pcmchannels(pdevinfo); 8166 device_printf(dev, "\n"); 8167 device_printf(dev, "+-------------------------------+\n"); 8168 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8169 device_printf(dev, "+-------------------------------+\n"); 8170 hdac_dump_dac(pdevinfo); 8171 hdac_dump_adc(pdevinfo); 8172 hdac_dump_mix(pdevinfo); 8173 device_printf(dev, "\n"); 8174 device_printf(dev, "+-------------------------+\n"); 8175 device_printf(dev, "| DUMPING Volume Controls |\n"); 8176 device_printf(dev, "+-------------------------+\n"); 8177 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8178 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8179 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8180 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8181 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8182 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8183 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8184 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8185 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8186 hdac_dump_ctls(pdevinfo, "Input Monitoring Level", SOUND_MASK_IGAIN); 8187 hdac_dump_ctls(pdevinfo, NULL, 0); 8188 device_printf(dev, "\n"); 8189 ); 8190 8191 if (resource_int_value(device_get_name(dev), 8192 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8193 i &= HDA_BLK_ALIGN; 8194 if (i < HDA_BLK_MIN) 8195 i = HDA_BLK_MIN; 8196 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8197 i = 0; 8198 while (pdevinfo->chan_blkcnt >> i) 8199 i++; 8200 pdevinfo->chan_blkcnt = 1 << (i - 1); 8201 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8202 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8203 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8204 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8205 } else 8206 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8207 8208 /* 8209 * We don't register interrupt handler with snd_setup_intr 8210 * in pcm device. Mark pcm device as MPSAFE manually. 8211 */ 8212 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8213 8214 HDA_BOOTHVERBOSE( 8215 device_printf(dev, "OSS mixer initialization...\n"); 8216 ); 8217 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8218 device_printf(dev, "Can't register mixer\n"); 8219 8220 HDA_BOOTHVERBOSE( 8221 device_printf(dev, "Registering PCM channels...\n"); 8222 ); 8223 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8224 (pdevinfo->rec >= 0)?1:0) != 0) 8225 device_printf(dev, "Can't register PCM\n"); 8226 8227 pdevinfo->registered++; 8228 8229 if (pdevinfo->play >= 0) 8230 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8231 if (pdevinfo->rec >= 0) 8232 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8233 8234 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8235 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8236 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8237 pcm_setstatus(dev, status); 8238 8239 return (0); 8240 } 8241 8242 static int 8243 hdac_pcm_detach(device_t dev) 8244 { 8245 struct hdac_pcm_devinfo *pdevinfo = 8246 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8247 int err; 8248 8249 if (pdevinfo->registered > 0) { 8250 err = pcm_unregister(dev); 8251 if (err != 0) 8252 return (err); 8253 } 8254 8255 return (0); 8256 } 8257 8258 static device_method_t hdac_pcm_methods[] = { 8259 /* device interface */ 8260 DEVMETHOD(device_probe, hdac_pcm_probe), 8261 DEVMETHOD(device_attach, hdac_pcm_attach), 8262 DEVMETHOD(device_detach, hdac_pcm_detach), 8263 { 0, 0 } 8264 }; 8265 8266 static driver_t hdac_pcm_driver = { 8267 "pcm", 8268 hdac_pcm_methods, 8269 PCM_SOFTC_SIZE, 8270 }; 8271 8272 DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8273 8274