1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 5 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Intel High Definition Audio (Controller) driver for FreeBSD. 33 */ 34 35 #ifdef HAVE_KERNEL_OPTION_HEADERS 36 #include "opt_snd.h" 37 #endif 38 39 #include <dev/sound/pcm/sound.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 43 #include <sys/ctype.h> 44 #include <sys/taskqueue.h> 45 46 #include <dev/sound/pci/hda/hdac_private.h> 47 #include <dev/sound/pci/hda/hdac_reg.h> 48 #include <dev/sound/pci/hda/hda_reg.h> 49 #include <dev/sound/pci/hda/hdac.h> 50 51 #define HDA_DRV_TEST_REV "20120126_0002" 52 53 SND_DECLARE_FILE("$FreeBSD$"); 54 55 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 56 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 57 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 58 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 59 60 #define HDAC_QUIRK_64BIT (1 << 0) 61 #define HDAC_QUIRK_DMAPOS (1 << 1) 62 #define HDAC_QUIRK_MSI (1 << 2) 63 64 static const struct { 65 const char *key; 66 uint32_t value; 67 } hdac_quirks_tab[] = { 68 { "64bit", HDAC_QUIRK_DMAPOS }, 69 { "dmapos", HDAC_QUIRK_DMAPOS }, 70 { "msi", HDAC_QUIRK_MSI }, 71 }; 72 73 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 74 75 static const struct { 76 uint32_t model; 77 const char *desc; 78 char quirks_on; 79 char quirks_off; 80 } hdac_devices[] = { 81 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 }, 82 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 }, 83 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 }, 84 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 }, 85 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 }, 86 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 }, 87 { HDA_INTEL_BDW2, "Intel Broadwell", 0, 0 }, 88 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 89 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 90 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 91 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 }, 92 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 }, 93 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 }, 94 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 }, 95 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 }, 96 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 }, 97 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 }, 98 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 }, 99 { HDA_INTEL_KBLKLP, "Intel Kabylake-LP", 0, 0 }, 100 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 }, 101 { HDA_INTEL_KBLK, "Intel Kabylake", 0, 0 }, 102 { HDA_INTEL_KBLKH, "Intel Kabylake-H", 0, 0 }, 103 { HDA_INTEL_CFLK, "Intel Coffelake", 0, 0 }, 104 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 105 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 106 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 107 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 108 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 109 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 110 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 111 { HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 }, 112 { HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 }, 113 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 114 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 115 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 116 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 117 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 118 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 119 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 120 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 121 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 122 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 123 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 124 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 125 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 126 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 127 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 128 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 129 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 130 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 131 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 132 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 133 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 134 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 135 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 136 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 137 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 138 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 139 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 140 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 141 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 142 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 143 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 144 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 145 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 146 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 147 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 148 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 149 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 150 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 151 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 152 { HDA_ATI_R600, "ATI R600", 0, 0 }, 153 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 154 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 155 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 156 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 157 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 158 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 159 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 160 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 161 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 162 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 163 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 164 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 165 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 166 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 167 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 168 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 169 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 170 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 }, 171 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 172 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 173 { HDA_SIS_966, "SiS 966", 0, 0 }, 174 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 175 /* Unknown */ 176 { HDA_INTEL_ALL, "Intel", 0, 0 }, 177 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 178 { HDA_ATI_ALL, "ATI", 0, 0 }, 179 { HDA_AMD_ALL, "AMD", 0, 0 }, 180 { HDA_CREATIVE_ALL, "Creative", 0, 0 }, 181 { HDA_VIA_ALL, "VIA", 0, 0 }, 182 { HDA_SIS_ALL, "SiS", 0, 0 }, 183 { HDA_ULI_ALL, "ULI", 0, 0 }, 184 }; 185 186 static const struct { 187 uint16_t vendor; 188 uint8_t reg; 189 uint8_t mask; 190 uint8_t enable; 191 } hdac_pcie_snoop[] = { 192 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 193 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 194 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 195 }; 196 197 /**************************************************************************** 198 * Function prototypes 199 ****************************************************************************/ 200 static void hdac_intr_handler(void *); 201 static int hdac_reset(struct hdac_softc *, int); 202 static int hdac_get_capabilities(struct hdac_softc *); 203 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 204 static int hdac_dma_alloc(struct hdac_softc *, 205 struct hdac_dma *, bus_size_t); 206 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 207 static int hdac_mem_alloc(struct hdac_softc *); 208 static void hdac_mem_free(struct hdac_softc *); 209 static int hdac_irq_alloc(struct hdac_softc *); 210 static void hdac_irq_free(struct hdac_softc *); 211 static void hdac_corb_init(struct hdac_softc *); 212 static void hdac_rirb_init(struct hdac_softc *); 213 static void hdac_corb_start(struct hdac_softc *); 214 static void hdac_rirb_start(struct hdac_softc *); 215 216 static void hdac_attach2(void *); 217 218 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 219 220 static int hdac_probe(device_t); 221 static int hdac_attach(device_t); 222 static int hdac_detach(device_t); 223 static int hdac_suspend(device_t); 224 static int hdac_resume(device_t); 225 226 static int hdac_rirb_flush(struct hdac_softc *sc); 227 static int hdac_unsolq_flush(struct hdac_softc *sc); 228 229 #define hdac_command(a1, a2, a3) \ 230 hdac_send_command(a1, a3, a2) 231 232 /* This function surely going to make its way into upper level someday. */ 233 static void 234 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 235 { 236 const char *res = NULL; 237 int i = 0, j, k, len, inv; 238 239 if (resource_string_value(device_get_name(sc->dev), 240 device_get_unit(sc->dev), "config", &res) != 0) 241 return; 242 if (!(res != NULL && strlen(res) > 0)) 243 return; 244 HDA_BOOTVERBOSE( 245 device_printf(sc->dev, "Config options:"); 246 ); 247 for (;;) { 248 while (res[i] != '\0' && 249 (res[i] == ',' || isspace(res[i]) != 0)) 250 i++; 251 if (res[i] == '\0') { 252 HDA_BOOTVERBOSE( 253 printf("\n"); 254 ); 255 return; 256 } 257 j = i; 258 while (res[j] != '\0' && 259 !(res[j] == ',' || isspace(res[j]) != 0)) 260 j++; 261 len = j - i; 262 if (len > 2 && strncmp(res + i, "no", 2) == 0) 263 inv = 2; 264 else 265 inv = 0; 266 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) { 267 if (strncmp(res + i + inv, 268 hdac_quirks_tab[k].key, len - inv) != 0) 269 continue; 270 if (len - inv != strlen(hdac_quirks_tab[k].key)) 271 continue; 272 HDA_BOOTVERBOSE( 273 printf(" %s%s", (inv != 0) ? "no" : "", 274 hdac_quirks_tab[k].key); 275 ); 276 if (inv == 0) { 277 *on |= hdac_quirks_tab[k].value; 278 *on &= ~hdac_quirks_tab[k].value; 279 } else if (inv != 0) { 280 *off |= hdac_quirks_tab[k].value; 281 *off &= ~hdac_quirks_tab[k].value; 282 } 283 break; 284 } 285 i = j; 286 } 287 } 288 289 /**************************************************************************** 290 * void hdac_intr_handler(void *) 291 * 292 * Interrupt handler. Processes interrupts received from the hdac. 293 ****************************************************************************/ 294 static void 295 hdac_intr_handler(void *context) 296 { 297 struct hdac_softc *sc; 298 device_t dev; 299 uint32_t intsts; 300 uint8_t rirbsts; 301 int i; 302 303 sc = (struct hdac_softc *)context; 304 hdac_lock(sc); 305 306 /* Do we have anything to do? */ 307 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 308 if ((intsts & HDAC_INTSTS_GIS) == 0) { 309 hdac_unlock(sc); 310 return; 311 } 312 313 /* Was this a controller interrupt? */ 314 if (intsts & HDAC_INTSTS_CIS) { 315 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 316 /* Get as many responses that we can */ 317 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 318 HDAC_WRITE_1(&sc->mem, 319 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 320 hdac_rirb_flush(sc); 321 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 322 } 323 if (sc->unsolq_rp != sc->unsolq_wp) 324 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 325 } 326 327 if (intsts & HDAC_INTSTS_SIS_MASK) { 328 for (i = 0; i < sc->num_ss; i++) { 329 if ((intsts & (1 << i)) == 0) 330 continue; 331 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 332 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 333 if ((dev = sc->streams[i].dev) != NULL) { 334 HDAC_STREAM_INTR(dev, 335 sc->streams[i].dir, sc->streams[i].stream); 336 } 337 } 338 } 339 340 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 341 hdac_unlock(sc); 342 } 343 344 static void 345 hdac_poll_callback(void *arg) 346 { 347 struct hdac_softc *sc = arg; 348 349 if (sc == NULL) 350 return; 351 352 hdac_lock(sc); 353 if (sc->polling == 0) { 354 hdac_unlock(sc); 355 return; 356 } 357 callout_reset(&sc->poll_callout, sc->poll_ival, 358 hdac_poll_callback, sc); 359 hdac_unlock(sc); 360 361 hdac_intr_handler(sc); 362 } 363 364 /**************************************************************************** 365 * int hdac_reset(hdac_softc *, int) 366 * 367 * Reset the hdac to a quiescent and known state. 368 ****************************************************************************/ 369 static int 370 hdac_reset(struct hdac_softc *sc, int wakeup) 371 { 372 uint32_t gctl; 373 int count, i; 374 375 /* 376 * Stop all Streams DMA engine 377 */ 378 for (i = 0; i < sc->num_iss; i++) 379 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 380 for (i = 0; i < sc->num_oss; i++) 381 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 382 for (i = 0; i < sc->num_bss; i++) 383 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 384 385 /* 386 * Stop Control DMA engines. 387 */ 388 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 389 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 390 391 /* 392 * Reset DMA position buffer. 393 */ 394 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 395 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 396 397 /* 398 * Reset the controller. The reset must remain asserted for 399 * a minimum of 100us. 400 */ 401 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 402 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 403 count = 10000; 404 do { 405 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 406 if (!(gctl & HDAC_GCTL_CRST)) 407 break; 408 DELAY(10); 409 } while (--count); 410 if (gctl & HDAC_GCTL_CRST) { 411 device_printf(sc->dev, "Unable to put hdac in reset\n"); 412 return (ENXIO); 413 } 414 415 /* If wakeup is not requested - leave the controller in reset state. */ 416 if (!wakeup) 417 return (0); 418 419 DELAY(100); 420 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 421 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 422 count = 10000; 423 do { 424 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 425 if (gctl & HDAC_GCTL_CRST) 426 break; 427 DELAY(10); 428 } while (--count); 429 if (!(gctl & HDAC_GCTL_CRST)) { 430 device_printf(sc->dev, "Device stuck in reset\n"); 431 return (ENXIO); 432 } 433 434 /* 435 * Wait for codecs to finish their own reset sequence. The delay here 436 * should be of 250us but for some reasons, it's not enough on my 437 * computer. Let's use twice as much as necessary to make sure that 438 * it's reset properly. 439 */ 440 DELAY(1000); 441 442 return (0); 443 } 444 445 446 /**************************************************************************** 447 * int hdac_get_capabilities(struct hdac_softc *); 448 * 449 * Retreive the general capabilities of the hdac; 450 * Number of Input Streams 451 * Number of Output Streams 452 * Number of bidirectional Streams 453 * 64bit ready 454 * CORB and RIRB sizes 455 ****************************************************************************/ 456 static int 457 hdac_get_capabilities(struct hdac_softc *sc) 458 { 459 uint16_t gcap; 460 uint8_t corbsize, rirbsize; 461 462 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 463 sc->num_iss = HDAC_GCAP_ISS(gcap); 464 sc->num_oss = HDAC_GCAP_OSS(gcap); 465 sc->num_bss = HDAC_GCAP_BSS(gcap); 466 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 467 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 468 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 469 if (sc->quirks_on & HDAC_QUIRK_64BIT) 470 sc->support_64bit = 1; 471 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 472 sc->support_64bit = 0; 473 474 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 475 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 476 HDAC_CORBSIZE_CORBSZCAP_256) 477 sc->corb_size = 256; 478 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 479 HDAC_CORBSIZE_CORBSZCAP_16) 480 sc->corb_size = 16; 481 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 482 HDAC_CORBSIZE_CORBSZCAP_2) 483 sc->corb_size = 2; 484 else { 485 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 486 __func__, corbsize); 487 return (ENXIO); 488 } 489 490 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 491 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 492 HDAC_RIRBSIZE_RIRBSZCAP_256) 493 sc->rirb_size = 256; 494 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 495 HDAC_RIRBSIZE_RIRBSZCAP_16) 496 sc->rirb_size = 16; 497 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 498 HDAC_RIRBSIZE_RIRBSZCAP_2) 499 sc->rirb_size = 2; 500 else { 501 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 502 __func__, rirbsize); 503 return (ENXIO); 504 } 505 506 HDA_BOOTVERBOSE( 507 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 508 "NSDO %d%s, CORB %d, RIRB %d\n", 509 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 510 sc->support_64bit ? ", 64bit" : "", 511 sc->corb_size, sc->rirb_size); 512 ); 513 514 return (0); 515 } 516 517 518 /**************************************************************************** 519 * void hdac_dma_cb 520 * 521 * This function is called by bus_dmamap_load when the mapping has been 522 * established. We just record the physical address of the mapping into 523 * the struct hdac_dma passed in. 524 ****************************************************************************/ 525 static void 526 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 527 { 528 struct hdac_dma *dma; 529 530 if (error == 0) { 531 dma = (struct hdac_dma *)callback_arg; 532 dma->dma_paddr = segs[0].ds_addr; 533 } 534 } 535 536 537 /**************************************************************************** 538 * int hdac_dma_alloc 539 * 540 * This function allocate and setup a dma region (struct hdac_dma). 541 * It must be freed by a corresponding hdac_dma_free. 542 ****************************************************************************/ 543 static int 544 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 545 { 546 bus_size_t roundsz; 547 int result; 548 549 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 550 bzero(dma, sizeof(*dma)); 551 552 /* 553 * Create a DMA tag 554 */ 555 result = bus_dma_tag_create( 556 bus_get_dma_tag(sc->dev), /* parent */ 557 HDA_DMA_ALIGNMENT, /* alignment */ 558 0, /* boundary */ 559 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 560 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 561 BUS_SPACE_MAXADDR, /* highaddr */ 562 NULL, /* filtfunc */ 563 NULL, /* fistfuncarg */ 564 roundsz, /* maxsize */ 565 1, /* nsegments */ 566 roundsz, /* maxsegsz */ 567 0, /* flags */ 568 NULL, /* lockfunc */ 569 NULL, /* lockfuncarg */ 570 &dma->dma_tag); /* dmat */ 571 if (result != 0) { 572 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 573 __func__, result); 574 goto hdac_dma_alloc_fail; 575 } 576 577 /* 578 * Allocate DMA memory 579 */ 580 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 581 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 582 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 583 &dma->dma_map); 584 if (result != 0) { 585 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 586 __func__, result); 587 goto hdac_dma_alloc_fail; 588 } 589 590 dma->dma_size = roundsz; 591 592 /* 593 * Map the memory 594 */ 595 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 596 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 597 if (result != 0 || dma->dma_paddr == 0) { 598 if (result == 0) 599 result = ENOMEM; 600 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 601 __func__, result); 602 goto hdac_dma_alloc_fail; 603 } 604 605 HDA_BOOTHVERBOSE( 606 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 607 __func__, (uintmax_t)size, (uintmax_t)roundsz); 608 ); 609 610 return (0); 611 612 hdac_dma_alloc_fail: 613 hdac_dma_free(sc, dma); 614 615 return (result); 616 } 617 618 619 /**************************************************************************** 620 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 621 * 622 * Free a struct dhac_dma that has been previously allocated via the 623 * hdac_dma_alloc function. 624 ****************************************************************************/ 625 static void 626 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 627 { 628 if (dma->dma_paddr != 0) { 629 #if 0 630 /* Flush caches */ 631 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 632 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 633 #endif 634 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 635 dma->dma_paddr = 0; 636 } 637 if (dma->dma_vaddr != NULL) { 638 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 639 dma->dma_vaddr = NULL; 640 } 641 if (dma->dma_tag != NULL) { 642 bus_dma_tag_destroy(dma->dma_tag); 643 dma->dma_tag = NULL; 644 } 645 dma->dma_size = 0; 646 } 647 648 /**************************************************************************** 649 * int hdac_mem_alloc(struct hdac_softc *) 650 * 651 * Allocate all the bus resources necessary to speak with the physical 652 * controller. 653 ****************************************************************************/ 654 static int 655 hdac_mem_alloc(struct hdac_softc *sc) 656 { 657 struct hdac_mem *mem; 658 659 mem = &sc->mem; 660 mem->mem_rid = PCIR_BAR(0); 661 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 662 &mem->mem_rid, RF_ACTIVE); 663 if (mem->mem_res == NULL) { 664 device_printf(sc->dev, 665 "%s: Unable to allocate memory resource\n", __func__); 666 return (ENOMEM); 667 } 668 mem->mem_tag = rman_get_bustag(mem->mem_res); 669 mem->mem_handle = rman_get_bushandle(mem->mem_res); 670 671 return (0); 672 } 673 674 /**************************************************************************** 675 * void hdac_mem_free(struct hdac_softc *) 676 * 677 * Free up resources previously allocated by hdac_mem_alloc. 678 ****************************************************************************/ 679 static void 680 hdac_mem_free(struct hdac_softc *sc) 681 { 682 struct hdac_mem *mem; 683 684 mem = &sc->mem; 685 if (mem->mem_res != NULL) 686 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 687 mem->mem_res); 688 mem->mem_res = NULL; 689 } 690 691 /**************************************************************************** 692 * int hdac_irq_alloc(struct hdac_softc *) 693 * 694 * Allocate and setup the resources necessary for interrupt handling. 695 ****************************************************************************/ 696 static int 697 hdac_irq_alloc(struct hdac_softc *sc) 698 { 699 struct hdac_irq *irq; 700 int result; 701 702 irq = &sc->irq; 703 irq->irq_rid = 0x0; 704 705 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 706 (result = pci_msi_count(sc->dev)) == 1 && 707 pci_alloc_msi(sc->dev, &result) == 0) 708 irq->irq_rid = 0x1; 709 710 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 711 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 712 if (irq->irq_res == NULL) { 713 device_printf(sc->dev, "%s: Unable to allocate irq\n", 714 __func__); 715 goto hdac_irq_alloc_fail; 716 } 717 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 718 NULL, hdac_intr_handler, sc, &irq->irq_handle); 719 if (result != 0) { 720 device_printf(sc->dev, 721 "%s: Unable to setup interrupt handler (%x)\n", 722 __func__, result); 723 goto hdac_irq_alloc_fail; 724 } 725 726 return (0); 727 728 hdac_irq_alloc_fail: 729 hdac_irq_free(sc); 730 731 return (ENXIO); 732 } 733 734 /**************************************************************************** 735 * void hdac_irq_free(struct hdac_softc *) 736 * 737 * Free up resources previously allocated by hdac_irq_alloc. 738 ****************************************************************************/ 739 static void 740 hdac_irq_free(struct hdac_softc *sc) 741 { 742 struct hdac_irq *irq; 743 744 irq = &sc->irq; 745 if (irq->irq_res != NULL && irq->irq_handle != NULL) 746 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 747 if (irq->irq_res != NULL) 748 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 749 irq->irq_res); 750 if (irq->irq_rid == 0x1) 751 pci_release_msi(sc->dev); 752 irq->irq_handle = NULL; 753 irq->irq_res = NULL; 754 irq->irq_rid = 0x0; 755 } 756 757 /**************************************************************************** 758 * void hdac_corb_init(struct hdac_softc *) 759 * 760 * Initialize the corb registers for operations but do not start it up yet. 761 * The CORB engine must not be running when this function is called. 762 ****************************************************************************/ 763 static void 764 hdac_corb_init(struct hdac_softc *sc) 765 { 766 uint8_t corbsize; 767 uint64_t corbpaddr; 768 769 /* Setup the CORB size. */ 770 switch (sc->corb_size) { 771 case 256: 772 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 773 break; 774 case 16: 775 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 776 break; 777 case 2: 778 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 779 break; 780 default: 781 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 782 } 783 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 784 785 /* Setup the CORB Address in the hdac */ 786 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 787 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 788 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 789 790 /* Set the WP and RP */ 791 sc->corb_wp = 0; 792 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 793 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 794 /* 795 * The HDA specification indicates that the CORBRPRST bit will always 796 * read as zero. Unfortunately, it seems that at least the 82801G 797 * doesn't reset the bit to zero, which stalls the corb engine. 798 * manually reset the bit to zero before continuing. 799 */ 800 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 801 802 /* Enable CORB error reporting */ 803 #if 0 804 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 805 #endif 806 } 807 808 /**************************************************************************** 809 * void hdac_rirb_init(struct hdac_softc *) 810 * 811 * Initialize the rirb registers for operations but do not start it up yet. 812 * The RIRB engine must not be running when this function is called. 813 ****************************************************************************/ 814 static void 815 hdac_rirb_init(struct hdac_softc *sc) 816 { 817 uint8_t rirbsize; 818 uint64_t rirbpaddr; 819 820 /* Setup the RIRB size. */ 821 switch (sc->rirb_size) { 822 case 256: 823 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 824 break; 825 case 16: 826 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 827 break; 828 case 2: 829 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 830 break; 831 default: 832 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 833 } 834 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 835 836 /* Setup the RIRB Address in the hdac */ 837 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 838 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 839 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 840 841 /* Setup the WP and RP */ 842 sc->rirb_rp = 0; 843 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 844 845 /* Setup the interrupt threshold */ 846 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 847 848 /* Enable Overrun and response received reporting */ 849 #if 0 850 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 851 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 852 #else 853 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 854 #endif 855 856 #if 0 857 /* 858 * Make sure that the Host CPU cache doesn't contain any dirty 859 * cache lines that falls in the rirb. If I understood correctly, it 860 * should be sufficient to do this only once as the rirb is purely 861 * read-only from now on. 862 */ 863 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 864 BUS_DMASYNC_PREREAD); 865 #endif 866 } 867 868 /**************************************************************************** 869 * void hdac_corb_start(hdac_softc *) 870 * 871 * Startup the corb DMA engine 872 ****************************************************************************/ 873 static void 874 hdac_corb_start(struct hdac_softc *sc) 875 { 876 uint32_t corbctl; 877 878 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 879 corbctl |= HDAC_CORBCTL_CORBRUN; 880 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 881 } 882 883 /**************************************************************************** 884 * void hdac_rirb_start(hdac_softc *) 885 * 886 * Startup the rirb DMA engine 887 ****************************************************************************/ 888 static void 889 hdac_rirb_start(struct hdac_softc *sc) 890 { 891 uint32_t rirbctl; 892 893 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 894 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 895 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 896 } 897 898 static int 899 hdac_rirb_flush(struct hdac_softc *sc) 900 { 901 struct hdac_rirb *rirb_base, *rirb; 902 nid_t cad; 903 uint32_t resp; 904 uint8_t rirbwp; 905 int ret; 906 907 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 908 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 909 #if 0 910 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 911 BUS_DMASYNC_POSTREAD); 912 #endif 913 914 ret = 0; 915 while (sc->rirb_rp != rirbwp) { 916 sc->rirb_rp++; 917 sc->rirb_rp %= sc->rirb_size; 918 rirb = &rirb_base[sc->rirb_rp]; 919 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 920 resp = rirb->response; 921 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 922 sc->unsolq[sc->unsolq_wp++] = resp; 923 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 924 sc->unsolq[sc->unsolq_wp++] = cad; 925 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 926 } else if (sc->codecs[cad].pending <= 0) { 927 device_printf(sc->dev, "Unexpected unsolicited " 928 "response from address %d: %08x\n", cad, resp); 929 } else { 930 sc->codecs[cad].response = resp; 931 sc->codecs[cad].pending--; 932 } 933 ret++; 934 } 935 return (ret); 936 } 937 938 static int 939 hdac_unsolq_flush(struct hdac_softc *sc) 940 { 941 device_t child; 942 nid_t cad; 943 uint32_t resp; 944 int ret = 0; 945 946 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 947 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 948 while (sc->unsolq_rp != sc->unsolq_wp) { 949 resp = sc->unsolq[sc->unsolq_rp++]; 950 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 951 cad = sc->unsolq[sc->unsolq_rp++]; 952 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 953 if ((child = sc->codecs[cad].dev) != NULL) 954 HDAC_UNSOL_INTR(child, resp); 955 ret++; 956 } 957 sc->unsolq_st = HDAC_UNSOLQ_READY; 958 } 959 960 return (ret); 961 } 962 963 /**************************************************************************** 964 * uint32_t hdac_command_sendone_internal 965 * 966 * Wrapper function that sends only one command to a given codec 967 ****************************************************************************/ 968 static uint32_t 969 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 970 { 971 int timeout; 972 uint32_t *corb; 973 974 if (!hdac_lockowned(sc)) 975 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 976 verb &= ~HDA_CMD_CAD_MASK; 977 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 978 sc->codecs[cad].response = HDA_INVALID; 979 980 sc->codecs[cad].pending++; 981 sc->corb_wp++; 982 sc->corb_wp %= sc->corb_size; 983 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 984 #if 0 985 bus_dmamap_sync(sc->corb_dma.dma_tag, 986 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 987 #endif 988 corb[sc->corb_wp] = verb; 989 #if 0 990 bus_dmamap_sync(sc->corb_dma.dma_tag, 991 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 992 #endif 993 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 994 995 timeout = 10000; 996 do { 997 if (hdac_rirb_flush(sc) == 0) 998 DELAY(10); 999 } while (sc->codecs[cad].pending != 0 && --timeout); 1000 1001 if (sc->codecs[cad].pending != 0) { 1002 device_printf(sc->dev, "Command timeout on address %d\n", cad); 1003 sc->codecs[cad].pending = 0; 1004 } 1005 1006 if (sc->unsolq_rp != sc->unsolq_wp) 1007 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1008 return (sc->codecs[cad].response); 1009 } 1010 1011 /**************************************************************************** 1012 * Device Methods 1013 ****************************************************************************/ 1014 1015 /**************************************************************************** 1016 * int hdac_probe(device_t) 1017 * 1018 * Probe for the presence of an hdac. If none is found, check for a generic 1019 * match using the subclass of the device. 1020 ****************************************************************************/ 1021 static int 1022 hdac_probe(device_t dev) 1023 { 1024 int i, result; 1025 uint32_t model; 1026 uint16_t class, subclass; 1027 char desc[64]; 1028 1029 model = (uint32_t)pci_get_device(dev) << 16; 1030 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1031 class = pci_get_class(dev); 1032 subclass = pci_get_subclass(dev); 1033 1034 bzero(desc, sizeof(desc)); 1035 result = ENXIO; 1036 for (i = 0; i < nitems(hdac_devices); i++) { 1037 if (hdac_devices[i].model == model) { 1038 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1039 result = BUS_PROBE_DEFAULT; 1040 break; 1041 } 1042 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1043 class == PCIC_MULTIMEDIA && 1044 subclass == PCIS_MULTIMEDIA_HDA) { 1045 snprintf(desc, sizeof(desc), 1046 "%s (0x%04x)", 1047 hdac_devices[i].desc, pci_get_device(dev)); 1048 result = BUS_PROBE_GENERIC; 1049 break; 1050 } 1051 } 1052 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1053 subclass == PCIS_MULTIMEDIA_HDA) { 1054 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1055 result = BUS_PROBE_GENERIC; 1056 } 1057 if (result != ENXIO) { 1058 strlcat(desc, " HDA Controller", sizeof(desc)); 1059 device_set_desc_copy(dev, desc); 1060 } 1061 1062 return (result); 1063 } 1064 1065 static void 1066 hdac_unsolq_task(void *context, int pending) 1067 { 1068 struct hdac_softc *sc; 1069 1070 sc = (struct hdac_softc *)context; 1071 1072 hdac_lock(sc); 1073 hdac_unsolq_flush(sc); 1074 hdac_unlock(sc); 1075 } 1076 1077 /**************************************************************************** 1078 * int hdac_attach(device_t) 1079 * 1080 * Attach the device into the kernel. Interrupts usually won't be enabled 1081 * when this function is called. Setup everything that doesn't require 1082 * interrupts and defer probing of codecs until interrupts are enabled. 1083 ****************************************************************************/ 1084 static int 1085 hdac_attach(device_t dev) 1086 { 1087 struct hdac_softc *sc; 1088 int result; 1089 int i, devid = -1; 1090 uint32_t model; 1091 uint16_t class, subclass; 1092 uint16_t vendor; 1093 uint8_t v; 1094 1095 sc = device_get_softc(dev); 1096 HDA_BOOTVERBOSE( 1097 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n", 1098 pci_get_subvendor(dev), pci_get_subdevice(dev)); 1099 device_printf(dev, "HDA Driver Revision: %s\n", 1100 HDA_DRV_TEST_REV); 1101 ); 1102 1103 model = (uint32_t)pci_get_device(dev) << 16; 1104 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1105 class = pci_get_class(dev); 1106 subclass = pci_get_subclass(dev); 1107 1108 for (i = 0; i < nitems(hdac_devices); i++) { 1109 if (hdac_devices[i].model == model) { 1110 devid = i; 1111 break; 1112 } 1113 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1114 class == PCIC_MULTIMEDIA && 1115 subclass == PCIS_MULTIMEDIA_HDA) { 1116 devid = i; 1117 break; 1118 } 1119 } 1120 1121 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1122 sc->dev = dev; 1123 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1124 callout_init(&sc->poll_callout, 1); 1125 for (i = 0; i < HDAC_CODEC_MAX; i++) 1126 sc->codecs[i].dev = NULL; 1127 if (devid >= 0) { 1128 sc->quirks_on = hdac_devices[devid].quirks_on; 1129 sc->quirks_off = hdac_devices[devid].quirks_off; 1130 } else { 1131 sc->quirks_on = 0; 1132 sc->quirks_off = 0; 1133 } 1134 if (resource_int_value(device_get_name(dev), 1135 device_get_unit(dev), "msi", &i) == 0) { 1136 if (i == 0) 1137 sc->quirks_off |= HDAC_QUIRK_MSI; 1138 else { 1139 sc->quirks_on |= HDAC_QUIRK_MSI; 1140 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1141 } 1142 } 1143 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1144 HDA_BOOTVERBOSE( 1145 device_printf(sc->dev, 1146 "Config options: on=0x%08x off=0x%08x\n", 1147 sc->quirks_on, sc->quirks_off); 1148 ); 1149 sc->poll_ival = hz; 1150 if (resource_int_value(device_get_name(dev), 1151 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1152 sc->polling = 1; 1153 else 1154 sc->polling = 0; 1155 1156 pci_enable_busmaster(dev); 1157 1158 vendor = pci_get_vendor(dev); 1159 if (vendor == INTEL_VENDORID) { 1160 /* TCSEL -> TC0 */ 1161 v = pci_read_config(dev, 0x44, 1); 1162 pci_write_config(dev, 0x44, v & 0xf8, 1); 1163 HDA_BOOTHVERBOSE( 1164 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1165 pci_read_config(dev, 0x44, 1)); 1166 ); 1167 } 1168 1169 #if defined(__i386__) || defined(__amd64__) 1170 sc->flags |= HDAC_F_DMA_NOCACHE; 1171 1172 if (resource_int_value(device_get_name(dev), 1173 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 1174 #else 1175 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1176 #endif 1177 /* 1178 * Try to enable PCIe snoop to avoid messing around with 1179 * uncacheable DMA attribute. Since PCIe snoop register 1180 * config is pretty much vendor specific, there are no 1181 * general solutions on how to enable it, forcing us (even 1182 * Microsoft) to enable uncacheable or write combined DMA 1183 * by default. 1184 * 1185 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 1186 */ 1187 for (i = 0; i < nitems(hdac_pcie_snoop); i++) { 1188 if (hdac_pcie_snoop[i].vendor != vendor) 1189 continue; 1190 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1191 if (hdac_pcie_snoop[i].reg == 0x00) 1192 break; 1193 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1194 if ((v & hdac_pcie_snoop[i].enable) == 1195 hdac_pcie_snoop[i].enable) 1196 break; 1197 v &= hdac_pcie_snoop[i].mask; 1198 v |= hdac_pcie_snoop[i].enable; 1199 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 1200 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1201 if ((v & hdac_pcie_snoop[i].enable) != 1202 hdac_pcie_snoop[i].enable) { 1203 HDA_BOOTVERBOSE( 1204 device_printf(dev, 1205 "WARNING: Failed to enable PCIe " 1206 "snoop!\n"); 1207 ); 1208 #if defined(__i386__) || defined(__amd64__) 1209 sc->flags |= HDAC_F_DMA_NOCACHE; 1210 #endif 1211 } 1212 break; 1213 } 1214 #if defined(__i386__) || defined(__amd64__) 1215 } 1216 #endif 1217 1218 HDA_BOOTHVERBOSE( 1219 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1220 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1221 "Uncacheable" : "PCIe snoop", vendor); 1222 ); 1223 1224 /* Allocate resources */ 1225 result = hdac_mem_alloc(sc); 1226 if (result != 0) 1227 goto hdac_attach_fail; 1228 result = hdac_irq_alloc(sc); 1229 if (result != 0) 1230 goto hdac_attach_fail; 1231 1232 /* Get Capabilities */ 1233 result = hdac_get_capabilities(sc); 1234 if (result != 0) 1235 goto hdac_attach_fail; 1236 1237 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1238 result = hdac_dma_alloc(sc, &sc->corb_dma, 1239 sc->corb_size * sizeof(uint32_t)); 1240 if (result != 0) 1241 goto hdac_attach_fail; 1242 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1243 sc->rirb_size * sizeof(struct hdac_rirb)); 1244 if (result != 0) 1245 goto hdac_attach_fail; 1246 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, 1247 M_HDAC, M_ZERO | M_WAITOK); 1248 for (i = 0; i < sc->num_ss; i++) { 1249 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1250 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1251 if (result != 0) 1252 goto hdac_attach_fail; 1253 } 1254 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1255 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1256 HDA_BOOTVERBOSE( 1257 device_printf(dev, "Failed to " 1258 "allocate DMA pos buffer " 1259 "(non-fatal)\n"); 1260 ); 1261 } else { 1262 uint64_t addr = sc->pos_dma.dma_paddr; 1263 1264 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1265 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1266 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1267 HDAC_DPLBASE_DPLBASE_DMAPBE); 1268 } 1269 } 1270 1271 result = bus_dma_tag_create( 1272 bus_get_dma_tag(sc->dev), /* parent */ 1273 HDA_DMA_ALIGNMENT, /* alignment */ 1274 0, /* boundary */ 1275 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1276 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1277 BUS_SPACE_MAXADDR, /* highaddr */ 1278 NULL, /* filtfunc */ 1279 NULL, /* fistfuncarg */ 1280 HDA_BUFSZ_MAX, /* maxsize */ 1281 1, /* nsegments */ 1282 HDA_BUFSZ_MAX, /* maxsegsz */ 1283 0, /* flags */ 1284 NULL, /* lockfunc */ 1285 NULL, /* lockfuncarg */ 1286 &sc->chan_dmat); /* dmat */ 1287 if (result != 0) { 1288 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 1289 __func__, result); 1290 goto hdac_attach_fail; 1291 } 1292 1293 /* Quiesce everything */ 1294 HDA_BOOTHVERBOSE( 1295 device_printf(dev, "Reset controller...\n"); 1296 ); 1297 hdac_reset(sc, 1); 1298 1299 /* Initialize the CORB and RIRB */ 1300 hdac_corb_init(sc); 1301 hdac_rirb_init(sc); 1302 1303 /* Defer remaining of initialization until interrupts are enabled */ 1304 sc->intrhook.ich_func = hdac_attach2; 1305 sc->intrhook.ich_arg = (void *)sc; 1306 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1307 sc->intrhook.ich_func = NULL; 1308 hdac_attach2((void *)sc); 1309 } 1310 1311 return (0); 1312 1313 hdac_attach_fail: 1314 hdac_irq_free(sc); 1315 for (i = 0; i < sc->num_ss; i++) 1316 hdac_dma_free(sc, &sc->streams[i].bdl); 1317 free(sc->streams, M_HDAC); 1318 hdac_dma_free(sc, &sc->rirb_dma); 1319 hdac_dma_free(sc, &sc->corb_dma); 1320 hdac_mem_free(sc); 1321 snd_mtxfree(sc->lock); 1322 1323 return (ENXIO); 1324 } 1325 1326 static int 1327 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1328 { 1329 struct hdac_softc *sc; 1330 device_t *devlist; 1331 device_t dev; 1332 int devcount, i, err, val; 1333 1334 dev = oidp->oid_arg1; 1335 sc = device_get_softc(dev); 1336 if (sc == NULL) 1337 return (EINVAL); 1338 val = 0; 1339 err = sysctl_handle_int(oidp, &val, 0, req); 1340 if (err != 0 || req->newptr == NULL || val == 0) 1341 return (err); 1342 1343 /* XXX: Temporary. For debugging. */ 1344 if (val == 100) { 1345 hdac_suspend(dev); 1346 return (0); 1347 } else if (val == 101) { 1348 hdac_resume(dev); 1349 return (0); 1350 } 1351 1352 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1353 return (err); 1354 hdac_lock(sc); 1355 for (i = 0; i < devcount; i++) 1356 HDAC_PINDUMP(devlist[i]); 1357 hdac_unlock(sc); 1358 free(devlist, M_TEMP); 1359 return (0); 1360 } 1361 1362 static int 1363 hdac_mdata_rate(uint16_t fmt) 1364 { 1365 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1366 int rate, bits; 1367 1368 if (fmt & (1 << 14)) 1369 rate = 44100; 1370 else 1371 rate = 48000; 1372 rate *= ((fmt >> 11) & 0x07) + 1; 1373 rate /= ((fmt >> 8) & 0x07) + 1; 1374 bits = mbits[(fmt >> 4) & 0x03]; 1375 bits *= (fmt & 0x0f) + 1; 1376 return (rate * bits); 1377 } 1378 1379 static int 1380 hdac_bdata_rate(uint16_t fmt, int output) 1381 { 1382 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1383 int rate, bits; 1384 1385 rate = 48000; 1386 rate *= ((fmt >> 11) & 0x07) + 1; 1387 bits = bbits[(fmt >> 4) & 0x03]; 1388 bits *= (fmt & 0x0f) + 1; 1389 if (!output) 1390 bits = ((bits + 7) & ~0x07) + 10; 1391 return (rate * bits); 1392 } 1393 1394 static void 1395 hdac_poll_reinit(struct hdac_softc *sc) 1396 { 1397 int i, pollticks, min = 1000000; 1398 struct hdac_stream *s; 1399 1400 if (sc->polling == 0) 1401 return; 1402 if (sc->unsol_registered > 0) 1403 min = hz / 2; 1404 for (i = 0; i < sc->num_ss; i++) { 1405 s = &sc->streams[i]; 1406 if (s->running == 0) 1407 continue; 1408 pollticks = ((uint64_t)hz * s->blksz) / 1409 (hdac_mdata_rate(s->format) / 8); 1410 pollticks >>= 1; 1411 if (pollticks > hz) 1412 pollticks = hz; 1413 if (pollticks < 1) { 1414 HDA_BOOTVERBOSE( 1415 device_printf(sc->dev, 1416 "poll interval < 1 tick !\n"); 1417 ); 1418 pollticks = 1; 1419 } 1420 if (min > pollticks) 1421 min = pollticks; 1422 } 1423 HDA_BOOTVERBOSE( 1424 device_printf(sc->dev, 1425 "poll interval %d -> %d ticks\n", 1426 sc->poll_ival, min); 1427 ); 1428 sc->poll_ival = min; 1429 if (min == 1000000) 1430 callout_stop(&sc->poll_callout); 1431 else 1432 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1433 } 1434 1435 static int 1436 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1437 { 1438 struct hdac_softc *sc; 1439 device_t dev; 1440 uint32_t ctl; 1441 int err, val; 1442 1443 dev = oidp->oid_arg1; 1444 sc = device_get_softc(dev); 1445 if (sc == NULL) 1446 return (EINVAL); 1447 hdac_lock(sc); 1448 val = sc->polling; 1449 hdac_unlock(sc); 1450 err = sysctl_handle_int(oidp, &val, 0, req); 1451 1452 if (err != 0 || req->newptr == NULL) 1453 return (err); 1454 if (val < 0 || val > 1) 1455 return (EINVAL); 1456 1457 hdac_lock(sc); 1458 if (val != sc->polling) { 1459 if (val == 0) { 1460 callout_stop(&sc->poll_callout); 1461 hdac_unlock(sc); 1462 callout_drain(&sc->poll_callout); 1463 hdac_lock(sc); 1464 sc->polling = 0; 1465 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1466 ctl |= HDAC_INTCTL_GIE; 1467 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1468 } else { 1469 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1470 ctl &= ~HDAC_INTCTL_GIE; 1471 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1472 sc->polling = 1; 1473 hdac_poll_reinit(sc); 1474 } 1475 } 1476 hdac_unlock(sc); 1477 1478 return (err); 1479 } 1480 1481 static void 1482 hdac_attach2(void *arg) 1483 { 1484 struct hdac_softc *sc; 1485 device_t child; 1486 uint32_t vendorid, revisionid; 1487 int i; 1488 uint16_t statests; 1489 1490 sc = (struct hdac_softc *)arg; 1491 1492 hdac_lock(sc); 1493 1494 /* Remove ourselves from the config hooks */ 1495 if (sc->intrhook.ich_func != NULL) { 1496 config_intrhook_disestablish(&sc->intrhook); 1497 sc->intrhook.ich_func = NULL; 1498 } 1499 1500 HDA_BOOTHVERBOSE( 1501 device_printf(sc->dev, "Starting CORB Engine...\n"); 1502 ); 1503 hdac_corb_start(sc); 1504 HDA_BOOTHVERBOSE( 1505 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1506 ); 1507 hdac_rirb_start(sc); 1508 HDA_BOOTHVERBOSE( 1509 device_printf(sc->dev, 1510 "Enabling controller interrupt...\n"); 1511 ); 1512 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1513 HDAC_GCTL_UNSOL); 1514 if (sc->polling == 0) { 1515 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1516 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1517 } 1518 DELAY(1000); 1519 1520 HDA_BOOTHVERBOSE( 1521 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1522 ); 1523 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1524 hdac_unlock(sc); 1525 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1526 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1527 HDA_BOOTHVERBOSE( 1528 device_printf(sc->dev, 1529 "Found CODEC at address %d\n", i); 1530 ); 1531 hdac_lock(sc); 1532 vendorid = hdac_send_command(sc, i, 1533 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1534 revisionid = hdac_send_command(sc, i, 1535 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1536 hdac_unlock(sc); 1537 if (vendorid == HDA_INVALID && 1538 revisionid == HDA_INVALID) { 1539 device_printf(sc->dev, 1540 "CODEC is not responding!\n"); 1541 continue; 1542 } 1543 sc->codecs[i].vendor_id = 1544 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1545 sc->codecs[i].device_id = 1546 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1547 sc->codecs[i].revision_id = 1548 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1549 sc->codecs[i].stepping_id = 1550 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1551 child = device_add_child(sc->dev, "hdacc", -1); 1552 if (child == NULL) { 1553 device_printf(sc->dev, 1554 "Failed to add CODEC device\n"); 1555 continue; 1556 } 1557 device_set_ivars(child, (void *)(intptr_t)i); 1558 sc->codecs[i].dev = child; 1559 } 1560 } 1561 bus_generic_attach(sc->dev); 1562 1563 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1564 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1565 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1566 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1567 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1568 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1569 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1570 sysctl_hdac_polling, "I", "Enable polling mode"); 1571 } 1572 1573 /**************************************************************************** 1574 * int hdac_suspend(device_t) 1575 * 1576 * Suspend and power down HDA bus and codecs. 1577 ****************************************************************************/ 1578 static int 1579 hdac_suspend(device_t dev) 1580 { 1581 struct hdac_softc *sc = device_get_softc(dev); 1582 1583 HDA_BOOTHVERBOSE( 1584 device_printf(dev, "Suspend...\n"); 1585 ); 1586 bus_generic_suspend(dev); 1587 1588 hdac_lock(sc); 1589 HDA_BOOTHVERBOSE( 1590 device_printf(dev, "Reset controller...\n"); 1591 ); 1592 callout_stop(&sc->poll_callout); 1593 hdac_reset(sc, 0); 1594 hdac_unlock(sc); 1595 callout_drain(&sc->poll_callout); 1596 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1597 HDA_BOOTHVERBOSE( 1598 device_printf(dev, "Suspend done\n"); 1599 ); 1600 return (0); 1601 } 1602 1603 /**************************************************************************** 1604 * int hdac_resume(device_t) 1605 * 1606 * Powerup and restore HDA bus and codecs state. 1607 ****************************************************************************/ 1608 static int 1609 hdac_resume(device_t dev) 1610 { 1611 struct hdac_softc *sc = device_get_softc(dev); 1612 int error; 1613 1614 HDA_BOOTHVERBOSE( 1615 device_printf(dev, "Resume...\n"); 1616 ); 1617 hdac_lock(sc); 1618 1619 /* Quiesce everything */ 1620 HDA_BOOTHVERBOSE( 1621 device_printf(dev, "Reset controller...\n"); 1622 ); 1623 hdac_reset(sc, 1); 1624 1625 /* Initialize the CORB and RIRB */ 1626 hdac_corb_init(sc); 1627 hdac_rirb_init(sc); 1628 1629 HDA_BOOTHVERBOSE( 1630 device_printf(dev, "Starting CORB Engine...\n"); 1631 ); 1632 hdac_corb_start(sc); 1633 HDA_BOOTHVERBOSE( 1634 device_printf(dev, "Starting RIRB Engine...\n"); 1635 ); 1636 hdac_rirb_start(sc); 1637 HDA_BOOTHVERBOSE( 1638 device_printf(dev, "Enabling controller interrupt...\n"); 1639 ); 1640 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1641 HDAC_GCTL_UNSOL); 1642 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1643 DELAY(1000); 1644 hdac_poll_reinit(sc); 1645 hdac_unlock(sc); 1646 1647 error = bus_generic_resume(dev); 1648 HDA_BOOTHVERBOSE( 1649 device_printf(dev, "Resume done\n"); 1650 ); 1651 return (error); 1652 } 1653 1654 /**************************************************************************** 1655 * int hdac_detach(device_t) 1656 * 1657 * Detach and free up resources utilized by the hdac device. 1658 ****************************************************************************/ 1659 static int 1660 hdac_detach(device_t dev) 1661 { 1662 struct hdac_softc *sc = device_get_softc(dev); 1663 device_t *devlist; 1664 int cad, i, devcount, error; 1665 1666 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1667 return (error); 1668 for (i = 0; i < devcount; i++) { 1669 cad = (intptr_t)device_get_ivars(devlist[i]); 1670 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1671 free(devlist, M_TEMP); 1672 return (error); 1673 } 1674 sc->codecs[cad].dev = NULL; 1675 } 1676 free(devlist, M_TEMP); 1677 1678 hdac_lock(sc); 1679 hdac_reset(sc, 0); 1680 hdac_unlock(sc); 1681 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1682 hdac_irq_free(sc); 1683 1684 for (i = 0; i < sc->num_ss; i++) 1685 hdac_dma_free(sc, &sc->streams[i].bdl); 1686 free(sc->streams, M_HDAC); 1687 hdac_dma_free(sc, &sc->pos_dma); 1688 hdac_dma_free(sc, &sc->rirb_dma); 1689 hdac_dma_free(sc, &sc->corb_dma); 1690 if (sc->chan_dmat != NULL) { 1691 bus_dma_tag_destroy(sc->chan_dmat); 1692 sc->chan_dmat = NULL; 1693 } 1694 hdac_mem_free(sc); 1695 snd_mtxfree(sc->lock); 1696 return (0); 1697 } 1698 1699 static bus_dma_tag_t 1700 hdac_get_dma_tag(device_t dev, device_t child) 1701 { 1702 struct hdac_softc *sc = device_get_softc(dev); 1703 1704 return (sc->chan_dmat); 1705 } 1706 1707 static int 1708 hdac_print_child(device_t dev, device_t child) 1709 { 1710 int retval; 1711 1712 retval = bus_print_child_header(dev, child); 1713 retval += printf(" at cad %d", 1714 (int)(intptr_t)device_get_ivars(child)); 1715 retval += bus_print_child_footer(dev, child); 1716 1717 return (retval); 1718 } 1719 1720 static int 1721 hdac_child_location_str(device_t dev, device_t child, char *buf, 1722 size_t buflen) 1723 { 1724 1725 snprintf(buf, buflen, "cad=%d", 1726 (int)(intptr_t)device_get_ivars(child)); 1727 return (0); 1728 } 1729 1730 static int 1731 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1732 size_t buflen) 1733 { 1734 struct hdac_softc *sc = device_get_softc(dev); 1735 nid_t cad = (uintptr_t)device_get_ivars(child); 1736 1737 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1738 "stepping=0x%02x", 1739 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1740 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1741 return (0); 1742 } 1743 1744 static int 1745 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1746 { 1747 struct hdac_softc *sc = device_get_softc(dev); 1748 nid_t cad = (uintptr_t)device_get_ivars(child); 1749 1750 switch (which) { 1751 case HDA_IVAR_CODEC_ID: 1752 *result = cad; 1753 break; 1754 case HDA_IVAR_VENDOR_ID: 1755 *result = sc->codecs[cad].vendor_id; 1756 break; 1757 case HDA_IVAR_DEVICE_ID: 1758 *result = sc->codecs[cad].device_id; 1759 break; 1760 case HDA_IVAR_REVISION_ID: 1761 *result = sc->codecs[cad].revision_id; 1762 break; 1763 case HDA_IVAR_STEPPING_ID: 1764 *result = sc->codecs[cad].stepping_id; 1765 break; 1766 case HDA_IVAR_SUBVENDOR_ID: 1767 *result = pci_get_subvendor(dev); 1768 break; 1769 case HDA_IVAR_SUBDEVICE_ID: 1770 *result = pci_get_subdevice(dev); 1771 break; 1772 case HDA_IVAR_DMA_NOCACHE: 1773 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1774 break; 1775 case HDA_IVAR_STRIPES_MASK: 1776 *result = (1 << (1 << sc->num_sdo)) - 1; 1777 break; 1778 default: 1779 return (ENOENT); 1780 } 1781 return (0); 1782 } 1783 1784 static struct mtx * 1785 hdac_get_mtx(device_t dev, device_t child) 1786 { 1787 struct hdac_softc *sc = device_get_softc(dev); 1788 1789 return (sc->lock); 1790 } 1791 1792 static uint32_t 1793 hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1794 { 1795 1796 return (hdac_send_command(device_get_softc(dev), 1797 (intptr_t)device_get_ivars(child), verb)); 1798 } 1799 1800 static int 1801 hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1802 { 1803 int i, ss; 1804 1805 ss = -1; 1806 /* Allocate ISS/OSS first. */ 1807 if (dir == 0) { 1808 for (i = 0; i < sc->num_iss; i++) { 1809 if (sc->streams[i].stream == stream) { 1810 ss = i; 1811 break; 1812 } 1813 } 1814 } else { 1815 for (i = 0; i < sc->num_oss; i++) { 1816 if (sc->streams[i + sc->num_iss].stream == stream) { 1817 ss = i + sc->num_iss; 1818 break; 1819 } 1820 } 1821 } 1822 /* Fallback to BSS. */ 1823 if (ss == -1) { 1824 for (i = 0; i < sc->num_bss; i++) { 1825 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1826 == stream) { 1827 ss = i + sc->num_iss + sc->num_oss; 1828 break; 1829 } 1830 } 1831 } 1832 return (ss); 1833 } 1834 1835 static int 1836 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1837 uint32_t **dmapos) 1838 { 1839 struct hdac_softc *sc = device_get_softc(dev); 1840 nid_t cad = (uintptr_t)device_get_ivars(child); 1841 int stream, ss, bw, maxbw, prevbw; 1842 1843 /* Look for empty stream. */ 1844 ss = hdac_find_stream(sc, dir, 0); 1845 1846 /* Return if found nothing. */ 1847 if (ss < 0) 1848 return (0); 1849 1850 /* Check bus bandwidth. */ 1851 bw = hdac_bdata_rate(format, dir); 1852 if (dir == 1) { 1853 bw *= 1 << (sc->num_sdo - stripe); 1854 prevbw = sc->sdo_bw_used; 1855 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1856 } else { 1857 prevbw = sc->codecs[cad].sdi_bw_used; 1858 maxbw = 48000 * 464; 1859 } 1860 HDA_BOOTHVERBOSE( 1861 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1862 (bw + prevbw) / 1000, maxbw / 1000, 1863 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1864 ); 1865 if (bw + prevbw > maxbw) 1866 return (0); 1867 if (dir == 1) 1868 sc->sdo_bw_used += bw; 1869 else 1870 sc->codecs[cad].sdi_bw_used += bw; 1871 1872 /* Allocate stream number */ 1873 if (ss >= sc->num_iss + sc->num_oss) 1874 stream = 15 - (ss - sc->num_iss - sc->num_oss); 1875 else if (ss >= sc->num_iss) 1876 stream = ss - sc->num_iss + 1; 1877 else 1878 stream = ss + 1; 1879 1880 sc->streams[ss].dev = child; 1881 sc->streams[ss].dir = dir; 1882 sc->streams[ss].stream = stream; 1883 sc->streams[ss].bw = bw; 1884 sc->streams[ss].format = format; 1885 sc->streams[ss].stripe = stripe; 1886 if (dmapos != NULL) { 1887 if (sc->pos_dma.dma_vaddr != NULL) 1888 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1889 else 1890 *dmapos = NULL; 1891 } 1892 return (stream); 1893 } 1894 1895 static void 1896 hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1897 { 1898 struct hdac_softc *sc = device_get_softc(dev); 1899 nid_t cad = (uintptr_t)device_get_ivars(child); 1900 int ss; 1901 1902 ss = hdac_find_stream(sc, dir, stream); 1903 KASSERT(ss >= 0, 1904 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1905 if (dir == 1) 1906 sc->sdo_bw_used -= sc->streams[ss].bw; 1907 else 1908 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1909 sc->streams[ss].stream = 0; 1910 sc->streams[ss].dev = NULL; 1911 } 1912 1913 static int 1914 hdac_stream_start(device_t dev, device_t child, 1915 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1916 { 1917 struct hdac_softc *sc = device_get_softc(dev); 1918 struct hdac_bdle *bdle; 1919 uint64_t addr; 1920 int i, ss, off; 1921 uint32_t ctl; 1922 1923 ss = hdac_find_stream(sc, dir, stream); 1924 KASSERT(ss >= 0, 1925 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1926 1927 addr = (uint64_t)buf; 1928 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1929 for (i = 0; i < blkcnt; i++, bdle++) { 1930 bdle->addrl = (uint32_t)addr; 1931 bdle->addrh = (uint32_t)(addr >> 32); 1932 bdle->len = blksz; 1933 bdle->ioc = 1; 1934 addr += blksz; 1935 } 1936 1937 off = ss << 5; 1938 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1939 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1940 addr = sc->streams[ss].bdl.dma_paddr; 1941 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1942 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1943 1944 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1945 if (dir) 1946 ctl |= HDAC_SDCTL2_DIR; 1947 else 1948 ctl &= ~HDAC_SDCTL2_DIR; 1949 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1950 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1951 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1952 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1953 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1954 1955 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1956 1957 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1958 ctl |= 1 << ss; 1959 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1960 1961 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 1962 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 1963 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1964 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1965 HDAC_SDCTL_RUN; 1966 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1967 1968 sc->streams[ss].blksz = blksz; 1969 sc->streams[ss].running = 1; 1970 hdac_poll_reinit(sc); 1971 return (0); 1972 } 1973 1974 static void 1975 hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1976 { 1977 struct hdac_softc *sc = device_get_softc(dev); 1978 int ss, off; 1979 uint32_t ctl; 1980 1981 ss = hdac_find_stream(sc, dir, stream); 1982 KASSERT(ss >= 0, 1983 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1984 1985 off = ss << 5; 1986 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1987 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1988 HDAC_SDCTL_RUN); 1989 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1990 1991 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1992 ctl &= ~(1 << ss); 1993 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1994 1995 sc->streams[ss].running = 0; 1996 hdac_poll_reinit(sc); 1997 } 1998 1999 static void 2000 hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 2001 { 2002 struct hdac_softc *sc = device_get_softc(dev); 2003 int timeout = 1000; 2004 int to = timeout; 2005 int ss, off; 2006 uint32_t ctl; 2007 2008 ss = hdac_find_stream(sc, dir, stream); 2009 KASSERT(ss >= 0, 2010 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2011 2012 off = ss << 5; 2013 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2014 ctl |= HDAC_SDCTL_SRST; 2015 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2016 do { 2017 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2018 if (ctl & HDAC_SDCTL_SRST) 2019 break; 2020 DELAY(10); 2021 } while (--to); 2022 if (!(ctl & HDAC_SDCTL_SRST)) 2023 device_printf(dev, "Reset setting timeout\n"); 2024 ctl &= ~HDAC_SDCTL_SRST; 2025 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2026 to = timeout; 2027 do { 2028 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2029 if (!(ctl & HDAC_SDCTL_SRST)) 2030 break; 2031 DELAY(10); 2032 } while (--to); 2033 if (ctl & HDAC_SDCTL_SRST) 2034 device_printf(dev, "Reset timeout!\n"); 2035 } 2036 2037 static uint32_t 2038 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2039 { 2040 struct hdac_softc *sc = device_get_softc(dev); 2041 int ss, off; 2042 2043 ss = hdac_find_stream(sc, dir, stream); 2044 KASSERT(ss >= 0, 2045 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2046 2047 off = ss << 5; 2048 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2049 } 2050 2051 static int 2052 hdac_unsol_alloc(device_t dev, device_t child, int tag) 2053 { 2054 struct hdac_softc *sc = device_get_softc(dev); 2055 2056 sc->unsol_registered++; 2057 hdac_poll_reinit(sc); 2058 return (tag); 2059 } 2060 2061 static void 2062 hdac_unsol_free(device_t dev, device_t child, int tag) 2063 { 2064 struct hdac_softc *sc = device_get_softc(dev); 2065 2066 sc->unsol_registered--; 2067 hdac_poll_reinit(sc); 2068 } 2069 2070 static device_method_t hdac_methods[] = { 2071 /* device interface */ 2072 DEVMETHOD(device_probe, hdac_probe), 2073 DEVMETHOD(device_attach, hdac_attach), 2074 DEVMETHOD(device_detach, hdac_detach), 2075 DEVMETHOD(device_suspend, hdac_suspend), 2076 DEVMETHOD(device_resume, hdac_resume), 2077 /* Bus interface */ 2078 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2079 DEVMETHOD(bus_print_child, hdac_print_child), 2080 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2081 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2082 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2083 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2084 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2085 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2086 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2087 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2088 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2089 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2090 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2091 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2092 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2093 DEVMETHOD_END 2094 }; 2095 2096 static driver_t hdac_driver = { 2097 "hdac", 2098 hdac_methods, 2099 sizeof(struct hdac_softc), 2100 }; 2101 2102 static devclass_t hdac_devclass; 2103 2104 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL); 2105