1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72 #include <dev/sound/pcm/sound.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 76 #include <sys/ctype.h> 77 #include <sys/taskqueue.h> 78 79 #include <dev/sound/pci/hda/hdac_private.h> 80 #include <dev/sound/pci/hda/hdac_reg.h> 81 #include <dev/sound/pci/hda/hda_reg.h> 82 #include <dev/sound/pci/hda/hdac.h> 83 84 #include "mixer_if.h" 85 86 #define HDA_DRV_TEST_REV "20090226_0129" 87 88 SND_DECLARE_FILE("$FreeBSD$"); 89 90 #define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94 } while(0) 95 96 #define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100 } while(0) 101 102 #if 1 103 #undef HDAC_INTR_EXTRA 104 #define HDAC_INTR_EXTRA 1 105 #endif 106 107 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 108 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 113 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 114 (fl) == 0xffffffff || \ 115 (((fl) & 0xffff0000) == 0xffff0000 && \ 116 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 117 (((fl) & 0x0000ffff) == 0x0000ffff && \ 118 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 119 #define HDA_MATCH_ALL 0xffffffff 120 #define HDAC_INVALID 0xffffffff 121 122 /* Default controller / jack sense poll: 250ms */ 123 #define HDAC_POLL_INTERVAL max(hz >> 2, 1) 124 125 /* 126 * Make room for possible 4096 playback/record channels, in 100 years to come. 127 */ 128 #define HDAC_TRIGGER_NONE 0x00000000 129 #define HDAC_TRIGGER_PLAY 0x00000fff 130 #define HDAC_TRIGGER_REC 0x00fff000 131 #define HDAC_TRIGGER_UNSOL 0x80000000 132 133 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 134 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 135 136 /* Controller models */ 137 138 /* Intel */ 139 #define INTEL_VENDORID 0x8086 140 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 141 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 142 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 143 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 144 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 145 #define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 146 #define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 147 #define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 148 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 149 150 /* Nvidia */ 151 #define NVIDIA_VENDORID 0x10de 152 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 153 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 154 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 155 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 156 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 157 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 158 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 159 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 160 #define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 161 #define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 162 #define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 163 #define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 164 #define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 165 #define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 166 #define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 167 #define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 168 #define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 169 #define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 170 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 171 172 /* ATI */ 173 #define ATI_VENDORID 0x1002 174 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 175 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 176 #define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 177 #define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 178 #define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 179 #define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 180 #define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 181 #define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 182 #define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 183 #define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 184 #define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 185 #define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 186 #define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 187 #define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 188 #define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 189 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 190 191 /* VIA */ 192 #define VIA_VENDORID 0x1106 193 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 194 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 195 196 /* SiS */ 197 #define SIS_VENDORID 0x1039 198 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 199 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 200 201 /* ULI */ 202 #define ULI_VENDORID 0x10b9 203 #define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 204 #define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 205 206 /* OEM/subvendors */ 207 208 /* Intel */ 209 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 210 211 /* HP/Compaq */ 212 #define HP_VENDORID 0x103c 213 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 214 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 215 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 216 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 217 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 218 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 219 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 220 #define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 221 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 222 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 223 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 224 #define HP_NX6325_SUBVENDORX 0x103c30b0 225 226 /* Dell */ 227 #define DELL_VENDORID 0x1028 228 #define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 229 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 230 #define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 231 #define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 232 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 233 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 234 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 235 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 236 237 /* Clevo */ 238 #define CLEVO_VENDORID 0x1558 239 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 240 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 241 242 /* Acer */ 243 #define ACER_VENDORID 0x1025 244 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 245 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 246 #define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 247 #define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 248 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 249 #define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 250 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 251 252 /* Asus */ 253 #define ASUS_VENDORID 0x1043 254 #define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 255 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 256 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 257 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 258 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 259 #define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 260 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 261 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 262 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 263 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 264 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 265 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 266 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 267 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 268 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 269 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 270 271 /* IBM / Lenovo */ 272 #define IBM_VENDORID 0x1014 273 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 274 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 275 276 /* Lenovo */ 277 #define LENOVO_VENDORID 0x17aa 278 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 279 #define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 280 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 281 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 282 283 /* Samsung */ 284 #define SAMSUNG_VENDORID 0x144d 285 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 286 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 287 288 /* Medion ? */ 289 #define MEDION_VENDORID 0x161f 290 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 291 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 292 293 /* Apple Computer Inc. */ 294 #define APPLE_VENDORID 0x106b 295 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 296 297 /* Sony */ 298 #define SONY_VENDORID 0x104d 299 #define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 300 #define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 301 302 /* 303 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 304 * instead of their own, which is beyond my comprehension 305 * (see HDA_CODEC_STAC9221 below). 306 */ 307 #define APPLE_INTEL_MAC 0x76808384 308 309 /* LG Electronics */ 310 #define LG_VENDORID 0x1854 311 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 312 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 313 314 /* Fujitsu Siemens */ 315 #define FS_VENDORID 0x1734 316 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 317 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 318 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 319 320 /* Fujitsu Limited */ 321 #define FL_VENDORID 0x10cf 322 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 323 #define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 324 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 325 326 /* Toshiba */ 327 #define TOSHIBA_VENDORID 0x1179 328 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 329 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 330 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 331 332 /* Micro-Star International (MSI) */ 333 #define MSI_VENDORID 0x1462 334 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 335 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 336 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 337 338 /* Giga-Byte Technology */ 339 #define GB_VENDORID 0x1458 340 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 341 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 342 343 /* Uniwill ? */ 344 #define UNIWILL_VENDORID 0x1584 345 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 346 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 347 348 349 /* Misc constants.. */ 350 #define HDA_AMP_VOL_DEFAULT (-1) 351 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 352 #define HDA_AMP_MUTE_NONE (0) 353 #define HDA_AMP_MUTE_LEFT (1 << 0) 354 #define HDA_AMP_MUTE_RIGHT (1 << 1) 355 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 356 357 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 358 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 359 360 #define HDA_ADC_MONITOR (1 << 0) 361 362 #define HDA_CTL_OUT 1 363 #define HDA_CTL_IN 2 364 365 #define HDA_GPIO_MAX 8 366 /* 0 - 7 = GPIO , 8 = Flush */ 367 #define HDA_QUIRK_GPIO0 (1 << 0) 368 #define HDA_QUIRK_GPIO1 (1 << 1) 369 #define HDA_QUIRK_GPIO2 (1 << 2) 370 #define HDA_QUIRK_GPIO3 (1 << 3) 371 #define HDA_QUIRK_GPIO4 (1 << 4) 372 #define HDA_QUIRK_GPIO5 (1 << 5) 373 #define HDA_QUIRK_GPIO6 (1 << 6) 374 #define HDA_QUIRK_GPIO7 (1 << 7) 375 #define HDA_QUIRK_GPIOFLUSH (1 << 8) 376 377 /* 9 - 25 = anything else */ 378 #define HDA_QUIRK_SOFTPCMVOL (1 << 9) 379 #define HDA_QUIRK_FIXEDRATE (1 << 10) 380 #define HDA_QUIRK_FORCESTEREO (1 << 11) 381 #define HDA_QUIRK_EAPDINV (1 << 12) 382 #define HDA_QUIRK_DMAPOS (1 << 13) 383 #define HDA_QUIRK_SENSEINV (1 << 14) 384 385 /* 26 - 31 = vrefs */ 386 #define HDA_QUIRK_IVREF50 (1 << 26) 387 #define HDA_QUIRK_IVREF80 (1 << 27) 388 #define HDA_QUIRK_IVREF100 (1 << 28) 389 #define HDA_QUIRK_OVREF50 (1 << 29) 390 #define HDA_QUIRK_OVREF80 (1 << 30) 391 #define HDA_QUIRK_OVREF100 (1 << 31) 392 393 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 394 HDA_QUIRK_IVREF100) 395 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 396 HDA_QUIRK_OVREF100) 397 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 398 399 #if __FreeBSD_version < 600000 400 #define taskqueue_drain(...) 401 #endif 402 403 static const struct { 404 char *key; 405 uint32_t value; 406 } hdac_quirks_tab[] = { 407 { "gpio0", HDA_QUIRK_GPIO0 }, 408 { "gpio1", HDA_QUIRK_GPIO1 }, 409 { "gpio2", HDA_QUIRK_GPIO2 }, 410 { "gpio3", HDA_QUIRK_GPIO3 }, 411 { "gpio4", HDA_QUIRK_GPIO4 }, 412 { "gpio5", HDA_QUIRK_GPIO5 }, 413 { "gpio6", HDA_QUIRK_GPIO6 }, 414 { "gpio7", HDA_QUIRK_GPIO7 }, 415 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 416 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 417 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 418 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 419 { "eapdinv", HDA_QUIRK_EAPDINV }, 420 { "dmapos", HDA_QUIRK_DMAPOS }, 421 { "senseinv", HDA_QUIRK_SENSEINV }, 422 { "ivref50", HDA_QUIRK_IVREF50 }, 423 { "ivref80", HDA_QUIRK_IVREF80 }, 424 { "ivref100", HDA_QUIRK_IVREF100 }, 425 { "ovref50", HDA_QUIRK_OVREF50 }, 426 { "ovref80", HDA_QUIRK_OVREF80 }, 427 { "ovref100", HDA_QUIRK_OVREF100 }, 428 { "ivref", HDA_QUIRK_IVREF }, 429 { "ovref", HDA_QUIRK_OVREF }, 430 { "vref", HDA_QUIRK_VREF }, 431 }; 432 #define HDAC_QUIRKS_TAB_LEN \ 433 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 434 435 #define HDA_BDL_MIN 2 436 #define HDA_BDL_MAX 256 437 #define HDA_BDL_DEFAULT HDA_BDL_MIN 438 439 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 440 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 441 442 #define HDA_BUFSZ_MIN 4096 443 #define HDA_BUFSZ_MAX 65536 444 #define HDA_BUFSZ_DEFAULT 16384 445 446 #define HDA_PARSE_MAXDEPTH 10 447 448 #define HDAC_UNSOLTAG_EVENT_HP 0x00 449 450 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 451 452 const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 453 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 454 "White", "Other"}; 455 456 const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 457 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 458 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 459 460 const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 461 462 /* Default */ 463 static uint32_t hdac_fmt[] = { 464 AFMT_STEREO | AFMT_S16_LE, 465 0 466 }; 467 468 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 469 470 #define HDAC_NO_MSI 1 471 472 static const struct { 473 uint32_t model; 474 char *desc; 475 char flags; 476 } hdac_devices[] = { 477 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 478 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 479 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 480 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 481 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 482 { HDA_INTEL_82801J, "Intel 82801J", 0 }, 483 { HDA_INTEL_PCH, "Intel PCH", 0 }, 484 { HDA_INTEL_SCH, "Intel SCH", 0 }, 485 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 486 { HDA_NVIDIA_MCP55, "NVidia MCP55", 0 }, 487 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 488 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 489 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 490 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 491 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 492 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 493 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 494 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 495 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", 0 }, 496 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", 0 }, 497 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", 0 }, 498 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", 0 }, 499 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 500 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 501 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 502 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 503 { HDA_ATI_SB450, "ATI SB450", 0 }, 504 { HDA_ATI_SB600, "ATI SB600", 0 }, 505 { HDA_ATI_RS600, "ATI RS600", 0 }, 506 { HDA_ATI_RS690, "ATI RS690", 0 }, 507 { HDA_ATI_RS780, "ATI RS780", 0 }, 508 { HDA_ATI_R600, "ATI R600", 0 }, 509 { HDA_ATI_RV610, "ATI RV610", 0 }, 510 { HDA_ATI_RV620, "ATI RV620", 0 }, 511 { HDA_ATI_RV630, "ATI RV630", 0 }, 512 { HDA_ATI_RV635, "ATI RV635", 0 }, 513 { HDA_ATI_RV710, "ATI RV710", 0 }, 514 { HDA_ATI_RV730, "ATI RV730", 0 }, 515 { HDA_ATI_RV740, "ATI RV740", 0 }, 516 { HDA_ATI_RV770, "ATI RV770", 0 }, 517 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 518 { HDA_SIS_966, "SiS 966", 0 }, 519 { HDA_ULI_M5461, "ULI M5461", 0 }, 520 /* Unknown */ 521 { HDA_INTEL_ALL, "Intel (Unknown)" }, 522 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 523 { HDA_ATI_ALL, "ATI (Unknown)" }, 524 { HDA_VIA_ALL, "VIA (Unknown)" }, 525 { HDA_SIS_ALL, "SiS (Unknown)" }, 526 { HDA_ULI_ALL, "ULI (Unknown)" }, 527 }; 528 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 529 530 static const struct { 531 uint16_t vendor; 532 uint8_t reg; 533 uint8_t mask; 534 uint8_t enable; 535 } hdac_pcie_snoop[] = { 536 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 537 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 538 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 539 }; 540 #define HDAC_PCIESNOOP_LEN \ 541 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 542 543 static const struct { 544 uint32_t rate; 545 int valid; 546 uint16_t base; 547 uint16_t mul; 548 uint16_t div; 549 } hda_rate_tab[] = { 550 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 551 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 552 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 553 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 554 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 555 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 556 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 557 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 558 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 559 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 560 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 561 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 562 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 563 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 564 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 565 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 566 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 567 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 568 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 569 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 570 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 571 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 572 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 573 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 574 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 575 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 576 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 577 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 578 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 579 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 580 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 581 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 582 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 583 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 584 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 585 }; 586 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 587 588 /* All codecs you can eat... */ 589 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 590 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 591 592 /* Realtek */ 593 #define REALTEK_VENDORID 0x10ec 594 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 595 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 596 #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 597 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 598 #define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 599 #define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 600 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 601 #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 602 #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 603 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 604 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 605 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 606 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 607 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 608 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 609 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 610 #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 611 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 612 613 /* Analog Devices */ 614 #define ANALOGDEVICES_VENDORID 0x11d4 615 #define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 616 #define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 617 #define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 618 #define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 619 #define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 620 #define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 621 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 622 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 623 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 624 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 625 #define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 626 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 627 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 628 #define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 629 #define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 630 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 631 632 /* CMedia */ 633 #define CMEDIA_VENDORID 0x434d 634 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 635 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 636 637 /* Sigmatel */ 638 #define SIGMATEL_VENDORID 0x8384 639 #define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 640 #define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 641 #define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 642 #define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 643 #define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 644 #define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 645 #define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 646 #define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 647 #define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 648 #define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 649 #define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 650 #define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 651 #define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 652 #define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 653 #define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 654 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 655 #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 656 #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 657 #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 658 #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 659 #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 660 #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 661 #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 662 #define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 663 #define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 664 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 665 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 666 #define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 667 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 668 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 669 #define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 670 #define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 671 #define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 672 #define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 673 #define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 674 #define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 675 #define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 676 #define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 677 #define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 678 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 679 680 /* IDT */ 681 #define IDT_VENDORID 0x111d 682 #define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 683 #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 684 #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 685 #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 686 #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 687 #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 688 #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 689 #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 690 #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 691 #define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 692 #define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 693 #define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 694 #define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 695 696 /* Silicon Image */ 697 #define SII_VENDORID 0x1095 698 #define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 699 #define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 700 #define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 701 702 /* Lucent/Agere */ 703 #define AGERE_VENDORID 0x11c1 704 #define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 705 706 /* Conexant */ 707 #define CONEXANT_VENDORID 0x14f1 708 #define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 709 #define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 710 #define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 711 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 712 713 /* VIA */ 714 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 715 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 716 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 717 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 718 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 719 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 720 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 721 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 722 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 723 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 724 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 725 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 726 #define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 727 #define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 728 #define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 729 #define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 730 #define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 731 #define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 732 #define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 733 #define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 734 #define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 735 #define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 736 #define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 737 #define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 738 #define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 739 #define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 740 #define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 741 #define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 742 #define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 743 #define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 744 #define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 745 #define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 746 #define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 747 #define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 748 #define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 749 #define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 750 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 751 752 /* ATI */ 753 #define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 754 #define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 755 #define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 756 #define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 757 #define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 758 759 /* NVIDIA */ 760 #define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 761 #define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 762 #define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 763 #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 764 #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 765 #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 766 767 /* INTEL */ 768 #define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 769 #define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 770 #define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 771 #define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 772 #define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 773 774 /* Codecs */ 775 static const struct { 776 uint32_t id; 777 char *name; 778 } hdac_codecs[] = { 779 { HDA_CODEC_ALC260, "Realtek ALC260" }, 780 { HDA_CODEC_ALC262, "Realtek ALC262" }, 781 { HDA_CODEC_ALC267, "Realtek ALC267" }, 782 { HDA_CODEC_ALC268, "Realtek ALC268" }, 783 { HDA_CODEC_ALC269, "Realtek ALC269" }, 784 { HDA_CODEC_ALC272, "Realtek ALC272" }, 785 { HDA_CODEC_ALC660, "Realtek ALC660" }, 786 { HDA_CODEC_ALC662, "Realtek ALC662" }, 787 { HDA_CODEC_ALC663, "Realtek ALC663" }, 788 { HDA_CODEC_ALC861, "Realtek ALC861" }, 789 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 790 { HDA_CODEC_ALC880, "Realtek ALC880" }, 791 { HDA_CODEC_ALC882, "Realtek ALC882" }, 792 { HDA_CODEC_ALC883, "Realtek ALC883" }, 793 { HDA_CODEC_ALC885, "Realtek ALC885" }, 794 { HDA_CODEC_ALC888, "Realtek ALC888" }, 795 { HDA_CODEC_ALC889, "Realtek ALC889" }, 796 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 797 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 798 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 799 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 800 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 801 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 802 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 803 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 804 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 805 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 806 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 807 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 808 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 809 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 810 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 811 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 812 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 813 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 814 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 815 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 816 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 817 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 818 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 819 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 820 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 821 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 822 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 823 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 824 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 825 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 826 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 827 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 828 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 829 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 830 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 831 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 832 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 833 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 834 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 835 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 836 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 837 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 838 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 839 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 840 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 841 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 842 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 843 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 844 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 845 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 846 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 847 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 848 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 849 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 850 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 851 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 852 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 853 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 854 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 855 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 856 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 857 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 858 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 859 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 860 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 861 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 862 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 863 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 864 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 865 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 866 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 867 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 868 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 869 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 870 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 871 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 872 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 873 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 874 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 875 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 876 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 877 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 878 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 879 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 880 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 881 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 882 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 883 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 884 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 885 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 886 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 887 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 888 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 889 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 890 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 891 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 892 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 893 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 894 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 895 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 896 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 897 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 898 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 899 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 900 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 901 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 902 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 903 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 904 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 905 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 906 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 907 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 908 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 909 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 910 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 911 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 912 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 913 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 914 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 915 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 916 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 917 /* Unknown codec */ 918 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 919 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 920 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 921 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 922 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 923 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 924 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 925 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 926 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 927 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 928 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 929 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 930 }; 931 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 932 933 934 /**************************************************************************** 935 * Function prototypes 936 ****************************************************************************/ 937 static void hdac_intr_handler(void *); 938 static int hdac_reset(struct hdac_softc *, int); 939 static int hdac_get_capabilities(struct hdac_softc *); 940 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 941 static int hdac_dma_alloc(struct hdac_softc *, 942 struct hdac_dma *, bus_size_t); 943 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 944 static int hdac_mem_alloc(struct hdac_softc *); 945 static void hdac_mem_free(struct hdac_softc *); 946 static int hdac_irq_alloc(struct hdac_softc *); 947 static void hdac_irq_free(struct hdac_softc *); 948 static void hdac_corb_init(struct hdac_softc *); 949 static void hdac_rirb_init(struct hdac_softc *); 950 static void hdac_corb_start(struct hdac_softc *); 951 static void hdac_rirb_start(struct hdac_softc *); 952 static void hdac_scan_codecs(struct hdac_softc *); 953 static void hdac_probe_codec(struct hdac_codec *); 954 static void hdac_probe_function(struct hdac_codec *, nid_t); 955 static int hdac_pcmchannel_setup(struct hdac_chan *); 956 957 static void hdac_attach2(void *); 958 959 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 960 uint32_t, int); 961 static void hdac_command_send_internal(struct hdac_softc *, 962 struct hdac_command_list *, int); 963 964 static int hdac_probe(device_t); 965 static int hdac_attach(device_t); 966 static int hdac_detach(device_t); 967 static int hdac_suspend(device_t); 968 static int hdac_resume(device_t); 969 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 970 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 971 uint32_t, int, int); 972 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 973 nid_t, int, int, int); 974 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 975 nid_t, nid_t, int, int, int, int, int, int); 976 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 977 978 static int hdac_rirb_flush(struct hdac_softc *sc); 979 static int hdac_unsolq_flush(struct hdac_softc *sc); 980 981 static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 982 983 #define hdac_command(a1, a2, a3) \ 984 hdac_command_sendone_internal(a1, a2, a3) 985 986 #define hdac_codec_id(c) \ 987 ((uint32_t)((c == NULL) ? 0x00000000 : \ 988 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 989 ((uint32_t)(c)->device_id & 0x0000ffff)))) 990 991 static char * 992 hdac_codec_name(struct hdac_codec *codec) 993 { 994 uint32_t id; 995 int i; 996 997 id = hdac_codec_id(codec); 998 999 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1000 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1001 return (hdac_codecs[i].name); 1002 } 1003 1004 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1005 } 1006 1007 static char * 1008 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1009 { 1010 static char *ossname[] = SOUND_DEVICE_NAMES; 1011 int i, first = 1; 1012 1013 bzero(buf, len); 1014 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1015 if (mask & (1 << i)) { 1016 if (first == 0) 1017 strlcat(buf, ", ", len); 1018 strlcat(buf, ossname[i], len); 1019 first = 0; 1020 } 1021 } 1022 return (buf); 1023 } 1024 1025 static struct hdac_audio_ctl * 1026 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1027 { 1028 if (devinfo == NULL || 1029 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1030 index == NULL || devinfo->function.audio.ctl == NULL || 1031 devinfo->function.audio.ctlcnt < 1 || 1032 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1033 return (NULL); 1034 return (&devinfo->function.audio.ctl[(*index)++]); 1035 } 1036 1037 static struct hdac_audio_ctl * 1038 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1039 int index, int cnt) 1040 { 1041 struct hdac_audio_ctl *ctl; 1042 int i, found = 0; 1043 1044 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1045 return (NULL); 1046 1047 i = 0; 1048 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1049 if (ctl->enable == 0) 1050 continue; 1051 if (ctl->widget->nid != nid) 1052 continue; 1053 if (dir && ctl->ndir != dir) 1054 continue; 1055 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1056 ctl->dir == ctl->ndir && ctl->index != index) 1057 continue; 1058 found++; 1059 if (found == cnt || cnt <= 0) 1060 return (ctl); 1061 } 1062 1063 return (NULL); 1064 } 1065 1066 /* 1067 * Jack detection (Speaker/HP redirection) event handler. 1068 */ 1069 static void 1070 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1071 { 1072 struct hdac_audio_as *as; 1073 struct hdac_softc *sc; 1074 struct hdac_widget *w; 1075 struct hdac_audio_ctl *ctl; 1076 uint32_t val, res; 1077 int i, j; 1078 nid_t cad; 1079 1080 if (devinfo == NULL || devinfo->codec == NULL || 1081 devinfo->codec->sc == NULL) 1082 return; 1083 1084 sc = devinfo->codec->sc; 1085 cad = devinfo->codec->cad; 1086 as = devinfo->function.audio.as; 1087 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1088 if (as[i].hpredir < 0) 1089 continue; 1090 1091 w = hdac_widget_get(devinfo, as[i].pins[15]); 1092 if (w == NULL || w->enable == 0 || w->type != 1093 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1094 continue; 1095 1096 res = hdac_command(sc, 1097 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1098 1099 HDA_BOOTVERBOSE( 1100 device_printf(sc->dev, 1101 "Pin sense: nid=%d res=0x%08x\n", 1102 as[i].pins[15], res); 1103 ); 1104 1105 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1106 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1107 res ^= 1; 1108 1109 /* (Un)Mute headphone pin. */ 1110 ctl = hdac_audio_ctl_amp_get(devinfo, 1111 as[i].pins[15], HDA_CTL_IN, -1, 1); 1112 if (ctl != NULL && ctl->mute) { 1113 /* If pin has muter - use it. */ 1114 val = (res != 0) ? 0 : 1; 1115 if (val != ctl->forcemute) { 1116 ctl->forcemute = val; 1117 hdac_audio_ctl_amp_set(ctl, 1118 HDA_AMP_MUTE_DEFAULT, 1119 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1120 } 1121 } else { 1122 /* If there is no muter - disable pin output. */ 1123 w = hdac_widget_get(devinfo, as[i].pins[15]); 1124 if (w != NULL && w->type == 1125 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1126 if (res != 0) 1127 val = w->wclass.pin.ctrl | 1128 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1129 else 1130 val = w->wclass.pin.ctrl & 1131 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1132 if (val != w->wclass.pin.ctrl) { 1133 w->wclass.pin.ctrl = val; 1134 hdac_command(sc, 1135 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1136 w->nid, w->wclass.pin.ctrl), cad); 1137 } 1138 } 1139 } 1140 /* (Un)Mute other pins. */ 1141 for (j = 0; j < 15; j++) { 1142 if (as[i].pins[j] <= 0) 1143 continue; 1144 ctl = hdac_audio_ctl_amp_get(devinfo, 1145 as[i].pins[j], HDA_CTL_IN, -1, 1); 1146 if (ctl != NULL && ctl->mute) { 1147 /* If pin has muter - use it. */ 1148 val = (res != 0) ? 1 : 0; 1149 if (val == ctl->forcemute) 1150 continue; 1151 ctl->forcemute = val; 1152 hdac_audio_ctl_amp_set(ctl, 1153 HDA_AMP_MUTE_DEFAULT, 1154 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1155 continue; 1156 } 1157 /* If there is no muter - disable pin output. */ 1158 w = hdac_widget_get(devinfo, as[i].pins[j]); 1159 if (w != NULL && w->type == 1160 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1161 if (res != 0) 1162 val = w->wclass.pin.ctrl & 1163 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1164 else 1165 val = w->wclass.pin.ctrl | 1166 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1167 if (val != w->wclass.pin.ctrl) { 1168 w->wclass.pin.ctrl = val; 1169 hdac_command(sc, 1170 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1171 w->nid, w->wclass.pin.ctrl), cad); 1172 } 1173 } 1174 } 1175 } 1176 } 1177 1178 /* 1179 * Callback for poll based jack detection. 1180 */ 1181 static void 1182 hdac_jack_poll_callback(void *arg) 1183 { 1184 struct hdac_devinfo *devinfo = arg; 1185 struct hdac_softc *sc; 1186 1187 if (devinfo == NULL || devinfo->codec == NULL || 1188 devinfo->codec->sc == NULL) 1189 return; 1190 sc = devinfo->codec->sc; 1191 hdac_lock(sc); 1192 if (sc->poll_ival == 0) { 1193 hdac_unlock(sc); 1194 return; 1195 } 1196 hdac_hp_switch_handler(devinfo); 1197 callout_reset(&sc->poll_jack, sc->poll_ival, 1198 hdac_jack_poll_callback, devinfo); 1199 hdac_unlock(sc); 1200 } 1201 1202 /* 1203 * Jack detection initializer. 1204 */ 1205 static void 1206 hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1207 { 1208 struct hdac_softc *sc = devinfo->codec->sc; 1209 struct hdac_audio_as *as = devinfo->function.audio.as; 1210 struct hdac_widget *w; 1211 uint32_t id; 1212 int i, enable = 0, poll = 0; 1213 nid_t cad; 1214 1215 id = hdac_codec_id(devinfo->codec); 1216 cad = devinfo->codec->cad; 1217 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1218 if (as[i].hpredir < 0) 1219 continue; 1220 1221 w = hdac_widget_get(devinfo, as[i].pins[15]); 1222 if (w == NULL || w->enable == 0 || w->type != 1223 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1224 continue; 1225 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1226 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1227 device_printf(sc->dev, 1228 "No jack detection support at pin %d\n", 1229 as[i].pins[15]); 1230 continue; 1231 } 1232 enable = 1; 1233 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1234 hdac_command(sc, 1235 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1236 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1237 HDAC_UNSOLTAG_EVENT_HP), cad); 1238 } else 1239 poll = 1; 1240 HDA_BOOTVERBOSE( 1241 device_printf(sc->dev, 1242 "Enabling headphone/speaker " 1243 "audio routing switching:\n"); 1244 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1245 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1246 ); 1247 } 1248 if (enable) { 1249 hdac_hp_switch_handler(devinfo); 1250 if (poll) { 1251 callout_reset(&sc->poll_jack, 1, 1252 hdac_jack_poll_callback, devinfo); 1253 } 1254 } 1255 } 1256 1257 /* 1258 * Unsolicited messages handler. 1259 */ 1260 static void 1261 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1262 { 1263 struct hdac_softc *sc; 1264 struct hdac_devinfo *devinfo = NULL; 1265 int i; 1266 1267 if (codec == NULL || codec->sc == NULL) 1268 return; 1269 1270 sc = codec->sc; 1271 1272 HDA_BOOTVERBOSE( 1273 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1274 ); 1275 1276 for (i = 0; i < codec->num_fgs; i++) { 1277 if (codec->fgs[i].node_type == 1278 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1279 devinfo = &codec->fgs[i]; 1280 break; 1281 } 1282 } 1283 1284 if (devinfo == NULL) 1285 return; 1286 1287 switch (tag) { 1288 case HDAC_UNSOLTAG_EVENT_HP: 1289 hdac_hp_switch_handler(devinfo); 1290 break; 1291 default: 1292 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1293 break; 1294 } 1295 } 1296 1297 static int 1298 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1299 { 1300 /* XXX to be removed */ 1301 #ifdef HDAC_INTR_EXTRA 1302 uint32_t res; 1303 #endif 1304 1305 if (!(ch->flags & HDAC_CHN_RUNNING)) 1306 return (0); 1307 1308 /* XXX to be removed */ 1309 #ifdef HDAC_INTR_EXTRA 1310 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1311 #endif 1312 1313 /* XXX to be removed */ 1314 #ifdef HDAC_INTR_EXTRA 1315 HDA_BOOTVERBOSE( 1316 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1317 device_printf(ch->pdevinfo->dev, 1318 "PCMDIR_%s intr triggered beyond stream boundary:" 1319 "%08x\n", 1320 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1321 ); 1322 #endif 1323 1324 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1325 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1326 1327 /* XXX to be removed */ 1328 #ifdef HDAC_INTR_EXTRA 1329 if (res & HDAC_SDSTS_BCIS) { 1330 #endif 1331 return (1); 1332 /* XXX to be removed */ 1333 #ifdef HDAC_INTR_EXTRA 1334 } 1335 #endif 1336 1337 return (0); 1338 } 1339 1340 /**************************************************************************** 1341 * void hdac_intr_handler(void *) 1342 * 1343 * Interrupt handler. Processes interrupts received from the hdac. 1344 ****************************************************************************/ 1345 static void 1346 hdac_intr_handler(void *context) 1347 { 1348 struct hdac_softc *sc; 1349 uint32_t intsts; 1350 uint8_t rirbsts; 1351 struct hdac_rirb *rirb_base; 1352 uint32_t trigger; 1353 int i; 1354 1355 sc = (struct hdac_softc *)context; 1356 1357 hdac_lock(sc); 1358 if (sc->polling != 0) { 1359 hdac_unlock(sc); 1360 return; 1361 } 1362 1363 /* Do we have anything to do? */ 1364 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1365 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1366 hdac_unlock(sc); 1367 return; 1368 } 1369 1370 trigger = 0; 1371 1372 /* Was this a controller interrupt? */ 1373 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1374 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1375 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1376 /* Get as many responses that we can */ 1377 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1378 HDAC_WRITE_1(&sc->mem, 1379 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1380 if (hdac_rirb_flush(sc) != 0) 1381 trigger |= HDAC_TRIGGER_UNSOL; 1382 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1383 } 1384 /* XXX to be removed */ 1385 /* Clear interrupt and exit */ 1386 #ifdef HDAC_INTR_EXTRA 1387 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1388 #endif 1389 } 1390 1391 if (intsts & HDAC_INTSTS_SIS_MASK) { 1392 for (i = 0; i < sc->num_chans; i++) { 1393 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1394 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1395 trigger |= (1 << i); 1396 } 1397 /* XXX to be removed */ 1398 #ifdef HDAC_INTR_EXTRA 1399 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1400 HDAC_INTSTS_SIS_MASK); 1401 #endif 1402 } 1403 1404 hdac_unlock(sc); 1405 1406 for (i = 0; i < sc->num_chans; i++) { 1407 if (trigger & (1 << i)) 1408 chn_intr(sc->chans[i].c); 1409 } 1410 if (trigger & HDAC_TRIGGER_UNSOL) 1411 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1412 } 1413 1414 /**************************************************************************** 1415 * int hdac_reset(hdac_softc *, int) 1416 * 1417 * Reset the hdac to a quiescent and known state. 1418 ****************************************************************************/ 1419 static int 1420 hdac_reset(struct hdac_softc *sc, int wakeup) 1421 { 1422 uint32_t gctl; 1423 int count, i; 1424 1425 /* 1426 * Stop all Streams DMA engine 1427 */ 1428 for (i = 0; i < sc->num_iss; i++) 1429 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1430 for (i = 0; i < sc->num_oss; i++) 1431 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1432 for (i = 0; i < sc->num_bss; i++) 1433 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1434 1435 /* 1436 * Stop Control DMA engines. 1437 */ 1438 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1439 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1440 1441 /* 1442 * Reset DMA position buffer. 1443 */ 1444 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1445 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1446 1447 /* 1448 * Reset the controller. The reset must remain asserted for 1449 * a minimum of 100us. 1450 */ 1451 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1452 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1453 count = 10000; 1454 do { 1455 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1456 if (!(gctl & HDAC_GCTL_CRST)) 1457 break; 1458 DELAY(10); 1459 } while (--count); 1460 if (gctl & HDAC_GCTL_CRST) { 1461 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1462 return (ENXIO); 1463 } 1464 1465 /* If wakeup is not requested - leave the controller in reset state. */ 1466 if (!wakeup) 1467 return (0); 1468 1469 DELAY(100); 1470 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1471 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1472 count = 10000; 1473 do { 1474 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1475 if (gctl & HDAC_GCTL_CRST) 1476 break; 1477 DELAY(10); 1478 } while (--count); 1479 if (!(gctl & HDAC_GCTL_CRST)) { 1480 device_printf(sc->dev, "Device stuck in reset\n"); 1481 return (ENXIO); 1482 } 1483 1484 /* 1485 * Wait for codecs to finish their own reset sequence. The delay here 1486 * should be of 250us but for some reasons, on it's not enough on my 1487 * computer. Let's use twice as much as necessary to make sure that 1488 * it's reset properly. 1489 */ 1490 DELAY(1000); 1491 1492 return (0); 1493 } 1494 1495 1496 /**************************************************************************** 1497 * int hdac_get_capabilities(struct hdac_softc *); 1498 * 1499 * Retreive the general capabilities of the hdac; 1500 * Number of Input Streams 1501 * Number of Output Streams 1502 * Number of bidirectional Streams 1503 * 64bit ready 1504 * CORB and RIRB sizes 1505 ****************************************************************************/ 1506 static int 1507 hdac_get_capabilities(struct hdac_softc *sc) 1508 { 1509 uint16_t gcap; 1510 uint8_t corbsize, rirbsize; 1511 1512 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1513 sc->num_iss = HDAC_GCAP_ISS(gcap); 1514 sc->num_oss = HDAC_GCAP_OSS(gcap); 1515 sc->num_bss = HDAC_GCAP_BSS(gcap); 1516 1517 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1518 1519 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1520 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1521 HDAC_CORBSIZE_CORBSZCAP_256) 1522 sc->corb_size = 256; 1523 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1524 HDAC_CORBSIZE_CORBSZCAP_16) 1525 sc->corb_size = 16; 1526 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1527 HDAC_CORBSIZE_CORBSZCAP_2) 1528 sc->corb_size = 2; 1529 else { 1530 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1531 __func__, corbsize); 1532 return (ENXIO); 1533 } 1534 1535 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1536 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1537 HDAC_RIRBSIZE_RIRBSZCAP_256) 1538 sc->rirb_size = 256; 1539 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1540 HDAC_RIRBSIZE_RIRBSZCAP_16) 1541 sc->rirb_size = 16; 1542 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1543 HDAC_RIRBSIZE_RIRBSZCAP_2) 1544 sc->rirb_size = 2; 1545 else { 1546 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1547 __func__, rirbsize); 1548 return (ENXIO); 1549 } 1550 1551 HDA_BOOTHVERBOSE( 1552 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1553 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1554 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1555 sc->num_iss, sc->num_oss, sc->num_bss); 1556 ); 1557 1558 return (0); 1559 } 1560 1561 1562 /**************************************************************************** 1563 * void hdac_dma_cb 1564 * 1565 * This function is called by bus_dmamap_load when the mapping has been 1566 * established. We just record the physical address of the mapping into 1567 * the struct hdac_dma passed in. 1568 ****************************************************************************/ 1569 static void 1570 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1571 { 1572 struct hdac_dma *dma; 1573 1574 if (error == 0) { 1575 dma = (struct hdac_dma *)callback_arg; 1576 dma->dma_paddr = segs[0].ds_addr; 1577 } 1578 } 1579 1580 1581 /**************************************************************************** 1582 * int hdac_dma_alloc 1583 * 1584 * This function allocate and setup a dma region (struct hdac_dma). 1585 * It must be freed by a corresponding hdac_dma_free. 1586 ****************************************************************************/ 1587 static int 1588 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1589 { 1590 bus_size_t roundsz; 1591 int result; 1592 int lowaddr; 1593 1594 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1595 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1596 BUS_SPACE_MAXADDR_32BIT; 1597 bzero(dma, sizeof(*dma)); 1598 1599 /* 1600 * Create a DMA tag 1601 */ 1602 result = bus_dma_tag_create(NULL, /* parent */ 1603 HDAC_DMA_ALIGNMENT, /* alignment */ 1604 0, /* boundary */ 1605 lowaddr, /* lowaddr */ 1606 BUS_SPACE_MAXADDR, /* highaddr */ 1607 NULL, /* filtfunc */ 1608 NULL, /* fistfuncarg */ 1609 roundsz, /* maxsize */ 1610 1, /* nsegments */ 1611 roundsz, /* maxsegsz */ 1612 0, /* flags */ 1613 NULL, /* lockfunc */ 1614 NULL, /* lockfuncarg */ 1615 &dma->dma_tag); /* dmat */ 1616 if (result != 0) { 1617 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1618 __func__, result); 1619 goto hdac_dma_alloc_fail; 1620 } 1621 1622 /* 1623 * Allocate DMA memory 1624 */ 1625 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1626 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1627 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1628 &dma->dma_map); 1629 if (result != 0) { 1630 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1631 __func__, result); 1632 goto hdac_dma_alloc_fail; 1633 } 1634 1635 dma->dma_size = roundsz; 1636 1637 /* 1638 * Map the memory 1639 */ 1640 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1641 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1642 if (result != 0 || dma->dma_paddr == 0) { 1643 if (result == 0) 1644 result = ENOMEM; 1645 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1646 __func__, result); 1647 goto hdac_dma_alloc_fail; 1648 } 1649 1650 HDA_BOOTHVERBOSE( 1651 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1652 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1653 ); 1654 1655 return (0); 1656 1657 hdac_dma_alloc_fail: 1658 hdac_dma_free(sc, dma); 1659 1660 return (result); 1661 } 1662 1663 1664 /**************************************************************************** 1665 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1666 * 1667 * Free a struct dhac_dma that has been previously allocated via the 1668 * hdac_dma_alloc function. 1669 ****************************************************************************/ 1670 static void 1671 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1672 { 1673 if (dma->dma_map != NULL) { 1674 #if 0 1675 /* Flush caches */ 1676 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1677 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1678 #endif 1679 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1680 } 1681 if (dma->dma_vaddr != NULL) { 1682 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1683 dma->dma_vaddr = NULL; 1684 } 1685 dma->dma_map = NULL; 1686 if (dma->dma_tag != NULL) { 1687 bus_dma_tag_destroy(dma->dma_tag); 1688 dma->dma_tag = NULL; 1689 } 1690 dma->dma_size = 0; 1691 } 1692 1693 /**************************************************************************** 1694 * int hdac_mem_alloc(struct hdac_softc *) 1695 * 1696 * Allocate all the bus resources necessary to speak with the physical 1697 * controller. 1698 ****************************************************************************/ 1699 static int 1700 hdac_mem_alloc(struct hdac_softc *sc) 1701 { 1702 struct hdac_mem *mem; 1703 1704 mem = &sc->mem; 1705 mem->mem_rid = PCIR_BAR(0); 1706 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1707 &mem->mem_rid, RF_ACTIVE); 1708 if (mem->mem_res == NULL) { 1709 device_printf(sc->dev, 1710 "%s: Unable to allocate memory resource\n", __func__); 1711 return (ENOMEM); 1712 } 1713 mem->mem_tag = rman_get_bustag(mem->mem_res); 1714 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1715 1716 return (0); 1717 } 1718 1719 /**************************************************************************** 1720 * void hdac_mem_free(struct hdac_softc *) 1721 * 1722 * Free up resources previously allocated by hdac_mem_alloc. 1723 ****************************************************************************/ 1724 static void 1725 hdac_mem_free(struct hdac_softc *sc) 1726 { 1727 struct hdac_mem *mem; 1728 1729 mem = &sc->mem; 1730 if (mem->mem_res != NULL) 1731 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1732 mem->mem_res); 1733 mem->mem_res = NULL; 1734 } 1735 1736 /**************************************************************************** 1737 * int hdac_irq_alloc(struct hdac_softc *) 1738 * 1739 * Allocate and setup the resources necessary for interrupt handling. 1740 ****************************************************************************/ 1741 static int 1742 hdac_irq_alloc(struct hdac_softc *sc) 1743 { 1744 struct hdac_irq *irq; 1745 int result; 1746 1747 irq = &sc->irq; 1748 irq->irq_rid = 0x0; 1749 1750 if ((sc->flags & HDAC_F_MSI) && 1751 (result = pci_msi_count(sc->dev)) == 1 && 1752 pci_alloc_msi(sc->dev, &result) == 0) 1753 irq->irq_rid = 0x1; 1754 else 1755 sc->flags &= ~HDAC_F_MSI; 1756 1757 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1758 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1759 if (irq->irq_res == NULL) { 1760 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1761 __func__); 1762 goto hdac_irq_alloc_fail; 1763 } 1764 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1765 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1766 if (result != 0) { 1767 device_printf(sc->dev, 1768 "%s: Unable to setup interrupt handler (%x)\n", 1769 __func__, result); 1770 goto hdac_irq_alloc_fail; 1771 } 1772 1773 return (0); 1774 1775 hdac_irq_alloc_fail: 1776 hdac_irq_free(sc); 1777 1778 return (ENXIO); 1779 } 1780 1781 /**************************************************************************** 1782 * void hdac_irq_free(struct hdac_softc *) 1783 * 1784 * Free up resources previously allocated by hdac_irq_alloc. 1785 ****************************************************************************/ 1786 static void 1787 hdac_irq_free(struct hdac_softc *sc) 1788 { 1789 struct hdac_irq *irq; 1790 1791 irq = &sc->irq; 1792 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1793 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1794 if (irq->irq_res != NULL) 1795 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1796 irq->irq_res); 1797 if (irq->irq_rid == 0x1) 1798 pci_release_msi(sc->dev); 1799 irq->irq_handle = NULL; 1800 irq->irq_res = NULL; 1801 irq->irq_rid = 0x0; 1802 } 1803 1804 /**************************************************************************** 1805 * void hdac_corb_init(struct hdac_softc *) 1806 * 1807 * Initialize the corb registers for operations but do not start it up yet. 1808 * The CORB engine must not be running when this function is called. 1809 ****************************************************************************/ 1810 static void 1811 hdac_corb_init(struct hdac_softc *sc) 1812 { 1813 uint8_t corbsize; 1814 uint64_t corbpaddr; 1815 1816 /* Setup the CORB size. */ 1817 switch (sc->corb_size) { 1818 case 256: 1819 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1820 break; 1821 case 16: 1822 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1823 break; 1824 case 2: 1825 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1826 break; 1827 default: 1828 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1829 } 1830 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1831 1832 /* Setup the CORB Address in the hdac */ 1833 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1834 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1835 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1836 1837 /* Set the WP and RP */ 1838 sc->corb_wp = 0; 1839 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1840 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1841 /* 1842 * The HDA specification indicates that the CORBRPRST bit will always 1843 * read as zero. Unfortunately, it seems that at least the 82801G 1844 * doesn't reset the bit to zero, which stalls the corb engine. 1845 * manually reset the bit to zero before continuing. 1846 */ 1847 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1848 1849 /* Enable CORB error reporting */ 1850 #if 0 1851 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1852 #endif 1853 } 1854 1855 /**************************************************************************** 1856 * void hdac_rirb_init(struct hdac_softc *) 1857 * 1858 * Initialize the rirb registers for operations but do not start it up yet. 1859 * The RIRB engine must not be running when this function is called. 1860 ****************************************************************************/ 1861 static void 1862 hdac_rirb_init(struct hdac_softc *sc) 1863 { 1864 uint8_t rirbsize; 1865 uint64_t rirbpaddr; 1866 1867 /* Setup the RIRB size. */ 1868 switch (sc->rirb_size) { 1869 case 256: 1870 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1871 break; 1872 case 16: 1873 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1874 break; 1875 case 2: 1876 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1877 break; 1878 default: 1879 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1880 } 1881 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1882 1883 /* Setup the RIRB Address in the hdac */ 1884 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1885 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1886 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1887 1888 /* Setup the WP and RP */ 1889 sc->rirb_rp = 0; 1890 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1891 1892 /* Setup the interrupt threshold */ 1893 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1894 1895 /* Enable Overrun and response received reporting */ 1896 #if 0 1897 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1898 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1899 #else 1900 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1901 #endif 1902 1903 #if 0 1904 /* 1905 * Make sure that the Host CPU cache doesn't contain any dirty 1906 * cache lines that falls in the rirb. If I understood correctly, it 1907 * should be sufficient to do this only once as the rirb is purely 1908 * read-only from now on. 1909 */ 1910 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1911 BUS_DMASYNC_PREREAD); 1912 #endif 1913 } 1914 1915 /**************************************************************************** 1916 * void hdac_corb_start(hdac_softc *) 1917 * 1918 * Startup the corb DMA engine 1919 ****************************************************************************/ 1920 static void 1921 hdac_corb_start(struct hdac_softc *sc) 1922 { 1923 uint32_t corbctl; 1924 1925 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1926 corbctl |= HDAC_CORBCTL_CORBRUN; 1927 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1928 } 1929 1930 /**************************************************************************** 1931 * void hdac_rirb_start(hdac_softc *) 1932 * 1933 * Startup the rirb DMA engine 1934 ****************************************************************************/ 1935 static void 1936 hdac_rirb_start(struct hdac_softc *sc) 1937 { 1938 uint32_t rirbctl; 1939 1940 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1941 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1942 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1943 } 1944 1945 1946 /**************************************************************************** 1947 * void hdac_scan_codecs(struct hdac_softc *, int) 1948 * 1949 * Scan the bus for available codecs, starting with num. 1950 ****************************************************************************/ 1951 static void 1952 hdac_scan_codecs(struct hdac_softc *sc) 1953 { 1954 struct hdac_codec *codec; 1955 int i; 1956 uint16_t statests; 1957 1958 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1959 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1960 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1961 /* We have found a codec. */ 1962 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1963 M_HDAC, M_ZERO | M_NOWAIT); 1964 if (codec == NULL) { 1965 device_printf(sc->dev, 1966 "Unable to allocate memory for codec\n"); 1967 continue; 1968 } 1969 codec->commands = NULL; 1970 codec->responses_received = 0; 1971 codec->verbs_sent = 0; 1972 codec->sc = sc; 1973 codec->cad = i; 1974 sc->codecs[i] = codec; 1975 hdac_probe_codec(codec); 1976 } 1977 } 1978 /* All codecs have been probed, now try to attach drivers to them */ 1979 /* bus_generic_attach(sc->dev); */ 1980 } 1981 1982 /**************************************************************************** 1983 * void hdac_probe_codec(struct hdac_softc *, int) 1984 * 1985 * Probe a the given codec_id for available function groups. 1986 ****************************************************************************/ 1987 static void 1988 hdac_probe_codec(struct hdac_codec *codec) 1989 { 1990 struct hdac_softc *sc = codec->sc; 1991 uint32_t vendorid, revisionid, subnode; 1992 int startnode; 1993 int endnode; 1994 int i; 1995 nid_t cad = codec->cad; 1996 1997 HDA_BOOTVERBOSE( 1998 device_printf(sc->dev, "Probing codec #%d...\n", cad); 1999 ); 2000 vendorid = hdac_command(sc, 2001 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2002 cad); 2003 revisionid = hdac_command(sc, 2004 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2005 cad); 2006 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2007 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2008 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2009 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2010 2011 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2012 device_printf(sc->dev, "Codec #%d is not responding!" 2013 " Probing aborted.\n", cad); 2014 return; 2015 } 2016 2017 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2018 cad, hdac_codec_name(codec)); 2019 HDA_BOOTVERBOSE( 2020 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2021 hdac_codec_id(codec)); 2022 device_printf(sc->dev, " Vendor: 0x%04x\n", 2023 codec->vendor_id); 2024 device_printf(sc->dev, " Device: 0x%04x\n", 2025 codec->device_id); 2026 device_printf(sc->dev, " Revision: 0x%02x\n", 2027 codec->revision_id); 2028 device_printf(sc->dev, " Stepping: 0x%02x\n", 2029 codec->stepping_id); 2030 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2031 sc->pci_subvendor); 2032 ); 2033 subnode = hdac_command(sc, 2034 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2035 cad); 2036 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2037 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2038 2039 HDA_BOOTHVERBOSE( 2040 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2041 startnode, endnode); 2042 ); 2043 2044 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2045 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2046 if (codec->fgs == NULL) { 2047 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2048 __func__); 2049 return; 2050 } 2051 2052 for (i = startnode; i < endnode; i++) 2053 hdac_probe_function(codec, i); 2054 return; 2055 } 2056 2057 /* 2058 * Probe codec function and add it to the list. 2059 */ 2060 static void 2061 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2062 { 2063 struct hdac_softc *sc = codec->sc; 2064 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2065 uint32_t fctgrptype; 2066 uint32_t res; 2067 nid_t cad = codec->cad; 2068 2069 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2070 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2071 2072 devinfo->nid = nid; 2073 devinfo->node_type = fctgrptype; 2074 devinfo->codec = codec; 2075 2076 res = hdac_command(sc, 2077 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2078 2079 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2080 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2081 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2082 2083 HDA_BOOTVERBOSE( 2084 device_printf(sc->dev, 2085 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2086 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2087 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2088 "unknown", nid, devinfo->startnode, devinfo->endnode, 2089 devinfo->nodecnt); 2090 ); 2091 2092 if (devinfo->nodecnt > 0) 2093 devinfo->widget = (struct hdac_widget *)malloc( 2094 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2095 M_NOWAIT | M_ZERO); 2096 else 2097 devinfo->widget = NULL; 2098 2099 if (devinfo->widget == NULL) { 2100 device_printf(sc->dev, "unable to allocate widgets!\n"); 2101 devinfo->endnode = devinfo->startnode; 2102 devinfo->nodecnt = 0; 2103 return; 2104 } 2105 2106 codec->num_fgs++; 2107 } 2108 2109 static void 2110 hdac_widget_connection_parse(struct hdac_widget *w) 2111 { 2112 struct hdac_softc *sc = w->devinfo->codec->sc; 2113 uint32_t res; 2114 int i, j, max, ents, entnum; 2115 nid_t cad = w->devinfo->codec->cad; 2116 nid_t nid = w->nid; 2117 nid_t cnid, addcnid, prevcnid; 2118 2119 w->nconns = 0; 2120 2121 res = hdac_command(sc, 2122 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2123 2124 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2125 2126 if (ents < 1) 2127 return; 2128 2129 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2130 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2131 prevcnid = 0; 2132 2133 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2134 #define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2135 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2136 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2137 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2138 2139 for (i = 0; i < ents; i += entnum) { 2140 res = hdac_command(sc, 2141 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2142 for (j = 0; j < entnum; j++) { 2143 cnid = CONN_CNID(res, entnum, j); 2144 if (cnid == 0) { 2145 if (w->nconns < ents) 2146 device_printf(sc->dev, 2147 "%s: nid=%d WARNING: zero cnid " 2148 "entnum=%d j=%d index=%d " 2149 "entries=%d found=%d res=0x%08x\n", 2150 __func__, nid, entnum, j, i, 2151 ents, w->nconns, res); 2152 else 2153 goto getconns_out; 2154 } 2155 if (cnid < w->devinfo->startnode || 2156 cnid >= w->devinfo->endnode) { 2157 HDA_BOOTVERBOSE( 2158 device_printf(sc->dev, 2159 "GHOST: nid=%d j=%d " 2160 "entnum=%d index=%d res=0x%08x\n", 2161 nid, j, entnum, i, res); 2162 ); 2163 } 2164 if (CONN_RANGE(res, entnum, j) == 0) 2165 addcnid = cnid; 2166 else if (prevcnid == 0 || prevcnid >= cnid) { 2167 device_printf(sc->dev, 2168 "%s: WARNING: Invalid child range " 2169 "nid=%d index=%d j=%d entnum=%d " 2170 "prevcnid=%d cnid=%d res=0x%08x\n", 2171 __func__, nid, i, j, entnum, prevcnid, 2172 cnid, res); 2173 addcnid = cnid; 2174 } else 2175 addcnid = prevcnid + 1; 2176 while (addcnid <= cnid) { 2177 if (w->nconns > max) { 2178 device_printf(sc->dev, 2179 "Adding %d (nid=%d): " 2180 "Max connection reached! max=%d\n", 2181 addcnid, nid, max + 1); 2182 goto getconns_out; 2183 } 2184 w->connsenable[w->nconns] = 1; 2185 w->conns[w->nconns++] = addcnid++; 2186 } 2187 prevcnid = cnid; 2188 } 2189 } 2190 2191 getconns_out: 2192 return; 2193 } 2194 2195 static uint32_t 2196 hdac_widget_pin_patch(uint32_t config, const char *str) 2197 { 2198 char buf[256]; 2199 char *key, *value, *rest, *bad; 2200 int ival, i; 2201 2202 strlcpy(buf, str, sizeof(buf)); 2203 rest = buf; 2204 while ((key = strsep(&rest, "=")) != NULL) { 2205 value = strsep(&rest, " \t"); 2206 if (value == NULL) 2207 break; 2208 ival = strtol(value, &bad, 10); 2209 if (strcmp(key, "seq") == 0) { 2210 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2211 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2212 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2213 } else if (strcmp(key, "as") == 0) { 2214 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2215 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2216 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2217 } else if (strcmp(key, "misc") == 0) { 2218 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2219 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2220 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2221 } else if (strcmp(key, "color") == 0) { 2222 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2223 if (bad[0] == 0) { 2224 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2225 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2226 }; 2227 for (i = 0; i < 16; i++) { 2228 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2229 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2230 break; 2231 } 2232 } 2233 } else if (strcmp(key, "ctype") == 0) { 2234 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2235 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2236 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2237 } else if (strcmp(key, "device") == 0) { 2238 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2239 if (bad[0] == 0) { 2240 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2241 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2242 continue; 2243 }; 2244 for (i = 0; i < 16; i++) { 2245 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2246 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2247 break; 2248 } 2249 } 2250 } else if (strcmp(key, "loc") == 0) { 2251 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2252 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2253 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2254 } else if (strcmp(key, "conn") == 0) { 2255 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2256 if (bad[0] == 0) { 2257 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2258 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2259 continue; 2260 }; 2261 for (i = 0; i < 4; i++) { 2262 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2263 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2264 break; 2265 } 2266 } 2267 } 2268 } 2269 return (config); 2270 } 2271 2272 static uint32_t 2273 hdac_widget_pin_getconfig(struct hdac_widget *w) 2274 { 2275 struct hdac_softc *sc; 2276 uint32_t config, orig, id; 2277 nid_t cad, nid; 2278 char buf[32]; 2279 const char *res = NULL, *patch = NULL; 2280 2281 sc = w->devinfo->codec->sc; 2282 cad = w->devinfo->codec->cad; 2283 nid = w->nid; 2284 id = hdac_codec_id(w->devinfo->codec); 2285 2286 config = hdac_command(sc, 2287 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2288 cad); 2289 orig = config; 2290 2291 HDA_BOOTVERBOSE( 2292 hdac_dump_pin_config(w, orig); 2293 ); 2294 2295 /* XXX: Old patches require complete review. 2296 * Now they may create more problem then solve due to 2297 * incorrect associations. 2298 */ 2299 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2300 switch (nid) { 2301 case 26: 2302 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2303 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2304 break; 2305 case 27: 2306 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2307 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2308 break; 2309 default: 2310 break; 2311 } 2312 } else if (id == HDA_CODEC_ALC880 && 2313 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2314 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2315 /* 2316 * Super broken BIOS 2317 */ 2318 switch (nid) { 2319 case 24: /* MIC1 */ 2320 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2321 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2322 break; 2323 case 25: /* XXX MIC2 */ 2324 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2325 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2326 break; 2327 case 26: /* LINE1 */ 2328 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2329 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2330 break; 2331 case 27: /* XXX LINE2 */ 2332 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2333 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2334 break; 2335 case 28: /* CD */ 2336 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2337 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2338 break; 2339 } 2340 } else if (id == HDA_CODEC_ALC883 && 2341 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2342 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2343 switch (nid) { 2344 case 25: 2345 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2346 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2347 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2348 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2349 break; 2350 case 28: 2351 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2352 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2353 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2354 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2355 break; 2356 } 2357 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2358 HP_V3000_SUBVENDOR) { 2359 switch (nid) { 2360 case 18: 2361 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2362 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2363 break; 2364 case 20: 2365 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2366 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2367 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2368 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2369 break; 2370 case 21: 2371 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2372 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2373 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2374 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2375 break; 2376 } 2377 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2378 HP_DV5000_SUBVENDOR) { 2379 switch (nid) { 2380 case 20: 2381 case 21: 2382 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2383 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2384 break; 2385 } 2386 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2387 ASUS_W6F_SUBVENDOR) { 2388 switch (nid) { 2389 case 11: 2390 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2391 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2392 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2393 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2394 break; 2395 case 12: 2396 case 14: 2397 case 16: 2398 case 31: 2399 case 32: 2400 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2401 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2402 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2403 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2404 break; 2405 case 15: 2406 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2407 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2408 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2409 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2410 break; 2411 } 2412 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2413 UNIWILL_9075_SUBVENDOR) { 2414 switch (nid) { 2415 case 15: 2416 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2417 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2418 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2419 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2420 break; 2421 } 2422 } 2423 2424 /* New patches */ 2425 if (id == HDA_CODEC_AD1986A && 2426 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2427 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2428 switch (nid) { 2429 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2430 patch = "device=Line-in as=8 seq=1"; 2431 break; 2432 case 29: 2433 patch = "device=Mic as=8 seq=2"; 2434 break; 2435 case 31: /* Lot of inputs configured with as=15 and unusable */ 2436 patch = "as=8 seq=3"; 2437 break; 2438 case 32: 2439 patch = "as=8 seq=4"; 2440 break; 2441 case 34: 2442 patch = "as=8 seq=5"; 2443 break; 2444 case 36: 2445 patch = "as=8 seq=6"; 2446 break; 2447 } 2448 } else if (id == HDA_CODEC_ALC260 && 2449 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2450 switch (nid) { 2451 case 16: 2452 patch = "seq=15 device=Headphones"; 2453 break; 2454 } 2455 } else if (id == HDA_CODEC_ALC268 && 2456 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2457 switch (nid) { 2458 case 28: 2459 patch = "device=CD conn=fixed"; 2460 break; 2461 } 2462 } 2463 2464 if (patch != NULL) 2465 config = hdac_widget_pin_patch(config, patch); 2466 2467 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2468 if (resource_string_value(device_get_name(sc->dev), 2469 device_get_unit(sc->dev), buf, &res) == 0) { 2470 if (strncmp(res, "0x", 2) == 0) { 2471 config = strtol(res + 2, NULL, 16); 2472 } else { 2473 config = hdac_widget_pin_patch(config, res); 2474 } 2475 } 2476 2477 HDA_BOOTVERBOSE( 2478 if (config != orig) 2479 device_printf(sc->dev, 2480 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2481 nid, orig, config); 2482 ); 2483 2484 return (config); 2485 } 2486 2487 static uint32_t 2488 hdac_widget_pin_getcaps(struct hdac_widget *w) 2489 { 2490 struct hdac_softc *sc; 2491 uint32_t caps, orig, id; 2492 nid_t cad, nid; 2493 2494 sc = w->devinfo->codec->sc; 2495 cad = w->devinfo->codec->cad; 2496 nid = w->nid; 2497 id = hdac_codec_id(w->devinfo->codec); 2498 2499 caps = hdac_command(sc, 2500 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2501 orig = caps; 2502 2503 HDA_BOOTVERBOSE( 2504 if (caps != orig) 2505 device_printf(sc->dev, 2506 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2507 nid, orig, caps); 2508 ); 2509 2510 return (caps); 2511 } 2512 2513 static void 2514 hdac_widget_pin_parse(struct hdac_widget *w) 2515 { 2516 struct hdac_softc *sc = w->devinfo->codec->sc; 2517 uint32_t config, pincap; 2518 const char *devstr; 2519 nid_t cad = w->devinfo->codec->cad; 2520 nid_t nid = w->nid; 2521 int conn, color; 2522 2523 config = hdac_widget_pin_getconfig(w); 2524 w->wclass.pin.config = config; 2525 2526 pincap = hdac_widget_pin_getcaps(w); 2527 w->wclass.pin.cap = pincap; 2528 2529 w->wclass.pin.ctrl = hdac_command(sc, 2530 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2531 2532 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2533 w->param.eapdbtl = hdac_command(sc, 2534 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2535 w->param.eapdbtl &= 0x7; 2536 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2537 } else 2538 w->param.eapdbtl = HDAC_INVALID; 2539 2540 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2541 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2542 2543 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2544 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2545 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2546 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2547 2548 strlcat(w->name, ": ", sizeof(w->name)); 2549 strlcat(w->name, devstr, sizeof(w->name)); 2550 strlcat(w->name, " (", sizeof(w->name)); 2551 if (conn == 0 && color != 0 && color != 15) { 2552 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2553 strlcat(w->name, " ", sizeof(w->name)); 2554 } 2555 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2556 strlcat(w->name, ")", sizeof(w->name)); 2557 } 2558 2559 static uint32_t 2560 hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2561 { 2562 struct hdac_softc *sc; 2563 uint32_t caps, orig, id; 2564 nid_t cad, nid, beeper = -1; 2565 2566 sc = w->devinfo->codec->sc; 2567 cad = w->devinfo->codec->cad; 2568 nid = w->nid; 2569 id = hdac_codec_id(w->devinfo->codec); 2570 2571 caps = hdac_command(sc, 2572 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2573 cad); 2574 orig = caps; 2575 2576 /* On some codecs beeper is an input pin, but it is not recordable 2577 alone. Also most of BIOSes does not declare beeper pin. 2578 Change beeper pin node type to beeper to help parser. */ 2579 *waspin = 0; 2580 switch (id) { 2581 case HDA_CODEC_AD1882: 2582 case HDA_CODEC_AD1883: 2583 case HDA_CODEC_AD1984: 2584 case HDA_CODEC_AD1984A: 2585 case HDA_CODEC_AD1984B: 2586 case HDA_CODEC_AD1987: 2587 case HDA_CODEC_AD1988: 2588 case HDA_CODEC_AD1988B: 2589 case HDA_CODEC_AD1989B: 2590 beeper = 26; 2591 break; 2592 case HDA_CODEC_ALC260: 2593 beeper = 23; 2594 break; 2595 case HDA_CODEC_ALC262: 2596 case HDA_CODEC_ALC268: 2597 case HDA_CODEC_ALC880: 2598 case HDA_CODEC_ALC882: 2599 case HDA_CODEC_ALC883: 2600 case HDA_CODEC_ALC885: 2601 case HDA_CODEC_ALC888: 2602 case HDA_CODEC_ALC889: 2603 beeper = 29; 2604 break; 2605 } 2606 if (nid == beeper) { 2607 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2608 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2609 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2610 *waspin = 1; 2611 } 2612 2613 HDA_BOOTVERBOSE( 2614 if (caps != orig) { 2615 device_printf(sc->dev, 2616 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2617 nid, orig, caps); 2618 } 2619 ); 2620 2621 return (caps); 2622 } 2623 2624 static void 2625 hdac_widget_parse(struct hdac_widget *w) 2626 { 2627 struct hdac_softc *sc = w->devinfo->codec->sc; 2628 uint32_t wcap, cap; 2629 char *typestr; 2630 nid_t cad = w->devinfo->codec->cad; 2631 nid_t nid = w->nid; 2632 2633 wcap = hdac_widget_getcaps(w, &w->waspin); 2634 2635 w->param.widget_cap = wcap; 2636 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2637 2638 switch (w->type) { 2639 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2640 typestr = "audio output"; 2641 break; 2642 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2643 typestr = "audio input"; 2644 break; 2645 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2646 typestr = "audio mixer"; 2647 break; 2648 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2649 typestr = "audio selector"; 2650 break; 2651 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2652 typestr = "pin"; 2653 break; 2654 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2655 typestr = "power widget"; 2656 break; 2657 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2658 typestr = "volume widget"; 2659 break; 2660 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2661 typestr = "beep widget"; 2662 break; 2663 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2664 typestr = "vendor widget"; 2665 break; 2666 default: 2667 typestr = "unknown type"; 2668 break; 2669 } 2670 2671 strlcpy(w->name, typestr, sizeof(w->name)); 2672 2673 hdac_widget_connection_parse(w); 2674 2675 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2676 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2677 w->param.outamp_cap = 2678 hdac_command(sc, 2679 HDA_CMD_GET_PARAMETER(cad, nid, 2680 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2681 else 2682 w->param.outamp_cap = 2683 w->devinfo->function.audio.outamp_cap; 2684 } else 2685 w->param.outamp_cap = 0; 2686 2687 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2688 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2689 w->param.inamp_cap = 2690 hdac_command(sc, 2691 HDA_CMD_GET_PARAMETER(cad, nid, 2692 HDA_PARAM_INPUT_AMP_CAP), cad); 2693 else 2694 w->param.inamp_cap = 2695 w->devinfo->function.audio.inamp_cap; 2696 } else 2697 w->param.inamp_cap = 0; 2698 2699 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2700 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2701 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2702 cap = hdac_command(sc, 2703 HDA_CMD_GET_PARAMETER(cad, nid, 2704 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2705 w->param.supp_stream_formats = (cap != 0) ? cap : 2706 w->devinfo->function.audio.supp_stream_formats; 2707 cap = hdac_command(sc, 2708 HDA_CMD_GET_PARAMETER(cad, nid, 2709 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2710 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2711 w->devinfo->function.audio.supp_pcm_size_rate; 2712 } else { 2713 w->param.supp_stream_formats = 2714 w->devinfo->function.audio.supp_stream_formats; 2715 w->param.supp_pcm_size_rate = 2716 w->devinfo->function.audio.supp_pcm_size_rate; 2717 } 2718 } else { 2719 w->param.supp_stream_formats = 0; 2720 w->param.supp_pcm_size_rate = 0; 2721 } 2722 2723 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2724 hdac_widget_pin_parse(w); 2725 } 2726 2727 static struct hdac_widget * 2728 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2729 { 2730 if (devinfo == NULL || devinfo->widget == NULL || 2731 nid < devinfo->startnode || nid >= devinfo->endnode) 2732 return (NULL); 2733 return (&devinfo->widget[nid - devinfo->startnode]); 2734 } 2735 2736 static __inline int 2737 hda_poll_channel(struct hdac_chan *ch) 2738 { 2739 uint32_t sz, delta; 2740 volatile uint32_t ptr; 2741 2742 if (!(ch->flags & HDAC_CHN_RUNNING)) 2743 return (0); 2744 2745 sz = ch->blksz * ch->blkcnt; 2746 if (ch->dmapos != NULL) 2747 ptr = *(ch->dmapos); 2748 else 2749 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2750 ch->off + HDAC_SDLPIB); 2751 ch->ptr = ptr; 2752 ptr %= sz; 2753 ptr &= ~(ch->blksz - 1); 2754 delta = (sz + ptr - ch->prevptr) % sz; 2755 2756 if (delta < ch->blksz) 2757 return (0); 2758 2759 ch->prevptr = ptr; 2760 2761 return (1); 2762 } 2763 2764 static void 2765 hda_poll_callback(void *arg) 2766 { 2767 struct hdac_softc *sc = arg; 2768 uint32_t trigger; 2769 int i, active = 0; 2770 2771 if (sc == NULL) 2772 return; 2773 2774 hdac_lock(sc); 2775 if (sc->polling == 0) { 2776 hdac_unlock(sc); 2777 return; 2778 } 2779 2780 trigger = 0; 2781 for (i = 0; i < sc->num_chans; i++) { 2782 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2783 continue; 2784 active = 1; 2785 if (hda_poll_channel(&sc->chans[i])) 2786 trigger |= (1 << i); 2787 } 2788 2789 /* XXX */ 2790 if (active) 2791 callout_reset(&sc->poll_hda, sc->poll_ticks, 2792 hda_poll_callback, sc); 2793 2794 hdac_unlock(sc); 2795 2796 for (i = 0; i < sc->num_chans; i++) { 2797 if (trigger & (1 << i)) 2798 chn_intr(sc->chans[i].c); 2799 } 2800 } 2801 2802 static int 2803 hdac_rirb_flush(struct hdac_softc *sc) 2804 { 2805 struct hdac_rirb *rirb_base, *rirb; 2806 struct hdac_codec *codec; 2807 struct hdac_command_list *commands; 2808 nid_t cad; 2809 uint32_t resp; 2810 uint8_t rirbwp; 2811 int ret; 2812 2813 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2814 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2815 #if 0 2816 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2817 BUS_DMASYNC_POSTREAD); 2818 #endif 2819 2820 ret = 0; 2821 2822 while (sc->rirb_rp != rirbwp) { 2823 sc->rirb_rp++; 2824 sc->rirb_rp %= sc->rirb_size; 2825 rirb = &rirb_base[sc->rirb_rp]; 2826 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2827 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2828 sc->codecs[cad] == NULL) 2829 continue; 2830 resp = rirb->response; 2831 codec = sc->codecs[cad]; 2832 commands = codec->commands; 2833 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2834 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2835 ((resp >> 26) & 0xffff); 2836 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2837 } else if (commands != NULL && commands->num_commands > 0 && 2838 codec->responses_received < commands->num_commands) 2839 commands->responses[codec->responses_received++] = 2840 resp; 2841 ret++; 2842 } 2843 2844 return (ret); 2845 } 2846 2847 static int 2848 hdac_unsolq_flush(struct hdac_softc *sc) 2849 { 2850 nid_t cad; 2851 uint32_t tag; 2852 int ret = 0; 2853 2854 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2855 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2856 while (sc->unsolq_rp != sc->unsolq_wp) { 2857 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2858 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2859 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2860 hdac_unsolicited_handler(sc->codecs[cad], tag); 2861 ret++; 2862 } 2863 sc->unsolq_st = HDAC_UNSOLQ_READY; 2864 } 2865 2866 return (ret); 2867 } 2868 2869 static void 2870 hdac_poll_callback(void *arg) 2871 { 2872 struct hdac_softc *sc = arg; 2873 if (sc == NULL) 2874 return; 2875 2876 hdac_lock(sc); 2877 if (sc->polling == 0 || sc->poll_ival == 0) { 2878 hdac_unlock(sc); 2879 return; 2880 } 2881 if (hdac_rirb_flush(sc) != 0) 2882 hdac_unsolq_flush(sc); 2883 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2884 hdac_unlock(sc); 2885 } 2886 2887 static void 2888 hdac_poll_reinit(struct hdac_softc *sc) 2889 { 2890 int i, pollticks, min = 1000000; 2891 struct hdac_chan *ch; 2892 2893 for (i = 0; i < sc->num_chans; i++) { 2894 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2895 continue; 2896 ch = &sc->chans[i]; 2897 pollticks = ((uint64_t)hz * ch->blksz) / 2898 ((uint64_t)sndbuf_getbps(ch->b) * 2899 sndbuf_getspd(ch->b)); 2900 pollticks >>= 1; 2901 if (pollticks > hz) 2902 pollticks = hz; 2903 if (pollticks < 1) { 2904 HDA_BOOTVERBOSE( 2905 device_printf(sc->dev, 2906 "%s: pollticks=%d < 1 !\n", 2907 __func__, pollticks); 2908 ); 2909 pollticks = 1; 2910 } 2911 if (min > pollticks) 2912 min = pollticks; 2913 } 2914 HDA_BOOTVERBOSE( 2915 device_printf(sc->dev, 2916 "%s: pollticks %d -> %d\n", 2917 __func__, sc->poll_ticks, min); 2918 ); 2919 sc->poll_ticks = min; 2920 if (min == 1000000) 2921 callout_stop(&sc->poll_hda); 2922 else 2923 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2924 } 2925 2926 static void 2927 hdac_stream_stop(struct hdac_chan *ch) 2928 { 2929 struct hdac_softc *sc = ch->devinfo->codec->sc; 2930 uint32_t ctl; 2931 2932 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2933 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2934 HDAC_SDCTL_RUN); 2935 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2936 2937 ch->flags &= ~HDAC_CHN_RUNNING; 2938 2939 if (sc->polling != 0) 2940 hdac_poll_reinit(sc); 2941 2942 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2943 ctl &= ~(1 << (ch->off >> 5)); 2944 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2945 } 2946 2947 static void 2948 hdac_stream_start(struct hdac_chan *ch) 2949 { 2950 struct hdac_softc *sc = ch->devinfo->codec->sc; 2951 uint32_t ctl; 2952 2953 ch->flags |= HDAC_CHN_RUNNING; 2954 2955 if (sc->polling != 0) 2956 hdac_poll_reinit(sc); 2957 2958 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2959 ctl |= 1 << (ch->off >> 5); 2960 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2961 2962 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2963 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2964 HDAC_SDCTL_RUN; 2965 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2966 } 2967 2968 static void 2969 hdac_stream_reset(struct hdac_chan *ch) 2970 { 2971 struct hdac_softc *sc = ch->devinfo->codec->sc; 2972 int timeout = 1000; 2973 int to = timeout; 2974 uint32_t ctl; 2975 2976 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2977 ctl |= HDAC_SDCTL_SRST; 2978 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2979 do { 2980 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2981 if (ctl & HDAC_SDCTL_SRST) 2982 break; 2983 DELAY(10); 2984 } while (--to); 2985 if (!(ctl & HDAC_SDCTL_SRST)) { 2986 device_printf(sc->dev, "timeout in reset\n"); 2987 } 2988 ctl &= ~HDAC_SDCTL_SRST; 2989 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2990 to = timeout; 2991 do { 2992 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2993 if (!(ctl & HDAC_SDCTL_SRST)) 2994 break; 2995 DELAY(10); 2996 } while (--to); 2997 if (ctl & HDAC_SDCTL_SRST) 2998 device_printf(sc->dev, "can't reset!\n"); 2999 } 3000 3001 static void 3002 hdac_stream_setid(struct hdac_chan *ch) 3003 { 3004 struct hdac_softc *sc = ch->devinfo->codec->sc; 3005 uint32_t ctl; 3006 3007 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3008 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3009 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3010 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3011 } 3012 3013 static void 3014 hdac_bdl_setup(struct hdac_chan *ch) 3015 { 3016 struct hdac_softc *sc = ch->devinfo->codec->sc; 3017 struct hdac_bdle *bdle; 3018 uint64_t addr; 3019 uint32_t blksz, blkcnt; 3020 int i; 3021 3022 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3023 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3024 3025 blksz = ch->blksz; 3026 blkcnt = ch->blkcnt; 3027 3028 for (i = 0; i < blkcnt; i++, bdle++) { 3029 bdle->addrl = (uint32_t)addr; 3030 bdle->addrh = (uint32_t)(addr >> 32); 3031 bdle->len = blksz; 3032 bdle->ioc = 1; 3033 addr += blksz; 3034 } 3035 3036 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3037 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3038 addr = ch->bdl_dma.dma_paddr; 3039 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3040 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3041 if (ch->dmapos != NULL && 3042 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3043 addr = sc->pos_dma.dma_paddr; 3044 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3045 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3046 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3047 } 3048 } 3049 3050 static int 3051 hdac_bdl_alloc(struct hdac_chan *ch) 3052 { 3053 struct hdac_softc *sc = ch->devinfo->codec->sc; 3054 int rc; 3055 3056 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3057 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3058 if (rc) { 3059 device_printf(sc->dev, "can't alloc bdl\n"); 3060 return (rc); 3061 } 3062 3063 return (0); 3064 } 3065 3066 static void 3067 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3068 int index, int lmute, int rmute, 3069 int left, int right, int dir) 3070 { 3071 uint16_t v = 0; 3072 3073 if (sc == NULL) 3074 return; 3075 3076 if (left != right || lmute != rmute) { 3077 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3078 (lmute << 7) | left; 3079 hdac_command(sc, 3080 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3081 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3082 (rmute << 7) | right; 3083 } else 3084 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3085 (lmute << 7) | left; 3086 3087 hdac_command(sc, 3088 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3089 } 3090 3091 static void 3092 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3093 int left, int right) 3094 { 3095 struct hdac_softc *sc; 3096 nid_t nid, cad; 3097 int lmute, rmute; 3098 3099 sc = ctl->widget->devinfo->codec->sc; 3100 cad = ctl->widget->devinfo->codec->cad; 3101 nid = ctl->widget->nid; 3102 3103 /* Save new values if valid. */ 3104 if (mute != HDA_AMP_MUTE_DEFAULT) 3105 ctl->muted = mute; 3106 if (left != HDA_AMP_VOL_DEFAULT) 3107 ctl->left = left; 3108 if (right != HDA_AMP_VOL_DEFAULT) 3109 ctl->right = right; 3110 /* Prepare effective values */ 3111 if (ctl->forcemute) { 3112 lmute = 1; 3113 rmute = 1; 3114 left = 0; 3115 right = 0; 3116 } else { 3117 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3118 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3119 left = ctl->left; 3120 right = ctl->right; 3121 } 3122 /* Apply effective values */ 3123 if (ctl->dir & HDA_CTL_OUT) 3124 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3125 lmute, rmute, left, right, 0); 3126 if (ctl->dir & HDA_CTL_IN) 3127 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3128 lmute, rmute, left, right, 1); 3129 } 3130 3131 static void 3132 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3133 { 3134 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3135 return; 3136 hdac_command(w->devinfo->codec->sc, 3137 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3138 w->nid, index), w->devinfo->codec->cad); 3139 w->selconn = index; 3140 } 3141 3142 3143 /**************************************************************************** 3144 * uint32_t hdac_command_sendone_internal 3145 * 3146 * Wrapper function that sends only one command to a given codec 3147 ****************************************************************************/ 3148 static uint32_t 3149 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3150 { 3151 struct hdac_command_list cl; 3152 uint32_t response = HDAC_INVALID; 3153 3154 if (!hdac_lockowned(sc)) 3155 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3156 cl.num_commands = 1; 3157 cl.verbs = &verb; 3158 cl.responses = &response; 3159 3160 hdac_command_send_internal(sc, &cl, cad); 3161 3162 return (response); 3163 } 3164 3165 /**************************************************************************** 3166 * hdac_command_send_internal 3167 * 3168 * Send a command list to the codec via the corb. We queue as much verbs as 3169 * we can and msleep on the codec. When the interrupt get the responses 3170 * back from the rirb, it will wake us up so we can queue the remaining verbs 3171 * if any. 3172 ****************************************************************************/ 3173 static void 3174 hdac_command_send_internal(struct hdac_softc *sc, 3175 struct hdac_command_list *commands, nid_t cad) 3176 { 3177 struct hdac_codec *codec; 3178 int corbrp; 3179 uint32_t *corb; 3180 int timeout; 3181 int retry = 10; 3182 struct hdac_rirb *rirb_base; 3183 3184 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3185 commands->num_commands < 1) 3186 return; 3187 3188 codec = sc->codecs[cad]; 3189 codec->commands = commands; 3190 codec->responses_received = 0; 3191 codec->verbs_sent = 0; 3192 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3193 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3194 3195 do { 3196 if (codec->verbs_sent != commands->num_commands) { 3197 /* Queue as many verbs as possible */ 3198 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3199 #if 0 3200 bus_dmamap_sync(sc->corb_dma.dma_tag, 3201 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3202 #endif 3203 while (codec->verbs_sent != commands->num_commands && 3204 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3205 sc->corb_wp++; 3206 sc->corb_wp %= sc->corb_size; 3207 corb[sc->corb_wp] = 3208 commands->verbs[codec->verbs_sent++]; 3209 } 3210 3211 /* Send the verbs to the codecs */ 3212 #if 0 3213 bus_dmamap_sync(sc->corb_dma.dma_tag, 3214 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3215 #endif 3216 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3217 } 3218 3219 timeout = 1000; 3220 while (hdac_rirb_flush(sc) == 0 && --timeout) 3221 DELAY(10); 3222 } while ((codec->verbs_sent != commands->num_commands || 3223 codec->responses_received != commands->num_commands) && --retry); 3224 3225 if (retry == 0) 3226 device_printf(sc->dev, 3227 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3228 __func__, commands->num_commands, codec->verbs_sent, 3229 codec->responses_received); 3230 3231 codec->commands = NULL; 3232 codec->responses_received = 0; 3233 codec->verbs_sent = 0; 3234 3235 hdac_unsolq_flush(sc); 3236 } 3237 3238 3239 /**************************************************************************** 3240 * Device Methods 3241 ****************************************************************************/ 3242 3243 /**************************************************************************** 3244 * int hdac_probe(device_t) 3245 * 3246 * Probe for the presence of an hdac. If none is found, check for a generic 3247 * match using the subclass of the device. 3248 ****************************************************************************/ 3249 static int 3250 hdac_probe(device_t dev) 3251 { 3252 int i, result; 3253 uint32_t model; 3254 uint16_t class, subclass; 3255 char desc[64]; 3256 3257 model = (uint32_t)pci_get_device(dev) << 16; 3258 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3259 class = pci_get_class(dev); 3260 subclass = pci_get_subclass(dev); 3261 3262 bzero(desc, sizeof(desc)); 3263 result = ENXIO; 3264 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3265 if (hdac_devices[i].model == model) { 3266 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3267 result = BUS_PROBE_DEFAULT; 3268 break; 3269 } 3270 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3271 class == PCIC_MULTIMEDIA && 3272 subclass == PCIS_MULTIMEDIA_HDA) { 3273 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3274 result = BUS_PROBE_GENERIC; 3275 break; 3276 } 3277 } 3278 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3279 subclass == PCIS_MULTIMEDIA_HDA) { 3280 strlcpy(desc, "Generic", sizeof(desc)); 3281 result = BUS_PROBE_GENERIC; 3282 } 3283 if (result != ENXIO) { 3284 strlcat(desc, " High Definition Audio Controller", 3285 sizeof(desc)); 3286 device_set_desc_copy(dev, desc); 3287 } 3288 3289 return (result); 3290 } 3291 3292 static void * 3293 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3294 struct pcm_channel *c, int dir) 3295 { 3296 struct hdac_pcm_devinfo *pdevinfo = data; 3297 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3298 struct hdac_softc *sc = devinfo->codec->sc; 3299 struct hdac_chan *ch; 3300 int i, ord = 0, chid; 3301 3302 hdac_lock(sc); 3303 3304 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3305 ch = &sc->chans[chid]; 3306 for (i = 0; i < sc->num_chans && i < chid; i++) { 3307 if (ch->dir == sc->chans[i].dir) 3308 ord++; 3309 } 3310 if (dir == PCMDIR_PLAY) { 3311 ch->off = (sc->num_iss + ord) << 5; 3312 } else { 3313 ch->off = ord << 5; 3314 } 3315 3316 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3317 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3318 ch->pcmrates[0] = 48000; 3319 ch->pcmrates[1] = 0; 3320 } 3321 if (sc->pos_dma.dma_vaddr != NULL) 3322 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3323 (sc->streamcnt * 8)); 3324 else 3325 ch->dmapos = NULL; 3326 ch->sid = ++sc->streamcnt; 3327 ch->dir = dir; 3328 ch->b = b; 3329 ch->c = c; 3330 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3331 ch->blkcnt = pdevinfo->chan_blkcnt; 3332 hdac_unlock(sc); 3333 3334 if (hdac_bdl_alloc(ch) != 0) { 3335 ch->blkcnt = 0; 3336 return (NULL); 3337 } 3338 3339 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3340 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3341 pdevinfo->chan_size) != 0) 3342 return (NULL); 3343 3344 return (ch); 3345 } 3346 3347 static int 3348 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3349 { 3350 struct hdac_chan *ch = data; 3351 int i; 3352 3353 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3354 if (format == ch->caps.fmtlist[i]) { 3355 ch->fmt = format; 3356 return (0); 3357 } 3358 } 3359 3360 return (EINVAL); 3361 } 3362 3363 static int 3364 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3365 { 3366 struct hdac_chan *ch = data; 3367 uint32_t spd = 0, threshold; 3368 int i; 3369 3370 for (i = 0; ch->pcmrates[i] != 0; i++) { 3371 spd = ch->pcmrates[i]; 3372 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3373 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3374 if (speed < threshold) 3375 break; 3376 } 3377 3378 if (spd == 0) /* impossible */ 3379 ch->spd = 48000; 3380 else 3381 ch->spd = spd; 3382 3383 return (ch->spd); 3384 } 3385 3386 static void 3387 hdac_stream_setup(struct hdac_chan *ch) 3388 { 3389 struct hdac_softc *sc = ch->devinfo->codec->sc; 3390 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3391 struct hdac_widget *w; 3392 int i, chn, totalchn, c; 3393 nid_t cad = ch->devinfo->codec->cad; 3394 uint16_t fmt, dfmt; 3395 3396 HDA_BOOTHVERBOSE( 3397 device_printf(ch->pdevinfo->dev, 3398 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3399 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3400 ch->fmt, ch->spd); 3401 ); 3402 fmt = 0; 3403 if (ch->fmt & AFMT_S16_LE) 3404 fmt |= ch->bit16 << 4; 3405 else if (ch->fmt & AFMT_S32_LE) 3406 fmt |= ch->bit32 << 4; 3407 else 3408 fmt |= 1 << 4; 3409 3410 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3411 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3412 fmt |= hda_rate_tab[i].base; 3413 fmt |= hda_rate_tab[i].mul; 3414 fmt |= hda_rate_tab[i].div; 3415 break; 3416 } 3417 } 3418 3419 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3420 fmt |= 1; 3421 totalchn = 2; 3422 } else 3423 totalchn = 1; 3424 3425 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3426 3427 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3428 if (ch->fmt & AFMT_AC3) 3429 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3430 3431 chn = 0; 3432 for (i = 0; ch->io[i] != -1; i++) { 3433 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3434 if (w == NULL) 3435 continue; 3436 3437 if (as->hpredir >= 0 && i == as->pincnt) 3438 chn = 0; 3439 HDA_BOOTHVERBOSE( 3440 device_printf(ch->pdevinfo->dev, 3441 "PCMDIR_%s: Stream setup nid=%d: " 3442 "fmt=0x%04x, dfmt=0x%04x\n", 3443 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3444 ch->io[i], fmt, dfmt); 3445 ); 3446 hdac_command(sc, 3447 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3448 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3449 hdac_command(sc, 3450 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3451 cad); 3452 } 3453 /* If HP redirection is enabled, but failed to use same 3454 DAC make last DAC one to duplicate first one. */ 3455 if (as->hpredir >= 0 && i == as->pincnt) { 3456 c = (ch->sid << 4); 3457 } else if (chn >= totalchn) { 3458 /* This is until OSS will support multichannel. 3459 Should be: c = 0; to disable unused DAC */ 3460 c = (ch->sid << 4); 3461 }else { 3462 c = (ch->sid << 4) | chn; 3463 } 3464 hdac_command(sc, 3465 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3466 chn += 3467 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3468 2 : 1; 3469 } 3470 } 3471 3472 static int 3473 hdac_channel_setfragments(kobj_t obj, void *data, 3474 uint32_t blksz, uint32_t blkcnt) 3475 { 3476 struct hdac_chan *ch = data; 3477 struct hdac_softc *sc = ch->devinfo->codec->sc; 3478 3479 blksz &= HDA_BLK_ALIGN; 3480 3481 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3482 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3483 if (blksz < HDA_BLK_MIN) 3484 blksz = HDA_BLK_MIN; 3485 if (blkcnt > HDA_BDL_MAX) 3486 blkcnt = HDA_BDL_MAX; 3487 if (blkcnt < HDA_BDL_MIN) 3488 blkcnt = HDA_BDL_MIN; 3489 3490 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3491 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3492 blkcnt >>= 1; 3493 else if ((blksz >> 1) >= HDA_BLK_MIN) 3494 blksz >>= 1; 3495 else 3496 break; 3497 } 3498 3499 if ((sndbuf_getblksz(ch->b) != blksz || 3500 sndbuf_getblkcnt(ch->b) != blkcnt) && 3501 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3502 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3503 __func__, blksz, blkcnt); 3504 3505 ch->blksz = sndbuf_getblksz(ch->b); 3506 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3507 3508 return (1); 3509 } 3510 3511 static int 3512 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3513 { 3514 struct hdac_chan *ch = data; 3515 3516 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3517 3518 return (ch->blksz); 3519 } 3520 3521 static void 3522 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3523 { 3524 struct hdac_devinfo *devinfo = ch->devinfo; 3525 struct hdac_widget *w; 3526 nid_t cad = devinfo->codec->cad; 3527 int i; 3528 3529 hdac_stream_stop(ch); 3530 3531 for (i = 0; ch->io[i] != -1; i++) { 3532 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3533 if (w == NULL) 3534 continue; 3535 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3536 hdac_command(sc, 3537 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3538 cad); 3539 } 3540 hdac_command(sc, 3541 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3542 0), cad); 3543 } 3544 } 3545 3546 static void 3547 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3548 { 3549 ch->ptr = 0; 3550 ch->prevptr = 0; 3551 hdac_stream_stop(ch); 3552 hdac_stream_reset(ch); 3553 hdac_bdl_setup(ch); 3554 hdac_stream_setid(ch); 3555 hdac_stream_setup(ch); 3556 hdac_stream_start(ch); 3557 } 3558 3559 static int 3560 hdac_channel_trigger(kobj_t obj, void *data, int go) 3561 { 3562 struct hdac_chan *ch = data; 3563 struct hdac_softc *sc = ch->devinfo->codec->sc; 3564 3565 if (!PCMTRIG_COMMON(go)) 3566 return (0); 3567 3568 hdac_lock(sc); 3569 switch (go) { 3570 case PCMTRIG_START: 3571 hdac_channel_start(sc, ch); 3572 break; 3573 case PCMTRIG_STOP: 3574 case PCMTRIG_ABORT: 3575 hdac_channel_stop(sc, ch); 3576 break; 3577 default: 3578 break; 3579 } 3580 hdac_unlock(sc); 3581 3582 return (0); 3583 } 3584 3585 static int 3586 hdac_channel_getptr(kobj_t obj, void *data) 3587 { 3588 struct hdac_chan *ch = data; 3589 struct hdac_softc *sc = ch->devinfo->codec->sc; 3590 uint32_t ptr; 3591 3592 hdac_lock(sc); 3593 if (sc->polling != 0) 3594 ptr = ch->ptr; 3595 else if (ch->dmapos != NULL) 3596 ptr = *(ch->dmapos); 3597 else 3598 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3599 hdac_unlock(sc); 3600 3601 /* 3602 * Round to available space and force 128 bytes aligment. 3603 */ 3604 ptr %= ch->blksz * ch->blkcnt; 3605 ptr &= HDA_BLK_ALIGN; 3606 3607 return (ptr); 3608 } 3609 3610 static struct pcmchan_caps * 3611 hdac_channel_getcaps(kobj_t obj, void *data) 3612 { 3613 return (&((struct hdac_chan *)data)->caps); 3614 } 3615 3616 static kobj_method_t hdac_channel_methods[] = { 3617 KOBJMETHOD(channel_init, hdac_channel_init), 3618 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3619 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3620 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3621 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3622 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3623 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3624 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3625 { 0, 0 } 3626 }; 3627 CHANNEL_DECLARE(hdac_channel); 3628 3629 static int 3630 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3631 { 3632 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3633 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3634 struct hdac_softc *sc = devinfo->codec->sc; 3635 struct hdac_widget *w, *cw; 3636 struct hdac_audio_ctl *ctl; 3637 uint32_t mask, recmask, id; 3638 int i, j, softpcmvol; 3639 3640 hdac_lock(sc); 3641 3642 /* Make sure that in case of soft volume it won't stay muted. */ 3643 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3644 pdevinfo->left[i] = 100; 3645 pdevinfo->right[i] = 100; 3646 } 3647 3648 mask = 0; 3649 recmask = 0; 3650 id = hdac_codec_id(devinfo->codec); 3651 3652 /* Declate EAPD as ogain control. */ 3653 if (pdevinfo->play >= 0) { 3654 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3655 w = hdac_widget_get(devinfo, i); 3656 if (w == NULL || w->enable == 0) 3657 continue; 3658 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3659 w->param.eapdbtl == HDAC_INVALID || 3660 w->bindas != sc->chans[pdevinfo->play].as) 3661 continue; 3662 mask |= SOUND_MASK_OGAIN; 3663 break; 3664 } 3665 } 3666 3667 /* Declare volume controls assigned to this association. */ 3668 i = 0; 3669 ctl = NULL; 3670 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3671 if (ctl->enable == 0) 3672 continue; 3673 if ((pdevinfo->play >= 0 && 3674 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3675 (pdevinfo->rec >= 0 && 3676 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3677 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3678 mask |= ctl->ossmask; 3679 } 3680 3681 /* Declare record sources available to this association. */ 3682 if (pdevinfo->rec >= 0) { 3683 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3684 for (i = 0; ch->io[i] != -1; i++) { 3685 w = hdac_widget_get(devinfo, ch->io[i]); 3686 if (w == NULL || w->enable == 0) 3687 continue; 3688 for (j = 0; j < w->nconns; j++) { 3689 if (w->connsenable[j] == 0) 3690 continue; 3691 cw = hdac_widget_get(devinfo, w->conns[j]); 3692 if (cw == NULL || cw->enable == 0) 3693 continue; 3694 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3695 cw->bindas != -2) 3696 continue; 3697 recmask |= cw->ossmask; 3698 } 3699 } 3700 } 3701 3702 /* Declare soft PCM volume if needed. */ 3703 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3704 ctl = NULL; 3705 if ((mask & SOUND_MASK_PCM) == 0 || 3706 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3707 softpcmvol = 1; 3708 mask |= SOUND_MASK_PCM; 3709 } else { 3710 softpcmvol = 0; 3711 i = 0; 3712 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3713 if (ctl->enable == 0) 3714 continue; 3715 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3716 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3717 continue; 3718 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3719 continue; 3720 if (ctl->step > 0) 3721 break; 3722 } 3723 } 3724 3725 if (softpcmvol == 1 || ctl == NULL) { 3726 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3727 HDA_BOOTVERBOSE( 3728 device_printf(pdevinfo->dev, 3729 "%s Soft PCM volume\n", 3730 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3731 ); 3732 } 3733 } 3734 3735 /* Declare master volume if needed. */ 3736 if (pdevinfo->play >= 0) { 3737 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3738 SOUND_MASK_PCM) { 3739 mask |= SOUND_MASK_VOLUME; 3740 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3741 SOUND_MASK_PCM); 3742 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3743 SOUND_MIXER_NONE); 3744 HDA_BOOTVERBOSE( 3745 device_printf(pdevinfo->dev, 3746 "Forcing master volume with PCM\n"); 3747 ); 3748 } 3749 } 3750 3751 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3752 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3753 3754 mix_setrecdevs(m, recmask); 3755 mix_setdevs(m, mask); 3756 3757 hdac_unlock(sc); 3758 3759 return (0); 3760 } 3761 3762 static int 3763 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3764 unsigned left, unsigned right) 3765 { 3766 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3767 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3768 struct hdac_softc *sc = devinfo->codec->sc; 3769 struct hdac_widget *w; 3770 struct hdac_audio_ctl *ctl; 3771 uint32_t mute; 3772 int lvol, rvol; 3773 int i, j; 3774 3775 hdac_lock(sc); 3776 /* Save new values. */ 3777 pdevinfo->left[dev] = left; 3778 pdevinfo->right[dev] = right; 3779 3780 /* 'ogain' is the special case implemented with EAPD. */ 3781 if (dev == SOUND_MIXER_OGAIN) { 3782 uint32_t orig; 3783 w = NULL; 3784 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3785 w = hdac_widget_get(devinfo, i); 3786 if (w == NULL || w->enable == 0) 3787 continue; 3788 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3789 w->param.eapdbtl == HDAC_INVALID) 3790 continue; 3791 break; 3792 } 3793 if (i >= devinfo->endnode) { 3794 hdac_unlock(sc); 3795 return (-1); 3796 } 3797 orig = w->param.eapdbtl; 3798 if (left == 0) 3799 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3800 else 3801 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3802 if (orig != w->param.eapdbtl) { 3803 uint32_t val; 3804 3805 val = w->param.eapdbtl; 3806 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3807 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3808 hdac_command(sc, 3809 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3810 w->nid, val), devinfo->codec->cad); 3811 } 3812 hdac_unlock(sc); 3813 return (left | (left << 8)); 3814 } 3815 3816 /* Recalculate all controls related to this OSS device. */ 3817 i = 0; 3818 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3819 if (ctl->enable == 0 || 3820 !(ctl->ossmask & (1 << dev))) 3821 continue; 3822 if (!((pdevinfo->play >= 0 && 3823 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3824 (pdevinfo->rec >= 0 && 3825 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3826 ctl->widget->bindas == -2)) 3827 continue; 3828 3829 lvol = 100; 3830 rvol = 100; 3831 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3832 if (ctl->ossmask & (1 << j)) { 3833 lvol = lvol * pdevinfo->left[j] / 100; 3834 rvol = rvol * pdevinfo->right[j] / 100; 3835 } 3836 } 3837 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3838 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3839 lvol = (lvol * ctl->step + 50) / 100; 3840 rvol = (rvol * ctl->step + 50) / 100; 3841 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3842 } 3843 hdac_unlock(sc); 3844 3845 return (left | (right << 8)); 3846 } 3847 3848 /* 3849 * Commutate specified record source. 3850 */ 3851 static uint32_t 3852 hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3853 { 3854 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3855 struct hdac_widget *w, *cw; 3856 struct hdac_audio_ctl *ctl; 3857 char buf[64]; 3858 int i, muted; 3859 uint32_t res = 0; 3860 3861 if (depth > HDA_PARSE_MAXDEPTH) 3862 return (0); 3863 3864 w = hdac_widget_get(devinfo, nid); 3865 if (w == NULL || w->enable == 0) 3866 return (0); 3867 3868 for (i = 0; i < w->nconns; i++) { 3869 if (w->connsenable[i] == 0) 3870 continue; 3871 cw = hdac_widget_get(devinfo, w->conns[i]); 3872 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3873 continue; 3874 /* Call recursively to trace signal to it's source if needed. */ 3875 if ((src & cw->ossmask) != 0) { 3876 if (cw->ossdev < 0) { 3877 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3878 w->conns[i], depth + 1); 3879 } else { 3880 res |= cw->ossmask; 3881 } 3882 } 3883 /* We have two special cases: mixers and others (selectors). */ 3884 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3885 ctl = hdac_audio_ctl_amp_get(devinfo, 3886 w->nid, HDA_CTL_IN, i, 1); 3887 if (ctl == NULL) 3888 continue; 3889 /* If we have input control on this node mute them 3890 * according to requested sources. */ 3891 muted = (src & cw->ossmask) ? 0 : 1; 3892 if (muted != ctl->forcemute) { 3893 ctl->forcemute = muted; 3894 hdac_audio_ctl_amp_set(ctl, 3895 HDA_AMP_MUTE_DEFAULT, 3896 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3897 } 3898 HDA_BOOTHVERBOSE( 3899 device_printf(pdevinfo->dev, 3900 "Recsel (%s): nid %d source %d %s\n", 3901 hdac_audio_ctl_ossmixer_mask2allname( 3902 src, buf, sizeof(buf)), 3903 nid, i, muted?"mute":"unmute"); 3904 ); 3905 } else { 3906 if (w->nconns == 1) 3907 break; 3908 if ((src & cw->ossmask) == 0) 3909 continue; 3910 /* If we found requested source - select it and exit. */ 3911 hdac_widget_connection_select(w, i); 3912 HDA_BOOTHVERBOSE( 3913 device_printf(pdevinfo->dev, 3914 "Recsel (%s): nid %d source %d select\n", 3915 hdac_audio_ctl_ossmixer_mask2allname( 3916 src, buf, sizeof(buf)), 3917 nid, i); 3918 ); 3919 break; 3920 } 3921 } 3922 return (res); 3923 } 3924 3925 static uint32_t 3926 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3927 { 3928 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3929 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3930 struct hdac_widget *w; 3931 struct hdac_softc *sc = devinfo->codec->sc; 3932 struct hdac_chan *ch; 3933 int i; 3934 uint32_t ret = 0xffffffff; 3935 3936 hdac_lock(sc); 3937 3938 /* Commutate requested recsrc for each ADC. */ 3939 ch = &sc->chans[pdevinfo->rec]; 3940 for (i = 0; ch->io[i] != -1; i++) { 3941 w = hdac_widget_get(devinfo, ch->io[i]); 3942 if (w == NULL || w->enable == 0) 3943 continue; 3944 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3945 } 3946 3947 hdac_unlock(sc); 3948 3949 return ((ret == 0xffffffff)? 0 : ret); 3950 } 3951 3952 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3953 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3954 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3955 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3956 { 0, 0 } 3957 }; 3958 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3959 3960 static void 3961 hdac_unsolq_task(void *context, int pending) 3962 { 3963 struct hdac_softc *sc; 3964 3965 sc = (struct hdac_softc *)context; 3966 3967 hdac_lock(sc); 3968 hdac_unsolq_flush(sc); 3969 hdac_unlock(sc); 3970 } 3971 3972 /**************************************************************************** 3973 * int hdac_attach(device_t) 3974 * 3975 * Attach the device into the kernel. Interrupts usually won't be enabled 3976 * when this function is called. Setup everything that doesn't require 3977 * interrupts and defer probing of codecs until interrupts are enabled. 3978 ****************************************************************************/ 3979 static int 3980 hdac_attach(device_t dev) 3981 { 3982 struct hdac_softc *sc; 3983 int result; 3984 int i, devid = -1; 3985 uint32_t model; 3986 uint16_t class, subclass; 3987 uint16_t vendor; 3988 uint8_t v; 3989 3990 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3991 3992 model = (uint32_t)pci_get_device(dev) << 16; 3993 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3994 class = pci_get_class(dev); 3995 subclass = pci_get_subclass(dev); 3996 3997 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3998 if (hdac_devices[i].model == model) { 3999 devid = i; 4000 break; 4001 } 4002 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4003 class == PCIC_MULTIMEDIA && 4004 subclass == PCIS_MULTIMEDIA_HDA) { 4005 devid = i; 4006 break; 4007 } 4008 } 4009 4010 sc = device_get_softc(dev); 4011 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4012 sc->dev = dev; 4013 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4014 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4015 vendor = pci_get_vendor(dev); 4016 4017 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4018 /* Screw nx6325 - subdevice/subvendor swapped */ 4019 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4020 } 4021 4022 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4023 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4024 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4025 4026 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4027 4028 sc->poll_ticks = 1000000; 4029 sc->poll_ival = HDAC_POLL_INTERVAL; 4030 if (resource_int_value(device_get_name(dev), 4031 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4032 sc->polling = 1; 4033 else 4034 sc->polling = 0; 4035 4036 result = bus_dma_tag_create(NULL, /* parent */ 4037 HDAC_DMA_ALIGNMENT, /* alignment */ 4038 0, /* boundary */ 4039 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4040 BUS_SPACE_MAXADDR, /* highaddr */ 4041 NULL, /* filtfunc */ 4042 NULL, /* fistfuncarg */ 4043 HDA_BUFSZ_MAX, /* maxsize */ 4044 1, /* nsegments */ 4045 HDA_BUFSZ_MAX, /* maxsegsz */ 4046 0, /* flags */ 4047 NULL, /* lockfunc */ 4048 NULL, /* lockfuncarg */ 4049 &sc->chan_dmat); /* dmat */ 4050 if (result != 0) { 4051 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4052 __func__, result); 4053 snd_mtxfree(sc->lock); 4054 free(sc, M_DEVBUF); 4055 return (ENXIO); 4056 } 4057 4058 4059 sc->hdabus = NULL; 4060 for (i = 0; i < HDAC_CODEC_MAX; i++) 4061 sc->codecs[i] = NULL; 4062 4063 pci_enable_busmaster(dev); 4064 4065 if (vendor == INTEL_VENDORID) { 4066 /* TCSEL -> TC0 */ 4067 v = pci_read_config(dev, 0x44, 1); 4068 pci_write_config(dev, 0x44, v & 0xf8, 1); 4069 HDA_BOOTHVERBOSE( 4070 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4071 pci_read_config(dev, 0x44, 1)); 4072 ); 4073 } 4074 4075 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4076 sc->flags &= ~HDAC_F_MSI; 4077 else 4078 sc->flags |= HDAC_F_MSI; 4079 if (resource_int_value(device_get_name(dev), 4080 device_get_unit(dev), "msi", &i) == 0) { 4081 if (i == 0) 4082 sc->flags &= ~HDAC_F_MSI; 4083 else 4084 sc->flags |= HDAC_F_MSI; 4085 } 4086 4087 #if defined(__i386__) || defined(__amd64__) 4088 sc->flags |= HDAC_F_DMA_NOCACHE; 4089 4090 if (resource_int_value(device_get_name(dev), 4091 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4092 #else 4093 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4094 #endif 4095 /* 4096 * Try to enable PCIe snoop to avoid messing around with 4097 * uncacheable DMA attribute. Since PCIe snoop register 4098 * config is pretty much vendor specific, there are no 4099 * general solutions on how to enable it, forcing us (even 4100 * Microsoft) to enable uncacheable or write combined DMA 4101 * by default. 4102 * 4103 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4104 */ 4105 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4106 if (hdac_pcie_snoop[i].vendor != vendor) 4107 continue; 4108 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4109 if (hdac_pcie_snoop[i].reg == 0x00) 4110 break; 4111 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4112 if ((v & hdac_pcie_snoop[i].enable) == 4113 hdac_pcie_snoop[i].enable) 4114 break; 4115 v &= hdac_pcie_snoop[i].mask; 4116 v |= hdac_pcie_snoop[i].enable; 4117 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4118 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4119 if ((v & hdac_pcie_snoop[i].enable) != 4120 hdac_pcie_snoop[i].enable) { 4121 HDA_BOOTVERBOSE( 4122 device_printf(dev, 4123 "WARNING: Failed to enable PCIe " 4124 "snoop!\n"); 4125 ); 4126 #if defined(__i386__) || defined(__amd64__) 4127 sc->flags |= HDAC_F_DMA_NOCACHE; 4128 #endif 4129 } 4130 break; 4131 } 4132 #if defined(__i386__) || defined(__amd64__) 4133 } 4134 #endif 4135 4136 HDA_BOOTHVERBOSE( 4137 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4138 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4139 "Uncacheable" : "PCIe snoop", vendor); 4140 ); 4141 4142 /* Allocate resources */ 4143 result = hdac_mem_alloc(sc); 4144 if (result != 0) 4145 goto hdac_attach_fail; 4146 result = hdac_irq_alloc(sc); 4147 if (result != 0) 4148 goto hdac_attach_fail; 4149 4150 /* Get Capabilities */ 4151 result = hdac_get_capabilities(sc); 4152 if (result != 0) 4153 goto hdac_attach_fail; 4154 4155 /* Allocate CORB and RIRB dma memory */ 4156 result = hdac_dma_alloc(sc, &sc->corb_dma, 4157 sc->corb_size * sizeof(uint32_t)); 4158 if (result != 0) 4159 goto hdac_attach_fail; 4160 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4161 sc->rirb_size * sizeof(struct hdac_rirb)); 4162 if (result != 0) 4163 goto hdac_attach_fail; 4164 4165 /* Quiesce everything */ 4166 HDA_BOOTHVERBOSE( 4167 device_printf(dev, "Reset controller...\n"); 4168 ); 4169 hdac_reset(sc, 1); 4170 4171 /* Initialize the CORB and RIRB */ 4172 hdac_corb_init(sc); 4173 hdac_rirb_init(sc); 4174 4175 /* Defer remaining of initialization until interrupts are enabled */ 4176 sc->intrhook.ich_func = hdac_attach2; 4177 sc->intrhook.ich_arg = (void *)sc; 4178 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4179 sc->intrhook.ich_func = NULL; 4180 hdac_attach2((void *)sc); 4181 } 4182 4183 return (0); 4184 4185 hdac_attach_fail: 4186 hdac_irq_free(sc); 4187 hdac_dma_free(sc, &sc->rirb_dma); 4188 hdac_dma_free(sc, &sc->corb_dma); 4189 hdac_mem_free(sc); 4190 snd_mtxfree(sc->lock); 4191 free(sc, M_DEVBUF); 4192 4193 return (ENXIO); 4194 } 4195 4196 static void 4197 hdac_audio_parse(struct hdac_devinfo *devinfo) 4198 { 4199 struct hdac_codec *codec = devinfo->codec; 4200 struct hdac_softc *sc = codec->sc; 4201 struct hdac_widget *w; 4202 uint32_t res; 4203 int i; 4204 nid_t cad, nid; 4205 4206 cad = devinfo->codec->cad; 4207 nid = devinfo->nid; 4208 4209 res = hdac_command(sc, 4210 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4211 devinfo->function.audio.gpio = res; 4212 4213 HDA_BOOTVERBOSE( 4214 device_printf(sc->dev, "GPIO: 0x%08x " 4215 "NumGPIO=%d NumGPO=%d " 4216 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4217 devinfo->function.audio.gpio, 4218 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4219 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4220 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4221 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4222 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4223 ); 4224 4225 res = hdac_command(sc, 4226 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4227 cad); 4228 devinfo->function.audio.supp_stream_formats = res; 4229 4230 res = hdac_command(sc, 4231 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4232 cad); 4233 devinfo->function.audio.supp_pcm_size_rate = res; 4234 4235 res = hdac_command(sc, 4236 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4237 cad); 4238 devinfo->function.audio.outamp_cap = res; 4239 4240 res = hdac_command(sc, 4241 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4242 cad); 4243 devinfo->function.audio.inamp_cap = res; 4244 4245 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4246 w = hdac_widget_get(devinfo, i); 4247 if (w == NULL) 4248 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4249 else { 4250 w->devinfo = devinfo; 4251 w->nid = i; 4252 w->enable = 1; 4253 w->selconn = -1; 4254 w->pflags = 0; 4255 w->ossdev = -1; 4256 w->bindas = -1; 4257 w->param.eapdbtl = HDAC_INVALID; 4258 hdac_widget_parse(w); 4259 } 4260 } 4261 } 4262 4263 static void 4264 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4265 { 4266 struct hdac_softc *sc = devinfo->codec->sc; 4267 struct hdac_audio_ctl *ctls; 4268 struct hdac_widget *w, *cw; 4269 int i, j, cnt, max, ocap, icap; 4270 int mute, offset, step, size; 4271 4272 /* XXX This is redundant */ 4273 max = 0; 4274 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4275 w = hdac_widget_get(devinfo, i); 4276 if (w == NULL || w->enable == 0) 4277 continue; 4278 if (w->param.outamp_cap != 0) 4279 max++; 4280 if (w->param.inamp_cap != 0) { 4281 switch (w->type) { 4282 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4283 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4284 for (j = 0; j < w->nconns; j++) { 4285 cw = hdac_widget_get(devinfo, 4286 w->conns[j]); 4287 if (cw == NULL || cw->enable == 0) 4288 continue; 4289 max++; 4290 } 4291 break; 4292 default: 4293 max++; 4294 break; 4295 } 4296 } 4297 } 4298 4299 devinfo->function.audio.ctlcnt = max; 4300 4301 if (max < 1) 4302 return; 4303 4304 ctls = (struct hdac_audio_ctl *)malloc( 4305 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4306 4307 if (ctls == NULL) { 4308 /* Blekh! */ 4309 device_printf(sc->dev, "unable to allocate ctls!\n"); 4310 devinfo->function.audio.ctlcnt = 0; 4311 return; 4312 } 4313 4314 cnt = 0; 4315 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4316 if (cnt >= max) { 4317 device_printf(sc->dev, "%s: Ctl overflow!\n", 4318 __func__); 4319 break; 4320 } 4321 w = hdac_widget_get(devinfo, i); 4322 if (w == NULL || w->enable == 0) 4323 continue; 4324 ocap = w->param.outamp_cap; 4325 icap = w->param.inamp_cap; 4326 if (ocap != 0) { 4327 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4328 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4329 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4330 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4331 /*if (offset > step) { 4332 HDA_BOOTVERBOSE( 4333 device_printf(sc->dev, 4334 "BUGGY outamp: nid=%d " 4335 "[offset=%d > step=%d]\n", 4336 w->nid, offset, step); 4337 ); 4338 offset = step; 4339 }*/ 4340 ctls[cnt].enable = 1; 4341 ctls[cnt].widget = w; 4342 ctls[cnt].mute = mute; 4343 ctls[cnt].step = step; 4344 ctls[cnt].size = size; 4345 ctls[cnt].offset = offset; 4346 ctls[cnt].left = offset; 4347 ctls[cnt].right = offset; 4348 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4349 w->waspin) 4350 ctls[cnt].ndir = HDA_CTL_IN; 4351 else 4352 ctls[cnt].ndir = HDA_CTL_OUT; 4353 ctls[cnt++].dir = HDA_CTL_OUT; 4354 } 4355 4356 if (icap != 0) { 4357 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4358 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4359 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4360 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4361 /*if (offset > step) { 4362 HDA_BOOTVERBOSE( 4363 device_printf(sc->dev, 4364 "BUGGY inamp: nid=%d " 4365 "[offset=%d > step=%d]\n", 4366 w->nid, offset, step); 4367 ); 4368 offset = step; 4369 }*/ 4370 switch (w->type) { 4371 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4372 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4373 for (j = 0; j < w->nconns; j++) { 4374 if (cnt >= max) { 4375 device_printf(sc->dev, 4376 "%s: Ctl overflow!\n", 4377 __func__); 4378 break; 4379 } 4380 cw = hdac_widget_get(devinfo, 4381 w->conns[j]); 4382 if (cw == NULL || cw->enable == 0) 4383 continue; 4384 ctls[cnt].enable = 1; 4385 ctls[cnt].widget = w; 4386 ctls[cnt].childwidget = cw; 4387 ctls[cnt].index = j; 4388 ctls[cnt].mute = mute; 4389 ctls[cnt].step = step; 4390 ctls[cnt].size = size; 4391 ctls[cnt].offset = offset; 4392 ctls[cnt].left = offset; 4393 ctls[cnt].right = offset; 4394 ctls[cnt].ndir = HDA_CTL_IN; 4395 ctls[cnt++].dir = HDA_CTL_IN; 4396 } 4397 break; 4398 default: 4399 if (cnt >= max) { 4400 device_printf(sc->dev, 4401 "%s: Ctl overflow!\n", 4402 __func__); 4403 break; 4404 } 4405 ctls[cnt].enable = 1; 4406 ctls[cnt].widget = w; 4407 ctls[cnt].mute = mute; 4408 ctls[cnt].step = step; 4409 ctls[cnt].size = size; 4410 ctls[cnt].offset = offset; 4411 ctls[cnt].left = offset; 4412 ctls[cnt].right = offset; 4413 if (w->type == 4414 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4415 ctls[cnt].ndir = HDA_CTL_OUT; 4416 else 4417 ctls[cnt].ndir = HDA_CTL_IN; 4418 ctls[cnt++].dir = HDA_CTL_IN; 4419 break; 4420 } 4421 } 4422 } 4423 4424 devinfo->function.audio.ctl = ctls; 4425 } 4426 4427 static void 4428 hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4429 { 4430 struct hdac_softc *sc = devinfo->codec->sc; 4431 struct hdac_audio_as *as; 4432 struct hdac_widget *w; 4433 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4434 4435 /* Count present associations */ 4436 max = 0; 4437 for (j = 1; j < 16; j++) { 4438 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4439 w = hdac_widget_get(devinfo, i); 4440 if (w == NULL || w->enable == 0) 4441 continue; 4442 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4443 continue; 4444 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4445 != j) 4446 continue; 4447 max++; 4448 if (j != 15) /* There could be many 1-pin assocs #15 */ 4449 break; 4450 } 4451 } 4452 4453 devinfo->function.audio.ascnt = max; 4454 4455 if (max < 1) 4456 return; 4457 4458 as = (struct hdac_audio_as *)malloc( 4459 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4460 4461 if (as == NULL) { 4462 /* Blekh! */ 4463 device_printf(sc->dev, "unable to allocate assocs!\n"); 4464 devinfo->function.audio.ascnt = 0; 4465 return; 4466 } 4467 4468 for (i = 0; i < max; i++) { 4469 as[i].hpredir = -1; 4470 as[i].chan = -1; 4471 as[i].digital = 1; 4472 } 4473 4474 /* Scan associations skipping as=0. */ 4475 cnt = 0; 4476 for (j = 1; j < 16; j++) { 4477 first = 16; 4478 hpredir = 0; 4479 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4480 w = hdac_widget_get(devinfo, i); 4481 if (w == NULL || w->enable == 0) 4482 continue; 4483 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4484 continue; 4485 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4486 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4487 if (assoc != j) { 4488 continue; 4489 } 4490 KASSERT(cnt < max, 4491 ("%s: Associations owerflow (%d of %d)", 4492 __func__, cnt, max)); 4493 type = w->wclass.pin.config & 4494 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4495 /* Get pin direction. */ 4496 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4497 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4498 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4499 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4500 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4501 dir = HDA_CTL_OUT; 4502 else 4503 dir = HDA_CTL_IN; 4504 /* If this is a first pin - create new association. */ 4505 if (as[cnt].pincnt == 0) { 4506 as[cnt].enable = 1; 4507 as[cnt].index = j; 4508 as[cnt].dir = dir; 4509 } 4510 if (seq < first) 4511 first = seq; 4512 /* Check association correctness. */ 4513 if (as[cnt].pins[seq] != 0) { 4514 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4515 "in association %d! Disabling association.\n", 4516 __func__, seq, w->nid, j); 4517 as[cnt].enable = 0; 4518 } 4519 if (dir != as[cnt].dir) { 4520 device_printf(sc->dev, "%s: Pin %d has wrong " 4521 "direction for association %d! Disabling " 4522 "association.\n", 4523 __func__, w->nid, j); 4524 as[cnt].enable = 0; 4525 } 4526 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4527 as[cnt].digital = 0; 4528 /* Headphones with seq=15 may mean redirection. */ 4529 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4530 seq == 15) 4531 hpredir = 1; 4532 as[cnt].pins[seq] = w->nid; 4533 as[cnt].pincnt++; 4534 /* Association 15 is a multiple unassociated pins. */ 4535 if (j == 15) 4536 cnt++; 4537 } 4538 if (j != 15 && as[cnt].pincnt > 0) { 4539 if (hpredir && as[cnt].pincnt > 1) 4540 as[cnt].hpredir = first; 4541 cnt++; 4542 } 4543 } 4544 HDA_BOOTVERBOSE( 4545 device_printf(sc->dev, 4546 "%d associations found:\n", max); 4547 for (i = 0; i < max; i++) { 4548 device_printf(sc->dev, 4549 "Association %d (%d) %s%s:\n", 4550 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4551 as[i].enable?"":" (disabled)"); 4552 for (j = 0; j < 16; j++) { 4553 if (as[i].pins[j] == 0) 4554 continue; 4555 device_printf(sc->dev, 4556 " Pin nid=%d seq=%d\n", 4557 as[i].pins[j], j); 4558 } 4559 } 4560 ); 4561 4562 devinfo->function.audio.as = as; 4563 } 4564 4565 static const struct { 4566 uint32_t model; 4567 uint32_t id; 4568 uint32_t set, unset; 4569 } hdac_quirks[] = { 4570 /* 4571 * XXX Force stereo quirk. Monoural recording / playback 4572 * on few codecs (especially ALC880) seems broken or 4573 * perhaps unsupported. 4574 */ 4575 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4576 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4577 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4578 HDA_QUIRK_GPIO0, 0 }, 4579 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4580 HDA_QUIRK_GPIO0, 0 }, 4581 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4582 HDA_QUIRK_GPIO0, 0 }, 4583 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4584 HDA_QUIRK_GPIO0, 0 }, 4585 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4586 HDA_QUIRK_GPIO0, 0 }, 4587 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4588 HDA_QUIRK_GPIO0, 0 }, 4589 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4590 HDA_QUIRK_EAPDINV, 0 }, 4591 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4592 HDA_QUIRK_EAPDINV, 0 }, 4593 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4594 HDA_QUIRK_OVREF, 0 }, 4595 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4596 HDA_QUIRK_OVREF, 0 }, 4597 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4598 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4599 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4600 HDA_QUIRK_GPIO1, 0 }, 4601 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4602 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4603 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4604 HDA_QUIRK_EAPDINV, 0 }, 4605 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4606 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4607 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4608 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4609 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4610 HDA_QUIRK_GPIO0, 0 }, 4611 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4612 HDA_QUIRK_GPIO2, 0 }, 4613 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4614 HDA_QUIRK_GPIO0, 0 }, 4615 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4616 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4617 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4618 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4619 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4620 0, HDA_QUIRK_FORCESTEREO } 4621 }; 4622 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4623 4624 static void 4625 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4626 { 4627 struct hdac_widget *w; 4628 uint32_t id, subvendor; 4629 int i; 4630 4631 id = hdac_codec_id(devinfo->codec); 4632 subvendor = devinfo->codec->sc->pci_subvendor; 4633 4634 /* 4635 * Quirks 4636 */ 4637 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4638 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4639 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4640 continue; 4641 if (hdac_quirks[i].set != 0) 4642 devinfo->function.audio.quirks |= 4643 hdac_quirks[i].set; 4644 if (hdac_quirks[i].unset != 0) 4645 devinfo->function.audio.quirks &= 4646 ~(hdac_quirks[i].unset); 4647 } 4648 4649 switch (id) { 4650 case HDA_CODEC_ALC883: 4651 /* 4652 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4653 * Clear vref cap for jack connectivity. 4654 */ 4655 w = hdac_widget_get(devinfo, 24); 4656 if (w != NULL && w->enable != 0 && w->type == 4657 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4658 (w->wclass.pin.config & 4659 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4660 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4661 w->wclass.pin.cap &= ~( 4662 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4663 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4664 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4665 w = hdac_widget_get(devinfo, 25); 4666 if (w != NULL && w->enable != 0 && w->type == 4667 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4668 (w->wclass.pin.config & 4669 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4670 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4671 w->wclass.pin.cap &= ~( 4672 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4673 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4674 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4675 /* 4676 * nid: 26 = Line-in, leave it alone. 4677 */ 4678 break; 4679 case HDA_CODEC_AD1983: 4680 /* 4681 * This codec has several possible usages, but none 4682 * fit the parser best. Help parser to choose better. 4683 */ 4684 /* Disable direct unmixed playback to get pcm volume. */ 4685 w = hdac_widget_get(devinfo, 5); 4686 if (w != NULL) 4687 w->connsenable[0] = 0; 4688 w = hdac_widget_get(devinfo, 6); 4689 if (w != NULL) 4690 w->connsenable[0] = 0; 4691 w = hdac_widget_get(devinfo, 11); 4692 if (w != NULL) 4693 w->connsenable[0] = 0; 4694 /* Disable mic and line selectors. */ 4695 w = hdac_widget_get(devinfo, 12); 4696 if (w != NULL) 4697 w->connsenable[1] = 0; 4698 w = hdac_widget_get(devinfo, 13); 4699 if (w != NULL) 4700 w->connsenable[1] = 0; 4701 /* Disable recording from mono playback mix. */ 4702 w = hdac_widget_get(devinfo, 20); 4703 if (w != NULL) 4704 w->connsenable[3] = 0; 4705 break; 4706 case HDA_CODEC_AD1986A: 4707 /* 4708 * This codec has overcomplicated input mixing. 4709 * Make some cleaning there. 4710 */ 4711 /* Disable input mono mixer. Not needed and not supported. */ 4712 w = hdac_widget_get(devinfo, 43); 4713 if (w != NULL) 4714 w->enable = 0; 4715 /* Disable any with any input mixing mesh. Use separately. */ 4716 w = hdac_widget_get(devinfo, 39); 4717 if (w != NULL) 4718 w->enable = 0; 4719 w = hdac_widget_get(devinfo, 40); 4720 if (w != NULL) 4721 w->enable = 0; 4722 w = hdac_widget_get(devinfo, 41); 4723 if (w != NULL) 4724 w->enable = 0; 4725 w = hdac_widget_get(devinfo, 42); 4726 if (w != NULL) 4727 w->enable = 0; 4728 /* Disable duplicate mixer node connector. */ 4729 w = hdac_widget_get(devinfo, 15); 4730 if (w != NULL) 4731 w->connsenable[3] = 0; 4732 4733 if (subvendor == ASUS_A8X_SUBVENDOR) { 4734 /* 4735 * This is just plain ridiculous.. There 4736 * are several A8 series that share the same 4737 * pci id but works differently (EAPD). 4738 */ 4739 w = hdac_widget_get(devinfo, 26); 4740 if (w != NULL && w->type == 4741 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4742 (w->wclass.pin.config & 4743 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4744 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4745 devinfo->function.audio.quirks &= 4746 ~HDA_QUIRK_EAPDINV; 4747 } 4748 break; 4749 case HDA_CODEC_AD1981HD: 4750 /* 4751 * This codec has very unusual design with several 4752 * points inappropriate for the present parser. 4753 */ 4754 /* Disable recording from mono playback mix. */ 4755 w = hdac_widget_get(devinfo, 21); 4756 if (w != NULL) 4757 w->connsenable[3] = 0; 4758 /* Disable rear to front mic mixer, use separately. */ 4759 w = hdac_widget_get(devinfo, 31); 4760 if (w != NULL) 4761 w->enable = 0; 4762 /* Disable playback mixer, use direct bypass. */ 4763 w = hdac_widget_get(devinfo, 14); 4764 if (w != NULL) 4765 w->enable = 0; 4766 break; 4767 } 4768 } 4769 4770 /* 4771 * Trace path from DAC to pin. 4772 */ 4773 static nid_t 4774 hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4775 int dupseq, int min, int only, int depth) 4776 { 4777 struct hdac_widget *w; 4778 int i, im = -1; 4779 nid_t m = 0, ret; 4780 4781 if (depth > HDA_PARSE_MAXDEPTH) 4782 return (0); 4783 w = hdac_widget_get(devinfo, nid); 4784 if (w == NULL || w->enable == 0) 4785 return (0); 4786 HDA_BOOTHVERBOSE( 4787 if (!only) { 4788 device_printf(devinfo->codec->sc->dev, 4789 " %*stracing via nid %d\n", 4790 depth + 1, "", w->nid); 4791 } 4792 ); 4793 /* Use only unused widgets */ 4794 if (w->bindas >= 0 && w->bindas != as) { 4795 HDA_BOOTHVERBOSE( 4796 if (!only) { 4797 device_printf(devinfo->codec->sc->dev, 4798 " %*snid %d busy by association %d\n", 4799 depth + 1, "", w->nid, w->bindas); 4800 } 4801 ); 4802 return (0); 4803 } 4804 if (dupseq < 0) { 4805 if (w->bindseqmask != 0) { 4806 HDA_BOOTHVERBOSE( 4807 if (!only) { 4808 device_printf(devinfo->codec->sc->dev, 4809 " %*snid %d busy by seqmask %x\n", 4810 depth + 1, "", w->nid, w->bindseqmask); 4811 } 4812 ); 4813 return (0); 4814 } 4815 } else { 4816 /* If this is headphones - allow duplicate first pin. */ 4817 if (w->bindseqmask != 0 && 4818 (w->bindseqmask & (1 << dupseq)) == 0) { 4819 HDA_BOOTHVERBOSE( 4820 device_printf(devinfo->codec->sc->dev, 4821 " %*snid %d busy by seqmask %x\n", 4822 depth + 1, "", w->nid, w->bindseqmask); 4823 ); 4824 return (0); 4825 } 4826 } 4827 4828 switch (w->type) { 4829 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4830 /* Do not traverse input. AD1988 has digital monitor 4831 for which we are not ready. */ 4832 break; 4833 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4834 /* If we are tracing HP take only dac of first pin. */ 4835 if ((only == 0 || only == w->nid) && 4836 (w->nid >= min) && (dupseq < 0 || w->nid == 4837 devinfo->function.audio.as[as].dacs[dupseq])) 4838 m = w->nid; 4839 break; 4840 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4841 if (depth > 0) 4842 break; 4843 /* Fall */ 4844 default: 4845 /* Find reachable DACs with smallest nid respecting constraints. */ 4846 for (i = 0; i < w->nconns; i++) { 4847 if (w->connsenable[i] == 0) 4848 continue; 4849 if (w->selconn != -1 && w->selconn != i) 4850 continue; 4851 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4852 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4853 if (m == 0 || ret < m) { 4854 m = ret; 4855 im = i; 4856 } 4857 if (only || dupseq >= 0) 4858 break; 4859 } 4860 } 4861 if (m && only && ((w->nconns > 1 && 4862 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4863 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4864 w->selconn = im; 4865 break; 4866 } 4867 if (m && only) { 4868 w->bindas = as; 4869 w->bindseqmask |= (1 << seq); 4870 } 4871 HDA_BOOTHVERBOSE( 4872 if (!only) { 4873 device_printf(devinfo->codec->sc->dev, 4874 " %*snid %d returned %d\n", 4875 depth + 1, "", w->nid, m); 4876 } 4877 ); 4878 return (m); 4879 } 4880 4881 /* 4882 * Trace path from widget to ADC. 4883 */ 4884 static nid_t 4885 hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4886 int only, int depth) 4887 { 4888 struct hdac_widget *w, *wc; 4889 int i, j; 4890 nid_t res = 0; 4891 4892 if (depth > HDA_PARSE_MAXDEPTH) 4893 return (0); 4894 w = hdac_widget_get(devinfo, nid); 4895 if (w == NULL || w->enable == 0) 4896 return (0); 4897 HDA_BOOTHVERBOSE( 4898 device_printf(devinfo->codec->sc->dev, 4899 " %*stracing via nid %d\n", 4900 depth + 1, "", w->nid); 4901 ); 4902 /* Use only unused widgets */ 4903 if (w->bindas >= 0 && w->bindas != as) { 4904 HDA_BOOTHVERBOSE( 4905 device_printf(devinfo->codec->sc->dev, 4906 " %*snid %d busy by association %d\n", 4907 depth + 1, "", w->nid, w->bindas); 4908 ); 4909 return (0); 4910 } 4911 4912 switch (w->type) { 4913 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4914 /* If we are tracing HP take only dac of first pin. */ 4915 if (only == w->nid) 4916 res = 1; 4917 break; 4918 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4919 if (depth > 0) 4920 break; 4921 /* Fall */ 4922 default: 4923 /* Try to find reachable ADCs with specified nid. */ 4924 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4925 wc = hdac_widget_get(devinfo, j); 4926 if (wc == NULL || wc->enable == 0) 4927 continue; 4928 for (i = 0; i < wc->nconns; i++) { 4929 if (wc->connsenable[i] == 0) 4930 continue; 4931 if (wc->conns[i] != nid) 4932 continue; 4933 if (hdac_audio_trace_adc(devinfo, as, seq, 4934 j, only, depth + 1) != 0) { 4935 res = 1; 4936 if (((wc->nconns > 1 && 4937 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4938 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4939 wc->selconn == -1) 4940 wc->selconn = i; 4941 } 4942 } 4943 } 4944 break; 4945 } 4946 if (res) { 4947 w->bindas = as; 4948 w->bindseqmask |= (1 << seq); 4949 } 4950 HDA_BOOTHVERBOSE( 4951 device_printf(devinfo->codec->sc->dev, 4952 " %*snid %d returned %d\n", 4953 depth + 1, "", w->nid, res); 4954 ); 4955 return (res); 4956 } 4957 4958 /* 4959 * Erase trace path of the specified association. 4960 */ 4961 static void 4962 hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4963 { 4964 struct hdac_widget *w; 4965 int i; 4966 4967 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4968 w = hdac_widget_get(devinfo, i); 4969 if (w == NULL || w->enable == 0) 4970 continue; 4971 if (w->bindas == as) { 4972 if (seq >= 0) { 4973 w->bindseqmask &= ~(1 << seq); 4974 if (w->bindseqmask == 0) { 4975 w->bindas = -1; 4976 w->selconn = -1; 4977 } 4978 } else { 4979 w->bindas = -1; 4980 w->bindseqmask = 0; 4981 w->selconn = -1; 4982 } 4983 } 4984 } 4985 } 4986 4987 /* 4988 * Trace association path from DAC to output 4989 */ 4990 static int 4991 hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4992 { 4993 struct hdac_audio_as *ases = devinfo->function.audio.as; 4994 int i, hpredir; 4995 nid_t min, res; 4996 4997 /* Find next pin */ 4998 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4999 ; 5000 /* Check if there is no any left. If so - we succeeded. */ 5001 if (i == 16) 5002 return (1); 5003 5004 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5005 min = 0; 5006 res = 0; 5007 do { 5008 HDA_BOOTHVERBOSE( 5009 device_printf(devinfo->codec->sc->dev, 5010 " Tracing pin %d with min nid %d", 5011 ases[as].pins[i], min); 5012 if (hpredir >= 0) 5013 printf(" and hpredir %d", hpredir); 5014 printf("\n"); 5015 ); 5016 /* Trace this pin taking min nid into account. */ 5017 res = hdac_audio_trace_dac(devinfo, as, i, 5018 ases[as].pins[i], hpredir, min, 0, 0); 5019 if (res == 0) { 5020 /* If we failed - return to previous and redo it. */ 5021 HDA_BOOTVERBOSE( 5022 device_printf(devinfo->codec->sc->dev, 5023 " Unable to trace pin %d seq %d with min " 5024 "nid %d", 5025 ases[as].pins[i], i, min); 5026 if (hpredir >= 0) 5027 printf(" and hpredir %d", hpredir); 5028 printf("\n"); 5029 ); 5030 return (0); 5031 } 5032 HDA_BOOTVERBOSE( 5033 device_printf(devinfo->codec->sc->dev, 5034 " Pin %d traced to DAC %d", 5035 ases[as].pins[i], res); 5036 if (hpredir >= 0) 5037 printf(" and hpredir %d", hpredir); 5038 if (ases[as].fakeredir) 5039 printf(" with fake redirection"); 5040 printf("\n"); 5041 ); 5042 /* Trace again to mark the path */ 5043 hdac_audio_trace_dac(devinfo, as, i, 5044 ases[as].pins[i], hpredir, min, res, 0); 5045 ases[as].dacs[i] = res; 5046 /* We succeeded, so call next. */ 5047 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5048 return (1); 5049 /* If next failed, we should retry with next min */ 5050 hdac_audio_undo_trace(devinfo, as, i); 5051 ases[as].dacs[i] = 0; 5052 min = res + 1; 5053 } while (1); 5054 } 5055 5056 /* 5057 * Trace association path from input to ADC 5058 */ 5059 static int 5060 hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5061 { 5062 struct hdac_audio_as *ases = devinfo->function.audio.as; 5063 struct hdac_widget *w; 5064 int i, j, k; 5065 5066 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5067 w = hdac_widget_get(devinfo, j); 5068 if (w == NULL || w->enable == 0) 5069 continue; 5070 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5071 continue; 5072 if (w->bindas >= 0 && w->bindas != as) 5073 continue; 5074 5075 /* Find next pin */ 5076 for (i = 0; i < 16; i++) { 5077 if (ases[as].pins[i] == 0) 5078 continue; 5079 5080 HDA_BOOTHVERBOSE( 5081 device_printf(devinfo->codec->sc->dev, 5082 " Tracing pin %d to ADC %d\n", 5083 ases[as].pins[i], j); 5084 ); 5085 /* Trace this pin taking goal into account. */ 5086 if (hdac_audio_trace_adc(devinfo, as, i, 5087 ases[as].pins[i], j, 0) == 0) { 5088 /* If we failed - return to previous and redo it. */ 5089 HDA_BOOTVERBOSE( 5090 device_printf(devinfo->codec->sc->dev, 5091 " Unable to trace pin %d to ADC %d, undo traces\n", 5092 ases[as].pins[i], j); 5093 ); 5094 hdac_audio_undo_trace(devinfo, as, -1); 5095 for (k = 0; k < 16; k++) 5096 ases[as].dacs[k] = 0; 5097 break; 5098 } 5099 HDA_BOOTVERBOSE( 5100 device_printf(devinfo->codec->sc->dev, 5101 " Pin %d traced to ADC %d\n", 5102 ases[as].pins[i], j); 5103 ); 5104 ases[as].dacs[i] = j; 5105 } 5106 if (i == 16) 5107 return (1); 5108 } 5109 return (0); 5110 } 5111 5112 /* 5113 * Trace input monitor path from mixer to output association. 5114 */ 5115 static int 5116 hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5117 { 5118 struct hdac_audio_as *ases = devinfo->function.audio.as; 5119 struct hdac_widget *w, *wc; 5120 int i, j; 5121 nid_t res = 0; 5122 5123 if (depth > HDA_PARSE_MAXDEPTH) 5124 return (0); 5125 w = hdac_widget_get(devinfo, nid); 5126 if (w == NULL || w->enable == 0) 5127 return (0); 5128 HDA_BOOTHVERBOSE( 5129 device_printf(devinfo->codec->sc->dev, 5130 " %*stracing via nid %d\n", 5131 depth + 1, "", w->nid); 5132 ); 5133 /* Use only unused widgets */ 5134 if (depth > 0 && w->bindas != -1) { 5135 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5136 HDA_BOOTHVERBOSE( 5137 device_printf(devinfo->codec->sc->dev, 5138 " %*snid %d found output association %d\n", 5139 depth + 1, "", w->nid, w->bindas); 5140 ); 5141 return (1); 5142 } else { 5143 HDA_BOOTHVERBOSE( 5144 device_printf(devinfo->codec->sc->dev, 5145 " %*snid %d busy by input association %d\n", 5146 depth + 1, "", w->nid, w->bindas); 5147 ); 5148 return (0); 5149 } 5150 } 5151 5152 switch (w->type) { 5153 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5154 /* Do not traverse input. AD1988 has digital monitor 5155 for which we are not ready. */ 5156 break; 5157 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5158 if (depth > 0) 5159 break; 5160 /* Fall */ 5161 default: 5162 /* Try to find reachable ADCs with specified nid. */ 5163 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5164 wc = hdac_widget_get(devinfo, j); 5165 if (wc == NULL || wc->enable == 0) 5166 continue; 5167 for (i = 0; i < wc->nconns; i++) { 5168 if (wc->connsenable[i] == 0) 5169 continue; 5170 if (wc->conns[i] != nid) 5171 continue; 5172 if (hdac_audio_trace_to_out(devinfo, 5173 j, depth + 1) != 0) { 5174 res = 1; 5175 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5176 wc->selconn == -1) 5177 wc->selconn = i; 5178 } 5179 } 5180 } 5181 break; 5182 } 5183 if (res) 5184 w->bindas = -2; 5185 5186 HDA_BOOTHVERBOSE( 5187 device_printf(devinfo->codec->sc->dev, 5188 " %*snid %d returned %d\n", 5189 depth + 1, "", w->nid, res); 5190 ); 5191 return (res); 5192 } 5193 5194 /* 5195 * Trace extra associations (beeper, monitor) 5196 */ 5197 static void 5198 hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5199 { 5200 struct hdac_audio_as *as = devinfo->function.audio.as; 5201 struct hdac_widget *w; 5202 int j; 5203 5204 /* Input monitor */ 5205 /* Find mixer associated with input, but supplying signal 5206 for output associations. Hope it will be input monitor. */ 5207 HDA_BOOTVERBOSE( 5208 device_printf(devinfo->codec->sc->dev, 5209 "Tracing input monitor\n"); 5210 ); 5211 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5212 w = hdac_widget_get(devinfo, j); 5213 if (w == NULL || w->enable == 0) 5214 continue; 5215 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5216 continue; 5217 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5218 continue; 5219 HDA_BOOTVERBOSE( 5220 device_printf(devinfo->codec->sc->dev, 5221 " Tracing nid %d to out\n", 5222 j); 5223 ); 5224 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5225 HDA_BOOTVERBOSE( 5226 device_printf(devinfo->codec->sc->dev, 5227 " nid %d is input monitor\n", 5228 w->nid); 5229 ); 5230 w->pflags |= HDA_ADC_MONITOR; 5231 w->ossdev = SOUND_MIXER_IMIX; 5232 } 5233 } 5234 5235 /* Beeper */ 5236 HDA_BOOTVERBOSE( 5237 device_printf(devinfo->codec->sc->dev, 5238 "Tracing beeper\n"); 5239 ); 5240 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5241 w = hdac_widget_get(devinfo, j); 5242 if (w == NULL || w->enable == 0) 5243 continue; 5244 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5245 continue; 5246 HDA_BOOTHVERBOSE( 5247 device_printf(devinfo->codec->sc->dev, 5248 " Tracing nid %d to out\n", 5249 j); 5250 ); 5251 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5252 HDA_BOOTVERBOSE( 5253 device_printf(devinfo->codec->sc->dev, 5254 " nid %d traced to out\n", 5255 j); 5256 ); 5257 } 5258 w->bindas = -2; 5259 } 5260 } 5261 5262 /* 5263 * Bind assotiations to PCM channels 5264 */ 5265 static void 5266 hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5267 { 5268 struct hdac_softc *sc = devinfo->codec->sc; 5269 struct hdac_audio_as *as = devinfo->function.audio.as; 5270 int j, cnt = 0, free; 5271 5272 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5273 if (as[j].enable) 5274 cnt++; 5275 } 5276 if (sc->num_chans == 0) { 5277 sc->chans = (struct hdac_chan *)malloc( 5278 sizeof(struct hdac_chan) * cnt, 5279 M_HDAC, M_ZERO | M_NOWAIT); 5280 if (sc->chans == NULL) { 5281 device_printf(devinfo->codec->sc->dev, 5282 "Channels memory allocation failed!\n"); 5283 return; 5284 } 5285 } else { 5286 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5287 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5288 M_HDAC, M_ZERO | M_NOWAIT); 5289 if (sc->chans == NULL) { 5290 sc->num_chans = 0; 5291 device_printf(devinfo->codec->sc->dev, 5292 "Channels memory allocation failed!\n"); 5293 return; 5294 } 5295 } 5296 free = sc->num_chans; 5297 sc->num_chans += cnt; 5298 5299 for (j = free; j < free + cnt; j++) { 5300 devinfo->codec->sc->chans[j].devinfo = devinfo; 5301 devinfo->codec->sc->chans[j].as = -1; 5302 } 5303 5304 /* Assign associations in order of their numbers, */ 5305 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5306 if (as[j].enable == 0) 5307 continue; 5308 5309 as[j].chan = free; 5310 devinfo->codec->sc->chans[free].as = j; 5311 devinfo->codec->sc->chans[free].dir = 5312 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5313 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5314 free++; 5315 } 5316 } 5317 5318 static void 5319 hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5320 { 5321 struct hdac_widget *w; 5322 int i; 5323 5324 /* Disable power and volume widgets. */ 5325 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5326 w = hdac_widget_get(devinfo, i); 5327 if (w == NULL || w->enable == 0) 5328 continue; 5329 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5330 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5331 w->enable = 0; 5332 HDA_BOOTHVERBOSE( 5333 device_printf(devinfo->codec->sc->dev, 5334 " Disabling nid %d due to it's" 5335 " non-audio type.\n", 5336 w->nid); 5337 ); 5338 } 5339 } 5340 } 5341 5342 static void 5343 hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5344 { 5345 struct hdac_widget *w, *cw; 5346 struct hdac_audio_ctl *ctl; 5347 int done, found, i, j, k; 5348 5349 /* Disable useless pins. */ 5350 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5351 w = hdac_widget_get(devinfo, i); 5352 if (w == NULL || w->enable == 0) 5353 continue; 5354 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5355 if ((w->wclass.pin.config & 5356 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5357 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5358 w->enable = 0; 5359 HDA_BOOTHVERBOSE( 5360 device_printf(devinfo->codec->sc->dev, 5361 " Disabling pin nid %d due" 5362 " to None connectivity.\n", 5363 w->nid); 5364 ); 5365 } else if ((w->wclass.pin.config & 5366 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5367 w->enable = 0; 5368 HDA_BOOTHVERBOSE( 5369 device_printf(devinfo->codec->sc->dev, 5370 " Disabling unassociated" 5371 " pin nid %d.\n", 5372 w->nid); 5373 ); 5374 } 5375 } 5376 } 5377 do { 5378 done = 1; 5379 /* Disable and mute controls for disabled widgets. */ 5380 i = 0; 5381 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5382 if (ctl->enable == 0) 5383 continue; 5384 if (ctl->widget->enable == 0 || 5385 (ctl->childwidget != NULL && 5386 ctl->childwidget->enable == 0)) { 5387 ctl->forcemute = 1; 5388 ctl->muted = HDA_AMP_MUTE_ALL; 5389 ctl->left = 0; 5390 ctl->right = 0; 5391 ctl->enable = 0; 5392 if (ctl->ndir == HDA_CTL_IN) 5393 ctl->widget->connsenable[ctl->index] = 0; 5394 done = 0; 5395 HDA_BOOTHVERBOSE( 5396 device_printf(devinfo->codec->sc->dev, 5397 " Disabling ctl %d nid %d cnid %d due" 5398 " to disabled widget.\n", i, 5399 ctl->widget->nid, 5400 (ctl->childwidget != NULL)? 5401 ctl->childwidget->nid:-1); 5402 ); 5403 } 5404 } 5405 /* Disable useless widgets. */ 5406 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5407 w = hdac_widget_get(devinfo, i); 5408 if (w == NULL || w->enable == 0) 5409 continue; 5410 /* Disable inputs with disabled child widgets. */ 5411 for (j = 0; j < w->nconns; j++) { 5412 if (w->connsenable[j]) { 5413 cw = hdac_widget_get(devinfo, w->conns[j]); 5414 if (cw == NULL || cw->enable == 0) { 5415 w->connsenable[j] = 0; 5416 HDA_BOOTHVERBOSE( 5417 device_printf(devinfo->codec->sc->dev, 5418 " Disabling nid %d connection %d due" 5419 " to disabled child widget.\n", 5420 i, j); 5421 ); 5422 } 5423 } 5424 } 5425 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5426 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5427 continue; 5428 /* Disable mixers and selectors without inputs. */ 5429 found = 0; 5430 for (j = 0; j < w->nconns; j++) { 5431 if (w->connsenable[j]) { 5432 found = 1; 5433 break; 5434 } 5435 } 5436 if (found == 0) { 5437 w->enable = 0; 5438 done = 0; 5439 HDA_BOOTHVERBOSE( 5440 device_printf(devinfo->codec->sc->dev, 5441 " Disabling nid %d due to all it's" 5442 " inputs disabled.\n", w->nid); 5443 ); 5444 } 5445 /* Disable nodes without consumers. */ 5446 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5447 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5448 continue; 5449 found = 0; 5450 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5451 cw = hdac_widget_get(devinfo, k); 5452 if (cw == NULL || cw->enable == 0) 5453 continue; 5454 for (j = 0; j < cw->nconns; j++) { 5455 if (cw->connsenable[j] && cw->conns[j] == i) { 5456 found = 1; 5457 break; 5458 } 5459 } 5460 } 5461 if (found == 0) { 5462 w->enable = 0; 5463 done = 0; 5464 HDA_BOOTHVERBOSE( 5465 device_printf(devinfo->codec->sc->dev, 5466 " Disabling nid %d due to all it's" 5467 " consumers disabled.\n", w->nid); 5468 ); 5469 } 5470 } 5471 } while (done == 0); 5472 5473 } 5474 5475 static void 5476 hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5477 { 5478 struct hdac_audio_as *as = devinfo->function.audio.as; 5479 struct hdac_widget *w, *cw; 5480 struct hdac_audio_ctl *ctl; 5481 int i, j, k; 5482 5483 /* Disable unassosiated widgets. */ 5484 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5485 w = hdac_widget_get(devinfo, i); 5486 if (w == NULL || w->enable == 0) 5487 continue; 5488 if (w->bindas == -1) { 5489 w->enable = 0; 5490 HDA_BOOTHVERBOSE( 5491 device_printf(devinfo->codec->sc->dev, 5492 " Disabling unassociated nid %d.\n", 5493 w->nid); 5494 ); 5495 } 5496 } 5497 /* Disable input connections on input pin and 5498 * output on output. */ 5499 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5500 w = hdac_widget_get(devinfo, i); 5501 if (w == NULL || w->enable == 0) 5502 continue; 5503 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5504 continue; 5505 if (w->bindas < 0) 5506 continue; 5507 if (as[w->bindas].dir == HDA_CTL_IN) { 5508 for (j = 0; j < w->nconns; j++) { 5509 if (w->connsenable[j] == 0) 5510 continue; 5511 w->connsenable[j] = 0; 5512 HDA_BOOTHVERBOSE( 5513 device_printf(devinfo->codec->sc->dev, 5514 " Disabling connection to input pin " 5515 "nid %d conn %d.\n", 5516 i, j); 5517 ); 5518 } 5519 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5520 HDA_CTL_IN, -1, 1); 5521 if (ctl && ctl->enable) { 5522 ctl->forcemute = 1; 5523 ctl->muted = HDA_AMP_MUTE_ALL; 5524 ctl->left = 0; 5525 ctl->right = 0; 5526 ctl->enable = 0; 5527 } 5528 } else { 5529 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5530 HDA_CTL_OUT, -1, 1); 5531 if (ctl && ctl->enable) { 5532 ctl->forcemute = 1; 5533 ctl->muted = HDA_AMP_MUTE_ALL; 5534 ctl->left = 0; 5535 ctl->right = 0; 5536 ctl->enable = 0; 5537 } 5538 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5539 cw = hdac_widget_get(devinfo, k); 5540 if (cw == NULL || cw->enable == 0) 5541 continue; 5542 for (j = 0; j < cw->nconns; j++) { 5543 if (cw->connsenable[j] && cw->conns[j] == i) { 5544 cw->connsenable[j] = 0; 5545 HDA_BOOTHVERBOSE( 5546 device_printf(devinfo->codec->sc->dev, 5547 " Disabling connection from output pin " 5548 "nid %d conn %d cnid %d.\n", 5549 k, j, i); 5550 ); 5551 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5552 cw->nconns > 1) 5553 continue; 5554 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5555 HDA_CTL_IN, j, 1); 5556 if (ctl && ctl->enable) { 5557 ctl->forcemute = 1; 5558 ctl->muted = HDA_AMP_MUTE_ALL; 5559 ctl->left = 0; 5560 ctl->right = 0; 5561 ctl->enable = 0; 5562 } 5563 } 5564 } 5565 } 5566 } 5567 } 5568 } 5569 5570 static void 5571 hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5572 { 5573 struct hdac_audio_as *as = devinfo->function.audio.as; 5574 struct hdac_widget *w; 5575 int i, j; 5576 5577 /* On playback path we can safely disable all unseleted inputs. */ 5578 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5579 w = hdac_widget_get(devinfo, i); 5580 if (w == NULL || w->enable == 0) 5581 continue; 5582 if (w->nconns <= 1) 5583 continue; 5584 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5585 continue; 5586 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5587 continue; 5588 for (j = 0; j < w->nconns; j++) { 5589 if (w->connsenable[j] == 0) 5590 continue; 5591 if (w->selconn < 0 || w->selconn == j) 5592 continue; 5593 w->connsenable[j] = 0; 5594 HDA_BOOTHVERBOSE( 5595 device_printf(devinfo->codec->sc->dev, 5596 " Disabling unselected connection " 5597 "nid %d conn %d.\n", 5598 i, j); 5599 ); 5600 } 5601 } 5602 } 5603 5604 static void 5605 hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5606 { 5607 struct hdac_widget *w, *cw; 5608 struct hdac_audio_ctl *ctl; 5609 int i, j; 5610 5611 /* Disable crossassociatement and unwanted crosschannel connections. */ 5612 /* ... using selectors */ 5613 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5614 w = hdac_widget_get(devinfo, i); 5615 if (w == NULL || w->enable == 0) 5616 continue; 5617 if (w->nconns <= 1) 5618 continue; 5619 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5620 continue; 5621 if (w->bindas == -2) 5622 continue; 5623 for (j = 0; j < w->nconns; j++) { 5624 if (w->connsenable[j] == 0) 5625 continue; 5626 cw = hdac_widget_get(devinfo, w->conns[j]); 5627 if (cw == NULL || w->enable == 0) 5628 continue; 5629 if (cw->bindas == -2) 5630 continue; 5631 if (w->bindas == cw->bindas && 5632 (w->bindseqmask & cw->bindseqmask) != 0) 5633 continue; 5634 w->connsenable[j] = 0; 5635 HDA_BOOTHVERBOSE( 5636 device_printf(devinfo->codec->sc->dev, 5637 " Disabling crossassociatement connection " 5638 "nid %d conn %d cnid %d.\n", 5639 i, j, cw->nid); 5640 ); 5641 } 5642 } 5643 /* ... using controls */ 5644 i = 0; 5645 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5646 if (ctl->enable == 0 || ctl->childwidget == NULL) 5647 continue; 5648 if (ctl->widget->bindas == -2 || 5649 ctl->childwidget->bindas == -2) 5650 continue; 5651 if (ctl->widget->bindas != ctl->childwidget->bindas || 5652 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5653 ctl->forcemute = 1; 5654 ctl->muted = HDA_AMP_MUTE_ALL; 5655 ctl->left = 0; 5656 ctl->right = 0; 5657 ctl->enable = 0; 5658 if (ctl->ndir == HDA_CTL_IN) 5659 ctl->widget->connsenable[ctl->index] = 0; 5660 HDA_BOOTHVERBOSE( 5661 device_printf(devinfo->codec->sc->dev, 5662 " Disabling crossassociatement connection " 5663 "ctl %d nid %d cnid %d.\n", i, 5664 ctl->widget->nid, 5665 ctl->childwidget->nid); 5666 ); 5667 } 5668 } 5669 5670 } 5671 5672 #define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5673 5674 /* 5675 * Find controls to control amplification for source. 5676 */ 5677 static int 5678 hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5679 int ossdev, int ctlable, int depth, int need) 5680 { 5681 struct hdac_widget *w, *wc; 5682 struct hdac_audio_ctl *ctl; 5683 int i, j, conns = 0, rneed; 5684 5685 if (depth > HDA_PARSE_MAXDEPTH) 5686 return (need); 5687 5688 w = hdac_widget_get(devinfo, nid); 5689 if (w == NULL || w->enable == 0) 5690 return (need); 5691 5692 /* Count number of active inputs. */ 5693 if (depth > 0) { 5694 for (j = 0; j < w->nconns; j++) { 5695 if (w->connsenable[j]) 5696 conns++; 5697 } 5698 } 5699 5700 /* If this is not a first step - use input mixer. 5701 Pins have common input ctl so care must be taken. */ 5702 if (depth > 0 && ctlable && (conns == 1 || 5703 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5704 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5705 index, 1); 5706 if (ctl) { 5707 if (HDA_CTL_GIVE(ctl) & need) 5708 ctl->ossmask |= (1 << ossdev); 5709 else 5710 ctl->possmask |= (1 << ossdev); 5711 need &= ~HDA_CTL_GIVE(ctl); 5712 } 5713 } 5714 5715 /* If widget has own ossdev - not traverse it. 5716 It will be traversed on it's own. */ 5717 if (w->ossdev >= 0 && depth > 0) 5718 return (need); 5719 5720 /* We must not traverse pin */ 5721 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5722 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5723 depth > 0) 5724 return (need); 5725 5726 /* record that this widget exports such signal, */ 5727 w->ossmask |= (1 << ossdev); 5728 5729 /* If signals mixed, we can't assign controls farther. 5730 * Ignore this on depth zero. Caller must knows why. 5731 * Ignore this for static selectors if this input selected. 5732 */ 5733 if (conns > 1) 5734 ctlable = 0; 5735 5736 if (ctlable) { 5737 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5738 if (ctl) { 5739 if (HDA_CTL_GIVE(ctl) & need) 5740 ctl->ossmask |= (1 << ossdev); 5741 else 5742 ctl->possmask |= (1 << ossdev); 5743 need &= ~HDA_CTL_GIVE(ctl); 5744 } 5745 } 5746 5747 rneed = 0; 5748 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5749 wc = hdac_widget_get(devinfo, i); 5750 if (wc == NULL || wc->enable == 0) 5751 continue; 5752 for (j = 0; j < wc->nconns; j++) { 5753 if (wc->connsenable[j] && wc->conns[j] == nid) { 5754 rneed |= hdac_audio_ctl_source_amp(devinfo, 5755 wc->nid, j, ossdev, ctlable, depth + 1, need); 5756 } 5757 } 5758 } 5759 rneed &= need; 5760 5761 return (rneed); 5762 } 5763 5764 /* 5765 * Find controls to control amplification for destination. 5766 */ 5767 static void 5768 hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5769 int ossdev, int depth, int need) 5770 { 5771 struct hdac_audio_as *as = devinfo->function.audio.as; 5772 struct hdac_widget *w, *wc; 5773 struct hdac_audio_ctl *ctl; 5774 int i, j, consumers; 5775 5776 if (depth > HDA_PARSE_MAXDEPTH) 5777 return; 5778 5779 w = hdac_widget_get(devinfo, nid); 5780 if (w == NULL || w->enable == 0) 5781 return; 5782 5783 if (depth > 0) { 5784 /* If this node produce output for several consumers, 5785 we can't touch it. */ 5786 consumers = 0; 5787 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5788 wc = hdac_widget_get(devinfo, i); 5789 if (wc == NULL || wc->enable == 0) 5790 continue; 5791 for (j = 0; j < wc->nconns; j++) { 5792 if (wc->connsenable[j] && wc->conns[j] == nid) 5793 consumers++; 5794 } 5795 } 5796 /* The only exception is if real HP redirection is configured 5797 and this is a duplication point. 5798 XXX: Actually exception is not completely correct. 5799 XXX: Duplication point check is not perfect. */ 5800 if ((consumers == 2 && (w->bindas < 0 || 5801 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5802 (w->bindseqmask & (1 << 15)) == 0)) || 5803 consumers > 2) 5804 return; 5805 5806 /* Else use it's output mixer. */ 5807 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5808 HDA_CTL_OUT, -1, 1); 5809 if (ctl) { 5810 if (HDA_CTL_GIVE(ctl) & need) 5811 ctl->ossmask |= (1 << ossdev); 5812 else 5813 ctl->possmask |= (1 << ossdev); 5814 need &= ~HDA_CTL_GIVE(ctl); 5815 } 5816 } 5817 5818 /* We must not traverse pin */ 5819 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5820 depth > 0) 5821 return; 5822 5823 for (i = 0; i < w->nconns; i++) { 5824 int tneed = need; 5825 if (w->connsenable[i] == 0) 5826 continue; 5827 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5828 HDA_CTL_IN, i, 1); 5829 if (ctl) { 5830 if (HDA_CTL_GIVE(ctl) & tneed) 5831 ctl->ossmask |= (1 << ossdev); 5832 else 5833 ctl->possmask |= (1 << ossdev); 5834 tneed &= ~HDA_CTL_GIVE(ctl); 5835 } 5836 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5837 depth + 1, tneed); 5838 } 5839 } 5840 5841 /* 5842 * Assign OSS names to sound sources 5843 */ 5844 static void 5845 hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5846 { 5847 struct hdac_audio_as *as = devinfo->function.audio.as; 5848 struct hdac_widget *w; 5849 int i, j; 5850 int type = -1, use, used = 0; 5851 static const int types[7][13] = { 5852 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5853 SOUND_MIXER_LINE3, -1 }, /* line */ 5854 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5855 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5856 { SOUND_MIXER_CD, -1 }, /* cd */ 5857 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5858 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5859 -1 }, /* digital */ 5860 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5861 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5862 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5863 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5864 -1 } /* others */ 5865 }; 5866 5867 /* Surely known names */ 5868 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5869 w = hdac_widget_get(devinfo, i); 5870 if (w == NULL || w->enable == 0) 5871 continue; 5872 if (w->bindas == -1) 5873 continue; 5874 use = -1; 5875 switch (w->type) { 5876 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5877 if (as[w->bindas].dir == HDA_CTL_OUT) 5878 break; 5879 type = -1; 5880 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5881 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5882 type = 0; 5883 break; 5884 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5885 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5886 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5887 break; 5888 type = 1; 5889 break; 5890 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5891 type = 3; 5892 break; 5893 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5894 type = 4; 5895 break; 5896 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5897 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5898 type = 5; 5899 break; 5900 } 5901 if (type == -1) 5902 break; 5903 j = 0; 5904 while (types[type][j] >= 0 && 5905 (used & (1 << types[type][j])) != 0) { 5906 j++; 5907 } 5908 if (types[type][j] >= 0) 5909 use = types[type][j]; 5910 break; 5911 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5912 use = SOUND_MIXER_PCM; 5913 break; 5914 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5915 use = SOUND_MIXER_SPEAKER; 5916 break; 5917 default: 5918 break; 5919 } 5920 if (use >= 0) { 5921 w->ossdev = use; 5922 used |= (1 << use); 5923 } 5924 } 5925 /* Semi-known names */ 5926 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5927 w = hdac_widget_get(devinfo, i); 5928 if (w == NULL || w->enable == 0) 5929 continue; 5930 if (w->ossdev >= 0) 5931 continue; 5932 if (w->bindas == -1) 5933 continue; 5934 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5935 continue; 5936 if (as[w->bindas].dir == HDA_CTL_OUT) 5937 continue; 5938 type = -1; 5939 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5940 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5941 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5942 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5943 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5944 type = 0; 5945 break; 5946 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5947 type = 2; 5948 break; 5949 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5950 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5951 type = 5; 5952 break; 5953 } 5954 if (type == -1) 5955 break; 5956 j = 0; 5957 while (types[type][j] >= 0 && 5958 (used & (1 << types[type][j])) != 0) { 5959 j++; 5960 } 5961 if (types[type][j] >= 0) { 5962 w->ossdev = types[type][j]; 5963 used |= (1 << types[type][j]); 5964 } 5965 } 5966 /* Others */ 5967 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5968 w = hdac_widget_get(devinfo, i); 5969 if (w == NULL || w->enable == 0) 5970 continue; 5971 if (w->ossdev >= 0) 5972 continue; 5973 if (w->bindas == -1) 5974 continue; 5975 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5976 continue; 5977 if (as[w->bindas].dir == HDA_CTL_OUT) 5978 continue; 5979 j = 0; 5980 while (types[6][j] >= 0 && 5981 (used & (1 << types[6][j])) != 0) { 5982 j++; 5983 } 5984 if (types[6][j] >= 0) { 5985 w->ossdev = types[6][j]; 5986 used |= (1 << types[6][j]); 5987 } 5988 } 5989 } 5990 5991 static void 5992 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5993 { 5994 struct hdac_audio_as *as = devinfo->function.audio.as; 5995 int j, res; 5996 5997 /* Trace all associations in order of their numbers, */ 5998 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5999 if (as[j].enable == 0) 6000 continue; 6001 HDA_BOOTVERBOSE( 6002 device_printf(devinfo->codec->sc->dev, 6003 "Tracing association %d (%d)\n", j, as[j].index); 6004 ); 6005 if (as[j].dir == HDA_CTL_OUT) { 6006 retry: 6007 res = hdac_audio_trace_as_out(devinfo, j, 0); 6008 if (res == 0 && as[j].hpredir >= 0 && 6009 as[j].fakeredir == 0) { 6010 /* If codec can't do analog HP redirection 6011 try to make it using one more DAC. */ 6012 as[j].fakeredir = 1; 6013 goto retry; 6014 } 6015 } else { 6016 res = hdac_audio_trace_as_in(devinfo, j); 6017 } 6018 if (res) { 6019 HDA_BOOTVERBOSE( 6020 device_printf(devinfo->codec->sc->dev, 6021 "Association %d (%d) trace succeeded\n", 6022 j, as[j].index); 6023 ); 6024 } else { 6025 HDA_BOOTVERBOSE( 6026 device_printf(devinfo->codec->sc->dev, 6027 "Association %d (%d) trace failed\n", 6028 j, as[j].index); 6029 ); 6030 as[j].enable = 0; 6031 } 6032 } 6033 6034 /* Trace mixer and beeper pseudo associations. */ 6035 hdac_audio_trace_as_extra(devinfo); 6036 } 6037 6038 static void 6039 hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6040 { 6041 struct hdac_audio_as *as = devinfo->function.audio.as; 6042 struct hdac_audio_ctl *ctl; 6043 struct hdac_widget *w; 6044 int i; 6045 6046 /* Assign mixers to the tree. */ 6047 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6048 w = hdac_widget_get(devinfo, i); 6049 if (w == NULL || w->enable == 0) 6050 continue; 6051 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6052 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6053 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6054 as[w->bindas].dir == HDA_CTL_IN)) { 6055 if (w->ossdev < 0) 6056 continue; 6057 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6058 w->ossdev, 1, 0, 1); 6059 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6060 if (w->ossdev < 0) 6061 continue; 6062 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6063 w->ossdev, 1, 0, 1)) { 6064 /* If we are unable to control input monitor 6065 as source - try to control it as destination. */ 6066 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6067 w->ossdev, 0, 1); 6068 } 6069 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6070 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6071 SOUND_MIXER_RECLEV, 0, 1); 6072 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6073 as[w->bindas].dir == HDA_CTL_OUT) { 6074 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6075 SOUND_MIXER_VOLUME, 0, 1); 6076 } 6077 } 6078 /* Treat unrequired as possible. */ 6079 i = 0; 6080 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6081 if (ctl->ossmask == 0) 6082 ctl->ossmask = ctl->possmask; 6083 } 6084 } 6085 6086 static void 6087 hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6088 { 6089 struct hdac_audio_as *as = devinfo->function.audio.as; 6090 struct hdac_widget *w; 6091 uint32_t pincap; 6092 int i; 6093 6094 for (i = 0; i < devinfo->nodecnt; i++) { 6095 w = &devinfo->widget[i]; 6096 if (w == NULL) 6097 continue; 6098 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6099 continue; 6100 6101 pincap = w->wclass.pin.cap; 6102 6103 /* Disable everything. */ 6104 w->wclass.pin.ctrl &= ~( 6105 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6106 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6107 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6108 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6109 6110 if (w->enable == 0 || 6111 w->bindas < 0 || as[w->bindas].enable == 0) { 6112 /* Pin is unused so left it disabled. */ 6113 continue; 6114 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6115 /* Input pin, configure for input. */ 6116 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6117 w->wclass.pin.ctrl |= 6118 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6119 6120 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6121 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6122 w->wclass.pin.ctrl |= 6123 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6124 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6125 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6126 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6127 w->wclass.pin.ctrl |= 6128 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6129 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6130 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6131 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6132 w->wclass.pin.ctrl |= 6133 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6134 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6135 } else { 6136 /* Output pin, configure for output. */ 6137 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6138 w->wclass.pin.ctrl |= 6139 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6140 6141 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6142 (w->wclass.pin.config & 6143 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6144 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6145 w->wclass.pin.ctrl |= 6146 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6147 6148 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6149 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6150 w->wclass.pin.ctrl |= 6151 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6152 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6153 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6154 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6155 w->wclass.pin.ctrl |= 6156 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6157 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6158 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6159 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6160 w->wclass.pin.ctrl |= 6161 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6162 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6163 } 6164 } 6165 } 6166 6167 static void 6168 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6169 { 6170 struct hdac_audio_ctl *ctl; 6171 int i, z; 6172 6173 i = 0; 6174 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6175 if (ctl->enable == 0 || ctl->ossmask != 0) { 6176 /* Mute disabled and mixer controllable controls. 6177 * Last will be initialized by mixer_init(). 6178 * This expected to reduce click on startup. */ 6179 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6180 continue; 6181 } 6182 /* Init fixed controls to 0dB amplification. */ 6183 z = ctl->offset; 6184 if (z > ctl->step) 6185 z = ctl->step; 6186 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6187 } 6188 } 6189 6190 static void 6191 hdac_audio_commit(struct hdac_devinfo *devinfo) 6192 { 6193 struct hdac_softc *sc = devinfo->codec->sc; 6194 struct hdac_widget *w; 6195 nid_t cad; 6196 uint32_t gdata, gmask, gdir; 6197 int commitgpio, numgpio; 6198 int i; 6199 6200 cad = devinfo->codec->cad; 6201 6202 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6203 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6204 0x7e7, 0), cad); 6205 6206 /* Commit controls. */ 6207 hdac_audio_ctl_commit(devinfo); 6208 6209 /* Commit selectors, pins and EAPD. */ 6210 for (i = 0; i < devinfo->nodecnt; i++) { 6211 w = &devinfo->widget[i]; 6212 if (w == NULL) 6213 continue; 6214 if (w->selconn == -1) 6215 w->selconn = 0; 6216 if (w->nconns > 0) 6217 hdac_widget_connection_select(w, w->selconn); 6218 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6219 hdac_command(sc, 6220 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6221 w->wclass.pin.ctrl), cad); 6222 } 6223 if (w->param.eapdbtl != HDAC_INVALID) { 6224 uint32_t val; 6225 6226 val = w->param.eapdbtl; 6227 if (devinfo->function.audio.quirks & 6228 HDA_QUIRK_EAPDINV) 6229 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6230 hdac_command(sc, 6231 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6232 val), cad); 6233 } 6234 } 6235 6236 /* Commit GPIOs. */ 6237 gdata = 0; 6238 gmask = 0; 6239 gdir = 0; 6240 commitgpio = 0; 6241 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6242 devinfo->function.audio.gpio); 6243 6244 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6245 commitgpio = (numgpio > 0) ? 1 : 0; 6246 else { 6247 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6248 if (!(devinfo->function.audio.quirks & 6249 (1 << i))) 6250 continue; 6251 if (commitgpio == 0) { 6252 commitgpio = 1; 6253 HDA_BOOTVERBOSE( 6254 gdata = hdac_command(sc, 6255 HDA_CMD_GET_GPIO_DATA(cad, 6256 devinfo->nid), cad); 6257 gmask = hdac_command(sc, 6258 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6259 devinfo->nid), cad); 6260 gdir = hdac_command(sc, 6261 HDA_CMD_GET_GPIO_DIRECTION(cad, 6262 devinfo->nid), cad); 6263 device_printf(sc->dev, 6264 "GPIO init: data=0x%08x " 6265 "mask=0x%08x dir=0x%08x\n", 6266 gdata, gmask, gdir); 6267 gdata = 0; 6268 gmask = 0; 6269 gdir = 0; 6270 ); 6271 } 6272 gdata |= 1 << i; 6273 gmask |= 1 << i; 6274 gdir |= 1 << i; 6275 } 6276 } 6277 6278 if (commitgpio != 0) { 6279 HDA_BOOTVERBOSE( 6280 device_printf(sc->dev, 6281 "GPIO commit: data=0x%08x mask=0x%08x " 6282 "dir=0x%08x\n", 6283 gdata, gmask, gdir); 6284 ); 6285 hdac_command(sc, 6286 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6287 gmask), cad); 6288 hdac_command(sc, 6289 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6290 gdir), cad); 6291 hdac_command(sc, 6292 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6293 gdata), cad); 6294 } 6295 } 6296 6297 static void 6298 hdac_powerup(struct hdac_devinfo *devinfo) 6299 { 6300 struct hdac_softc *sc = devinfo->codec->sc; 6301 nid_t cad = devinfo->codec->cad; 6302 int i; 6303 6304 hdac_command(sc, 6305 HDA_CMD_SET_POWER_STATE(cad, 6306 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6307 cad); 6308 DELAY(100); 6309 6310 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6311 hdac_command(sc, 6312 HDA_CMD_SET_POWER_STATE(cad, 6313 i, HDA_CMD_POWER_STATE_D0), 6314 cad); 6315 } 6316 DELAY(1000); 6317 } 6318 6319 static int 6320 hdac_pcmchannel_setup(struct hdac_chan *ch) 6321 { 6322 struct hdac_devinfo *devinfo = ch->devinfo; 6323 struct hdac_audio_as *as = devinfo->function.audio.as; 6324 struct hdac_widget *w; 6325 uint32_t cap, fmtcap, pcmcap; 6326 int i, j, ret, max; 6327 6328 ch->caps = hdac_caps; 6329 ch->caps.fmtlist = ch->fmtlist; 6330 ch->bit16 = 1; 6331 ch->bit32 = 0; 6332 ch->pcmrates[0] = 48000; 6333 ch->pcmrates[1] = 0; 6334 6335 ret = 0; 6336 fmtcap = devinfo->function.audio.supp_stream_formats; 6337 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6338 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6339 6340 for (i = 0; i < 16 && ret < max; i++) { 6341 /* Check as is correct */ 6342 if (ch->as < 0) 6343 break; 6344 /* Cound only present DACs */ 6345 if (as[ch->as].dacs[i] <= 0) 6346 continue; 6347 /* Ignore duplicates */ 6348 for (j = 0; j < ret; j++) { 6349 if (ch->io[j] == as[ch->as].dacs[i]) 6350 break; 6351 } 6352 if (j < ret) 6353 continue; 6354 6355 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6356 if (w == NULL || w->enable == 0) 6357 continue; 6358 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6359 continue; 6360 cap = w->param.supp_stream_formats; 6361 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6362 }*/ 6363 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6364 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6365 continue; 6366 /* Many codec does not declare AC3 support on SPDIF. 6367 I don't beleave that they doesn't support it! */ 6368 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6369 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6370 if (ret == 0) { 6371 fmtcap = cap; 6372 pcmcap = w->param.supp_pcm_size_rate; 6373 } else { 6374 fmtcap &= cap; 6375 pcmcap &= w->param.supp_pcm_size_rate; 6376 } 6377 ch->io[ret++] = as[ch->as].dacs[i]; 6378 } 6379 ch->io[ret] = -1; 6380 6381 ch->supp_stream_formats = fmtcap; 6382 ch->supp_pcm_size_rate = pcmcap; 6383 6384 /* 6385 * 8bit = 0 6386 * 16bit = 1 6387 * 20bit = 2 6388 * 24bit = 3 6389 * 32bit = 4 6390 */ 6391 if (ret > 0) { 6392 i = 0; 6393 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6394 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6395 ch->bit16 = 1; 6396 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6397 ch->bit16 = 0; 6398 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6399 ch->bit32 = 4; 6400 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6401 ch->bit32 = 3; 6402 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6403 ch->bit32 = 2; 6404 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6405 ch->fmtlist[i++] = AFMT_S16_LE; 6406 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6407 if (ch->bit32 > 0) { 6408 if (!(devinfo->function.audio.quirks & 6409 HDA_QUIRK_FORCESTEREO)) 6410 ch->fmtlist[i++] = AFMT_S32_LE; 6411 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6412 } 6413 } 6414 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6415 ch->fmtlist[i++] = AFMT_AC3; 6416 } 6417 ch->fmtlist[i] = 0; 6418 i = 0; 6419 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6420 ch->pcmrates[i++] = 8000; 6421 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6422 ch->pcmrates[i++] = 11025; 6423 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6424 ch->pcmrates[i++] = 16000; 6425 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6426 ch->pcmrates[i++] = 22050; 6427 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6428 ch->pcmrates[i++] = 32000; 6429 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6430 ch->pcmrates[i++] = 44100; 6431 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6432 ch->pcmrates[i++] = 48000; 6433 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6434 ch->pcmrates[i++] = 88200; 6435 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6436 ch->pcmrates[i++] = 96000; 6437 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6438 ch->pcmrates[i++] = 176400; 6439 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6440 ch->pcmrates[i++] = 192000; 6441 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6442 ch->pcmrates[i] = 0; 6443 if (i > 0) { 6444 ch->caps.minspeed = ch->pcmrates[0]; 6445 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6446 } 6447 } 6448 6449 return (ret); 6450 } 6451 6452 static void 6453 hdac_create_pcms(struct hdac_devinfo *devinfo) 6454 { 6455 struct hdac_softc *sc = devinfo->codec->sc; 6456 struct hdac_audio_as *as = devinfo->function.audio.as; 6457 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6458 6459 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6460 if (as[i].enable == 0) 6461 continue; 6462 if (as[i].dir == HDA_CTL_IN) { 6463 if (as[i].digital) 6464 drdev++; 6465 else 6466 ardev++; 6467 } else { 6468 if (as[i].digital) 6469 dpdev++; 6470 else 6471 apdev++; 6472 } 6473 } 6474 devinfo->function.audio.num_devs = 6475 max(ardev, apdev) + max(drdev, dpdev); 6476 devinfo->function.audio.devs = 6477 (struct hdac_pcm_devinfo *)malloc( 6478 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6479 M_HDAC, M_ZERO | M_NOWAIT); 6480 if (devinfo->function.audio.devs == NULL) { 6481 device_printf(sc->dev, 6482 "Unable to allocate memory for devices\n"); 6483 return; 6484 } 6485 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6486 devinfo->function.audio.devs[i].index = i; 6487 devinfo->function.audio.devs[i].devinfo = devinfo; 6488 devinfo->function.audio.devs[i].play = -1; 6489 devinfo->function.audio.devs[i].rec = -1; 6490 devinfo->function.audio.devs[i].digital = 2; 6491 } 6492 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6493 if (as[i].enable == 0) 6494 continue; 6495 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6496 if (devinfo->function.audio.devs[j].digital != 2 && 6497 devinfo->function.audio.devs[j].digital != 6498 as[i].digital) 6499 continue; 6500 if (as[i].dir == HDA_CTL_IN) { 6501 if (devinfo->function.audio.devs[j].rec >= 0) 6502 continue; 6503 devinfo->function.audio.devs[j].rec 6504 = as[i].chan; 6505 } else { 6506 if (devinfo->function.audio.devs[j].play >= 0) 6507 continue; 6508 devinfo->function.audio.devs[j].play 6509 = as[i].chan; 6510 } 6511 sc->chans[as[i].chan].pdevinfo = 6512 &devinfo->function.audio.devs[j]; 6513 devinfo->function.audio.devs[j].digital = 6514 as[i].digital; 6515 break; 6516 } 6517 } 6518 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6519 struct hdac_pcm_devinfo *pdevinfo = 6520 &devinfo->function.audio.devs[i]; 6521 pdevinfo->dev = 6522 device_add_child(sc->dev, "pcm", -1); 6523 device_set_ivars(pdevinfo->dev, 6524 (void *)pdevinfo); 6525 } 6526 } 6527 6528 static void 6529 hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6530 { 6531 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6532 struct hdac_audio_ctl *ctl; 6533 struct hdac_softc *sc = devinfo->codec->sc; 6534 char buf[64]; 6535 int i, j, printed; 6536 6537 if (flag == 0) { 6538 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6539 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6540 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6541 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6542 } 6543 6544 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6545 if ((flag & (1 << j)) == 0) 6546 continue; 6547 i = 0; 6548 printed = 0; 6549 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6550 if (ctl->enable == 0 || 6551 ctl->widget->enable == 0) 6552 continue; 6553 if (!((pdevinfo->play >= 0 && 6554 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6555 (pdevinfo->rec >= 0 && 6556 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6557 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6558 continue; 6559 if ((ctl->ossmask & (1 << j)) == 0) 6560 continue; 6561 6562 if (printed == 0) { 6563 device_printf(pdevinfo->dev, "\n"); 6564 if (banner != NULL) { 6565 device_printf(pdevinfo->dev, "%s", banner); 6566 } else { 6567 device_printf(pdevinfo->dev, "Unknown Ctl"); 6568 } 6569 printf(" (OSS: %s)\n", 6570 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6571 buf, sizeof(buf))); 6572 device_printf(pdevinfo->dev, " |\n"); 6573 printed = 1; 6574 } 6575 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6576 ctl->widget->nid, 6577 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6578 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6579 printf(" %2d): ", ctl->index); 6580 else 6581 printf("): "); 6582 if (ctl->step > 0) { 6583 printf("%+d/%+ddB (%d steps)%s\n", 6584 (0 - ctl->offset) * (ctl->size + 1) / 4, 6585 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6586 ctl->step + 1, 6587 ctl->mute?" + mute":""); 6588 } else 6589 printf("%s\n", ctl->mute?"mute":""); 6590 } 6591 } 6592 } 6593 6594 static void 6595 hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6596 { 6597 uint32_t cap; 6598 6599 cap = fcap; 6600 if (cap != 0) { 6601 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6602 device_printf(dev, " "); 6603 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6604 printf(" AC3"); 6605 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6606 printf(" FLOAT32"); 6607 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6608 printf(" PCM"); 6609 printf("\n"); 6610 } 6611 cap = pcmcap; 6612 if (cap != 0) { 6613 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6614 device_printf(dev, " "); 6615 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6616 printf(" 8"); 6617 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6618 printf(" 16"); 6619 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6620 printf(" 20"); 6621 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6622 printf(" 24"); 6623 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6624 printf(" 32"); 6625 printf(" bits,"); 6626 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6627 printf(" 8"); 6628 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6629 printf(" 11"); 6630 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6631 printf(" 16"); 6632 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6633 printf(" 22"); 6634 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6635 printf(" 32"); 6636 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6637 printf(" 44"); 6638 printf(" 48"); 6639 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6640 printf(" 88"); 6641 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6642 printf(" 96"); 6643 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6644 printf(" 176"); 6645 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6646 printf(" 192"); 6647 printf(" KHz\n"); 6648 } 6649 } 6650 6651 static void 6652 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6653 { 6654 uint32_t pincap; 6655 6656 pincap = w->wclass.pin.cap; 6657 6658 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6659 device_printf(sc->dev, " "); 6660 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6661 printf(" ISC"); 6662 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6663 printf(" TRQD"); 6664 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6665 printf(" PDC"); 6666 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6667 printf(" HP"); 6668 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6669 printf(" OUT"); 6670 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6671 printf(" IN"); 6672 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6673 printf(" BAL"); 6674 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6675 printf(" VREF["); 6676 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6677 printf(" 50"); 6678 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6679 printf(" 80"); 6680 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6681 printf(" 100"); 6682 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6683 printf(" GROUND"); 6684 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6685 printf(" HIZ"); 6686 printf(" ]"); 6687 } 6688 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6689 printf(" EAPD"); 6690 printf("\n"); 6691 device_printf(sc->dev, " Pin config: 0x%08x\n", 6692 w->wclass.pin.config); 6693 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6694 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6695 printf(" HP"); 6696 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6697 printf(" IN"); 6698 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6699 printf(" OUT"); 6700 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6701 printf(" VREFs"); 6702 printf("\n"); 6703 } 6704 6705 static void 6706 hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6707 { 6708 struct hdac_softc *sc = w->devinfo->codec->sc; 6709 6710 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6711 "jack %2d loc %2d color %7s misc %d%s\n", 6712 w->nid, conf, 6713 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6714 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6715 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6716 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6717 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6718 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6719 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6720 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6721 (w->enable == 0)?" [DISABLED]":""); 6722 } 6723 6724 static void 6725 hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6726 { 6727 struct hdac_widget *w; 6728 int i; 6729 6730 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6731 w = hdac_widget_get(devinfo, i); 6732 if (w == NULL) 6733 continue; 6734 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6735 continue; 6736 hdac_dump_pin_config(w, w->wclass.pin.config); 6737 } 6738 } 6739 6740 static void 6741 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6742 { 6743 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6744 device_printf(sc->dev, " " 6745 "mute=%d step=%d size=%d offset=%d\n", 6746 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6747 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6748 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6749 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6750 } 6751 6752 static void 6753 hdac_dump_nodes(struct hdac_devinfo *devinfo) 6754 { 6755 struct hdac_softc *sc = devinfo->codec->sc; 6756 static char *ossname[] = SOUND_DEVICE_NAMES; 6757 struct hdac_widget *w, *cw; 6758 char buf[64]; 6759 int i, j; 6760 6761 device_printf(sc->dev, "\n"); 6762 device_printf(sc->dev, "Default Parameter\n"); 6763 device_printf(sc->dev, "-----------------\n"); 6764 hdac_dump_audio_formats(sc->dev, 6765 devinfo->function.audio.supp_stream_formats, 6766 devinfo->function.audio.supp_pcm_size_rate); 6767 device_printf(sc->dev, " IN amp: 0x%08x\n", 6768 devinfo->function.audio.inamp_cap); 6769 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6770 devinfo->function.audio.outamp_cap); 6771 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6772 w = hdac_widget_get(devinfo, i); 6773 if (w == NULL) { 6774 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6775 continue; 6776 } 6777 device_printf(sc->dev, "\n"); 6778 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6779 (w->enable == 0) ? " [DISABLED]" : ""); 6780 device_printf(sc->dev, " Name: %s\n", w->name); 6781 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6782 w->param.widget_cap); 6783 if (w->param.widget_cap & 0x0ee1) { 6784 device_printf(sc->dev, " "); 6785 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6786 printf(" LRSWAP"); 6787 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6788 printf(" PWR"); 6789 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6790 printf(" DIGITAL"); 6791 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6792 printf(" UNSOL"); 6793 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6794 printf(" PROC"); 6795 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6796 printf(" STRIPE"); 6797 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6798 printf(" STEREO"); 6799 printf("\n"); 6800 } 6801 if (w->bindas != -1) { 6802 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6803 w->bindas, w->bindseqmask); 6804 } 6805 if (w->ossmask != 0 || w->ossdev >= 0) { 6806 device_printf(sc->dev, " OSS: %s", 6807 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6808 if (w->ossdev >= 0) 6809 printf(" (%s)", ossname[w->ossdev]); 6810 printf("\n"); 6811 } 6812 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6813 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6814 hdac_dump_audio_formats(sc->dev, 6815 w->param.supp_stream_formats, 6816 w->param.supp_pcm_size_rate); 6817 } else if (w->type == 6818 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6819 hdac_dump_pin(sc, w); 6820 if (w->param.eapdbtl != HDAC_INVALID) 6821 device_printf(sc->dev, " EAPD: 0x%08x\n", 6822 w->param.eapdbtl); 6823 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6824 w->param.outamp_cap != 0) 6825 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6826 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6827 w->param.inamp_cap != 0) 6828 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6829 if (w->nconns > 0) { 6830 device_printf(sc->dev, " connections: %d\n", w->nconns); 6831 device_printf(sc->dev, " |\n"); 6832 } 6833 for (j = 0; j < w->nconns; j++) { 6834 cw = hdac_widget_get(devinfo, w->conns[j]); 6835 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6836 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6837 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6838 if (cw == NULL) 6839 printf(" [UNKNOWN]"); 6840 else if (cw->enable == 0) 6841 printf(" [DISABLED]"); 6842 if (w->nconns > 1 && w->selconn == j && w->type != 6843 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6844 printf(" (selected)"); 6845 printf("\n"); 6846 } 6847 } 6848 6849 } 6850 6851 static void 6852 hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6853 { 6854 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6855 struct hdac_widget *w, *cw; 6856 char buf[64]; 6857 int i, printed = 0; 6858 6859 if (depth > HDA_PARSE_MAXDEPTH) 6860 return; 6861 6862 w = hdac_widget_get(devinfo, nid); 6863 if (w == NULL || w->enable == 0) 6864 return; 6865 6866 if (depth == 0) 6867 device_printf(pdevinfo->dev, "%*s", 4, ""); 6868 else 6869 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6870 printf("nid=%d [%s]", w->nid, w->name); 6871 6872 if (depth > 0) { 6873 if (w->ossmask == 0) { 6874 printf("\n"); 6875 return; 6876 } 6877 printf(" [src: %s]", 6878 hdac_audio_ctl_ossmixer_mask2allname( 6879 w->ossmask, buf, sizeof(buf))); 6880 if (w->ossdev >= 0) { 6881 printf("\n"); 6882 return; 6883 } 6884 } 6885 printf("\n"); 6886 6887 for (i = 0; i < w->nconns; i++) { 6888 if (w->connsenable[i] == 0) 6889 continue; 6890 cw = hdac_widget_get(devinfo, w->conns[i]); 6891 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6892 continue; 6893 if (printed == 0) { 6894 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6895 printed = 1; 6896 } 6897 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6898 } 6899 6900 } 6901 6902 static void 6903 hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6904 { 6905 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6906 struct hdac_softc *sc = devinfo->codec->sc; 6907 struct hdac_widget *w; 6908 int i, printed = 0; 6909 6910 if (pdevinfo->play < 0) 6911 return; 6912 6913 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6914 w = hdac_widget_get(devinfo, i); 6915 if (w == NULL || w->enable == 0) 6916 continue; 6917 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6918 continue; 6919 if (w->bindas != sc->chans[pdevinfo->play].as) 6920 continue; 6921 if (printed == 0) { 6922 printed = 1; 6923 device_printf(pdevinfo->dev, "\n"); 6924 device_printf(pdevinfo->dev, "Playback:\n"); 6925 } 6926 device_printf(pdevinfo->dev, "\n"); 6927 hdac_dump_dst_nid(pdevinfo, i, 0); 6928 } 6929 } 6930 6931 static void 6932 hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6933 { 6934 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6935 struct hdac_softc *sc = devinfo->codec->sc; 6936 struct hdac_widget *w; 6937 int i; 6938 int printed = 0; 6939 6940 if (pdevinfo->rec < 0) 6941 return; 6942 6943 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6944 w = hdac_widget_get(devinfo, i); 6945 if (w == NULL || w->enable == 0) 6946 continue; 6947 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6948 continue; 6949 if (w->bindas != sc->chans[pdevinfo->rec].as) 6950 continue; 6951 if (printed == 0) { 6952 printed = 1; 6953 device_printf(pdevinfo->dev, "\n"); 6954 device_printf(pdevinfo->dev, "Record:\n"); 6955 } 6956 device_printf(pdevinfo->dev, "\n"); 6957 hdac_dump_dst_nid(pdevinfo, i, 0); 6958 } 6959 } 6960 6961 static void 6962 hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6963 { 6964 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6965 struct hdac_widget *w; 6966 int i; 6967 int printed = 0; 6968 6969 if (pdevinfo->index != 0) 6970 return; 6971 6972 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6973 w = hdac_widget_get(devinfo, i); 6974 if (w == NULL || w->enable == 0) 6975 continue; 6976 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6977 continue; 6978 if (printed == 0) { 6979 printed = 1; 6980 device_printf(pdevinfo->dev, "\n"); 6981 device_printf(pdevinfo->dev, "Input Mix:\n"); 6982 } 6983 device_printf(pdevinfo->dev, "\n"); 6984 hdac_dump_dst_nid(pdevinfo, i, 0); 6985 } 6986 } 6987 6988 static void 6989 hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6990 { 6991 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6992 nid_t *nids; 6993 int i; 6994 6995 if (pdevinfo->play >= 0) { 6996 i = pdevinfo->play; 6997 device_printf(pdevinfo->dev, "\n"); 6998 device_printf(pdevinfo->dev, "Playback:\n"); 6999 device_printf(pdevinfo->dev, "\n"); 7000 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7001 sc->chans[i].supp_pcm_size_rate); 7002 device_printf(pdevinfo->dev, " DAC:"); 7003 for (nids = sc->chans[i].io; *nids != -1; nids++) 7004 printf(" %d", *nids); 7005 printf("\n"); 7006 } 7007 if (pdevinfo->rec >= 0) { 7008 i = pdevinfo->rec; 7009 device_printf(pdevinfo->dev, "\n"); 7010 device_printf(pdevinfo->dev, "Record:\n"); 7011 device_printf(pdevinfo->dev, "\n"); 7012 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7013 sc->chans[i].supp_pcm_size_rate); 7014 device_printf(pdevinfo->dev, " ADC:"); 7015 for (nids = sc->chans[i].io; *nids != -1; nids++) 7016 printf(" %d", *nids); 7017 printf("\n"); 7018 } 7019 } 7020 7021 static void 7022 hdac_release_resources(struct hdac_softc *sc) 7023 { 7024 int i, j; 7025 7026 if (sc == NULL) 7027 return; 7028 7029 hdac_lock(sc); 7030 sc->polling = 0; 7031 sc->poll_ival = 0; 7032 callout_stop(&sc->poll_hda); 7033 callout_stop(&sc->poll_hdac); 7034 callout_stop(&sc->poll_jack); 7035 hdac_reset(sc, 0); 7036 hdac_unlock(sc); 7037 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7038 callout_drain(&sc->poll_hda); 7039 callout_drain(&sc->poll_hdac); 7040 callout_drain(&sc->poll_jack); 7041 7042 hdac_irq_free(sc); 7043 7044 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7045 if (sc->codecs[i] == NULL) 7046 continue; 7047 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7048 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7049 if (sc->codecs[i]->fgs[j].node_type == 7050 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7051 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7052 M_HDAC); 7053 free(sc->codecs[i]->fgs[j].function.audio.as, 7054 M_HDAC); 7055 free(sc->codecs[i]->fgs[j].function.audio.devs, 7056 M_HDAC); 7057 } 7058 } 7059 free(sc->codecs[i]->fgs, M_HDAC); 7060 free(sc->codecs[i], M_HDAC); 7061 sc->codecs[i] = NULL; 7062 } 7063 7064 hdac_dma_free(sc, &sc->pos_dma); 7065 hdac_dma_free(sc, &sc->rirb_dma); 7066 hdac_dma_free(sc, &sc->corb_dma); 7067 for (i = 0; i < sc->num_chans; i++) { 7068 if (sc->chans[i].blkcnt > 0) 7069 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7070 } 7071 free(sc->chans, M_HDAC); 7072 if (sc->chan_dmat != NULL) { 7073 bus_dma_tag_destroy(sc->chan_dmat); 7074 sc->chan_dmat = NULL; 7075 } 7076 hdac_mem_free(sc); 7077 snd_mtxfree(sc->lock); 7078 } 7079 7080 /* This function surely going to make its way into upper level someday. */ 7081 static void 7082 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7083 { 7084 const char *res = NULL; 7085 int i = 0, j, k, len, inv; 7086 7087 if (on != NULL) 7088 *on = 0; 7089 if (off != NULL) 7090 *off = 0; 7091 if (sc == NULL) 7092 return; 7093 if (resource_string_value(device_get_name(sc->dev), 7094 device_get_unit(sc->dev), "config", &res) != 0) 7095 return; 7096 if (!(res != NULL && strlen(res) > 0)) 7097 return; 7098 HDA_BOOTVERBOSE( 7099 device_printf(sc->dev, "HDA Config:"); 7100 ); 7101 for (;;) { 7102 while (res[i] != '\0' && 7103 (res[i] == ',' || isspace(res[i]) != 0)) 7104 i++; 7105 if (res[i] == '\0') { 7106 HDA_BOOTVERBOSE( 7107 printf("\n"); 7108 ); 7109 return; 7110 } 7111 j = i; 7112 while (res[j] != '\0' && 7113 !(res[j] == ',' || isspace(res[j]) != 0)) 7114 j++; 7115 len = j - i; 7116 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7117 inv = 2; 7118 else 7119 inv = 0; 7120 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7121 if (strncmp(res + i + inv, 7122 hdac_quirks_tab[k].key, len - inv) != 0) 7123 continue; 7124 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7125 continue; 7126 HDA_BOOTVERBOSE( 7127 printf(" %s%s", (inv != 0) ? "no" : "", 7128 hdac_quirks_tab[k].key); 7129 ); 7130 if (inv == 0 && on != NULL) 7131 *on |= hdac_quirks_tab[k].value; 7132 else if (inv != 0 && off != NULL) 7133 *off |= hdac_quirks_tab[k].value; 7134 break; 7135 } 7136 i = j; 7137 } 7138 } 7139 7140 #ifdef SND_DYNSYSCTL 7141 static int 7142 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7143 { 7144 struct hdac_softc *sc; 7145 device_t dev; 7146 uint32_t ctl; 7147 int err, val; 7148 7149 dev = oidp->oid_arg1; 7150 sc = device_get_softc(dev); 7151 if (sc == NULL) 7152 return (EINVAL); 7153 hdac_lock(sc); 7154 val = sc->polling; 7155 hdac_unlock(sc); 7156 err = sysctl_handle_int(oidp, &val, 0, req); 7157 7158 if (err != 0 || req->newptr == NULL) 7159 return (err); 7160 if (val < 0 || val > 1) 7161 return (EINVAL); 7162 7163 hdac_lock(sc); 7164 if (val != sc->polling) { 7165 if (val == 0) { 7166 callout_stop(&sc->poll_hda); 7167 callout_stop(&sc->poll_hdac); 7168 hdac_unlock(sc); 7169 callout_drain(&sc->poll_hda); 7170 callout_drain(&sc->poll_hdac); 7171 hdac_lock(sc); 7172 sc->polling = 0; 7173 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7174 ctl |= HDAC_INTCTL_GIE; 7175 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7176 } else { 7177 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7178 ctl &= ~HDAC_INTCTL_GIE; 7179 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7180 hdac_unlock(sc); 7181 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7182 hdac_lock(sc); 7183 sc->polling = 1; 7184 hdac_poll_reinit(sc); 7185 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7186 } 7187 } 7188 hdac_unlock(sc); 7189 7190 return (err); 7191 } 7192 7193 static int 7194 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7195 { 7196 struct hdac_softc *sc; 7197 device_t dev; 7198 int err, val; 7199 7200 dev = oidp->oid_arg1; 7201 sc = device_get_softc(dev); 7202 if (sc == NULL) 7203 return (EINVAL); 7204 hdac_lock(sc); 7205 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7206 hdac_unlock(sc); 7207 err = sysctl_handle_int(oidp, &val, 0, req); 7208 7209 if (err != 0 || req->newptr == NULL) 7210 return (err); 7211 7212 if (val < 1) 7213 val = 1; 7214 if (val > 5000) 7215 val = 5000; 7216 val = ((uint64_t)val * hz) / 1000; 7217 if (val < 1) 7218 val = 1; 7219 if (val > (hz * 5)) 7220 val = hz * 5; 7221 7222 hdac_lock(sc); 7223 sc->poll_ival = val; 7224 hdac_unlock(sc); 7225 7226 return (err); 7227 } 7228 7229 static int 7230 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7231 { 7232 struct hdac_softc *sc; 7233 struct hdac_codec *codec; 7234 struct hdac_devinfo *devinfo; 7235 struct hdac_widget *w; 7236 device_t dev; 7237 uint32_t res, pincap, delay; 7238 int codec_index, fg_index; 7239 int i, err, val; 7240 nid_t cad; 7241 7242 dev = oidp->oid_arg1; 7243 sc = device_get_softc(dev); 7244 if (sc == NULL) 7245 return (EINVAL); 7246 val = 0; 7247 err = sysctl_handle_int(oidp, &val, 0, req); 7248 if (err != 0 || req->newptr == NULL || val == 0) 7249 return (err); 7250 7251 /* XXX: Temporary. For debugging. */ 7252 if (val == 100) { 7253 hdac_suspend(dev); 7254 return (0); 7255 } else if (val == 101) { 7256 hdac_resume(dev); 7257 return (0); 7258 } 7259 7260 hdac_lock(sc); 7261 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7262 codec = sc->codecs[codec_index]; 7263 if (codec == NULL) 7264 continue; 7265 cad = codec->cad; 7266 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7267 devinfo = &codec->fgs[fg_index]; 7268 if (devinfo->node_type != 7269 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7270 continue; 7271 7272 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7273 codec_index, devinfo->nid); 7274 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7275 w = hdac_widget_get(devinfo, i); 7276 if (w == NULL || w->type != 7277 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7278 continue; 7279 hdac_dump_pin_config(w, w->wclass.pin.config); 7280 pincap = w->wclass.pin.cap; 7281 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7282 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7283 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7284 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7285 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7286 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7287 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7288 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7289 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7290 delay = 0; 7291 hdac_command(sc, 7292 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7293 do { 7294 res = hdac_command(sc, 7295 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7296 if (res != 0x7fffffff && res != 0xffffffff) 7297 break; 7298 DELAY(10); 7299 } while (++delay < 10000); 7300 } else { 7301 delay = 0; 7302 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7303 w->nid), cad); 7304 } 7305 printf(" Sense: 0x%08x", res); 7306 if (delay > 0) 7307 printf(" delay %dus", delay * 10); 7308 } 7309 printf("\n"); 7310 } 7311 device_printf(dev, 7312 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7313 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7314 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7315 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7316 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7317 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7318 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7319 device_printf(dev, " GPI:"); 7320 res = hdac_command(sc, 7321 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7322 printf(" data=0x%08x", res); 7323 res = hdac_command(sc, 7324 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7325 cad); 7326 printf(" wake=0x%08x", res); 7327 res = hdac_command(sc, 7328 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7329 cad); 7330 printf(" unsol=0x%08x", res); 7331 res = hdac_command(sc, 7332 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7333 printf(" sticky=0x%08x\n", res); 7334 } 7335 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7336 device_printf(dev, " GPO:"); 7337 res = hdac_command(sc, 7338 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7339 printf(" data=0x%08x\n", res); 7340 } 7341 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7342 device_printf(dev, "GPIO:"); 7343 res = hdac_command(sc, 7344 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7345 printf(" data=0x%08x", res); 7346 res = hdac_command(sc, 7347 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7348 printf(" enable=0x%08x", res); 7349 res = hdac_command(sc, 7350 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7351 printf(" direction=0x%08x\n", res); 7352 res = hdac_command(sc, 7353 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7354 device_printf(dev, " wake=0x%08x", res); 7355 res = hdac_command(sc, 7356 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7357 cad); 7358 printf(" unsol=0x%08x", res); 7359 res = hdac_command(sc, 7360 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7361 printf(" sticky=0x%08x\n", res); 7362 } 7363 } 7364 } 7365 hdac_unlock(sc); 7366 return (0); 7367 } 7368 #endif 7369 7370 static void 7371 hdac_attach2(void *arg) 7372 { 7373 struct hdac_codec *codec; 7374 struct hdac_softc *sc; 7375 struct hdac_audio_ctl *ctl; 7376 uint32_t quirks_on, quirks_off; 7377 int codec_index, fg_index; 7378 int i, dmaalloc = 0; 7379 struct hdac_devinfo *devinfo; 7380 7381 sc = (struct hdac_softc *)arg; 7382 7383 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7384 7385 HDA_BOOTHVERBOSE( 7386 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7387 quirks_on, quirks_off); 7388 ); 7389 7390 hdac_lock(sc); 7391 7392 /* Remove ourselves from the config hooks */ 7393 if (sc->intrhook.ich_func != NULL) { 7394 config_intrhook_disestablish(&sc->intrhook); 7395 sc->intrhook.ich_func = NULL; 7396 } 7397 7398 /* Start the corb and rirb engines */ 7399 HDA_BOOTHVERBOSE( 7400 device_printf(sc->dev, "Starting CORB Engine...\n"); 7401 ); 7402 hdac_corb_start(sc); 7403 HDA_BOOTHVERBOSE( 7404 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7405 ); 7406 hdac_rirb_start(sc); 7407 7408 HDA_BOOTHVERBOSE( 7409 device_printf(sc->dev, 7410 "Enabling controller interrupt...\n"); 7411 ); 7412 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7413 HDAC_GCTL_UNSOL); 7414 if (sc->polling == 0) { 7415 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7416 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7417 } else { 7418 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7419 } 7420 DELAY(1000); 7421 7422 HDA_BOOTHVERBOSE( 7423 device_printf(sc->dev, 7424 "Scanning HDA codecs ...\n"); 7425 ); 7426 hdac_scan_codecs(sc); 7427 7428 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7429 codec = sc->codecs[codec_index]; 7430 if (codec == NULL) 7431 continue; 7432 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7433 devinfo = &codec->fgs[fg_index]; 7434 HDA_BOOTVERBOSE( 7435 device_printf(sc->dev, "\n"); 7436 device_printf(sc->dev, 7437 "Processing %s FG cad=%d nid=%d...\n", 7438 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7439 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7440 "unknown", 7441 devinfo->codec->cad, devinfo->nid); 7442 ); 7443 if (devinfo->node_type != 7444 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7445 HDA_BOOTHVERBOSE( 7446 device_printf(sc->dev, 7447 "Powering down...\n"); 7448 ); 7449 hdac_command(sc, 7450 HDA_CMD_SET_POWER_STATE(codec->cad, 7451 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7452 codec->cad); 7453 continue; 7454 } 7455 7456 HDA_BOOTHVERBOSE( 7457 device_printf(sc->dev, "Powering up...\n"); 7458 ); 7459 hdac_powerup(devinfo); 7460 HDA_BOOTHVERBOSE( 7461 device_printf(sc->dev, "Parsing audio FG...\n"); 7462 ); 7463 hdac_audio_parse(devinfo); 7464 HDA_BOOTHVERBOSE( 7465 device_printf(sc->dev, "Parsing Ctls...\n"); 7466 ); 7467 hdac_audio_ctl_parse(devinfo); 7468 HDA_BOOTHVERBOSE( 7469 device_printf(sc->dev, "Parsing vendor patch...\n"); 7470 ); 7471 hdac_vendor_patch_parse(devinfo); 7472 devinfo->function.audio.quirks |= quirks_on; 7473 devinfo->function.audio.quirks &= ~quirks_off; 7474 7475 HDA_BOOTHVERBOSE( 7476 device_printf(sc->dev, "Disabling nonaudio...\n"); 7477 ); 7478 hdac_audio_disable_nonaudio(devinfo); 7479 HDA_BOOTHVERBOSE( 7480 device_printf(sc->dev, "Disabling useless...\n"); 7481 ); 7482 hdac_audio_disable_useless(devinfo); 7483 HDA_BOOTVERBOSE( 7484 device_printf(sc->dev, "Patched pins configuration:\n"); 7485 hdac_dump_pin_configs(devinfo); 7486 ); 7487 HDA_BOOTHVERBOSE( 7488 device_printf(sc->dev, "Parsing pin associations...\n"); 7489 ); 7490 hdac_audio_as_parse(devinfo); 7491 HDA_BOOTHVERBOSE( 7492 device_printf(sc->dev, "Building AFG tree...\n"); 7493 ); 7494 hdac_audio_build_tree(devinfo); 7495 HDA_BOOTHVERBOSE( 7496 device_printf(sc->dev, "Disabling unassociated " 7497 "widgets...\n"); 7498 ); 7499 hdac_audio_disable_unas(devinfo); 7500 HDA_BOOTHVERBOSE( 7501 device_printf(sc->dev, "Disabling nonselected " 7502 "inputs...\n"); 7503 ); 7504 hdac_audio_disable_notselected(devinfo); 7505 HDA_BOOTHVERBOSE( 7506 device_printf(sc->dev, "Disabling useless...\n"); 7507 ); 7508 hdac_audio_disable_useless(devinfo); 7509 HDA_BOOTHVERBOSE( 7510 device_printf(sc->dev, "Disabling " 7511 "crossassociatement connections...\n"); 7512 ); 7513 hdac_audio_disable_crossas(devinfo); 7514 HDA_BOOTHVERBOSE( 7515 device_printf(sc->dev, "Disabling useless...\n"); 7516 ); 7517 hdac_audio_disable_useless(devinfo); 7518 HDA_BOOTHVERBOSE( 7519 device_printf(sc->dev, "Binding associations to channels...\n"); 7520 ); 7521 hdac_audio_bind_as(devinfo); 7522 HDA_BOOTHVERBOSE( 7523 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7524 ); 7525 hdac_audio_assign_names(devinfo); 7526 HDA_BOOTHVERBOSE( 7527 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7528 ); 7529 hdac_audio_assign_mixers(devinfo); 7530 HDA_BOOTHVERBOSE( 7531 device_printf(sc->dev, "Preparing pin controls...\n"); 7532 ); 7533 hdac_audio_prepare_pin_ctrl(devinfo); 7534 HDA_BOOTHVERBOSE( 7535 device_printf(sc->dev, "AFG commit...\n"); 7536 ); 7537 hdac_audio_commit(devinfo); 7538 HDA_BOOTHVERBOSE( 7539 device_printf(sc->dev, "HP switch init...\n"); 7540 ); 7541 hdac_hp_switch_init(devinfo); 7542 7543 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7544 dmaalloc == 0) { 7545 if (hdac_dma_alloc(sc, &sc->pos_dma, 7546 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7547 HDA_BOOTVERBOSE( 7548 device_printf(sc->dev, "Failed to " 7549 "allocate DMA pos buffer " 7550 "(non-fatal)\n"); 7551 ); 7552 } else 7553 dmaalloc = 1; 7554 } 7555 7556 HDA_BOOTHVERBOSE( 7557 device_printf(sc->dev, "Creating PCM devices...\n"); 7558 ); 7559 hdac_create_pcms(devinfo); 7560 7561 HDA_BOOTVERBOSE( 7562 if (devinfo->function.audio.quirks != 0) { 7563 device_printf(sc->dev, "FG config/quirks:"); 7564 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7565 if ((devinfo->function.audio.quirks & 7566 hdac_quirks_tab[i].value) == 7567 hdac_quirks_tab[i].value) 7568 printf(" %s", hdac_quirks_tab[i].key); 7569 } 7570 printf("\n"); 7571 } 7572 7573 device_printf(sc->dev, "\n"); 7574 device_printf(sc->dev, "+-------------------+\n"); 7575 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7576 device_printf(sc->dev, "+-------------------+\n"); 7577 hdac_dump_nodes(devinfo); 7578 ); 7579 7580 HDA_BOOTHVERBOSE( 7581 device_printf(sc->dev, "\n"); 7582 device_printf(sc->dev, "+------------------------+\n"); 7583 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7584 device_printf(sc->dev, "+------------------------+\n"); 7585 device_printf(sc->dev, "\n"); 7586 i = 0; 7587 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7588 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7589 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7590 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7591 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7592 ctl->index); 7593 if (ctl->childwidget != NULL) 7594 printf(" cnid %3d", ctl->childwidget->nid); 7595 else 7596 printf(" "); 7597 printf(" ossmask=0x%08x\n", 7598 ctl->ossmask); 7599 device_printf(sc->dev, 7600 " mute: %d step: %3d size: %3d off: %3d%s\n", 7601 ctl->mute, ctl->step, ctl->size, ctl->offset, 7602 (ctl->enable == 0) ? " [DISABLED]" : 7603 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7604 } 7605 ); 7606 } 7607 } 7608 hdac_unlock(sc); 7609 7610 HDA_BOOTVERBOSE( 7611 device_printf(sc->dev, "\n"); 7612 ); 7613 7614 bus_generic_attach(sc->dev); 7615 7616 #ifdef SND_DYNSYSCTL 7617 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7618 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7619 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7620 sysctl_hdac_polling, "I", "Enable polling mode"); 7621 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7622 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7623 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7624 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7625 "Controller/Jack Sense polling interval (1-1000 ms)"); 7626 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7627 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7628 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7629 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7630 #endif 7631 } 7632 7633 /**************************************************************************** 7634 * int hdac_suspend(device_t) 7635 * 7636 * Suspend and power down HDA bus and codecs. 7637 ****************************************************************************/ 7638 static int 7639 hdac_suspend(device_t dev) 7640 { 7641 struct hdac_softc *sc; 7642 struct hdac_codec *codec; 7643 struct hdac_devinfo *devinfo; 7644 int codec_index, fg_index, i; 7645 7646 HDA_BOOTHVERBOSE( 7647 device_printf(dev, "Suspend...\n"); 7648 ); 7649 7650 sc = device_get_softc(dev); 7651 hdac_lock(sc); 7652 7653 HDA_BOOTHVERBOSE( 7654 device_printf(dev, "Stop streams...\n"); 7655 ); 7656 for (i = 0; i < sc->num_chans; i++) { 7657 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7658 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7659 hdac_channel_stop(sc, &sc->chans[i]); 7660 } 7661 } 7662 7663 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7664 codec = sc->codecs[codec_index]; 7665 if (codec == NULL) 7666 continue; 7667 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7668 devinfo = &codec->fgs[fg_index]; 7669 HDA_BOOTHVERBOSE( 7670 device_printf(dev, 7671 "Power down FG" 7672 " cad=%d nid=%d to the D3 state...\n", 7673 codec->cad, devinfo->nid); 7674 ); 7675 hdac_command(sc, 7676 HDA_CMD_SET_POWER_STATE(codec->cad, 7677 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7678 codec->cad); 7679 } 7680 } 7681 7682 HDA_BOOTHVERBOSE( 7683 device_printf(dev, "Reset controller...\n"); 7684 ); 7685 callout_stop(&sc->poll_hda); 7686 callout_stop(&sc->poll_hdac); 7687 callout_stop(&sc->poll_jack); 7688 hdac_reset(sc, 0); 7689 hdac_unlock(sc); 7690 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7691 callout_drain(&sc->poll_hda); 7692 callout_drain(&sc->poll_hdac); 7693 callout_drain(&sc->poll_jack); 7694 7695 HDA_BOOTHVERBOSE( 7696 device_printf(dev, "Suspend done\n"); 7697 ); 7698 7699 return (0); 7700 } 7701 7702 /**************************************************************************** 7703 * int hdac_resume(device_t) 7704 * 7705 * Powerup and restore HDA bus and codecs state. 7706 ****************************************************************************/ 7707 static int 7708 hdac_resume(device_t dev) 7709 { 7710 struct hdac_softc *sc; 7711 struct hdac_codec *codec; 7712 struct hdac_devinfo *devinfo; 7713 int codec_index, fg_index, i; 7714 7715 HDA_BOOTHVERBOSE( 7716 device_printf(dev, "Resume...\n"); 7717 ); 7718 7719 sc = device_get_softc(dev); 7720 hdac_lock(sc); 7721 7722 /* Quiesce everything */ 7723 HDA_BOOTHVERBOSE( 7724 device_printf(dev, "Reset controller...\n"); 7725 ); 7726 hdac_reset(sc, 1); 7727 7728 /* Initialize the CORB and RIRB */ 7729 hdac_corb_init(sc); 7730 hdac_rirb_init(sc); 7731 7732 /* Start the corb and rirb engines */ 7733 HDA_BOOTHVERBOSE( 7734 device_printf(dev, "Starting CORB Engine...\n"); 7735 ); 7736 hdac_corb_start(sc); 7737 HDA_BOOTHVERBOSE( 7738 device_printf(dev, "Starting RIRB Engine...\n"); 7739 ); 7740 hdac_rirb_start(sc); 7741 7742 HDA_BOOTHVERBOSE( 7743 device_printf(dev, 7744 "Enabling controller interrupt...\n"); 7745 ); 7746 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7747 HDAC_GCTL_UNSOL); 7748 if (sc->polling == 0) { 7749 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7750 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7751 } else { 7752 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7753 } 7754 DELAY(1000); 7755 7756 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7757 codec = sc->codecs[codec_index]; 7758 if (codec == NULL) 7759 continue; 7760 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7761 devinfo = &codec->fgs[fg_index]; 7762 if (devinfo->node_type != 7763 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7764 HDA_BOOTHVERBOSE( 7765 device_printf(dev, 7766 "Power down unsupported non-audio FG" 7767 " cad=%d nid=%d to the D3 state...\n", 7768 codec->cad, devinfo->nid); 7769 ); 7770 hdac_command(sc, 7771 HDA_CMD_SET_POWER_STATE(codec->cad, 7772 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7773 codec->cad); 7774 continue; 7775 } 7776 7777 HDA_BOOTHVERBOSE( 7778 device_printf(dev, 7779 "Power up audio FG cad=%d nid=%d...\n", 7780 devinfo->codec->cad, devinfo->nid); 7781 ); 7782 hdac_powerup(devinfo); 7783 HDA_BOOTHVERBOSE( 7784 device_printf(dev, "AFG commit...\n"); 7785 ); 7786 hdac_audio_commit(devinfo); 7787 HDA_BOOTHVERBOSE( 7788 device_printf(dev, "HP switch init...\n"); 7789 ); 7790 hdac_hp_switch_init(devinfo); 7791 7792 hdac_unlock(sc); 7793 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7794 struct hdac_pcm_devinfo *pdevinfo = 7795 &devinfo->function.audio.devs[i]; 7796 HDA_BOOTHVERBOSE( 7797 device_printf(pdevinfo->dev, 7798 "OSS mixer reinitialization...\n"); 7799 ); 7800 if (mixer_reinit(pdevinfo->dev) == -1) 7801 device_printf(pdevinfo->dev, 7802 "unable to reinitialize the mixer\n"); 7803 } 7804 hdac_lock(sc); 7805 } 7806 } 7807 7808 HDA_BOOTHVERBOSE( 7809 device_printf(dev, "Start streams...\n"); 7810 ); 7811 for (i = 0; i < sc->num_chans; i++) { 7812 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7813 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7814 hdac_channel_start(sc, &sc->chans[i]); 7815 } 7816 } 7817 7818 hdac_unlock(sc); 7819 7820 HDA_BOOTHVERBOSE( 7821 device_printf(dev, "Resume done\n"); 7822 ); 7823 7824 return (0); 7825 } 7826 /**************************************************************************** 7827 * int hdac_detach(device_t) 7828 * 7829 * Detach and free up resources utilized by the hdac device. 7830 ****************************************************************************/ 7831 static int 7832 hdac_detach(device_t dev) 7833 { 7834 struct hdac_softc *sc; 7835 device_t *devlist; 7836 int i, devcount, error; 7837 7838 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7839 return (error); 7840 for (i = 0; i < devcount; i++) { 7841 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7842 free(devlist, M_TEMP); 7843 return (error); 7844 } 7845 } 7846 free(devlist, M_TEMP); 7847 7848 sc = device_get_softc(dev); 7849 hdac_release_resources(sc); 7850 7851 return (0); 7852 } 7853 7854 static int 7855 hdac_print_child(device_t dev, device_t child) 7856 { 7857 struct hdac_pcm_devinfo *pdevinfo = 7858 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7859 int retval; 7860 7861 retval = bus_print_child_header(dev, child); 7862 retval += printf(" at cad %d nid %d", 7863 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7864 retval += bus_print_child_footer(dev, child); 7865 7866 return (retval); 7867 } 7868 7869 static device_method_t hdac_methods[] = { 7870 /* device interface */ 7871 DEVMETHOD(device_probe, hdac_probe), 7872 DEVMETHOD(device_attach, hdac_attach), 7873 DEVMETHOD(device_detach, hdac_detach), 7874 DEVMETHOD(device_suspend, hdac_suspend), 7875 DEVMETHOD(device_resume, hdac_resume), 7876 /* Bus interface */ 7877 DEVMETHOD(bus_print_child, hdac_print_child), 7878 { 0, 0 } 7879 }; 7880 7881 static driver_t hdac_driver = { 7882 "hdac", 7883 hdac_methods, 7884 sizeof(struct hdac_softc), 7885 }; 7886 7887 static devclass_t hdac_devclass; 7888 7889 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7890 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7891 MODULE_VERSION(snd_hda, 1); 7892 7893 static int 7894 hdac_pcm_probe(device_t dev) 7895 { 7896 struct hdac_pcm_devinfo *pdevinfo = 7897 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7898 char buf[128]; 7899 7900 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7901 hdac_codec_name(pdevinfo->devinfo->codec), 7902 pdevinfo->index, 7903 pdevinfo->digital?"Digital":"Analog"); 7904 device_set_desc_copy(dev, buf); 7905 return (0); 7906 } 7907 7908 static int 7909 hdac_pcm_attach(device_t dev) 7910 { 7911 struct hdac_pcm_devinfo *pdevinfo = 7912 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7913 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7914 char status[SND_STATUSLEN]; 7915 int i; 7916 7917 pdevinfo->chan_size = pcm_getbuffersize(dev, 7918 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7919 7920 HDA_BOOTVERBOSE( 7921 device_printf(dev, "+--------------------------------------+\n"); 7922 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7923 device_printf(dev, "+--------------------------------------+\n"); 7924 hdac_dump_pcmchannels(pdevinfo); 7925 device_printf(dev, "\n"); 7926 device_printf(dev, "+--------------------------------+\n"); 7927 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7928 device_printf(dev, "+--------------------------------+\n"); 7929 hdac_dump_dac(pdevinfo); 7930 hdac_dump_adc(pdevinfo); 7931 hdac_dump_mix(pdevinfo); 7932 device_printf(dev, "\n"); 7933 device_printf(dev, "+-------------------------+\n"); 7934 device_printf(dev, "| DUMPING Volume Controls |\n"); 7935 device_printf(dev, "+-------------------------+\n"); 7936 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7937 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7938 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7939 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7940 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7941 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7942 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7943 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7944 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7945 hdac_dump_ctls(pdevinfo, NULL, 0); 7946 device_printf(dev, "\n"); 7947 ); 7948 7949 if (resource_int_value(device_get_name(dev), 7950 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7951 i &= HDA_BLK_ALIGN; 7952 if (i < HDA_BLK_MIN) 7953 i = HDA_BLK_MIN; 7954 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7955 i = 0; 7956 while (pdevinfo->chan_blkcnt >> i) 7957 i++; 7958 pdevinfo->chan_blkcnt = 1 << (i - 1); 7959 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7960 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7961 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7962 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7963 } else 7964 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7965 7966 /* 7967 * We don't register interrupt handler with snd_setup_intr 7968 * in pcm device. Mark pcm device as MPSAFE manually. 7969 */ 7970 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7971 7972 HDA_BOOTHVERBOSE( 7973 device_printf(dev, "OSS mixer initialization...\n"); 7974 ); 7975 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7976 device_printf(dev, "Can't register mixer\n"); 7977 7978 HDA_BOOTHVERBOSE( 7979 device_printf(dev, "Registering PCM channels...\n"); 7980 ); 7981 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7982 (pdevinfo->rec >= 0)?1:0) != 0) 7983 device_printf(dev, "Can't register PCM\n"); 7984 7985 pdevinfo->registered++; 7986 7987 if (pdevinfo->play >= 0) 7988 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7989 if (pdevinfo->rec >= 0) 7990 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7991 7992 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7993 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7994 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7995 pcm_setstatus(dev, status); 7996 7997 return (0); 7998 } 7999 8000 static int 8001 hdac_pcm_detach(device_t dev) 8002 { 8003 struct hdac_pcm_devinfo *pdevinfo = 8004 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8005 int err; 8006 8007 if (pdevinfo->registered > 0) { 8008 err = pcm_unregister(dev); 8009 if (err != 0) 8010 return (err); 8011 } 8012 8013 return (0); 8014 } 8015 8016 static device_method_t hdac_pcm_methods[] = { 8017 /* device interface */ 8018 DEVMETHOD(device_probe, hdac_pcm_probe), 8019 DEVMETHOD(device_attach, hdac_pcm_attach), 8020 DEVMETHOD(device_detach, hdac_pcm_detach), 8021 { 0, 0 } 8022 }; 8023 8024 static driver_t hdac_pcm_driver = { 8025 "pcm", 8026 hdac_pcm_methods, 8027 PCM_SOFTC_SIZE, 8028 }; 8029 8030 DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8031 8032