1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70 #include <sys/ctype.h> 71 72 #include <dev/sound/pcm/sound.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 76 #include <dev/sound/pci/hda/hdac_private.h> 77 #include <dev/sound/pci/hda/hdac_reg.h> 78 #include <dev/sound/pci/hda/hda_reg.h> 79 #include <dev/sound/pci/hda/hdac.h> 80 81 #include "mixer_if.h" 82 83 #define HDA_DRV_TEST_REV "20070225_0040" 84 #define HDA_WIDGET_PARSER_REV 1 85 86 SND_DECLARE_FILE("$FreeBSD$"); 87 88 #undef HDA_DEBUG_ENABLED 89 #define HDA_DEBUG_ENABLED 1 90 91 #ifdef HDA_DEBUG_ENABLED 92 #define HDA_DEBUG(stmt) do { \ 93 stmt \ 94 } while(0) 95 #else 96 #define HDA_DEBUG(stmt) 97 #endif 98 99 #define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103 } while(0) 104 105 #if 1 106 #undef HDAC_INTR_EXTRA 107 #define HDAC_INTR_EXTRA 1 108 #endif 109 110 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 111 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122 #define HDA_MATCH_ALL 0xffffffff 123 #define HDAC_INVALID 0xffffffff 124 125 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128 /* Controller models */ 129 130 /* Intel */ 131 #define INTEL_VENDORID 0x8086 132 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138 /* Nvidia */ 139 #define NVIDIA_VENDORID 0x10de 140 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142 #define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143 #define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144 #define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145 #define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148 /* ATI */ 149 #define ATI_VENDORID 0x1002 150 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154 /* VIA */ 155 #define VIA_VENDORID 0x1106 156 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159 /* SiS */ 160 #define SIS_VENDORID 0x1039 161 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164 /* OEM/subvendors */ 165 166 /* Intel */ 167 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 168 169 /* HP/Compaq */ 170 #define HP_VENDORID 0x103c 171 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 172 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 173 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 174 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 175 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 176 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 177 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 178 #define HP_NX6325_SUBVENDORX 0x103c30b0 179 180 /* Dell */ 181 #define DELL_VENDORID 0x1028 182 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 183 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 184 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 185 186 /* Clevo */ 187 #define CLEVO_VENDORID 0x1558 188 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 189 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 190 191 /* Acer */ 192 #define ACER_VENDORID 0x1025 193 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 194 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 195 196 /* Asus */ 197 #define ASUS_VENDORID 0x1043 198 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 199 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 200 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 201 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 202 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 203 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 204 205 /* IBM / Lenovo */ 206 #define IBM_VENDORID 0x1014 207 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 208 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 209 210 /* Lenovo */ 211 #define LENOVO_VENDORID 0x17aa 212 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 213 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 214 215 /* Samsung */ 216 #define SAMSUNG_VENDORID 0x144d 217 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 218 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 219 220 /* Medion ? */ 221 #define MEDION_VENDORID 0x161f 222 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 223 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 224 225 /* 226 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 227 * instead of their own, which is beyond my comprehension 228 * (see HDA_CODEC_STAC9221 below). 229 */ 230 #define APPLE_INTEL_MAC 0x76808384 231 232 /* LG Electronics */ 233 #define LG_VENDORID 0x1854 234 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 235 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 236 237 /* Fujitsu Siemens */ 238 #define FS_VENDORID 0x1734 239 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 240 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 241 242 /* Toshiba */ 243 #define TOSHIBA_VENDORID 0x1179 244 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 245 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 246 247 /* Micro-Star International (MSI) */ 248 #define MSI_VENDORID 0x1462 249 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 250 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 251 252 /* Misc constants.. */ 253 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 254 #define HDA_AMP_MUTE_NONE (0) 255 #define HDA_AMP_MUTE_LEFT (1 << 0) 256 #define HDA_AMP_MUTE_RIGHT (1 << 1) 257 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 258 259 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 260 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 261 262 #define HDA_DAC_PATH (1 << 0) 263 #define HDA_ADC_PATH (1 << 1) 264 #define HDA_ADC_RECSEL (1 << 2) 265 266 #define HDA_CTL_OUT (1 << 0) 267 #define HDA_CTL_IN (1 << 1) 268 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 269 270 #define HDA_GPIO_MAX 15 271 /* 0 - 14 = GPIO */ 272 #define HDA_QUIRK_GPIO0 (1 << 0) 273 #define HDA_QUIRK_GPIO1 (1 << 1) 274 #define HDA_QUIRK_GPIO2 (1 << 2) 275 #define HDA_QUIRK_GPIOFLUSH (1 << 15) 276 #define HDA_QUIRK_SOFTPCMVOL (1 << 16) 277 #define HDA_QUIRK_FIXEDRATE (1 << 17) 278 #define HDA_QUIRK_FORCESTEREO (1 << 18) 279 #define HDA_QUIRK_EAPDINV (1 << 19) 280 #define HDA_QUIRK_VREF (1 << 20) 281 282 static const struct { 283 char *key; 284 uint32_t value; 285 } hdac_quirks_tab[] = { 286 { "gpio0", HDA_QUIRK_GPIO0 }, 287 { "gpio1", HDA_QUIRK_GPIO1 }, 288 { "gpio2", HDA_QUIRK_GPIO2 }, 289 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 290 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 291 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 292 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 293 { "eapdinv", HDA_QUIRK_EAPDINV }, 294 { "vref", HDA_QUIRK_VREF }, 295 }; 296 #define HDAC_QUIRKS_TAB_LEN \ 297 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 298 299 #define HDA_BDL_MIN 2 300 #define HDA_BDL_MAX 256 301 #define HDA_BDL_DEFAULT HDA_BDL_MIN 302 303 #define HDA_BUFSZ_MIN 4096 304 #define HDA_BUFSZ_MAX 65536 305 #define HDA_BUFSZ_DEFAULT 16384 306 307 #define HDA_PARSE_MAXDEPTH 10 308 309 #define HDAC_UNSOLTAG_EVENT_HP 0x00 310 311 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 312 313 enum { 314 HDA_PARSE_MIXER, 315 HDA_PARSE_DIRECT 316 }; 317 318 /* Default */ 319 static uint32_t hdac_fmt[] = { 320 AFMT_STEREO | AFMT_S16_LE, 321 0 322 }; 323 324 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 325 326 static const struct { 327 uint32_t model; 328 char *desc; 329 } hdac_devices[] = { 330 { HDA_INTEL_82801F, "Intel 82801F" }, 331 { HDA_INTEL_82801G, "Intel 82801G" }, 332 { HDA_INTEL_82801H, "Intel 82801H" }, 333 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 334 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 335 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 336 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 337 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 338 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 339 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 340 { HDA_ATI_SB450, "ATI SB450" }, 341 { HDA_ATI_SB600, "ATI SB600" }, 342 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 343 { HDA_SIS_966, "SiS 966" }, 344 /* Unknown */ 345 { HDA_INTEL_ALL, "Intel (Unknown)" }, 346 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 347 { HDA_ATI_ALL, "ATI (Unknown)" }, 348 { HDA_VIA_ALL, "VIA (Unknown)" }, 349 { HDA_SIS_ALL, "SiS (Unknown)" }, 350 }; 351 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 352 353 static const struct { 354 uint32_t rate; 355 int valid; 356 uint16_t base; 357 uint16_t mul; 358 uint16_t div; 359 } hda_rate_tab[] = { 360 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 361 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 362 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 363 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 364 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 365 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 366 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 367 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 368 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 369 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 370 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 371 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 372 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 373 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 374 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 375 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 376 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 377 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 378 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 379 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 380 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 381 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 382 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 383 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 384 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 385 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 386 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 387 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 388 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 389 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 390 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 391 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 392 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 393 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 394 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 395 }; 396 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 397 398 /* All codecs you can eat... */ 399 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 400 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 401 402 /* Realtek */ 403 #define REALTEK_VENDORID 0x10ec 404 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 405 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 406 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 407 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 408 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 409 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 410 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 411 412 /* Analog Device */ 413 #define ANALOGDEVICE_VENDORID 0x11d4 414 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 415 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 416 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 417 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 418 419 /* CMedia */ 420 #define CMEDIA_VENDORID 0x434d 421 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 422 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 423 424 /* Sigmatel */ 425 #define SIGMATEL_VENDORID 0x8384 426 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 427 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 428 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 429 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 430 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 431 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 432 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 433 434 /* 435 * Conexant 436 * 437 * Ok, the truth is, I don't have any idea at all whether 438 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 439 * place that tell me it is "Venice" is from its Windows driver INF. 440 * 441 * Venice - CX????? 442 * Waikiki - CX20551-22 443 */ 444 #define CONEXANT_VENDORID 0x14f1 445 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 446 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 447 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 448 449 450 /* Codecs */ 451 static const struct { 452 uint32_t id; 453 char *name; 454 } hdac_codecs[] = { 455 { HDA_CODEC_ALC260, "Realtek ALC260" }, 456 { HDA_CODEC_ALC861, "Realtek ALC861" }, 457 { HDA_CODEC_ALC880, "Realtek ALC880" }, 458 { HDA_CODEC_ALC882, "Realtek ALC882" }, 459 { HDA_CODEC_ALC883, "Realtek ALC883" }, 460 { HDA_CODEC_ALC888, "Realtek ALC888" }, 461 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 462 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 463 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 464 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 465 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 466 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 467 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 468 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 469 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 470 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 471 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 472 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 473 /* Unknown codec */ 474 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 475 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 476 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 477 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 478 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 479 }; 480 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 481 482 enum { 483 HDAC_HP_SWITCH_CTL, 484 HDAC_HP_SWITCH_CTRL 485 }; 486 487 static const struct { 488 uint32_t model; 489 uint32_t id; 490 int type; 491 int inverted; 492 nid_t hpnid; 493 nid_t spkrnid[8]; 494 nid_t eapdnid; 495 } hdac_hp_switch[] = { 496 /* Specific OEM models */ 497 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 498 17, { 16, -1 }, 16 }, 499 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 500 6, { 5, -1 }, 5 }, 501 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 502 6, { 5, -1 }, 5 }, 503 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 504 6, { 5, -1 }, 5 }, 505 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 506 6, { 5, -1 }, -1 }, 507 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 508 13, { 14, -1 }, -1 }, 509 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 510 13, { 14, -1 }, -1 }, 511 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 512 10, { 13, -1 }, -1 }, 513 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 514 26, { 27, -1 }, -1 }, 515 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 516 27, { 20, -1 }, -1 }, 517 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 518 20, { 21, -1 }, -1 }, 519 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 520 20, { 27, -1 }, -1 }, 521 /* 522 * All models that at least come from the same vendor with 523 * simmilar codec. 524 */ 525 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 526 17, { 16, -1 }, 16 }, 527 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 528 6, { 5, -1 }, 5 }, 529 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 530 6, { 5, -1 }, -1 }, 531 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 532 13, { 14, -1 }, -1 }, 533 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 534 26, { 27, -1 }, -1 }, 535 #if 0 536 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 537 20, { 21, -1 }, -1 }, 538 #endif 539 }; 540 #define HDAC_HP_SWITCH_LEN \ 541 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 542 543 static const struct { 544 uint32_t model; 545 uint32_t id; 546 nid_t eapdnid; 547 int hp_switch; 548 } hdac_eapd_switch[] = { 549 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 550 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 551 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 552 }; 553 #define HDAC_EAPD_SWITCH_LEN \ 554 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 555 556 /**************************************************************************** 557 * Function prototypes 558 ****************************************************************************/ 559 static void hdac_intr_handler(void *); 560 static int hdac_reset(struct hdac_softc *); 561 static int hdac_get_capabilities(struct hdac_softc *); 562 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 563 static int hdac_dma_alloc(struct hdac_softc *, 564 struct hdac_dma *, bus_size_t); 565 static void hdac_dma_free(struct hdac_dma *); 566 static int hdac_mem_alloc(struct hdac_softc *); 567 static void hdac_mem_free(struct hdac_softc *); 568 static int hdac_irq_alloc(struct hdac_softc *); 569 static void hdac_irq_free(struct hdac_softc *); 570 static void hdac_corb_init(struct hdac_softc *); 571 static void hdac_rirb_init(struct hdac_softc *); 572 static void hdac_corb_start(struct hdac_softc *); 573 static void hdac_rirb_start(struct hdac_softc *); 574 static void hdac_scan_codecs(struct hdac_softc *); 575 static int hdac_probe_codec(struct hdac_codec *); 576 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 577 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 578 579 static void hdac_attach2(void *); 580 581 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 582 uint32_t, int); 583 static void hdac_command_send_internal(struct hdac_softc *, 584 struct hdac_command_list *, int); 585 586 static int hdac_probe(device_t); 587 static int hdac_attach(device_t); 588 static int hdac_detach(device_t); 589 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 590 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 591 uint32_t, int, int); 592 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 593 nid_t, int, int); 594 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 595 nid_t, nid_t, int, int, int, int, int, int); 596 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 597 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 598 599 static int hdac_rirb_flush(struct hdac_softc *sc); 600 static int hdac_unsolq_flush(struct hdac_softc *sc); 601 602 #define hdac_command(a1, a2, a3) \ 603 hdac_command_sendone_internal(a1, a2, a3) 604 605 #define hdac_codec_id(d) \ 606 ((uint32_t)((d == NULL) ? 0x00000000 : \ 607 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 608 ((uint32_t)(d)->device_id & 0x0000ffff)))) 609 610 static char * 611 hdac_codec_name(struct hdac_devinfo *devinfo) 612 { 613 uint32_t id; 614 int i; 615 616 id = hdac_codec_id(devinfo); 617 618 for (i = 0; i < HDAC_CODECS_LEN; i++) { 619 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 620 return (hdac_codecs[i].name); 621 } 622 623 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 624 } 625 626 static char * 627 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 628 { 629 static char *ossname[] = SOUND_DEVICE_NAMES; 630 static char *unknown = "???"; 631 int i; 632 633 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 634 if (devmask & (1 << i)) 635 return (ossname[i]); 636 } 637 return (unknown); 638 } 639 640 static void 641 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 642 { 643 static char *ossname[] = SOUND_DEVICE_NAMES; 644 int i, first = 1; 645 646 bzero(buf, len); 647 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 648 if (mask & (1 << i)) { 649 if (first == 0) 650 strlcat(buf, ", ", len); 651 strlcat(buf, ossname[i], len); 652 first = 0; 653 } 654 } 655 } 656 657 static struct hdac_audio_ctl * 658 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 659 { 660 if (devinfo == NULL || 661 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 662 index == NULL || devinfo->function.audio.ctl == NULL || 663 devinfo->function.audio.ctlcnt < 1 || 664 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 665 return (NULL); 666 return (&devinfo->function.audio.ctl[(*index)++]); 667 } 668 669 static struct hdac_audio_ctl * 670 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 671 int index, int cnt) 672 { 673 struct hdac_audio_ctl *ctl, *retctl = NULL; 674 int i, at, atindex, found = 0; 675 676 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 677 return (NULL); 678 679 at = cnt; 680 if (at == 0) 681 at = 1; 682 else if (at < 0) 683 at = -1; 684 atindex = index; 685 if (atindex < 0) 686 atindex = -1; 687 688 i = 0; 689 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 690 if (ctl->enable == 0 || ctl->widget == NULL) 691 continue; 692 if (!(ctl->widget->nid == nid && (atindex == -1 || 693 ctl->index == atindex))) 694 continue; 695 found++; 696 if (found == cnt) 697 return (ctl); 698 retctl = ctl; 699 } 700 701 return ((at == -1) ? retctl : NULL); 702 } 703 704 static void 705 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 706 { 707 struct hdac_softc *sc; 708 struct hdac_widget *w; 709 struct hdac_audio_ctl *ctl; 710 uint32_t id, res; 711 int i = 0, j, forcemute; 712 nid_t cad; 713 714 if (devinfo == NULL || devinfo->codec == NULL || 715 devinfo->codec->sc == NULL) 716 return; 717 718 sc = devinfo->codec->sc; 719 cad = devinfo->codec->cad; 720 id = hdac_codec_id(devinfo); 721 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 722 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 723 sc->pci_subvendor) && 724 hdac_hp_switch[i].id == id) 725 break; 726 } 727 728 if (i >= HDAC_HP_SWITCH_LEN) 729 return; 730 731 forcemute = 0; 732 if (hdac_hp_switch[i].eapdnid != -1) { 733 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 734 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 735 forcemute = (w->param.eapdbtl & 736 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 737 } 738 739 res = hdac_command(sc, 740 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 741 HDA_BOOTVERBOSE( 742 device_printf(sc->dev, 743 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 744 hdac_hp_switch[i].hpnid, res); 745 ); 746 res >>= 31; 747 res ^= hdac_hp_switch[i].inverted; 748 749 switch (hdac_hp_switch[i].type) { 750 case HDAC_HP_SWITCH_CTL: 751 ctl = hdac_audio_ctl_amp_get(devinfo, 752 hdac_hp_switch[i].hpnid, 0, 1); 753 if (ctl != NULL) { 754 ctl->muted = (res != 0 && forcemute == 0) ? 755 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 756 hdac_audio_ctl_amp_set(ctl, 757 HDA_AMP_MUTE_DEFAULT, ctl->left, 758 ctl->right); 759 } 760 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 761 ctl = hdac_audio_ctl_amp_get(devinfo, 762 hdac_hp_switch[i].spkrnid[j], 0, 1); 763 if (ctl != NULL) { 764 ctl->muted = (res != 0 || forcemute == 1) ? 765 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 766 hdac_audio_ctl_amp_set(ctl, 767 HDA_AMP_MUTE_DEFAULT, ctl->left, 768 ctl->right); 769 } 770 } 771 break; 772 case HDAC_HP_SWITCH_CTRL: 773 if (res != 0) { 774 /* HP in */ 775 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 776 if (w != NULL && w->type == 777 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 778 if (forcemute == 0) 779 w->wclass.pin.ctrl |= 780 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 781 else 782 w->wclass.pin.ctrl &= 783 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 784 hdac_command(sc, 785 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 786 w->wclass.pin.ctrl), cad); 787 } 788 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 789 w = hdac_widget_get(devinfo, 790 hdac_hp_switch[i].spkrnid[j]); 791 if (w != NULL && w->type == 792 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 793 w->wclass.pin.ctrl &= 794 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 795 hdac_command(sc, 796 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 797 w->nid, 798 w->wclass.pin.ctrl), cad); 799 } 800 } 801 } else { 802 /* HP out */ 803 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 804 if (w != NULL && w->type == 805 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 806 w->wclass.pin.ctrl &= 807 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 808 hdac_command(sc, 809 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 810 w->wclass.pin.ctrl), cad); 811 } 812 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 813 w = hdac_widget_get(devinfo, 814 hdac_hp_switch[i].spkrnid[j]); 815 if (w != NULL && w->type == 816 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 817 if (forcemute == 0) 818 w->wclass.pin.ctrl |= 819 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 820 else 821 w->wclass.pin.ctrl &= 822 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 823 hdac_command(sc, 824 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 825 w->nid, 826 w->wclass.pin.ctrl), cad); 827 } 828 } 829 } 830 break; 831 default: 832 break; 833 } 834 } 835 836 static void 837 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 838 { 839 struct hdac_softc *sc; 840 struct hdac_devinfo *devinfo = NULL; 841 device_t *devlist = NULL; 842 int devcount, i; 843 844 if (codec == NULL || codec->sc == NULL) 845 return; 846 847 sc = codec->sc; 848 849 HDA_BOOTVERBOSE( 850 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 851 ); 852 853 device_get_children(sc->dev, &devlist, &devcount); 854 for (i = 0; devlist != NULL && i < devcount; i++) { 855 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 856 if (devinfo != NULL && devinfo->node_type == 857 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 858 devinfo->codec != NULL && 859 devinfo->codec->cad == codec->cad) { 860 break; 861 } else 862 devinfo = NULL; 863 } 864 if (devlist != NULL) 865 free(devlist, M_TEMP); 866 867 if (devinfo == NULL) 868 return; 869 870 switch (tag) { 871 case HDAC_UNSOLTAG_EVENT_HP: 872 hdac_hp_switch_handler(devinfo); 873 break; 874 default: 875 break; 876 } 877 } 878 879 static int 880 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 881 { 882 /* XXX to be removed */ 883 #ifdef HDAC_INTR_EXTRA 884 uint32_t res; 885 #endif 886 887 if (ch->blkcnt == 0) 888 return (0); 889 890 /* XXX to be removed */ 891 #ifdef HDAC_INTR_EXTRA 892 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 893 #endif 894 895 /* XXX to be removed */ 896 #ifdef HDAC_INTR_EXTRA 897 HDA_BOOTVERBOSE( 898 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 899 device_printf(sc->dev, 900 "PCMDIR_%s intr triggered beyond stream boundary:" 901 "%08x\n", 902 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 903 ); 904 #endif 905 906 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 907 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 908 909 /* XXX to be removed */ 910 #ifdef HDAC_INTR_EXTRA 911 if (res & HDAC_SDSTS_BCIS) { 912 #endif 913 return (1); 914 /* XXX to be removed */ 915 #ifdef HDAC_INTR_EXTRA 916 } 917 #endif 918 919 return (0); 920 } 921 922 /**************************************************************************** 923 * void hdac_intr_handler(void *) 924 * 925 * Interrupt handler. Processes interrupts received from the hdac. 926 ****************************************************************************/ 927 static void 928 hdac_intr_handler(void *context) 929 { 930 struct hdac_softc *sc; 931 uint32_t intsts; 932 uint8_t rirbsts; 933 struct hdac_rirb *rirb_base; 934 uint32_t trigger = 0; 935 936 sc = (struct hdac_softc *)context; 937 938 hdac_lock(sc); 939 if (sc->polling != 0) { 940 hdac_unlock(sc); 941 return; 942 } 943 /* Do we have anything to do? */ 944 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 945 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 946 hdac_unlock(sc); 947 return; 948 } 949 950 /* Was this a controller interrupt? */ 951 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 952 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 953 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 954 /* Get as many responses that we can */ 955 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 956 HDAC_WRITE_1(&sc->mem, 957 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 958 hdac_rirb_flush(sc); 959 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 960 } 961 /* XXX to be removed */ 962 /* Clear interrupt and exit */ 963 #ifdef HDAC_INTR_EXTRA 964 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 965 #endif 966 } 967 968 hdac_unsolq_flush(sc); 969 970 if (intsts & HDAC_INTSTS_SIS_MASK) { 971 if ((intsts & (1 << sc->num_iss)) && 972 hdac_stream_intr(sc, &sc->play) != 0) 973 trigger |= 1; 974 if ((intsts & (1 << 0)) && 975 hdac_stream_intr(sc, &sc->rec) != 0) 976 trigger |= 2; 977 /* XXX to be removed */ 978 #ifdef HDAC_INTR_EXTRA 979 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 980 HDAC_INTSTS_SIS_MASK); 981 #endif 982 } 983 984 hdac_unlock(sc); 985 986 if (trigger & 1) 987 chn_intr(sc->play.c); 988 if (trigger & 2) 989 chn_intr(sc->rec.c); 990 } 991 992 /**************************************************************************** 993 * int hdac_reset(hdac_softc *) 994 * 995 * Reset the hdac to a quiescent and known state. 996 ****************************************************************************/ 997 static int 998 hdac_reset(struct hdac_softc *sc) 999 { 1000 uint32_t gctl; 1001 int count, i; 1002 1003 /* 1004 * Stop all Streams DMA engine 1005 */ 1006 for (i = 0; i < sc->num_iss; i++) 1007 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1008 for (i = 0; i < sc->num_oss; i++) 1009 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1010 for (i = 0; i < sc->num_bss; i++) 1011 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1012 1013 /* 1014 * Stop Control DMA engines 1015 */ 1016 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1017 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1018 1019 /* 1020 * Reset the controller. The reset must remain asserted for 1021 * a minimum of 100us. 1022 */ 1023 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1024 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1025 count = 10000; 1026 do { 1027 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1028 if (!(gctl & HDAC_GCTL_CRST)) 1029 break; 1030 DELAY(10); 1031 } while (--count); 1032 if (gctl & HDAC_GCTL_CRST) { 1033 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1034 return (ENXIO); 1035 } 1036 DELAY(100); 1037 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1038 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1039 count = 10000; 1040 do { 1041 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1042 if (gctl & HDAC_GCTL_CRST) 1043 break; 1044 DELAY(10); 1045 } while (--count); 1046 if (!(gctl & HDAC_GCTL_CRST)) { 1047 device_printf(sc->dev, "Device stuck in reset\n"); 1048 return (ENXIO); 1049 } 1050 1051 /* 1052 * Wait for codecs to finish their own reset sequence. The delay here 1053 * should be of 250us but for some reasons, on it's not enough on my 1054 * computer. Let's use twice as much as necessary to make sure that 1055 * it's reset properly. 1056 */ 1057 DELAY(1000); 1058 1059 return (0); 1060 } 1061 1062 1063 /**************************************************************************** 1064 * int hdac_get_capabilities(struct hdac_softc *); 1065 * 1066 * Retreive the general capabilities of the hdac; 1067 * Number of Input Streams 1068 * Number of Output Streams 1069 * Number of bidirectional Streams 1070 * 64bit ready 1071 * CORB and RIRB sizes 1072 ****************************************************************************/ 1073 static int 1074 hdac_get_capabilities(struct hdac_softc *sc) 1075 { 1076 uint16_t gcap; 1077 uint8_t corbsize, rirbsize; 1078 1079 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1080 sc->num_iss = HDAC_GCAP_ISS(gcap); 1081 sc->num_oss = HDAC_GCAP_OSS(gcap); 1082 sc->num_bss = HDAC_GCAP_BSS(gcap); 1083 1084 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1085 1086 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1087 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1088 HDAC_CORBSIZE_CORBSZCAP_256) 1089 sc->corb_size = 256; 1090 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1091 HDAC_CORBSIZE_CORBSZCAP_16) 1092 sc->corb_size = 16; 1093 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1094 HDAC_CORBSIZE_CORBSZCAP_2) 1095 sc->corb_size = 2; 1096 else { 1097 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1098 __func__, corbsize); 1099 return (ENXIO); 1100 } 1101 1102 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1103 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1104 HDAC_RIRBSIZE_RIRBSZCAP_256) 1105 sc->rirb_size = 256; 1106 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1107 HDAC_RIRBSIZE_RIRBSZCAP_16) 1108 sc->rirb_size = 16; 1109 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1110 HDAC_RIRBSIZE_RIRBSZCAP_2) 1111 sc->rirb_size = 2; 1112 else { 1113 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1114 __func__, rirbsize); 1115 return (ENXIO); 1116 } 1117 1118 return (0); 1119 } 1120 1121 1122 /**************************************************************************** 1123 * void hdac_dma_cb 1124 * 1125 * This function is called by bus_dmamap_load when the mapping has been 1126 * established. We just record the physical address of the mapping into 1127 * the struct hdac_dma passed in. 1128 ****************************************************************************/ 1129 static void 1130 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1131 { 1132 struct hdac_dma *dma; 1133 1134 if (error == 0) { 1135 dma = (struct hdac_dma *)callback_arg; 1136 dma->dma_paddr = segs[0].ds_addr; 1137 } 1138 } 1139 1140 static void 1141 hdac_dma_nocache(void *ptr) 1142 { 1143 #if defined(__i386__) || defined(__amd64__) 1144 pt_entry_t *pte; 1145 vm_offset_t va; 1146 1147 va = (vm_offset_t)ptr; 1148 pte = vtopte(va); 1149 if (pte) { 1150 *pte |= PG_N; 1151 invltlb(); 1152 } 1153 #endif 1154 } 1155 1156 /**************************************************************************** 1157 * int hdac_dma_alloc 1158 * 1159 * This function allocate and setup a dma region (struct hdac_dma). 1160 * It must be freed by a corresponding hdac_dma_free. 1161 ****************************************************************************/ 1162 static int 1163 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1164 { 1165 int result; 1166 int lowaddr; 1167 1168 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1169 BUS_SPACE_MAXADDR_32BIT; 1170 bzero(dma, sizeof(*dma)); 1171 1172 /* 1173 * Create a DMA tag 1174 */ 1175 result = bus_dma_tag_create(NULL, /* parent */ 1176 HDAC_DMA_ALIGNMENT, /* alignment */ 1177 0, /* boundary */ 1178 lowaddr, /* lowaddr */ 1179 BUS_SPACE_MAXADDR, /* highaddr */ 1180 NULL, /* filtfunc */ 1181 NULL, /* fistfuncarg */ 1182 size, /* maxsize */ 1183 1, /* nsegments */ 1184 size, /* maxsegsz */ 1185 0, /* flags */ 1186 NULL, /* lockfunc */ 1187 NULL, /* lockfuncarg */ 1188 &dma->dma_tag); /* dmat */ 1189 if (result != 0) { 1190 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1191 __func__, result); 1192 goto fail; 1193 } 1194 1195 /* 1196 * Allocate DMA memory 1197 */ 1198 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1199 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1200 if (result != 0) { 1201 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1202 __func__, result); 1203 goto fail; 1204 } 1205 1206 /* 1207 * Map the memory 1208 */ 1209 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1210 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1211 BUS_DMA_NOWAIT); 1212 if (result != 0 || dma->dma_paddr == 0) { 1213 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1214 __func__, result); 1215 goto fail; 1216 } 1217 bzero((void *)dma->dma_vaddr, size); 1218 hdac_dma_nocache(dma->dma_vaddr); 1219 1220 return (0); 1221 fail: 1222 if (dma->dma_map != NULL) 1223 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1224 if (dma->dma_tag != NULL) 1225 bus_dma_tag_destroy(dma->dma_tag); 1226 return (result); 1227 } 1228 1229 1230 /**************************************************************************** 1231 * void hdac_dma_free(struct hdac_dma *) 1232 * 1233 * Free a struct dhac_dma that has been previously allocated via the 1234 * hdac_dma_alloc function. 1235 ****************************************************************************/ 1236 static void 1237 hdac_dma_free(struct hdac_dma *dma) 1238 { 1239 if (dma->dma_tag != NULL) { 1240 /* Flush caches */ 1241 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1242 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1243 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1244 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1245 bus_dma_tag_destroy(dma->dma_tag); 1246 } 1247 } 1248 1249 /**************************************************************************** 1250 * int hdac_mem_alloc(struct hdac_softc *) 1251 * 1252 * Allocate all the bus resources necessary to speak with the physical 1253 * controller. 1254 ****************************************************************************/ 1255 static int 1256 hdac_mem_alloc(struct hdac_softc *sc) 1257 { 1258 struct hdac_mem *mem; 1259 1260 mem = &sc->mem; 1261 mem->mem_rid = PCIR_BAR(0); 1262 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1263 &mem->mem_rid, RF_ACTIVE); 1264 if (mem->mem_res == NULL) { 1265 device_printf(sc->dev, 1266 "%s: Unable to allocate memory resource\n", __func__); 1267 return (ENOMEM); 1268 } 1269 mem->mem_tag = rman_get_bustag(mem->mem_res); 1270 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1271 1272 return (0); 1273 } 1274 1275 /**************************************************************************** 1276 * void hdac_mem_free(struct hdac_softc *) 1277 * 1278 * Free up resources previously allocated by hdac_mem_alloc. 1279 ****************************************************************************/ 1280 static void 1281 hdac_mem_free(struct hdac_softc *sc) 1282 { 1283 struct hdac_mem *mem; 1284 1285 mem = &sc->mem; 1286 if (mem->mem_res != NULL) 1287 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1288 mem->mem_res); 1289 mem->mem_res = NULL; 1290 } 1291 1292 /**************************************************************************** 1293 * int hdac_irq_alloc(struct hdac_softc *) 1294 * 1295 * Allocate and setup the resources necessary for interrupt handling. 1296 ****************************************************************************/ 1297 static int 1298 hdac_irq_alloc(struct hdac_softc *sc) 1299 { 1300 struct hdac_irq *irq; 1301 int result; 1302 1303 irq = &sc->irq; 1304 irq->irq_rid = 0x0; 1305 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1306 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1307 if (irq->irq_res == NULL) { 1308 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1309 __func__); 1310 goto fail; 1311 } 1312 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1313 hdac_intr_handler, sc, &irq->irq_handle); 1314 if (result != 0) { 1315 device_printf(sc->dev, 1316 "%s: Unable to setup interrupt handler (%x)\n", 1317 __func__, result); 1318 goto fail; 1319 } 1320 1321 return (0); 1322 1323 fail: 1324 hdac_irq_free(sc); 1325 1326 return (ENXIO); 1327 } 1328 1329 /**************************************************************************** 1330 * void hdac_irq_free(struct hdac_softc *) 1331 * 1332 * Free up resources previously allocated by hdac_irq_alloc. 1333 ****************************************************************************/ 1334 static void 1335 hdac_irq_free(struct hdac_softc *sc) 1336 { 1337 struct hdac_irq *irq; 1338 1339 irq = &sc->irq; 1340 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1341 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1342 if (irq->irq_res != NULL) 1343 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1344 irq->irq_res); 1345 irq->irq_handle = NULL; 1346 irq->irq_res = NULL; 1347 } 1348 1349 /**************************************************************************** 1350 * void hdac_corb_init(struct hdac_softc *) 1351 * 1352 * Initialize the corb registers for operations but do not start it up yet. 1353 * The CORB engine must not be running when this function is called. 1354 ****************************************************************************/ 1355 static void 1356 hdac_corb_init(struct hdac_softc *sc) 1357 { 1358 uint8_t corbsize; 1359 uint64_t corbpaddr; 1360 1361 /* Setup the CORB size. */ 1362 switch (sc->corb_size) { 1363 case 256: 1364 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1365 break; 1366 case 16: 1367 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1368 break; 1369 case 2: 1370 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1371 break; 1372 default: 1373 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1374 } 1375 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1376 1377 /* Setup the CORB Address in the hdac */ 1378 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1379 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1380 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1381 1382 /* Set the WP and RP */ 1383 sc->corb_wp = 0; 1384 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1385 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1386 /* 1387 * The HDA specification indicates that the CORBRPRST bit will always 1388 * read as zero. Unfortunately, it seems that at least the 82801G 1389 * doesn't reset the bit to zero, which stalls the corb engine. 1390 * manually reset the bit to zero before continuing. 1391 */ 1392 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1393 1394 /* Enable CORB error reporting */ 1395 #if 0 1396 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1397 #endif 1398 } 1399 1400 /**************************************************************************** 1401 * void hdac_rirb_init(struct hdac_softc *) 1402 * 1403 * Initialize the rirb registers for operations but do not start it up yet. 1404 * The RIRB engine must not be running when this function is called. 1405 ****************************************************************************/ 1406 static void 1407 hdac_rirb_init(struct hdac_softc *sc) 1408 { 1409 uint8_t rirbsize; 1410 uint64_t rirbpaddr; 1411 1412 /* Setup the RIRB size. */ 1413 switch (sc->rirb_size) { 1414 case 256: 1415 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1416 break; 1417 case 16: 1418 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1419 break; 1420 case 2: 1421 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1422 break; 1423 default: 1424 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1425 } 1426 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1427 1428 /* Setup the RIRB Address in the hdac */ 1429 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1430 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1431 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1432 1433 /* Setup the WP and RP */ 1434 sc->rirb_rp = 0; 1435 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1436 1437 if (sc->polling == 0) { 1438 /* Setup the interrupt threshold */ 1439 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1440 1441 /* Enable Overrun and response received reporting */ 1442 #if 0 1443 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1444 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1445 #else 1446 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1447 #endif 1448 } 1449 1450 /* 1451 * Make sure that the Host CPU cache doesn't contain any dirty 1452 * cache lines that falls in the rirb. If I understood correctly, it 1453 * should be sufficient to do this only once as the rirb is purely 1454 * read-only from now on. 1455 */ 1456 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1457 BUS_DMASYNC_PREREAD); 1458 } 1459 1460 /**************************************************************************** 1461 * void hdac_corb_start(hdac_softc *) 1462 * 1463 * Startup the corb DMA engine 1464 ****************************************************************************/ 1465 static void 1466 hdac_corb_start(struct hdac_softc *sc) 1467 { 1468 uint32_t corbctl; 1469 1470 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1471 corbctl |= HDAC_CORBCTL_CORBRUN; 1472 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1473 } 1474 1475 /**************************************************************************** 1476 * void hdac_rirb_start(hdac_softc *) 1477 * 1478 * Startup the rirb DMA engine 1479 ****************************************************************************/ 1480 static void 1481 hdac_rirb_start(struct hdac_softc *sc) 1482 { 1483 uint32_t rirbctl; 1484 1485 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1486 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1487 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1488 } 1489 1490 1491 /**************************************************************************** 1492 * void hdac_scan_codecs(struct hdac_softc *) 1493 * 1494 * Scan the bus for available codecs. 1495 ****************************************************************************/ 1496 static void 1497 hdac_scan_codecs(struct hdac_softc *sc) 1498 { 1499 struct hdac_codec *codec; 1500 int i; 1501 uint16_t statests; 1502 1503 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1504 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1505 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1506 /* We have found a codec. */ 1507 hdac_unlock(sc); 1508 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1509 M_HDAC, M_ZERO | M_NOWAIT); 1510 hdac_lock(sc); 1511 if (codec == NULL) { 1512 device_printf(sc->dev, 1513 "Unable to allocate memory for codec\n"); 1514 continue; 1515 } 1516 codec->commands = NULL; 1517 codec->responses_received = 0; 1518 codec->verbs_sent = 0; 1519 codec->sc = sc; 1520 codec->cad = i; 1521 sc->codecs[i] = codec; 1522 if (hdac_probe_codec(codec) != 0) 1523 break; 1524 } 1525 } 1526 /* All codecs have been probed, now try to attach drivers to them */ 1527 /* bus_generic_attach(sc->dev); */ 1528 } 1529 1530 /**************************************************************************** 1531 * void hdac_probe_codec(struct hdac_softc *, int) 1532 * 1533 * Probe a the given codec_id for available function groups. 1534 ****************************************************************************/ 1535 static int 1536 hdac_probe_codec(struct hdac_codec *codec) 1537 { 1538 struct hdac_softc *sc = codec->sc; 1539 struct hdac_devinfo *devinfo; 1540 uint32_t vendorid, revisionid, subnode; 1541 int startnode; 1542 int endnode; 1543 int i; 1544 nid_t cad = codec->cad; 1545 1546 HDA_BOOTVERBOSE( 1547 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1548 ); 1549 vendorid = hdac_command(sc, 1550 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1551 cad); 1552 revisionid = hdac_command(sc, 1553 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1554 cad); 1555 subnode = hdac_command(sc, 1556 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1557 cad); 1558 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1559 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1560 1561 HDA_BOOTVERBOSE( 1562 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1563 startnode, endnode); 1564 ); 1565 for (i = startnode; i < endnode; i++) { 1566 devinfo = hdac_probe_function(codec, i); 1567 if (devinfo != NULL) { 1568 /* XXX Ignore other FG. */ 1569 devinfo->vendor_id = 1570 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1571 devinfo->device_id = 1572 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1573 devinfo->revision_id = 1574 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1575 devinfo->stepping_id = 1576 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1577 HDA_BOOTVERBOSE( 1578 device_printf(sc->dev, 1579 "HDA_DEBUG: \tFound AFG nid=%d " 1580 "[startnode=%d endnode=%d]\n", 1581 devinfo->nid, startnode, endnode); 1582 ); 1583 return (1); 1584 } 1585 } 1586 1587 HDA_BOOTVERBOSE( 1588 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1589 ); 1590 return (0); 1591 } 1592 1593 static struct hdac_devinfo * 1594 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1595 { 1596 struct hdac_softc *sc = codec->sc; 1597 struct hdac_devinfo *devinfo; 1598 uint32_t fctgrptype; 1599 nid_t cad = codec->cad; 1600 1601 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1602 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1603 1604 /* XXX For now, ignore other FG. */ 1605 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1606 return (NULL); 1607 1608 hdac_unlock(sc); 1609 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1610 M_NOWAIT | M_ZERO); 1611 hdac_lock(sc); 1612 if (devinfo == NULL) { 1613 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1614 __func__); 1615 return (NULL); 1616 } 1617 1618 devinfo->nid = nid; 1619 devinfo->node_type = fctgrptype; 1620 devinfo->codec = codec; 1621 1622 hdac_add_child(sc, devinfo); 1623 1624 return (devinfo); 1625 } 1626 1627 static void 1628 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1629 { 1630 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1631 device_set_ivars(devinfo->dev, (void *)devinfo); 1632 /* XXX - Print more information when booting verbose??? */ 1633 } 1634 1635 static void 1636 hdac_widget_connection_parse(struct hdac_widget *w) 1637 { 1638 struct hdac_softc *sc = w->devinfo->codec->sc; 1639 uint32_t res; 1640 int i, j, max, found, entnum, cnid; 1641 nid_t cad = w->devinfo->codec->cad; 1642 nid_t nid = w->nid; 1643 1644 res = hdac_command(sc, 1645 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1646 1647 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1648 1649 if (w->nconns < 1) 1650 return; 1651 1652 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1653 res = 0; 1654 i = 0; 1655 found = 0; 1656 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1657 1658 while (i < w->nconns) { 1659 res = hdac_command(sc, 1660 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1661 for (j = 0; j < entnum; j++) { 1662 cnid = res; 1663 cnid >>= (32 / entnum) * j; 1664 cnid &= (1 << (32 / entnum)) - 1; 1665 if (cnid == 0) 1666 continue; 1667 if (found > max) { 1668 device_printf(sc->dev, 1669 "node %d: Adding %d: " 1670 "Max connection reached!\n", 1671 nid, cnid); 1672 continue; 1673 } 1674 w->conns[found++] = cnid; 1675 } 1676 i += entnum; 1677 } 1678 1679 HDA_BOOTVERBOSE( 1680 if (w->nconns != found) { 1681 device_printf(sc->dev, 1682 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1683 "length=%d != found=%d\n", 1684 nid, w->nconns, found); 1685 } 1686 ); 1687 } 1688 1689 static uint32_t 1690 hdac_widget_pin_getconfig(struct hdac_widget *w) 1691 { 1692 struct hdac_softc *sc; 1693 uint32_t config, orig, id; 1694 nid_t cad, nid; 1695 1696 sc = w->devinfo->codec->sc; 1697 cad = w->devinfo->codec->cad; 1698 nid = w->nid; 1699 id = hdac_codec_id(w->devinfo); 1700 1701 config = hdac_command(sc, 1702 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1703 cad); 1704 orig = config; 1705 1706 /* 1707 * XXX REWRITE!!!! Don't argue! 1708 */ 1709 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1710 switch (nid) { 1711 case 26: 1712 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1713 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1714 break; 1715 case 27: 1716 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1717 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1718 break; 1719 } 1720 } else if (id == HDA_CODEC_ALC880 && 1721 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1722 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1723 /* 1724 * Super broken BIOS 1725 */ 1726 switch (nid) { 1727 case 20: 1728 break; 1729 case 21: 1730 break; 1731 case 22: 1732 break; 1733 case 23: 1734 break; 1735 case 24: /* MIC1 */ 1736 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1737 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1738 break; 1739 case 25: /* XXX MIC2 */ 1740 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1741 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1742 break; 1743 case 26: /* LINE1 */ 1744 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1745 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1746 break; 1747 case 27: /* XXX LINE2 */ 1748 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1749 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1750 break; 1751 case 28: /* CD */ 1752 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1753 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1754 break; 1755 case 30: 1756 break; 1757 case 31: 1758 break; 1759 default: 1760 break; 1761 } 1762 } else if (id == HDA_CODEC_ALC883 && 1763 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 1764 switch (nid) { 1765 case 25: 1766 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1767 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1768 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1769 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1770 break; 1771 default: 1772 break; 1773 } 1774 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 1775 HP_V3000_SUBVENDOR) { 1776 switch (nid) { 1777 case 18: 1778 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 1779 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 1780 break; 1781 case 20: 1782 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1783 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1784 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1785 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1786 break; 1787 default: 1788 break; 1789 } 1790 } 1791 1792 HDA_BOOTVERBOSE( 1793 if (config != orig) 1794 device_printf(sc->dev, 1795 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 1796 nid, orig, config); 1797 ); 1798 1799 return (config); 1800 } 1801 1802 static uint32_t 1803 hdac_widget_pin_getcaps(struct hdac_widget *w) 1804 { 1805 struct hdac_softc *sc; 1806 uint32_t caps, orig, id; 1807 nid_t cad, nid; 1808 1809 sc = w->devinfo->codec->sc; 1810 cad = w->devinfo->codec->cad; 1811 nid = w->nid; 1812 id = hdac_codec_id(w->devinfo); 1813 1814 caps = hdac_command(sc, 1815 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1816 orig = caps; 1817 1818 HDA_BOOTVERBOSE( 1819 if (caps != orig) 1820 device_printf(sc->dev, 1821 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 1822 nid, orig, caps); 1823 ); 1824 1825 return (caps); 1826 } 1827 1828 static void 1829 hdac_widget_pin_parse(struct hdac_widget *w) 1830 { 1831 struct hdac_softc *sc = w->devinfo->codec->sc; 1832 uint32_t config, pincap; 1833 char *devstr, *connstr; 1834 nid_t cad = w->devinfo->codec->cad; 1835 nid_t nid = w->nid; 1836 1837 config = hdac_widget_pin_getconfig(w); 1838 w->wclass.pin.config = config; 1839 1840 pincap = hdac_widget_pin_getcaps(w); 1841 w->wclass.pin.cap = pincap; 1842 1843 w->wclass.pin.ctrl = hdac_command(sc, 1844 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1845 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1846 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1847 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1848 1849 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1850 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1851 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1852 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1853 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1854 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1855 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1856 w->param.eapdbtl = hdac_command(sc, 1857 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1858 w->param.eapdbtl &= 0x7; 1859 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1860 } else 1861 w->param.eapdbtl = HDAC_INVALID; 1862 1863 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1864 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1865 devstr = "line out"; 1866 break; 1867 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1868 devstr = "speaker"; 1869 break; 1870 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1871 devstr = "headphones out"; 1872 break; 1873 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1874 devstr = "CD"; 1875 break; 1876 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1877 devstr = "SPDIF out"; 1878 break; 1879 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1880 devstr = "digital (other) out"; 1881 break; 1882 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1883 devstr = "modem, line side"; 1884 break; 1885 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1886 devstr = "modem, handset side"; 1887 break; 1888 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1889 devstr = "line in"; 1890 break; 1891 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1892 devstr = "AUX"; 1893 break; 1894 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1895 devstr = "Mic in"; 1896 break; 1897 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1898 devstr = "telephony"; 1899 break; 1900 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1901 devstr = "SPDIF in"; 1902 break; 1903 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1904 devstr = "digital (other) in"; 1905 break; 1906 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1907 devstr = "other"; 1908 break; 1909 default: 1910 devstr = "unknown"; 1911 break; 1912 } 1913 1914 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1915 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1916 connstr = "jack"; 1917 break; 1918 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1919 connstr = "none"; 1920 break; 1921 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1922 connstr = "fixed"; 1923 break; 1924 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1925 connstr = "jack / fixed"; 1926 break; 1927 default: 1928 connstr = "unknown"; 1929 break; 1930 } 1931 1932 strlcat(w->name, ": ", sizeof(w->name)); 1933 strlcat(w->name, devstr, sizeof(w->name)); 1934 strlcat(w->name, " (", sizeof(w->name)); 1935 strlcat(w->name, connstr, sizeof(w->name)); 1936 strlcat(w->name, ")", sizeof(w->name)); 1937 } 1938 1939 static void 1940 hdac_widget_parse(struct hdac_widget *w) 1941 { 1942 struct hdac_softc *sc = w->devinfo->codec->sc; 1943 uint32_t wcap, cap; 1944 char *typestr; 1945 nid_t cad = w->devinfo->codec->cad; 1946 nid_t nid = w->nid; 1947 1948 wcap = hdac_command(sc, 1949 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1950 cad); 1951 w->param.widget_cap = wcap; 1952 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1953 1954 switch (w->type) { 1955 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1956 typestr = "audio output"; 1957 break; 1958 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1959 typestr = "audio input"; 1960 break; 1961 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1962 typestr = "audio mixer"; 1963 break; 1964 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1965 typestr = "audio selector"; 1966 break; 1967 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1968 typestr = "pin"; 1969 break; 1970 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1971 typestr = "power widget"; 1972 break; 1973 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1974 typestr = "volume widget"; 1975 break; 1976 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1977 typestr = "beep widget"; 1978 break; 1979 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1980 typestr = "vendor widget"; 1981 break; 1982 default: 1983 typestr = "unknown type"; 1984 break; 1985 } 1986 1987 strlcpy(w->name, typestr, sizeof(w->name)); 1988 1989 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1990 hdac_command(sc, 1991 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1992 cad); 1993 DELAY(1000); 1994 } 1995 1996 hdac_widget_connection_parse(w); 1997 1998 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1999 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2000 w->param.outamp_cap = 2001 hdac_command(sc, 2002 HDA_CMD_GET_PARAMETER(cad, nid, 2003 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2004 else 2005 w->param.outamp_cap = 2006 w->devinfo->function.audio.outamp_cap; 2007 } else 2008 w->param.outamp_cap = 0; 2009 2010 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2011 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2012 w->param.inamp_cap = 2013 hdac_command(sc, 2014 HDA_CMD_GET_PARAMETER(cad, nid, 2015 HDA_PARAM_INPUT_AMP_CAP), cad); 2016 else 2017 w->param.inamp_cap = 2018 w->devinfo->function.audio.inamp_cap; 2019 } else 2020 w->param.inamp_cap = 0; 2021 2022 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2023 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2024 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2025 cap = hdac_command(sc, 2026 HDA_CMD_GET_PARAMETER(cad, nid, 2027 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2028 w->param.supp_stream_formats = (cap != 0) ? cap : 2029 w->devinfo->function.audio.supp_stream_formats; 2030 cap = hdac_command(sc, 2031 HDA_CMD_GET_PARAMETER(cad, nid, 2032 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2033 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2034 w->devinfo->function.audio.supp_pcm_size_rate; 2035 } else { 2036 w->param.supp_stream_formats = 2037 w->devinfo->function.audio.supp_stream_formats; 2038 w->param.supp_pcm_size_rate = 2039 w->devinfo->function.audio.supp_pcm_size_rate; 2040 } 2041 } else { 2042 w->param.supp_stream_formats = 0; 2043 w->param.supp_pcm_size_rate = 0; 2044 } 2045 2046 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2047 hdac_widget_pin_parse(w); 2048 } 2049 2050 static struct hdac_widget * 2051 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2052 { 2053 if (devinfo == NULL || devinfo->widget == NULL || 2054 nid < devinfo->startnode || nid >= devinfo->endnode) 2055 return (NULL); 2056 return (&devinfo->widget[nid - devinfo->startnode]); 2057 } 2058 2059 static __inline int 2060 hda_poll_channel(struct hdac_chan *ch) 2061 { 2062 uint32_t sz, delta; 2063 volatile uint32_t ptr; 2064 2065 if (ch->active == 0) 2066 return (0); 2067 2068 sz = ch->blksz * ch->blkcnt; 2069 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 2070 ch->ptr = ptr; 2071 ptr %= sz; 2072 ptr &= ~(ch->blksz - 1); 2073 delta = (sz + ptr - ch->prevptr) % sz; 2074 2075 if (delta < ch->blksz) 2076 return (0); 2077 2078 ch->prevptr = ptr; 2079 2080 return (1); 2081 } 2082 2083 #define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2084 2085 static void 2086 hda_poll_callback(void *arg) 2087 { 2088 struct hdac_softc *sc = arg; 2089 uint32_t trigger = 0; 2090 2091 if (sc == NULL) 2092 return; 2093 2094 hdac_lock(sc); 2095 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2096 hdac_unlock(sc); 2097 return; 2098 } 2099 2100 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2101 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2102 2103 /* XXX */ 2104 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2105 hda_poll_callback, sc); 2106 2107 hdac_unlock(sc); 2108 2109 if (trigger & 1) 2110 chn_intr(sc->play.c); 2111 if (trigger & 2) 2112 chn_intr(sc->rec.c); 2113 } 2114 2115 static int 2116 hdac_rirb_flush(struct hdac_softc *sc) 2117 { 2118 struct hdac_rirb *rirb_base, *rirb; 2119 struct hdac_codec *codec; 2120 struct hdac_command_list *commands; 2121 nid_t cad; 2122 uint32_t resp; 2123 uint8_t rirbwp; 2124 int ret = 0; 2125 2126 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2127 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2128 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2129 BUS_DMASYNC_POSTREAD); 2130 2131 while (sc->rirb_rp != rirbwp) { 2132 sc->rirb_rp++; 2133 sc->rirb_rp %= sc->rirb_size; 2134 rirb = &rirb_base[sc->rirb_rp]; 2135 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2136 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2137 sc->codecs[cad] == NULL) 2138 continue; 2139 resp = rirb->response; 2140 codec = sc->codecs[cad]; 2141 commands = codec->commands; 2142 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2143 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2144 ((resp >> 26) & 0xffff); 2145 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2146 } else if (commands != NULL && commands->num_commands > 0 && 2147 codec->responses_received < commands->num_commands) 2148 commands->responses[codec->responses_received++] = 2149 resp; 2150 ret++; 2151 } 2152 2153 return (ret); 2154 } 2155 2156 static int 2157 hdac_unsolq_flush(struct hdac_softc *sc) 2158 { 2159 nid_t cad; 2160 uint32_t tag; 2161 int ret = 0; 2162 2163 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2164 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2165 while (sc->unsolq_rp != sc->unsolq_wp) { 2166 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2167 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2168 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2169 hdac_unsolicited_handler(sc->codecs[cad], tag); 2170 ret++; 2171 } 2172 sc->unsolq_st = HDAC_UNSOLQ_READY; 2173 } 2174 2175 return (ret); 2176 } 2177 2178 static void 2179 hdac_poll_callback(void *arg) 2180 { 2181 struct hdac_softc *sc = arg; 2182 if (sc == NULL) 2183 return; 2184 2185 hdac_lock(sc); 2186 if (sc->polling == 0) { 2187 hdac_unlock(sc); 2188 return; 2189 } 2190 hdac_rirb_flush(sc); 2191 hdac_unsolq_flush(sc); 2192 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2193 hdac_poll_callback, sc); 2194 hdac_unlock(sc); 2195 } 2196 2197 static void 2198 hdac_stream_stop(struct hdac_chan *ch) 2199 { 2200 struct hdac_softc *sc = ch->devinfo->codec->sc; 2201 uint32_t ctl; 2202 2203 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2204 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2205 HDAC_SDCTL_RUN); 2206 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2207 2208 ch->active = 0; 2209 2210 if (sc->polling != 0) { 2211 int pollticks; 2212 2213 if (hda_chan_active(sc) == 0) { 2214 callout_stop(&sc->poll_hda); 2215 sc->poll_ticks = 1; 2216 } else { 2217 if (sc->play.active != 0) 2218 ch = &sc->play; 2219 else 2220 ch = &sc->rec; 2221 pollticks = ((uint64_t)hz * ch->blksz) / 2222 ((uint64_t)sndbuf_getbps(ch->b) * 2223 sndbuf_getspd(ch->b)); 2224 pollticks >>= 2; 2225 if (pollticks > hz) 2226 pollticks = hz; 2227 if (pollticks < 1) { 2228 HDA_BOOTVERBOSE( 2229 device_printf(sc->dev, 2230 "%s: pollticks=%d < 1 !\n", 2231 __func__, pollticks); 2232 ); 2233 pollticks = 1; 2234 } 2235 if (pollticks > sc->poll_ticks) { 2236 HDA_BOOTVERBOSE( 2237 device_printf(sc->dev, 2238 "%s: pollticks %d -> %d\n", 2239 __func__, sc->poll_ticks, 2240 pollticks); 2241 ); 2242 sc->poll_ticks = pollticks; 2243 callout_reset(&sc->poll_hda, 1, 2244 hda_poll_callback, sc); 2245 } 2246 } 2247 } else { 2248 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2249 ctl &= ~(1 << (ch->off >> 5)); 2250 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2251 } 2252 } 2253 2254 static void 2255 hdac_stream_start(struct hdac_chan *ch) 2256 { 2257 struct hdac_softc *sc = ch->devinfo->codec->sc; 2258 uint32_t ctl; 2259 2260 if (sc->polling != 0) { 2261 int pollticks; 2262 2263 pollticks = ((uint64_t)hz * ch->blksz) / 2264 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2265 pollticks >>= 2; 2266 if (pollticks > hz) 2267 pollticks = hz; 2268 if (pollticks < 1) { 2269 HDA_BOOTVERBOSE( 2270 device_printf(sc->dev, 2271 "%s: pollticks=%d < 1 !\n", 2272 __func__, pollticks); 2273 ); 2274 pollticks = 1; 2275 } 2276 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2277 HDA_BOOTVERBOSE( 2278 if (hda_chan_active(sc) == 0) { 2279 device_printf(sc->dev, 2280 "%s: pollticks=%d\n", 2281 __func__, pollticks); 2282 } else { 2283 device_printf(sc->dev, 2284 "%s: pollticks %d -> %d\n", 2285 __func__, sc->poll_ticks, 2286 pollticks); 2287 } 2288 ); 2289 sc->poll_ticks = pollticks; 2290 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2291 sc); 2292 } 2293 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2294 ctl |= HDAC_SDCTL_RUN; 2295 } else { 2296 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2297 ctl |= 1 << (ch->off >> 5); 2298 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2299 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2300 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2301 HDAC_SDCTL_RUN; 2302 } 2303 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2304 2305 ch->active = 1; 2306 } 2307 2308 static void 2309 hdac_stream_reset(struct hdac_chan *ch) 2310 { 2311 struct hdac_softc *sc = ch->devinfo->codec->sc; 2312 int timeout = 1000; 2313 int to = timeout; 2314 uint32_t ctl; 2315 2316 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2317 ctl |= HDAC_SDCTL_SRST; 2318 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2319 do { 2320 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2321 if (ctl & HDAC_SDCTL_SRST) 2322 break; 2323 DELAY(10); 2324 } while (--to); 2325 if (!(ctl & HDAC_SDCTL_SRST)) { 2326 device_printf(sc->dev, "timeout in reset\n"); 2327 } 2328 ctl &= ~HDAC_SDCTL_SRST; 2329 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2330 to = timeout; 2331 do { 2332 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2333 if (!(ctl & HDAC_SDCTL_SRST)) 2334 break; 2335 DELAY(10); 2336 } while (--to); 2337 if (ctl & HDAC_SDCTL_SRST) 2338 device_printf(sc->dev, "can't reset!\n"); 2339 } 2340 2341 static void 2342 hdac_stream_setid(struct hdac_chan *ch) 2343 { 2344 struct hdac_softc *sc = ch->devinfo->codec->sc; 2345 uint32_t ctl; 2346 2347 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2348 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2349 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2350 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2351 } 2352 2353 static void 2354 hdac_bdl_setup(struct hdac_chan *ch) 2355 { 2356 struct hdac_softc *sc = ch->devinfo->codec->sc; 2357 struct hdac_bdle *bdle; 2358 uint64_t addr; 2359 uint32_t blksz, blkcnt; 2360 int i; 2361 2362 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2363 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2364 2365 if (sc->polling != 0) { 2366 blksz = ch->blksz * ch->blkcnt; 2367 blkcnt = 1; 2368 } else { 2369 blksz = ch->blksz; 2370 blkcnt = ch->blkcnt; 2371 } 2372 2373 for (i = 0; i < blkcnt; i++, bdle++) { 2374 bdle->addrl = (uint32_t)addr; 2375 bdle->addrh = (uint32_t)(addr >> 32); 2376 bdle->len = blksz; 2377 bdle->ioc = 1 ^ sc->polling; 2378 addr += blksz; 2379 } 2380 2381 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2382 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2383 addr = ch->bdl_dma.dma_paddr; 2384 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2385 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2386 } 2387 2388 static int 2389 hdac_bdl_alloc(struct hdac_chan *ch) 2390 { 2391 struct hdac_softc *sc = ch->devinfo->codec->sc; 2392 int rc; 2393 2394 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2395 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2396 if (rc) { 2397 device_printf(sc->dev, "can't alloc bdl\n"); 2398 return (rc); 2399 } 2400 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2401 2402 return (0); 2403 } 2404 2405 static void 2406 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2407 int index, int lmute, int rmute, 2408 int left, int right, int dir) 2409 { 2410 uint16_t v = 0; 2411 2412 if (sc == NULL) 2413 return; 2414 2415 if (left != right || lmute != rmute) { 2416 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2417 (lmute << 7) | left; 2418 hdac_command(sc, 2419 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2420 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2421 (rmute << 7) | right; 2422 } else 2423 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2424 (lmute << 7) | left; 2425 2426 hdac_command(sc, 2427 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2428 } 2429 2430 static void 2431 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2432 int left, int right) 2433 { 2434 struct hdac_softc *sc; 2435 nid_t nid, cad; 2436 int lmute, rmute; 2437 2438 if (ctl == NULL || ctl->widget == NULL || 2439 ctl->widget->devinfo == NULL || 2440 ctl->widget->devinfo->codec == NULL || 2441 ctl->widget->devinfo->codec->sc == NULL) 2442 return; 2443 2444 sc = ctl->widget->devinfo->codec->sc; 2445 cad = ctl->widget->devinfo->codec->cad; 2446 nid = ctl->widget->nid; 2447 2448 if (mute == HDA_AMP_MUTE_DEFAULT) { 2449 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2450 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2451 } else { 2452 lmute = HDA_AMP_LEFT_MUTED(mute); 2453 rmute = HDA_AMP_RIGHT_MUTED(mute); 2454 } 2455 2456 if (ctl->dir & HDA_CTL_OUT) 2457 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2458 lmute, rmute, left, right, 0); 2459 if (ctl->dir & HDA_CTL_IN) 2460 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2461 lmute, rmute, left, right, 1); 2462 ctl->left = left; 2463 ctl->right = right; 2464 } 2465 2466 static void 2467 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2468 { 2469 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2470 return; 2471 hdac_command(w->devinfo->codec->sc, 2472 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2473 w->nid, index), w->devinfo->codec->cad); 2474 w->selconn = index; 2475 } 2476 2477 2478 /**************************************************************************** 2479 * uint32_t hdac_command_sendone_internal 2480 * 2481 * Wrapper function that sends only one command to a given codec 2482 ****************************************************************************/ 2483 static uint32_t 2484 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2485 { 2486 struct hdac_command_list cl; 2487 uint32_t response = HDAC_INVALID; 2488 2489 if (!hdac_lockowned(sc)) 2490 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2491 cl.num_commands = 1; 2492 cl.verbs = &verb; 2493 cl.responses = &response; 2494 2495 hdac_command_send_internal(sc, &cl, cad); 2496 2497 return (response); 2498 } 2499 2500 /**************************************************************************** 2501 * hdac_command_send_internal 2502 * 2503 * Send a command list to the codec via the corb. We queue as much verbs as 2504 * we can and msleep on the codec. When the interrupt get the responses 2505 * back from the rirb, it will wake us up so we can queue the remaining verbs 2506 * if any. 2507 ****************************************************************************/ 2508 static void 2509 hdac_command_send_internal(struct hdac_softc *sc, 2510 struct hdac_command_list *commands, nid_t cad) 2511 { 2512 struct hdac_codec *codec; 2513 int corbrp; 2514 uint32_t *corb; 2515 int timeout; 2516 int retry = 10; 2517 struct hdac_rirb *rirb_base; 2518 2519 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2520 commands->num_commands < 1) 2521 return; 2522 2523 codec = sc->codecs[cad]; 2524 codec->commands = commands; 2525 codec->responses_received = 0; 2526 codec->verbs_sent = 0; 2527 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2528 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2529 2530 do { 2531 if (codec->verbs_sent != commands->num_commands) { 2532 /* Queue as many verbs as possible */ 2533 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2534 bus_dmamap_sync(sc->corb_dma.dma_tag, 2535 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2536 while (codec->verbs_sent != commands->num_commands && 2537 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2538 sc->corb_wp++; 2539 sc->corb_wp %= sc->corb_size; 2540 corb[sc->corb_wp] = 2541 commands->verbs[codec->verbs_sent++]; 2542 } 2543 2544 /* Send the verbs to the codecs */ 2545 bus_dmamap_sync(sc->corb_dma.dma_tag, 2546 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2547 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2548 } 2549 2550 timeout = 1000; 2551 while (hdac_rirb_flush(sc) == 0 && --timeout) 2552 DELAY(10); 2553 } while ((codec->verbs_sent != commands->num_commands || 2554 codec->responses_received != commands->num_commands) && --retry); 2555 2556 if (retry == 0) 2557 device_printf(sc->dev, 2558 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2559 __func__, commands->num_commands, codec->verbs_sent, 2560 codec->responses_received); 2561 2562 codec->commands = NULL; 2563 codec->responses_received = 0; 2564 codec->verbs_sent = 0; 2565 2566 hdac_unsolq_flush(sc); 2567 } 2568 2569 2570 /**************************************************************************** 2571 * Device Methods 2572 ****************************************************************************/ 2573 2574 /**************************************************************************** 2575 * int hdac_probe(device_t) 2576 * 2577 * Probe for the presence of an hdac. If none is found, check for a generic 2578 * match using the subclass of the device. 2579 ****************************************************************************/ 2580 static int 2581 hdac_probe(device_t dev) 2582 { 2583 int i, result; 2584 uint32_t model; 2585 uint16_t class, subclass; 2586 char desc[64]; 2587 2588 model = (uint32_t)pci_get_device(dev) << 16; 2589 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2590 class = pci_get_class(dev); 2591 subclass = pci_get_subclass(dev); 2592 2593 bzero(desc, sizeof(desc)); 2594 result = ENXIO; 2595 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2596 if (hdac_devices[i].model == model) { 2597 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2598 result = BUS_PROBE_DEFAULT; 2599 break; 2600 } 2601 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2602 class == PCIC_MULTIMEDIA && 2603 subclass == PCIS_MULTIMEDIA_HDA) { 2604 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2605 result = BUS_PROBE_GENERIC; 2606 break; 2607 } 2608 } 2609 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2610 subclass == PCIS_MULTIMEDIA_HDA) { 2611 strlcpy(desc, "Generic", sizeof(desc)); 2612 result = BUS_PROBE_GENERIC; 2613 } 2614 if (result != ENXIO) { 2615 strlcat(desc, " High Definition Audio Controller", 2616 sizeof(desc)); 2617 device_set_desc_copy(dev, desc); 2618 } 2619 2620 return (result); 2621 } 2622 2623 static void * 2624 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2625 struct pcm_channel *c, int dir) 2626 { 2627 struct hdac_devinfo *devinfo = data; 2628 struct hdac_softc *sc = devinfo->codec->sc; 2629 struct hdac_chan *ch; 2630 2631 hdac_lock(sc); 2632 if (dir == PCMDIR_PLAY) { 2633 ch = &sc->play; 2634 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2635 ch->dir = PCMDIR_PLAY; 2636 ch->sid = ++sc->streamcnt; 2637 devinfo->function.audio.playcnt++; 2638 } else { 2639 ch = &sc->rec; 2640 ch->off = devinfo->function.audio.reccnt << 5; 2641 ch->dir = PCMDIR_REC; 2642 ch->sid = ++sc->streamcnt; 2643 devinfo->function.audio.reccnt++; 2644 } 2645 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2646 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2647 ch->pcmrates[0] = 48000; 2648 ch->pcmrates[1] = 0; 2649 } 2650 ch->b = b; 2651 ch->c = c; 2652 ch->devinfo = devinfo; 2653 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2654 ch->blkcnt = sc->chan_blkcnt; 2655 hdac_unlock(sc); 2656 2657 if (hdac_bdl_alloc(ch) != 0) { 2658 ch->blkcnt = 0; 2659 return (NULL); 2660 } 2661 2662 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2663 return (NULL); 2664 2665 hdac_dma_nocache(ch->b->buf); 2666 2667 return (ch); 2668 } 2669 2670 static int 2671 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2672 { 2673 struct hdac_chan *ch = data; 2674 int i; 2675 2676 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2677 if (format == ch->caps.fmtlist[i]) { 2678 ch->fmt = format; 2679 return (0); 2680 } 2681 } 2682 2683 return (EINVAL); 2684 } 2685 2686 static int 2687 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2688 { 2689 struct hdac_chan *ch = data; 2690 uint32_t spd = 0, threshold; 2691 int i; 2692 2693 for (i = 0; ch->pcmrates[i] != 0; i++) { 2694 spd = ch->pcmrates[i]; 2695 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2696 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2697 if (speed < threshold) 2698 break; 2699 } 2700 2701 if (spd == 0) /* impossible */ 2702 ch->spd = 48000; 2703 else 2704 ch->spd = spd; 2705 2706 return (ch->spd); 2707 } 2708 2709 static void 2710 hdac_stream_setup(struct hdac_chan *ch) 2711 { 2712 struct hdac_softc *sc = ch->devinfo->codec->sc; 2713 int i; 2714 nid_t cad = ch->devinfo->codec->cad; 2715 uint16_t fmt; 2716 2717 fmt = 0; 2718 if (ch->fmt & AFMT_S16_LE) 2719 fmt |= ch->bit16 << 4; 2720 else if (ch->fmt & AFMT_S32_LE) 2721 fmt |= ch->bit32 << 4; 2722 else 2723 fmt |= 1 << 4; 2724 2725 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2726 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2727 fmt |= hda_rate_tab[i].base; 2728 fmt |= hda_rate_tab[i].mul; 2729 fmt |= hda_rate_tab[i].div; 2730 break; 2731 } 2732 } 2733 2734 if (ch->fmt & AFMT_STEREO) 2735 fmt |= 1; 2736 2737 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2738 2739 for (i = 0; ch->io[i] != -1; i++) { 2740 HDA_BOOTVERBOSE( 2741 device_printf(sc->dev, 2742 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2743 "fmt=0x%08x\n", 2744 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2745 ch->io[i], fmt); 2746 ); 2747 hdac_command(sc, 2748 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2749 hdac_command(sc, 2750 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2751 ch->sid << 4), cad); 2752 } 2753 } 2754 2755 static int 2756 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2757 { 2758 struct hdac_chan *ch = data; 2759 struct hdac_softc *sc = ch->devinfo->codec->sc; 2760 2761 blksz &= ~0x7f; 2762 if (blksz < 0x80) 2763 blksz = 0x80; 2764 2765 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2766 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2767 2768 if ((sndbuf_getblksz(ch->b) != blksz || 2769 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2770 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2771 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2772 __func__, blksz, ch->blkcnt); 2773 2774 ch->blksz = sndbuf_getblksz(ch->b); 2775 2776 return (ch->blksz); 2777 } 2778 2779 static void 2780 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2781 { 2782 struct hdac_devinfo *devinfo = ch->devinfo; 2783 nid_t cad = devinfo->codec->cad; 2784 int i; 2785 2786 hdac_stream_stop(ch); 2787 2788 for (i = 0; ch->io[i] != -1; i++) { 2789 hdac_command(sc, 2790 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2791 0), cad); 2792 } 2793 } 2794 2795 static void 2796 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2797 { 2798 ch->ptr = 0; 2799 ch->prevptr = 0; 2800 hdac_stream_stop(ch); 2801 hdac_stream_reset(ch); 2802 hdac_bdl_setup(ch); 2803 hdac_stream_setid(ch); 2804 hdac_stream_setup(ch); 2805 hdac_stream_start(ch); 2806 } 2807 2808 static int 2809 hdac_channel_trigger(kobj_t obj, void *data, int go) 2810 { 2811 struct hdac_chan *ch = data; 2812 struct hdac_softc *sc = ch->devinfo->codec->sc; 2813 2814 hdac_lock(sc); 2815 switch (go) { 2816 case PCMTRIG_START: 2817 hdac_channel_start(sc, ch); 2818 break; 2819 case PCMTRIG_STOP: 2820 case PCMTRIG_ABORT: 2821 hdac_channel_stop(sc, ch); 2822 break; 2823 } 2824 hdac_unlock(sc); 2825 2826 return (0); 2827 } 2828 2829 static int 2830 hdac_channel_getptr(kobj_t obj, void *data) 2831 { 2832 struct hdac_chan *ch = data; 2833 struct hdac_softc *sc = ch->devinfo->codec->sc; 2834 uint32_t ptr; 2835 2836 hdac_lock(sc); 2837 if (sc->polling != 0) 2838 ptr = ch->ptr; 2839 else 2840 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2841 hdac_unlock(sc); 2842 2843 /* 2844 * Round to available space and force 128 bytes aligment. 2845 */ 2846 ptr %= ch->blksz * ch->blkcnt; 2847 ptr &= ~0x7f; 2848 2849 return (ptr); 2850 } 2851 2852 static struct pcmchan_caps * 2853 hdac_channel_getcaps(kobj_t obj, void *data) 2854 { 2855 return (&((struct hdac_chan *)data)->caps); 2856 } 2857 2858 static kobj_method_t hdac_channel_methods[] = { 2859 KOBJMETHOD(channel_init, hdac_channel_init), 2860 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2861 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2862 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2863 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2864 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2865 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2866 { 0, 0 } 2867 }; 2868 CHANNEL_DECLARE(hdac_channel); 2869 2870 static int 2871 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2872 { 2873 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2874 struct hdac_softc *sc = devinfo->codec->sc; 2875 struct hdac_widget *w, *cw; 2876 struct hdac_audio_ctl *ctl; 2877 uint32_t mask, recmask, id; 2878 int i, j, softpcmvol; 2879 nid_t cad; 2880 2881 hdac_lock(sc); 2882 2883 mask = 0; 2884 recmask = 0; 2885 2886 id = hdac_codec_id(devinfo); 2887 cad = devinfo->codec->cad; 2888 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2889 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2890 sc->pci_subvendor) && 2891 hdac_hp_switch[i].id == id)) 2892 continue; 2893 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2894 if (w != NULL && w->enable != 0 2895 && w->type == 2896 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2897 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2898 hdac_command(sc, 2899 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2900 w->nid, 2901 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2902 HDAC_UNSOLTAG_EVENT_HP), cad); 2903 hdac_hp_switch_handler(devinfo); 2904 HDA_BOOTVERBOSE( 2905 device_printf(sc->dev, 2906 "HDA_DEBUG: Enabling headphone/speaker " 2907 "audio routing switching:\n"); 2908 device_printf(sc->dev, 2909 "HDA_DEBUG: \tindex=%d nid=%d " 2910 "pci_subvendor=0x%08x " 2911 "codec=0x%08x\n", 2912 i, w->nid, sc->pci_subvendor, id); 2913 ); 2914 } 2915 break; 2916 } 2917 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2918 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2919 sc->pci_subvendor) && 2920 hdac_eapd_switch[i].id == id)) 2921 continue; 2922 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2923 if (w == NULL || w->enable == 0) 2924 break; 2925 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2926 w->param.eapdbtl == HDAC_INVALID) 2927 break; 2928 mask |= SOUND_MASK_OGAIN; 2929 break; 2930 } 2931 2932 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2933 w = hdac_widget_get(devinfo, i); 2934 if (w == NULL || w->enable == 0) 2935 continue; 2936 mask |= w->ctlflags; 2937 if (!(w->pflags & HDA_ADC_RECSEL)) 2938 continue; 2939 for (j = 0; j < w->nconns; j++) { 2940 cw = hdac_widget_get(devinfo, w->conns[j]); 2941 if (cw == NULL || cw->enable == 0) 2942 continue; 2943 recmask |= cw->ctlflags; 2944 } 2945 } 2946 2947 if (!(mask & SOUND_MASK_PCM)) { 2948 softpcmvol = 1; 2949 mask |= SOUND_MASK_PCM; 2950 } else 2951 softpcmvol = (devinfo->function.audio.quirks & 2952 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2953 2954 i = 0; 2955 ctl = NULL; 2956 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2957 if (ctl->widget == NULL || ctl->enable == 0) 2958 continue; 2959 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2960 continue; 2961 if (ctl->step > 0) 2962 break; 2963 } 2964 2965 if (softpcmvol == 1 || ctl == NULL) { 2966 struct snddev_info *d = NULL; 2967 d = device_get_softc(sc->dev); 2968 if (d != NULL) { 2969 d->flags |= SD_F_SOFTPCMVOL; 2970 HDA_BOOTVERBOSE( 2971 device_printf(sc->dev, 2972 "HDA_DEBUG: %s Soft PCM volume\n", 2973 (softpcmvol == 1) ? 2974 "Forcing" : "Enabling"); 2975 ); 2976 } 2977 i = 0; 2978 /* 2979 * XXX Temporary quirk for STAC9220, until the parser 2980 * become smarter. 2981 */ 2982 if (id == HDA_CODEC_STAC9220) { 2983 mask |= SOUND_MASK_VOLUME; 2984 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2985 NULL) { 2986 if (ctl->widget == NULL || ctl->enable == 0) 2987 continue; 2988 if (ctl->widget->nid == 11 && ctl->index == 0) { 2989 ctl->ossmask = SOUND_MASK_VOLUME; 2990 ctl->ossval = 100 | (100 << 8); 2991 } else 2992 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2993 } 2994 } else if (id == HDA_CODEC_STAC9221) { 2995 mask |= SOUND_MASK_VOLUME; 2996 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2997 NULL) { 2998 if (ctl->widget == NULL) 2999 continue; 3000 if (ctl->widget->nid == 2 && ctl->index == 0) { 3001 ctl->enable = 1; 3002 ctl->ossmask = SOUND_MASK_VOLUME; 3003 ctl->ossval = 100 | (100 << 8); 3004 } else if (ctl->enable == 0) 3005 continue; 3006 else 3007 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3008 } 3009 } else { 3010 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3011 SOUND_MASK_PCM); 3012 if (!(mask & SOUND_MASK_VOLUME)) 3013 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3014 SOUND_MIXER_NONE); 3015 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3016 NULL) { 3017 if (ctl->widget == NULL || ctl->enable == 0) 3018 continue; 3019 if (!HDA_FLAG_MATCH(ctl->ossmask, 3020 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3021 continue; 3022 if (!(ctl->mute == 1 && ctl->step == 0)) 3023 ctl->enable = 0; 3024 } 3025 } 3026 } 3027 3028 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 3029 3030 mix_setrecdevs(m, recmask); 3031 mix_setdevs(m, mask); 3032 3033 hdac_unlock(sc); 3034 3035 return (0); 3036 } 3037 3038 static int 3039 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3040 unsigned left, unsigned right) 3041 { 3042 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3043 struct hdac_softc *sc = devinfo->codec->sc; 3044 struct hdac_widget *w; 3045 struct hdac_audio_ctl *ctl; 3046 uint32_t id, mute; 3047 int lvol, rvol, mlvol, mrvol; 3048 int i = 0; 3049 3050 hdac_lock(sc); 3051 if (dev == SOUND_MIXER_OGAIN) { 3052 uint32_t orig; 3053 /*if (left != right || !(left == 0 || left == 1)) { 3054 hdac_unlock(sc); 3055 return (-1); 3056 }*/ 3057 id = hdac_codec_id(devinfo); 3058 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3059 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3060 sc->pci_subvendor) && 3061 hdac_eapd_switch[i].id == id) 3062 break; 3063 } 3064 if (i >= HDAC_EAPD_SWITCH_LEN) { 3065 hdac_unlock(sc); 3066 return (-1); 3067 } 3068 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3069 if (w == NULL || 3070 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3071 w->param.eapdbtl == HDAC_INVALID) { 3072 hdac_unlock(sc); 3073 return (-1); 3074 } 3075 orig = w->param.eapdbtl; 3076 if (left == 0) 3077 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3078 else 3079 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3080 if (orig != w->param.eapdbtl) { 3081 uint32_t val; 3082 3083 if (hdac_eapd_switch[i].hp_switch != 0) 3084 hdac_hp_switch_handler(devinfo); 3085 val = w->param.eapdbtl; 3086 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3087 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3088 hdac_command(sc, 3089 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3090 w->nid, val), devinfo->codec->cad); 3091 } 3092 hdac_unlock(sc); 3093 return (left | (left << 8)); 3094 } 3095 if (dev == SOUND_MIXER_VOLUME) 3096 devinfo->function.audio.mvol = left | (right << 8); 3097 3098 mlvol = devinfo->function.audio.mvol & 0x7f; 3099 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3100 lvol = 0; 3101 rvol = 0; 3102 3103 i = 0; 3104 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3105 if (ctl->widget == NULL || ctl->enable == 0 || 3106 !(ctl->ossmask & (1 << dev))) 3107 continue; 3108 switch (dev) { 3109 case SOUND_MIXER_VOLUME: 3110 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3111 lvol = (lvol * ctl->step) / 100; 3112 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3113 rvol = (rvol * ctl->step) / 100; 3114 break; 3115 default: 3116 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3117 lvol = (left * mlvol) / 100; 3118 lvol = (lvol * ctl->step) / 100; 3119 rvol = (right * mrvol) / 100; 3120 rvol = (rvol * ctl->step) / 100; 3121 } else { 3122 lvol = (left * ctl->step) / 100; 3123 rvol = (right * ctl->step) / 100; 3124 } 3125 ctl->ossval = left | (right << 8); 3126 break; 3127 } 3128 mute = 0; 3129 if (ctl->step < 1) { 3130 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3131 (ctl->muted & HDA_AMP_MUTE_LEFT); 3132 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3133 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3134 } else { 3135 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3136 (ctl->muted & HDA_AMP_MUTE_LEFT); 3137 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3138 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3139 } 3140 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3141 } 3142 hdac_unlock(sc); 3143 3144 return (left | (right << 8)); 3145 } 3146 3147 static int 3148 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3149 { 3150 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3151 struct hdac_widget *w, *cw; 3152 struct hdac_softc *sc = devinfo->codec->sc; 3153 uint32_t ret = src, target; 3154 int i, j; 3155 3156 target = 0; 3157 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3158 if (src & (1 << i)) { 3159 target = 1 << i; 3160 break; 3161 } 3162 } 3163 3164 hdac_lock(sc); 3165 3166 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3167 w = hdac_widget_get(devinfo, i); 3168 if (w == NULL || w->enable == 0) 3169 continue; 3170 if (!(w->pflags & HDA_ADC_RECSEL)) 3171 continue; 3172 for (j = 0; j < w->nconns; j++) { 3173 cw = hdac_widget_get(devinfo, w->conns[j]); 3174 if (cw == NULL || cw->enable == 0) 3175 continue; 3176 if ((target == SOUND_MASK_VOLUME && 3177 cw->type != 3178 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3179 (target != SOUND_MASK_VOLUME && 3180 cw->type == 3181 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3182 continue; 3183 if (cw->ctlflags & target) { 3184 hdac_widget_connection_select(w, j); 3185 ret = target; 3186 j += w->nconns; 3187 } 3188 } 3189 } 3190 3191 hdac_unlock(sc); 3192 3193 return (ret); 3194 } 3195 3196 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3197 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3198 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3199 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3200 { 0, 0 } 3201 }; 3202 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3203 3204 /**************************************************************************** 3205 * int hdac_attach(device_t) 3206 * 3207 * Attach the device into the kernel. Interrupts usually won't be enabled 3208 * when this function is called. Setup everything that doesn't require 3209 * interrupts and defer probing of codecs until interrupts are enabled. 3210 ****************************************************************************/ 3211 static int 3212 hdac_attach(device_t dev) 3213 { 3214 struct hdac_softc *sc; 3215 int result; 3216 int i = 0; 3217 3218 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3219 if (sc == NULL) { 3220 device_printf(dev, "cannot allocate softc\n"); 3221 return (ENOMEM); 3222 } 3223 3224 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3225 if (sc->lock == NULL) { 3226 device_printf(dev, "mutex creation failed\n"); 3227 free(sc, M_DEVBUF); 3228 return (ENOMEM); 3229 } 3230 3231 sc->dev = dev; 3232 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3233 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3234 3235 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3236 /* Screw nx6325 - subdevice/subvendor swapped */ 3237 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3238 } 3239 3240 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3241 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3242 3243 sc->poll_ticks = 1; 3244 if (resource_int_value(device_get_name(sc->dev), 3245 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3246 sc->polling = 1; 3247 else 3248 sc->polling = 0; 3249 3250 sc->chan_size = pcm_getbuffersize(dev, 3251 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3252 3253 if (resource_int_value(device_get_name(sc->dev), 3254 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3255 i &= ~0x7f; 3256 if (i < 0x80) 3257 i = 0x80; 3258 sc->chan_blkcnt = sc->chan_size / i; 3259 i = 0; 3260 while (sc->chan_blkcnt >> i) 3261 i++; 3262 sc->chan_blkcnt = 1 << (i - 1); 3263 if (sc->chan_blkcnt < HDA_BDL_MIN) 3264 sc->chan_blkcnt = HDA_BDL_MIN; 3265 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3266 sc->chan_blkcnt = HDA_BDL_MAX; 3267 } else 3268 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3269 3270 result = bus_dma_tag_create(NULL, /* parent */ 3271 HDAC_DMA_ALIGNMENT, /* alignment */ 3272 0, /* boundary */ 3273 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3274 BUS_SPACE_MAXADDR, /* highaddr */ 3275 NULL, /* filtfunc */ 3276 NULL, /* fistfuncarg */ 3277 sc->chan_size, /* maxsize */ 3278 1, /* nsegments */ 3279 sc->chan_size, /* maxsegsz */ 3280 0, /* flags */ 3281 NULL, /* lockfunc */ 3282 NULL, /* lockfuncarg */ 3283 &sc->chan_dmat); /* dmat */ 3284 if (result != 0) { 3285 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3286 __func__, result); 3287 snd_mtxfree(sc->lock); 3288 free(sc, M_DEVBUF); 3289 return (ENXIO); 3290 } 3291 3292 3293 sc->hdabus = NULL; 3294 for (i = 0; i < HDAC_CODEC_MAX; i++) 3295 sc->codecs[i] = NULL; 3296 3297 pci_enable_busmaster(dev); 3298 3299 /* Allocate resources */ 3300 result = hdac_mem_alloc(sc); 3301 if (result != 0) 3302 goto hdac_attach_fail; 3303 result = hdac_irq_alloc(sc); 3304 if (result != 0) 3305 goto hdac_attach_fail; 3306 3307 /* Get Capabilities */ 3308 result = hdac_get_capabilities(sc); 3309 if (result != 0) 3310 goto hdac_attach_fail; 3311 3312 /* Allocate CORB and RIRB dma memory */ 3313 result = hdac_dma_alloc(sc, &sc->corb_dma, 3314 sc->corb_size * sizeof(uint32_t)); 3315 if (result != 0) 3316 goto hdac_attach_fail; 3317 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3318 sc->rirb_size * sizeof(struct hdac_rirb)); 3319 if (result != 0) 3320 goto hdac_attach_fail; 3321 3322 /* Quiesce everything */ 3323 hdac_reset(sc); 3324 3325 /* Disable PCI-Express QOS */ 3326 pci_write_config(sc->dev, 0x44, 3327 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3328 3329 /* Initialize the CORB and RIRB */ 3330 hdac_corb_init(sc); 3331 hdac_rirb_init(sc); 3332 3333 /* Defer remaining of initialization until interrupts are enabled */ 3334 sc->intrhook.ich_func = hdac_attach2; 3335 sc->intrhook.ich_arg = (void *)sc; 3336 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3337 sc->intrhook.ich_func = NULL; 3338 hdac_attach2((void *)sc); 3339 } 3340 3341 return (0); 3342 3343 hdac_attach_fail: 3344 hdac_dma_free(&sc->rirb_dma); 3345 hdac_dma_free(&sc->corb_dma); 3346 hdac_irq_free(sc); 3347 hdac_mem_free(sc); 3348 snd_mtxfree(sc->lock); 3349 free(sc, M_DEVBUF); 3350 3351 return (ENXIO); 3352 } 3353 3354 static void 3355 hdac_audio_parse(struct hdac_devinfo *devinfo) 3356 { 3357 struct hdac_softc *sc = devinfo->codec->sc; 3358 struct hdac_widget *w; 3359 uint32_t res; 3360 int i; 3361 nid_t cad, nid; 3362 3363 cad = devinfo->codec->cad; 3364 nid = devinfo->nid; 3365 3366 hdac_command(sc, 3367 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3368 3369 DELAY(100); 3370 3371 res = hdac_command(sc, 3372 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3373 3374 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3375 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3376 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3377 3378 HDA_BOOTVERBOSE( 3379 device_printf(sc->dev, " Vendor: 0x%08x\n", 3380 devinfo->vendor_id); 3381 device_printf(sc->dev, " Device: 0x%08x\n", 3382 devinfo->device_id); 3383 device_printf(sc->dev, " Revision: 0x%08x\n", 3384 devinfo->revision_id); 3385 device_printf(sc->dev, " Stepping: 0x%08x\n", 3386 devinfo->stepping_id); 3387 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3388 sc->pci_subvendor); 3389 device_printf(sc->dev, " Nodes: start=%d " 3390 "endnode=%d total=%d\n", 3391 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3392 ); 3393 3394 res = hdac_command(sc, 3395 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3396 cad); 3397 devinfo->function.audio.supp_stream_formats = res; 3398 3399 res = hdac_command(sc, 3400 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3401 cad); 3402 devinfo->function.audio.supp_pcm_size_rate = res; 3403 3404 res = hdac_command(sc, 3405 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3406 cad); 3407 devinfo->function.audio.outamp_cap = res; 3408 3409 res = hdac_command(sc, 3410 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3411 cad); 3412 devinfo->function.audio.inamp_cap = res; 3413 3414 if (devinfo->nodecnt > 0) { 3415 hdac_unlock(sc); 3416 devinfo->widget = (struct hdac_widget *)malloc( 3417 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3418 M_NOWAIT | M_ZERO); 3419 hdac_lock(sc); 3420 } else 3421 devinfo->widget = NULL; 3422 3423 if (devinfo->widget == NULL) { 3424 device_printf(sc->dev, "unable to allocate widgets!\n"); 3425 devinfo->endnode = devinfo->startnode; 3426 devinfo->nodecnt = 0; 3427 return; 3428 } 3429 3430 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3431 w = hdac_widget_get(devinfo, i); 3432 if (w == NULL) 3433 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3434 else { 3435 w->devinfo = devinfo; 3436 w->nid = i; 3437 w->enable = 1; 3438 w->selconn = -1; 3439 w->pflags = 0; 3440 w->ctlflags = 0; 3441 w->param.eapdbtl = HDAC_INVALID; 3442 hdac_widget_parse(w); 3443 } 3444 } 3445 } 3446 3447 static void 3448 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3449 { 3450 struct hdac_softc *sc = devinfo->codec->sc; 3451 struct hdac_audio_ctl *ctls; 3452 struct hdac_widget *w, *cw; 3453 int i, j, cnt, max, ocap, icap; 3454 int mute, offset, step, size; 3455 3456 /* XXX This is redundant */ 3457 max = 0; 3458 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3459 w = hdac_widget_get(devinfo, i); 3460 if (w == NULL || w->enable == 0) 3461 continue; 3462 if (w->param.outamp_cap != 0) 3463 max++; 3464 if (w->param.inamp_cap != 0) { 3465 switch (w->type) { 3466 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3467 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3468 for (j = 0; j < w->nconns; j++) { 3469 cw = hdac_widget_get(devinfo, 3470 w->conns[j]); 3471 if (cw == NULL || cw->enable == 0) 3472 continue; 3473 max++; 3474 } 3475 break; 3476 default: 3477 max++; 3478 break; 3479 } 3480 } 3481 } 3482 3483 devinfo->function.audio.ctlcnt = max; 3484 3485 if (max < 1) 3486 return; 3487 3488 hdac_unlock(sc); 3489 ctls = (struct hdac_audio_ctl *)malloc( 3490 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3491 hdac_lock(sc); 3492 3493 if (ctls == NULL) { 3494 /* Blekh! */ 3495 device_printf(sc->dev, "unable to allocate ctls!\n"); 3496 devinfo->function.audio.ctlcnt = 0; 3497 return; 3498 } 3499 3500 cnt = 0; 3501 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3502 if (cnt >= max) { 3503 device_printf(sc->dev, "%s: Ctl overflow!\n", 3504 __func__); 3505 break; 3506 } 3507 w = hdac_widget_get(devinfo, i); 3508 if (w == NULL || w->enable == 0) 3509 continue; 3510 ocap = w->param.outamp_cap; 3511 icap = w->param.inamp_cap; 3512 if (ocap != 0) { 3513 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3514 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3515 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3516 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3517 /*if (offset > step) { 3518 HDA_BOOTVERBOSE( 3519 device_printf(sc->dev, 3520 "HDA_DEBUG: BUGGY outamp: nid=%d " 3521 "[offset=%d > step=%d]\n", 3522 w->nid, offset, step); 3523 ); 3524 offset = step; 3525 }*/ 3526 ctls[cnt].enable = 1; 3527 ctls[cnt].widget = w; 3528 ctls[cnt].mute = mute; 3529 ctls[cnt].step = step; 3530 ctls[cnt].size = size; 3531 ctls[cnt].offset = offset; 3532 ctls[cnt].left = offset; 3533 ctls[cnt].right = offset; 3534 ctls[cnt++].dir = HDA_CTL_OUT; 3535 } 3536 3537 if (icap != 0) { 3538 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3539 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3540 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3541 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3542 /*if (offset > step) { 3543 HDA_BOOTVERBOSE( 3544 device_printf(sc->dev, 3545 "HDA_DEBUG: BUGGY inamp: nid=%d " 3546 "[offset=%d > step=%d]\n", 3547 w->nid, offset, step); 3548 ); 3549 offset = step; 3550 }*/ 3551 switch (w->type) { 3552 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3553 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3554 for (j = 0; j < w->nconns; j++) { 3555 if (cnt >= max) { 3556 device_printf(sc->dev, 3557 "%s: Ctl overflow!\n", 3558 __func__); 3559 break; 3560 } 3561 cw = hdac_widget_get(devinfo, 3562 w->conns[j]); 3563 if (cw == NULL || cw->enable == 0) 3564 continue; 3565 ctls[cnt].enable = 1; 3566 ctls[cnt].widget = w; 3567 ctls[cnt].childwidget = cw; 3568 ctls[cnt].index = j; 3569 ctls[cnt].mute = mute; 3570 ctls[cnt].step = step; 3571 ctls[cnt].size = size; 3572 ctls[cnt].offset = offset; 3573 ctls[cnt].left = offset; 3574 ctls[cnt].right = offset; 3575 ctls[cnt++].dir = HDA_CTL_IN; 3576 } 3577 break; 3578 default: 3579 if (cnt >= max) { 3580 device_printf(sc->dev, 3581 "%s: Ctl overflow!\n", 3582 __func__); 3583 break; 3584 } 3585 ctls[cnt].enable = 1; 3586 ctls[cnt].widget = w; 3587 ctls[cnt].mute = mute; 3588 ctls[cnt].step = step; 3589 ctls[cnt].size = size; 3590 ctls[cnt].offset = offset; 3591 ctls[cnt].left = offset; 3592 ctls[cnt].right = offset; 3593 ctls[cnt++].dir = HDA_CTL_IN; 3594 break; 3595 } 3596 } 3597 } 3598 3599 devinfo->function.audio.ctl = ctls; 3600 } 3601 3602 static const struct { 3603 uint32_t model; 3604 uint32_t id; 3605 uint32_t set, unset; 3606 } hdac_quirks[] = { 3607 /* 3608 * XXX Force stereo quirk. Monoural recording / playback 3609 * on few codecs (especially ALC880) seems broken or 3610 * perhaps unsupported. 3611 */ 3612 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3613 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3614 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3615 HDA_QUIRK_GPIO0, 0 }, 3616 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3617 HDA_QUIRK_GPIO0, 0 }, 3618 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3619 HDA_QUIRK_GPIO0, 0 }, 3620 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3621 HDA_QUIRK_EAPDINV, 0 }, 3622 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3623 HDA_QUIRK_EAPDINV, 0 }, 3624 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3625 HDA_QUIRK_GPIO1, 0 }, 3626 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3627 HDA_QUIRK_EAPDINV, 0 }, 3628 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3629 HDA_QUIRK_EAPDINV, 0 }, 3630 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3631 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3632 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3633 0, HDA_QUIRK_FORCESTEREO }, 3634 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3635 HDA_QUIRK_SOFTPCMVOL, 0 } 3636 }; 3637 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3638 3639 static void 3640 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3641 { 3642 struct hdac_widget *w; 3643 struct hdac_audio_ctl *ctl; 3644 uint32_t id, subvendor; 3645 int i; 3646 3647 id = hdac_codec_id(devinfo); 3648 subvendor = devinfo->codec->sc->pci_subvendor; 3649 3650 /* 3651 * Quirks 3652 */ 3653 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3654 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3655 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3656 continue; 3657 if (hdac_quirks[i].set != 0) 3658 devinfo->function.audio.quirks |= 3659 hdac_quirks[i].set; 3660 if (hdac_quirks[i].unset != 0) 3661 devinfo->function.audio.quirks &= 3662 ~(hdac_quirks[i].unset); 3663 } 3664 3665 switch (id) { 3666 case HDA_CODEC_ALC260: 3667 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3668 w = hdac_widget_get(devinfo, i); 3669 if (w == NULL || w->enable == 0) 3670 continue; 3671 if (w->type != 3672 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3673 continue; 3674 if (w->nid != 5) 3675 w->enable = 0; 3676 } 3677 if (subvendor == HP_XW4300_SUBVENDOR) { 3678 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 3679 if (ctl != NULL && ctl->widget != NULL) { 3680 ctl->ossmask = SOUND_MASK_SPEAKER; 3681 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3682 } 3683 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 3684 if (ctl != NULL && ctl->widget != NULL) { 3685 ctl->ossmask = SOUND_MASK_SPEAKER; 3686 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3687 } 3688 } 3689 break; 3690 case HDA_CODEC_ALC861: 3691 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3692 if (ctl != NULL) 3693 ctl->muted = HDA_AMP_MUTE_ALL; 3694 break; 3695 case HDA_CODEC_ALC880: 3696 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3697 w = hdac_widget_get(devinfo, i); 3698 if (w == NULL || w->enable == 0) 3699 continue; 3700 if (w->type == 3701 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3702 w->nid != 9 && w->nid != 29) { 3703 w->enable = 0; 3704 } else if (w->type != 3705 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3706 w->nid == 29) { 3707 w->type = 3708 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3709 w->param.widget_cap &= 3710 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3711 w->param.widget_cap |= 3712 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3713 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3714 strlcpy(w->name, "beep widget", sizeof(w->name)); 3715 } 3716 } 3717 break; 3718 case HDA_CODEC_ALC883: 3719 /* 3720 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 3721 * Clear vref cap for jack connectivity. 3722 */ 3723 w = hdac_widget_get(devinfo, 24); 3724 if (w != NULL && w->enable != 0 && w->type == 3725 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3726 (w->wclass.pin.config & 3727 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3728 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3729 w->wclass.pin.cap &= ~( 3730 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3731 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3732 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3733 w = hdac_widget_get(devinfo, 25); 3734 if (w != NULL && w->enable != 0 && w->type == 3735 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3736 (w->wclass.pin.config & 3737 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3738 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3739 w->wclass.pin.cap &= ~( 3740 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3741 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3742 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3743 /* 3744 * nid: 26 = Line-in, leave it alone. 3745 */ 3746 break; 3747 case HDA_CODEC_AD1981HD: 3748 w = hdac_widget_get(devinfo, 11); 3749 if (w != NULL && w->enable != 0 && w->nconns > 3) 3750 w->selconn = 3; 3751 if (subvendor == IBM_M52_SUBVENDOR) { 3752 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3753 if (ctl != NULL) 3754 ctl->ossmask = SOUND_MASK_SPEAKER; 3755 } 3756 break; 3757 case HDA_CODEC_AD1986A: 3758 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3759 w = hdac_widget_get(devinfo, i); 3760 if (w == NULL || w->enable == 0) 3761 continue; 3762 if (w->type != 3763 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3764 continue; 3765 if (w->nid != 3) 3766 w->enable = 0; 3767 } 3768 break; 3769 case HDA_CODEC_STAC9221: 3770 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3771 w = hdac_widget_get(devinfo, i); 3772 if (w == NULL || w->enable == 0) 3773 continue; 3774 if (w->type != 3775 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3776 continue; 3777 if (w->nid != 2) 3778 w->enable = 0; 3779 } 3780 break; 3781 case HDA_CODEC_STAC9221D: 3782 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3783 w = hdac_widget_get(devinfo, i); 3784 if (w == NULL || w->enable == 0) 3785 continue; 3786 if (w->type == 3787 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3788 w->nid != 6) 3789 w->enable = 0; 3790 3791 } 3792 break; 3793 default: 3794 break; 3795 } 3796 } 3797 3798 static int 3799 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3800 { 3801 int *dev = &devinfo->function.audio.ossidx; 3802 3803 while (*dev < SOUND_MIXER_NRDEVICES) { 3804 switch (*dev) { 3805 case SOUND_MIXER_VOLUME: 3806 case SOUND_MIXER_BASS: 3807 case SOUND_MIXER_TREBLE: 3808 case SOUND_MIXER_PCM: 3809 case SOUND_MIXER_SPEAKER: 3810 case SOUND_MIXER_LINE: 3811 case SOUND_MIXER_MIC: 3812 case SOUND_MIXER_CD: 3813 case SOUND_MIXER_RECLEV: 3814 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3815 (*dev)++; 3816 break; 3817 default: 3818 return (*dev)++; 3819 break; 3820 } 3821 } 3822 3823 return (-1); 3824 } 3825 3826 static int 3827 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3828 { 3829 struct hdac_widget *w; 3830 int i, ret = 0; 3831 3832 if (depth > HDA_PARSE_MAXDEPTH) 3833 return (0); 3834 w = hdac_widget_get(devinfo, nid); 3835 if (w == NULL || w->enable == 0) 3836 return (0); 3837 switch (w->type) { 3838 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3839 w->pflags |= HDA_DAC_PATH; 3840 ret = 1; 3841 break; 3842 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3843 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3844 for (i = 0; i < w->nconns; i++) { 3845 if (hdac_widget_find_dac_path(devinfo, 3846 w->conns[i], depth + 1) != 0) { 3847 if (w->selconn == -1) 3848 w->selconn = i; 3849 ret = 1; 3850 w->pflags |= HDA_DAC_PATH; 3851 } 3852 } 3853 break; 3854 default: 3855 break; 3856 } 3857 return (ret); 3858 } 3859 3860 static int 3861 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3862 { 3863 struct hdac_widget *w; 3864 int i, conndev, ret = 0; 3865 3866 if (depth > HDA_PARSE_MAXDEPTH) 3867 return (0); 3868 w = hdac_widget_get(devinfo, nid); 3869 if (w == NULL || w->enable == 0) 3870 return (0); 3871 switch (w->type) { 3872 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3873 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3874 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3875 for (i = 0; i < w->nconns; i++) { 3876 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3877 depth + 1) != 0) { 3878 if (w->selconn == -1) 3879 w->selconn = i; 3880 w->pflags |= HDA_ADC_PATH; 3881 ret = 1; 3882 } 3883 } 3884 break; 3885 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3886 conndev = w->wclass.pin.config & 3887 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3888 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3889 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3890 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3891 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3892 w->pflags |= HDA_ADC_PATH; 3893 ret = 1; 3894 } 3895 break; 3896 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3897 if (w->pflags & HDA_DAC_PATH) { 3898 w->pflags |= HDA_ADC_PATH; 3899 ret = 1; 3900 } 3901 break;*/ 3902 default: 3903 break; 3904 } 3905 return (ret); 3906 } 3907 3908 static uint32_t 3909 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3910 nid_t nid, nid_t pnid, int index, int depth) 3911 { 3912 struct hdac_widget *w, *pw; 3913 struct hdac_audio_ctl *ctl; 3914 uint32_t fl = 0; 3915 int i, ossdev, conndev, strategy; 3916 3917 if (depth > HDA_PARSE_MAXDEPTH) 3918 return (0); 3919 3920 w = hdac_widget_get(devinfo, nid); 3921 if (w == NULL || w->enable == 0) 3922 return (0); 3923 3924 pw = hdac_widget_get(devinfo, pnid); 3925 strategy = devinfo->function.audio.parsing_strategy; 3926 3927 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3928 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3929 for (i = 0; i < w->nconns; i++) { 3930 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3931 w->nid, i, depth + 1); 3932 } 3933 w->ctlflags |= fl; 3934 return (fl); 3935 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3936 (w->pflags & HDA_DAC_PATH)) { 3937 i = 0; 3938 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3939 if (ctl->enable == 0 || ctl->widget == NULL) 3940 continue; 3941 /* XXX This should be compressed! */ 3942 if ((ctl->widget->nid == w->nid) || 3943 (ctl->widget->nid == pnid && ctl->index == index && 3944 (ctl->dir & HDA_CTL_IN)) || 3945 (ctl->widget->nid == pnid && pw != NULL && 3946 pw->type == 3947 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3948 (pw->nconns < 2 || pw->selconn == index || 3949 pw->selconn == -1) && 3950 (ctl->dir & HDA_CTL_OUT)) || 3951 (strategy == HDA_PARSE_DIRECT && 3952 ctl->widget->nid == w->nid)) { 3953 /*if (pw != NULL && pw->selconn == -1) 3954 pw->selconn = index; 3955 fl |= SOUND_MASK_VOLUME; 3956 fl |= SOUND_MASK_PCM; 3957 ctl->ossmask |= SOUND_MASK_VOLUME; 3958 ctl->ossmask |= SOUND_MASK_PCM; 3959 ctl->ossdev = SOUND_MIXER_PCM;*/ 3960 if (!(w->ctlflags & SOUND_MASK_PCM) || 3961 (pw != NULL && 3962 !(pw->ctlflags & SOUND_MASK_PCM))) { 3963 fl |= SOUND_MASK_VOLUME; 3964 fl |= SOUND_MASK_PCM; 3965 ctl->ossmask |= SOUND_MASK_VOLUME; 3966 ctl->ossmask |= SOUND_MASK_PCM; 3967 ctl->ossdev = SOUND_MIXER_PCM; 3968 w->ctlflags |= SOUND_MASK_VOLUME; 3969 w->ctlflags |= SOUND_MASK_PCM; 3970 if (pw != NULL) { 3971 if (pw->selconn == -1) 3972 pw->selconn = index; 3973 pw->ctlflags |= 3974 SOUND_MASK_VOLUME; 3975 pw->ctlflags |= 3976 SOUND_MASK_PCM; 3977 } 3978 } 3979 } 3980 } 3981 w->ctlflags |= fl; 3982 return (fl); 3983 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3984 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3985 (w->pflags & HDA_ADC_PATH)) { 3986 conndev = w->wclass.pin.config & 3987 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3988 i = 0; 3989 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3990 if (ctl->enable == 0 || ctl->widget == NULL) 3991 continue; 3992 /* XXX This should be compressed! */ 3993 if (((ctl->widget->nid == pnid && ctl->index == index && 3994 (ctl->dir & HDA_CTL_IN)) || 3995 (ctl->widget->nid == pnid && pw != NULL && 3996 pw->type == 3997 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3998 (pw->nconns < 2 || pw->selconn == index || 3999 pw->selconn == -1) && 4000 (ctl->dir & HDA_CTL_OUT)) || 4001 (strategy == HDA_PARSE_DIRECT && 4002 ctl->widget->nid == w->nid)) && 4003 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4004 if (pw != NULL && pw->selconn == -1) 4005 pw->selconn = index; 4006 ossdev = 0; 4007 switch (conndev) { 4008 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4009 ossdev = SOUND_MIXER_MIC; 4010 break; 4011 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4012 ossdev = SOUND_MIXER_LINE; 4013 break; 4014 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4015 ossdev = SOUND_MIXER_CD; 4016 break; 4017 default: 4018 ossdev = 4019 hdac_audio_ctl_ossmixer_getnextdev( 4020 devinfo); 4021 if (ossdev < 0) 4022 ossdev = 0; 4023 break; 4024 } 4025 if (strategy == HDA_PARSE_MIXER) { 4026 fl |= SOUND_MASK_VOLUME; 4027 ctl->ossmask |= SOUND_MASK_VOLUME; 4028 } 4029 fl |= 1 << ossdev; 4030 ctl->ossmask |= 1 << ossdev; 4031 ctl->ossdev = ossdev; 4032 } 4033 } 4034 w->ctlflags |= fl; 4035 return (fl); 4036 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4037 i = 0; 4038 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4039 if (ctl->enable == 0 || ctl->widget == NULL) 4040 continue; 4041 /* XXX This should be compressed! */ 4042 if (((ctl->widget->nid == pnid && ctl->index == index && 4043 (ctl->dir & HDA_CTL_IN)) || 4044 (ctl->widget->nid == pnid && pw != NULL && 4045 pw->type == 4046 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4047 (pw->nconns < 2 || pw->selconn == index || 4048 pw->selconn == -1) && 4049 (ctl->dir & HDA_CTL_OUT)) || 4050 (strategy == HDA_PARSE_DIRECT && 4051 ctl->widget->nid == w->nid)) && 4052 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4053 if (pw != NULL && pw->selconn == -1) 4054 pw->selconn = index; 4055 fl |= SOUND_MASK_VOLUME; 4056 fl |= SOUND_MASK_SPEAKER; 4057 ctl->ossmask |= SOUND_MASK_VOLUME; 4058 ctl->ossmask |= SOUND_MASK_SPEAKER; 4059 ctl->ossdev = SOUND_MIXER_SPEAKER; 4060 } 4061 } 4062 w->ctlflags |= fl; 4063 return (fl); 4064 } 4065 return (0); 4066 } 4067 4068 static uint32_t 4069 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4070 { 4071 struct hdac_widget *w, *cw; 4072 struct hdac_audio_ctl *ctl; 4073 uint32_t fl; 4074 int i; 4075 4076 if (depth > HDA_PARSE_MAXDEPTH) 4077 return (0); 4078 4079 w = hdac_widget_get(devinfo, nid); 4080 if (w == NULL || w->enable == 0) 4081 return (0); 4082 /*if (!(w->pflags & HDA_ADC_PATH)) 4083 return (0); 4084 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4085 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4086 return (0);*/ 4087 i = 0; 4088 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4089 if (ctl->enable == 0 || ctl->widget == NULL) 4090 continue; 4091 if (ctl->widget->nid == nid) { 4092 ctl->ossmask |= SOUND_MASK_RECLEV; 4093 w->ctlflags |= SOUND_MASK_RECLEV; 4094 return (SOUND_MASK_RECLEV); 4095 } 4096 } 4097 for (i = 0; i < w->nconns; i++) { 4098 cw = hdac_widget_get(devinfo, w->conns[i]); 4099 if (cw == NULL || cw->enable == 0) 4100 continue; 4101 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4102 continue; 4103 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4104 if (fl != 0) { 4105 cw->ctlflags |= fl; 4106 w->ctlflags |= fl; 4107 return (fl); 4108 } 4109 } 4110 return (0); 4111 } 4112 4113 static int 4114 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4115 { 4116 struct hdac_widget *w, *cw; 4117 int i, child = 0; 4118 4119 if (depth > HDA_PARSE_MAXDEPTH) 4120 return (0); 4121 4122 w = hdac_widget_get(devinfo, nid); 4123 if (w == NULL || w->enable == 0) 4124 return (0); 4125 /*if (!(w->pflags & HDA_ADC_PATH)) 4126 return (0); 4127 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4128 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4129 return (0);*/ 4130 /* XXX weak! */ 4131 for (i = 0; i < w->nconns; i++) { 4132 cw = hdac_widget_get(devinfo, w->conns[i]); 4133 if (cw == NULL) 4134 continue; 4135 if (++child > 1) { 4136 w->pflags |= HDA_ADC_RECSEL; 4137 return (1); 4138 } 4139 } 4140 for (i = 0; i < w->nconns; i++) { 4141 if (hdac_audio_ctl_recsel_build(devinfo, 4142 w->conns[i], depth + 1) != 0) 4143 return (1); 4144 } 4145 return (0); 4146 } 4147 4148 static int 4149 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4150 { 4151 struct hdac_widget *w, *cw; 4152 int i, j, conndev, found_dac = 0; 4153 int strategy; 4154 4155 strategy = devinfo->function.audio.parsing_strategy; 4156 4157 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4158 w = hdac_widget_get(devinfo, i); 4159 if (w == NULL || w->enable == 0) 4160 continue; 4161 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4162 continue; 4163 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4164 continue; 4165 conndev = w->wclass.pin.config & 4166 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4167 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4168 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4169 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4170 continue; 4171 for (j = 0; j < w->nconns; j++) { 4172 cw = hdac_widget_get(devinfo, w->conns[j]); 4173 if (cw == NULL || cw->enable == 0) 4174 continue; 4175 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4176 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4177 cw->type == 4178 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4179 continue; 4180 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4181 != 0) { 4182 if (w->selconn == -1) 4183 w->selconn = j; 4184 w->pflags |= HDA_DAC_PATH; 4185 found_dac++; 4186 } 4187 } 4188 } 4189 4190 return (found_dac); 4191 } 4192 4193 static void 4194 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4195 { 4196 struct hdac_widget *w; 4197 struct hdac_audio_ctl *ctl; 4198 int i, j, dacs, strategy; 4199 4200 /* Construct DAC path */ 4201 strategy = HDA_PARSE_MIXER; 4202 devinfo->function.audio.parsing_strategy = strategy; 4203 HDA_BOOTVERBOSE( 4204 device_printf(devinfo->codec->sc->dev, 4205 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4206 HDA_WIDGET_PARSER_REV); 4207 ); 4208 dacs = hdac_audio_build_tree_strategy(devinfo); 4209 if (dacs == 0) { 4210 HDA_BOOTVERBOSE( 4211 device_printf(devinfo->codec->sc->dev, 4212 "HDA_DEBUG: HWiP: 0 DAC path found! " 4213 "Retrying parser " 4214 "using HDA_PARSE_DIRECT strategy.\n"); 4215 ); 4216 strategy = HDA_PARSE_DIRECT; 4217 devinfo->function.audio.parsing_strategy = strategy; 4218 dacs = hdac_audio_build_tree_strategy(devinfo); 4219 } 4220 4221 HDA_BOOTVERBOSE( 4222 device_printf(devinfo->codec->sc->dev, 4223 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4224 "strategy.\n", 4225 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4226 ); 4227 4228 /* Construct ADC path */ 4229 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4230 w = hdac_widget_get(devinfo, i); 4231 if (w == NULL || w->enable == 0) 4232 continue; 4233 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4234 continue; 4235 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4236 } 4237 4238 /* Output mixers */ 4239 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4240 w = hdac_widget_get(devinfo, i); 4241 if (w == NULL || w->enable == 0) 4242 continue; 4243 if ((strategy == HDA_PARSE_MIXER && 4244 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4245 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4246 && (w->pflags & HDA_DAC_PATH)) || 4247 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4248 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4249 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4250 w->nid, devinfo->startnode - 1, 0, 0); 4251 } else if (w->type == 4252 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4253 j = 0; 4254 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4255 NULL) { 4256 if (ctl->enable == 0 || ctl->widget == NULL) 4257 continue; 4258 if (ctl->widget->nid != w->nid) 4259 continue; 4260 ctl->ossmask |= SOUND_MASK_VOLUME; 4261 ctl->ossmask |= SOUND_MASK_SPEAKER; 4262 ctl->ossdev = SOUND_MIXER_SPEAKER; 4263 w->ctlflags |= SOUND_MASK_VOLUME; 4264 w->ctlflags |= SOUND_MASK_SPEAKER; 4265 } 4266 } 4267 } 4268 4269 /* Input mixers (rec) */ 4270 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4271 w = hdac_widget_get(devinfo, i); 4272 if (w == NULL || w->enable == 0) 4273 continue; 4274 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4275 w->pflags & HDA_ADC_PATH)) 4276 continue; 4277 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4278 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4279 } 4280 } 4281 4282 #define HDA_COMMIT_CONN (1 << 0) 4283 #define HDA_COMMIT_CTRL (1 << 1) 4284 #define HDA_COMMIT_EAPD (1 << 2) 4285 #define HDA_COMMIT_GPIO (1 << 3) 4286 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4287 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4288 4289 static void 4290 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4291 { 4292 struct hdac_softc *sc = devinfo->codec->sc; 4293 struct hdac_widget *w; 4294 nid_t cad; 4295 int i; 4296 4297 if (!(cfl & HDA_COMMIT_ALL)) 4298 return; 4299 4300 cad = devinfo->codec->cad; 4301 4302 if (cfl & HDA_COMMIT_GPIO) { 4303 uint32_t gdata, gmask, gdir; 4304 int commitgpio = 0; 4305 4306 gdata = 0; 4307 gmask = 0; 4308 gdir = 0; 4309 4310 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4311 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4312 0x7e7, 0), cad); 4313 4314 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4315 commitgpio = 1; 4316 else { 4317 for (i = 0; i < HDA_GPIO_MAX; i++) { 4318 if (!(devinfo->function.audio.quirks & 4319 (1 << i))) 4320 continue; 4321 if (commitgpio == 0) { 4322 commitgpio = 1; 4323 gdata = hdac_command(sc, 4324 HDA_CMD_GET_GPIO_DATA(cad, 4325 devinfo->nid), cad); 4326 gmask = hdac_command(sc, 4327 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4328 devinfo->nid), cad); 4329 gdir = hdac_command(sc, 4330 HDA_CMD_GET_GPIO_DIRECTION(cad, 4331 devinfo->nid), cad); 4332 HDA_BOOTVERBOSE( 4333 device_printf(sc->dev, 4334 "GPIO init: data=0x%08x " 4335 "mask=0x%08x dir=0x%08x\n", 4336 gdata, gmask, gdir); 4337 ); 4338 } 4339 gdata |= 1 << i; 4340 gmask |= 1 << i; 4341 gdir |= 1 << i; 4342 } 4343 } 4344 4345 if (commitgpio != 0) { 4346 HDA_BOOTVERBOSE( 4347 device_printf(sc->dev, 4348 "GPIO commit: data=0x%08x mask=0x%08x " 4349 "dir=0x%08x\n", 4350 gdata, gmask, gdir); 4351 ); 4352 hdac_command(sc, 4353 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4354 gmask), cad); 4355 hdac_command(sc, 4356 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4357 gdir), cad); 4358 hdac_command(sc, 4359 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4360 gdata), cad); 4361 } 4362 } 4363 4364 for (i = 0; i < devinfo->nodecnt; i++) { 4365 w = &devinfo->widget[i]; 4366 if (w == NULL || w->enable == 0) 4367 continue; 4368 if (cfl & HDA_COMMIT_CONN) { 4369 if (w->selconn == -1) 4370 w->selconn = 0; 4371 if (w->nconns > 0) 4372 hdac_widget_connection_select(w, w->selconn); 4373 } 4374 if ((cfl & HDA_COMMIT_CTRL) && 4375 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4376 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4377 (HDA_DAC_PATH | HDA_ADC_PATH)) 4378 device_printf(sc->dev, "WARNING: node %d " 4379 "participate both for DAC/ADC!\n", w->nid); 4380 if (w->pflags & HDA_DAC_PATH) { 4381 w->wclass.pin.ctrl &= 4382 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4383 if ((w->wclass.pin.config & 4384 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4385 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4386 w->wclass.pin.ctrl &= 4387 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4388 } else if (w->pflags & HDA_ADC_PATH) { 4389 w->wclass.pin.ctrl &= 4390 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4391 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4392 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4393 uint32_t pincap = w->wclass.pin.cap; 4394 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4395 w->wclass.pin.ctrl |= 4396 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4397 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4398 ); 4399 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4400 w->wclass.pin.ctrl |= 4401 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4402 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4403 ); 4404 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4405 w->wclass.pin.ctrl |= 4406 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4407 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4408 ); 4409 } 4410 } else 4411 w->wclass.pin.ctrl &= ~( 4412 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4413 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4414 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4415 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4416 hdac_command(sc, 4417 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4418 w->wclass.pin.ctrl), cad); 4419 } 4420 if ((cfl & HDA_COMMIT_EAPD) && 4421 w->param.eapdbtl != HDAC_INVALID) { 4422 uint32_t val; 4423 4424 val = w->param.eapdbtl; 4425 if (devinfo->function.audio.quirks & 4426 HDA_QUIRK_EAPDINV) 4427 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4428 hdac_command(sc, 4429 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4430 val), cad); 4431 4432 } 4433 DELAY(1000); 4434 } 4435 } 4436 4437 static void 4438 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4439 { 4440 struct hdac_softc *sc = devinfo->codec->sc; 4441 struct hdac_audio_ctl *ctl; 4442 int i; 4443 4444 devinfo->function.audio.mvol = 100 | (100 << 8); 4445 i = 0; 4446 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4447 if (ctl->enable == 0 || ctl->widget == NULL) { 4448 HDA_BOOTVERBOSE( 4449 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4450 i, (ctl->widget != NULL) ? 4451 ctl->widget->nid : -1); 4452 if (ctl->childwidget != NULL) 4453 printf(" childnid=%d", 4454 ctl->childwidget->nid); 4455 if (ctl->widget == NULL) 4456 printf(" NULL WIDGET!"); 4457 printf(" DISABLED\n"); 4458 ); 4459 continue; 4460 } 4461 HDA_BOOTVERBOSE( 4462 if (ctl->ossmask == 0) { 4463 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4464 i, ctl->widget->nid); 4465 if (ctl->childwidget != NULL) 4466 printf(" childnid=%d", 4467 ctl->childwidget->nid); 4468 printf(" Bind to NONE\n"); 4469 } 4470 ); 4471 if (ctl->step > 0) { 4472 ctl->ossval = (ctl->left * 100) / ctl->step; 4473 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4474 } else 4475 ctl->ossval = 0; 4476 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4477 ctl->left, ctl->right); 4478 } 4479 } 4480 4481 static int 4482 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4483 { 4484 struct hdac_chan *ch; 4485 struct hdac_widget *w; 4486 uint32_t cap, fmtcap, pcmcap, path; 4487 int i, type, ret, max; 4488 4489 if (dir == PCMDIR_PLAY) { 4490 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4491 ch = &devinfo->codec->sc->play; 4492 path = HDA_DAC_PATH; 4493 } else { 4494 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4495 ch = &devinfo->codec->sc->rec; 4496 path = HDA_ADC_PATH; 4497 } 4498 4499 ch->caps = hdac_caps; 4500 ch->caps.fmtlist = ch->fmtlist; 4501 ch->bit16 = 1; 4502 ch->bit32 = 0; 4503 ch->pcmrates[0] = 48000; 4504 ch->pcmrates[1] = 0; 4505 4506 ret = 0; 4507 fmtcap = devinfo->function.audio.supp_stream_formats; 4508 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4509 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4510 4511 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4512 w = hdac_widget_get(devinfo, i); 4513 if (w == NULL || w->enable == 0 || w->type != type || 4514 !(w->pflags & path)) 4515 continue; 4516 cap = w->param.widget_cap; 4517 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4518 continue;*/ 4519 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4520 continue; 4521 cap = w->param.supp_stream_formats; 4522 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4523 } 4524 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4525 }*/ 4526 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4527 continue; 4528 if (ret == 0) { 4529 fmtcap = w->param.supp_stream_formats; 4530 pcmcap = w->param.supp_pcm_size_rate; 4531 } else { 4532 fmtcap &= w->param.supp_stream_formats; 4533 pcmcap &= w->param.supp_pcm_size_rate; 4534 } 4535 ch->io[ret++] = i; 4536 } 4537 ch->io[ret] = -1; 4538 4539 ch->supp_stream_formats = fmtcap; 4540 ch->supp_pcm_size_rate = pcmcap; 4541 4542 /* 4543 * 8bit = 0 4544 * 16bit = 1 4545 * 20bit = 2 4546 * 24bit = 3 4547 * 32bit = 4 4548 */ 4549 if (ret > 0) { 4550 cap = pcmcap; 4551 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4552 ch->bit16 = 1; 4553 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4554 ch->bit16 = 0; 4555 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4556 ch->bit32 = 4; 4557 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4558 ch->bit32 = 3; 4559 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4560 ch->bit32 = 2; 4561 i = 0; 4562 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4563 ch->fmtlist[i++] = AFMT_S16_LE; 4564 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4565 if (ch->bit32 > 0) { 4566 if (!(devinfo->function.audio.quirks & 4567 HDA_QUIRK_FORCESTEREO)) 4568 ch->fmtlist[i++] = AFMT_S32_LE; 4569 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4570 } 4571 ch->fmtlist[i] = 0; 4572 i = 0; 4573 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4574 ch->pcmrates[i++] = 8000; 4575 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4576 ch->pcmrates[i++] = 11025; 4577 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4578 ch->pcmrates[i++] = 16000; 4579 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4580 ch->pcmrates[i++] = 22050; 4581 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4582 ch->pcmrates[i++] = 32000; 4583 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4584 ch->pcmrates[i++] = 44100; 4585 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4586 ch->pcmrates[i++] = 48000; 4587 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4588 ch->pcmrates[i++] = 88200; 4589 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4590 ch->pcmrates[i++] = 96000; 4591 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4592 ch->pcmrates[i++] = 176400; 4593 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4594 ch->pcmrates[i++] = 192000; 4595 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4596 ch->pcmrates[i] = 0; 4597 if (i > 0) { 4598 ch->caps.minspeed = ch->pcmrates[0]; 4599 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4600 } 4601 } 4602 4603 return (ret); 4604 } 4605 4606 static void 4607 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4608 { 4609 struct hdac_audio_ctl *ctl; 4610 struct hdac_softc *sc = devinfo->codec->sc; 4611 int i; 4612 uint32_t fl = 0; 4613 4614 4615 if (flag == 0) { 4616 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4617 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4618 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4619 } 4620 4621 i = 0; 4622 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4623 if (ctl->enable == 0 || ctl->widget == NULL || 4624 ctl->widget->enable == 0) 4625 continue; 4626 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4627 (flag != 0 && (ctl->ossmask & flag))) { 4628 if (banner != NULL) { 4629 device_printf(sc->dev, "\n"); 4630 device_printf(sc->dev, "%s\n", banner); 4631 } 4632 goto hdac_ctl_dump_it_all; 4633 } 4634 } 4635 4636 return; 4637 4638 hdac_ctl_dump_it_all: 4639 i = 0; 4640 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4641 if (ctl->enable == 0 || ctl->widget == NULL || 4642 ctl->widget->enable == 0) 4643 continue; 4644 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4645 (flag != 0 && (ctl->ossmask & flag)))) 4646 continue; 4647 if (flag == 0) { 4648 device_printf(sc->dev, "\n"); 4649 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4650 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4651 } 4652 device_printf(sc->dev, " |\n"); 4653 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4654 ctl->widget->nid, ctl->index); 4655 if (ctl->childwidget != NULL) 4656 printf("(nid: %2d) ", ctl->childwidget->nid); 4657 else 4658 printf(" "); 4659 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4660 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4661 ctl->ossmask); 4662 } 4663 } 4664 4665 static void 4666 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4667 { 4668 uint32_t cap; 4669 4670 cap = fcap; 4671 if (cap != 0) { 4672 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4673 device_printf(sc->dev, " Format:"); 4674 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4675 printf(" AC3"); 4676 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4677 printf(" FLOAT32"); 4678 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4679 printf(" PCM"); 4680 printf("\n"); 4681 } 4682 cap = pcmcap; 4683 if (cap != 0) { 4684 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4685 device_printf(sc->dev, " PCM size:"); 4686 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4687 printf(" 8"); 4688 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4689 printf(" 16"); 4690 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4691 printf(" 20"); 4692 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4693 printf(" 24"); 4694 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4695 printf(" 32"); 4696 printf("\n"); 4697 device_printf(sc->dev, " PCM rate:"); 4698 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4699 printf(" 8"); 4700 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4701 printf(" 11"); 4702 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4703 printf(" 16"); 4704 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4705 printf(" 22"); 4706 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4707 printf(" 32"); 4708 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4709 printf(" 44"); 4710 printf(" 48"); 4711 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4712 printf(" 88"); 4713 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4714 printf(" 96"); 4715 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4716 printf(" 176"); 4717 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4718 printf(" 192"); 4719 printf("\n"); 4720 } 4721 } 4722 4723 static void 4724 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4725 { 4726 uint32_t pincap, wcap; 4727 4728 pincap = w->wclass.pin.cap; 4729 wcap = w->param.widget_cap; 4730 4731 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4732 device_printf(sc->dev, " "); 4733 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4734 printf(" ISC"); 4735 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4736 printf(" TRQD"); 4737 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4738 printf(" PDC"); 4739 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4740 printf(" HP"); 4741 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4742 printf(" OUT"); 4743 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4744 printf(" IN"); 4745 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4746 printf(" BAL"); 4747 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4748 printf(" VREF["); 4749 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4750 printf(" 50"); 4751 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4752 printf(" 80"); 4753 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4754 printf(" 100"); 4755 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4756 printf(" GROUND"); 4757 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4758 printf(" HIZ"); 4759 printf(" ]"); 4760 } 4761 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4762 printf(" EAPD"); 4763 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4764 printf(" : UNSOL"); 4765 printf("\n"); 4766 device_printf(sc->dev, " Pin config: 0x%08x\n", 4767 w->wclass.pin.config); 4768 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4769 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4770 printf(" HP"); 4771 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4772 printf(" IN"); 4773 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4774 printf(" OUT"); 4775 printf("\n"); 4776 } 4777 4778 static void 4779 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4780 { 4781 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4782 device_printf(sc->dev, " " 4783 "mute=%d step=%d size=%d offset=%d\n", 4784 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4785 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4786 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4787 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4788 } 4789 4790 static void 4791 hdac_dump_nodes(struct hdac_devinfo *devinfo) 4792 { 4793 struct hdac_softc *sc = devinfo->codec->sc; 4794 struct hdac_widget *w, *cw; 4795 int i, j; 4796 4797 device_printf(sc->dev, "\n"); 4798 device_printf(sc->dev, "Default Parameter\n"); 4799 device_printf(sc->dev, "-----------------\n"); 4800 hdac_dump_audio_formats(sc, 4801 devinfo->function.audio.supp_stream_formats, 4802 devinfo->function.audio.supp_pcm_size_rate); 4803 device_printf(sc->dev, " IN amp: 0x%08x\n", 4804 devinfo->function.audio.inamp_cap); 4805 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4806 devinfo->function.audio.outamp_cap); 4807 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4808 w = hdac_widget_get(devinfo, i); 4809 if (w == NULL) { 4810 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4811 continue; 4812 } 4813 device_printf(sc->dev, "\n"); 4814 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4815 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4816 "DIGITAL" : "ANALOG", 4817 (w->enable == 0) ? " [DISABLED]" : ""); 4818 device_printf(sc->dev, " name: %s\n", w->name); 4819 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4820 w->param.widget_cap); 4821 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4822 w->pflags); 4823 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4824 w->ctlflags); 4825 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4826 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4827 hdac_dump_audio_formats(sc, 4828 w->param.supp_stream_formats, 4829 w->param.supp_pcm_size_rate); 4830 } else if (w->type == 4831 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4832 hdac_dump_pin(sc, w); 4833 if (w->param.eapdbtl != HDAC_INVALID) 4834 device_printf(sc->dev, " EAPD: 0x%08x\n", 4835 w->param.eapdbtl); 4836 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4837 w->param.outamp_cap != 0) 4838 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4839 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4840 w->param.inamp_cap != 0) 4841 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4842 device_printf(sc->dev, " connections: %d\n", w->nconns); 4843 for (j = 0; j < w->nconns; j++) { 4844 cw = hdac_widget_get(devinfo, w->conns[j]); 4845 device_printf(sc->dev, " |\n"); 4846 device_printf(sc->dev, " + <- nid=%d [%s]", 4847 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4848 if (cw == NULL) 4849 printf(" [UNKNOWN]"); 4850 else if (cw->enable == 0) 4851 printf(" [DISABLED]"); 4852 if (w->nconns > 1 && w->selconn == j && w->type != 4853 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4854 printf(" (selected)"); 4855 printf("\n"); 4856 } 4857 } 4858 4859 } 4860 4861 static int 4862 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4863 { 4864 struct hdac_widget *w, *cw; 4865 struct hdac_softc *sc = devinfo->codec->sc; 4866 int i; 4867 4868 if (depth > HDA_PARSE_MAXDEPTH) 4869 return (0); 4870 4871 w = hdac_widget_get(devinfo, nid); 4872 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4873 return (0); 4874 4875 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4876 device_printf(sc->dev, "\n"); 4877 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4878 device_printf(sc->dev, " ^\n"); 4879 device_printf(sc->dev, " |\n"); 4880 device_printf(sc->dev, " +-----<------+\n"); 4881 } else { 4882 device_printf(sc->dev, " ^\n"); 4883 device_printf(sc->dev, " |\n"); 4884 device_printf(sc->dev, " "); 4885 printf(" nid=%d [%s]\n", w->nid, w->name); 4886 } 4887 4888 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4889 return (1); 4890 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4891 for (i = 0; i < w->nconns; i++) { 4892 cw = hdac_widget_get(devinfo, w->conns[i]); 4893 if (cw == NULL || cw->enable == 0 || cw->type == 4894 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4895 continue; 4896 if (hdac_dump_dac_internal(devinfo, cw->nid, 4897 depth + 1) != 0) 4898 return (1); 4899 } 4900 } else if ((w->type == 4901 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4902 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4903 w->selconn > -1 && w->selconn < w->nconns) { 4904 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4905 depth + 1) != 0) 4906 return (1); 4907 } 4908 4909 return (0); 4910 } 4911 4912 static void 4913 hdac_dump_dac(struct hdac_devinfo *devinfo) 4914 { 4915 struct hdac_widget *w; 4916 struct hdac_softc *sc = devinfo->codec->sc; 4917 int i, printed = 0; 4918 4919 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4920 w = hdac_widget_get(devinfo, i); 4921 if (w == NULL || w->enable == 0) 4922 continue; 4923 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4924 !(w->pflags & HDA_DAC_PATH)) 4925 continue; 4926 if (printed == 0) { 4927 printed = 1; 4928 device_printf(sc->dev, "\n"); 4929 device_printf(sc->dev, "Playback path:\n"); 4930 } 4931 hdac_dump_dac_internal(devinfo, w->nid, 0); 4932 } 4933 } 4934 4935 static void 4936 hdac_dump_adc(struct hdac_devinfo *devinfo) 4937 { 4938 struct hdac_widget *w, *cw; 4939 struct hdac_softc *sc = devinfo->codec->sc; 4940 int i, j; 4941 int printed = 0; 4942 char ossdevs[256]; 4943 4944 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4945 w = hdac_widget_get(devinfo, i); 4946 if (w == NULL || w->enable == 0) 4947 continue; 4948 if (!(w->pflags & HDA_ADC_RECSEL)) 4949 continue; 4950 if (printed == 0) { 4951 printed = 1; 4952 device_printf(sc->dev, "\n"); 4953 device_printf(sc->dev, "Recording sources:\n"); 4954 } 4955 device_printf(sc->dev, "\n"); 4956 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4957 for (j = 0; j < w->nconns; j++) { 4958 cw = hdac_widget_get(devinfo, w->conns[j]); 4959 if (cw == NULL || cw->enable == 0) 4960 continue; 4961 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4962 ossdevs, sizeof(ossdevs)); 4963 device_printf(sc->dev, " |\n"); 4964 device_printf(sc->dev, " + <- nid=%d [%s]", 4965 cw->nid, cw->name); 4966 if (strlen(ossdevs) > 0) { 4967 printf(" [recsrc: %s]", ossdevs); 4968 } 4969 printf("\n"); 4970 } 4971 } 4972 } 4973 4974 static void 4975 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4976 { 4977 nid_t *nids; 4978 4979 if (pcnt > 0) { 4980 device_printf(sc->dev, "\n"); 4981 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4982 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4983 sc->play.supp_pcm_size_rate); 4984 device_printf(sc->dev, " DAC:"); 4985 for (nids = sc->play.io; *nids != -1; nids++) 4986 printf(" %d", *nids); 4987 printf("\n"); 4988 } 4989 4990 if (rcnt > 0) { 4991 device_printf(sc->dev, "\n"); 4992 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4993 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4994 sc->rec.supp_pcm_size_rate); 4995 device_printf(sc->dev, " ADC:"); 4996 for (nids = sc->rec.io; *nids != -1; nids++) 4997 printf(" %d", *nids); 4998 printf("\n"); 4999 } 5000 } 5001 5002 static void 5003 hdac_release_resources(struct hdac_softc *sc) 5004 { 5005 struct hdac_devinfo *devinfo = NULL; 5006 device_t *devlist = NULL; 5007 int i, devcount; 5008 5009 if (sc == NULL) 5010 return; 5011 5012 hdac_lock(sc); 5013 if (sc->polling != 0) 5014 callout_stop(&sc->poll_hdac); 5015 hdac_reset(sc); 5016 hdac_unlock(sc); 5017 snd_mtxfree(sc->lock); 5018 5019 device_get_children(sc->dev, &devlist, &devcount); 5020 for (i = 0; devlist != NULL && i < devcount; i++) { 5021 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5022 if (devinfo == NULL) 5023 continue; 5024 if (devinfo->widget != NULL) 5025 free(devinfo->widget, M_HDAC); 5026 if (devinfo->node_type == 5027 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5028 devinfo->function.audio.ctl != NULL) 5029 free(devinfo->function.audio.ctl, M_HDAC); 5030 free(devinfo, M_HDAC); 5031 device_delete_child(sc->dev, devlist[i]); 5032 } 5033 if (devlist != NULL) 5034 free(devlist, M_TEMP); 5035 5036 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5037 if (sc->codecs[i] != NULL) 5038 free(sc->codecs[i], M_HDAC); 5039 sc->codecs[i] = NULL; 5040 } 5041 5042 hdac_dma_free(&sc->rirb_dma); 5043 hdac_dma_free(&sc->corb_dma); 5044 if (sc->play.blkcnt > 0) 5045 hdac_dma_free(&sc->play.bdl_dma); 5046 if (sc->rec.blkcnt > 0) 5047 hdac_dma_free(&sc->rec.bdl_dma); 5048 hdac_irq_free(sc); 5049 hdac_mem_free(sc); 5050 free(sc, M_DEVBUF); 5051 5052 } 5053 5054 /* This function surely going to make its way into upper level someday. */ 5055 static void 5056 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5057 { 5058 const char *res = NULL; 5059 int i = 0, j, k, len, inv; 5060 5061 if (on != NULL) 5062 *on = 0; 5063 if (off != NULL) 5064 *off = 0; 5065 if (sc == NULL) 5066 return; 5067 if (resource_string_value(device_get_name(sc->dev), 5068 device_get_unit(sc->dev), "config", &res) != 0) 5069 return; 5070 if (!(res != NULL && strlen(res) > 0)) 5071 return; 5072 HDA_BOOTVERBOSE( 5073 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5074 ); 5075 for (;;) { 5076 while (res[i] != '\0' && 5077 (res[i] == ',' || isspace(res[i]) != 0)) 5078 i++; 5079 if (res[i] == '\0') { 5080 HDA_BOOTVERBOSE( 5081 printf("\n"); 5082 ); 5083 return; 5084 } 5085 j = i; 5086 while (res[j] != '\0' && 5087 !(res[j] == ',' || isspace(res[j]) != 0)) 5088 j++; 5089 len = j - i; 5090 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5091 inv = 2; 5092 else 5093 inv = 0; 5094 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5095 if (strncmp(res + i + inv, 5096 hdac_quirks_tab[k].key, len - inv) != 0) 5097 continue; 5098 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5099 break; 5100 HDA_BOOTVERBOSE( 5101 printf(" %s%s", (inv != 0) ? "no" : "", 5102 hdac_quirks_tab[k].key); 5103 ); 5104 if (inv == 0 && on != NULL) 5105 *on |= hdac_quirks_tab[k].value; 5106 else if (inv != 0 && off != NULL) 5107 *off |= hdac_quirks_tab[k].value; 5108 break; 5109 } 5110 i = j; 5111 } 5112 } 5113 5114 #ifdef SND_DYNSYSCTL 5115 static int 5116 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5117 { 5118 struct hdac_softc *sc; 5119 struct hdac_devinfo *devinfo; 5120 device_t dev; 5121 uint32_t ctl; 5122 int err, val; 5123 5124 dev = oidp->oid_arg1; 5125 devinfo = pcm_getdevinfo(dev); 5126 if (devinfo == NULL || devinfo->codec == NULL || 5127 devinfo->codec->sc == NULL) 5128 return (EINVAL); 5129 sc = devinfo->codec->sc; 5130 hdac_lock(sc); 5131 val = sc->polling; 5132 hdac_unlock(sc); 5133 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5134 5135 if (err || req->newptr == NULL) 5136 return (err); 5137 if (val < 0 || val > 1) 5138 return (EINVAL); 5139 5140 hdac_lock(sc); 5141 if (val != sc->polling) { 5142 if (hda_chan_active(sc) != 0) 5143 err = EBUSY; 5144 else if (val == 0) { 5145 callout_stop(&sc->poll_hdac); 5146 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5147 sc->rirb_size / 2); 5148 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5149 ctl |= HDAC_RIRBCTL_RINTCTL; 5150 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5151 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5152 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5153 sc->polling = 0; 5154 DELAY(1000); 5155 } else { 5156 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5157 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5158 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5159 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5160 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5161 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5162 sc); 5163 sc->polling = 1; 5164 DELAY(1000); 5165 } 5166 } 5167 hdac_unlock(sc); 5168 5169 return (err); 5170 } 5171 #endif 5172 5173 static void 5174 hdac_attach2(void *arg) 5175 { 5176 struct hdac_softc *sc; 5177 struct hdac_widget *w; 5178 struct hdac_audio_ctl *ctl; 5179 uint32_t quirks_on, quirks_off; 5180 int pcnt, rcnt; 5181 int i; 5182 char status[SND_STATUSLEN]; 5183 device_t *devlist = NULL; 5184 int devcount; 5185 struct hdac_devinfo *devinfo = NULL; 5186 5187 sc = (struct hdac_softc *)arg; 5188 5189 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5190 5191 HDA_BOOTVERBOSE( 5192 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5193 quirks_on, quirks_off); 5194 ); 5195 5196 hdac_lock(sc); 5197 5198 /* Remove ourselves from the config hooks */ 5199 if (sc->intrhook.ich_func != NULL) { 5200 config_intrhook_disestablish(&sc->intrhook); 5201 sc->intrhook.ich_func = NULL; 5202 } 5203 5204 /* Start the corb and rirb engines */ 5205 HDA_BOOTVERBOSE( 5206 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5207 ); 5208 hdac_corb_start(sc); 5209 HDA_BOOTVERBOSE( 5210 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5211 ); 5212 hdac_rirb_start(sc); 5213 5214 HDA_BOOTVERBOSE( 5215 device_printf(sc->dev, 5216 "HDA_DEBUG: Enabling controller interrupt...\n"); 5217 ); 5218 if (sc->polling == 0) 5219 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5220 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5221 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5222 HDAC_GCTL_UNSOL); 5223 5224 DELAY(1000); 5225 5226 HDA_BOOTVERBOSE( 5227 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5228 ); 5229 hdac_scan_codecs(sc); 5230 5231 device_get_children(sc->dev, &devlist, &devcount); 5232 for (i = 0; devlist != NULL && i < devcount; i++) { 5233 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5234 if (devinfo != NULL && devinfo->node_type == 5235 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5236 break; 5237 } else 5238 devinfo = NULL; 5239 } 5240 if (devlist != NULL) 5241 free(devlist, M_TEMP); 5242 5243 if (devinfo == NULL) { 5244 hdac_unlock(sc); 5245 device_printf(sc->dev, "Audio Function Group not found!\n"); 5246 hdac_release_resources(sc); 5247 return; 5248 } 5249 5250 HDA_BOOTVERBOSE( 5251 device_printf(sc->dev, 5252 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5253 devinfo->nid, devinfo->codec->cad); 5254 ); 5255 hdac_audio_parse(devinfo); 5256 HDA_BOOTVERBOSE( 5257 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5258 ); 5259 hdac_audio_ctl_parse(devinfo); 5260 HDA_BOOTVERBOSE( 5261 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5262 ); 5263 hdac_vendor_patch_parse(devinfo); 5264 if (quirks_on != 0) 5265 devinfo->function.audio.quirks |= quirks_on; 5266 if (quirks_off != 0) 5267 devinfo->function.audio.quirks &= ~quirks_off; 5268 5269 /* XXX Disable all DIGITAL path. */ 5270 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5271 w = hdac_widget_get(devinfo, i); 5272 if (w == NULL) 5273 continue; 5274 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5275 w->enable = 0; 5276 continue; 5277 } 5278 /* XXX Disable useless pin ? */ 5279 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5280 (w->wclass.pin.config & 5281 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5282 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5283 w->enable = 0; 5284 } 5285 i = 0; 5286 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5287 if (ctl->widget == NULL) 5288 continue; 5289 w = ctl->widget; 5290 if (w->enable == 0) 5291 ctl->enable = 0; 5292 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5293 ctl->enable = 0; 5294 w = ctl->childwidget; 5295 if (w == NULL) 5296 continue; 5297 if (w->enable == 0 || 5298 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5299 ctl->enable = 0; 5300 } 5301 5302 HDA_BOOTVERBOSE( 5303 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5304 ); 5305 hdac_audio_build_tree(devinfo); 5306 5307 HDA_BOOTVERBOSE( 5308 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5309 ); 5310 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5311 HDA_BOOTVERBOSE( 5312 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5313 ); 5314 hdac_audio_ctl_commit(devinfo); 5315 5316 HDA_BOOTVERBOSE( 5317 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5318 ); 5319 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5320 HDA_BOOTVERBOSE( 5321 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5322 ); 5323 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5324 5325 hdac_unlock(sc); 5326 HDA_BOOTVERBOSE( 5327 device_printf(sc->dev, 5328 "HDA_DEBUG: OSS mixer initialization...\n"); 5329 ); 5330 5331 /* 5332 * There is no point of return after this. If the driver failed, 5333 * so be it. Let the detach procedure do all the cleanup. 5334 */ 5335 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5336 device_printf(sc->dev, "Can't register mixer\n"); 5337 5338 if (pcnt > 0) 5339 pcnt = 1; 5340 if (rcnt > 0) 5341 rcnt = 1; 5342 5343 HDA_BOOTVERBOSE( 5344 device_printf(sc->dev, 5345 "HDA_DEBUG: Registering PCM channels...\n"); 5346 ); 5347 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5348 device_printf(sc->dev, "Can't register PCM\n"); 5349 5350 sc->registered++; 5351 5352 for (i = 0; i < pcnt; i++) 5353 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5354 for (i = 0; i < rcnt; i++) 5355 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5356 5357 #ifdef SND_DYNSYSCTL 5358 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5359 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5360 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5361 sysctl_hdac_polling, "I", "Enable polling mode"); 5362 #endif 5363 5364 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5365 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5366 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5367 pcm_setstatus(sc->dev, status); 5368 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5369 HDA_BOOTVERBOSE( 5370 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5371 hdac_codec_id(devinfo)); 5372 ); 5373 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5374 HDA_DRV_TEST_REV); 5375 5376 HDA_BOOTVERBOSE( 5377 if (devinfo->function.audio.quirks != 0) { 5378 device_printf(sc->dev, "\n"); 5379 device_printf(sc->dev, "HDA config/quirks:"); 5380 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5381 if (devinfo->function.audio.quirks & 5382 hdac_quirks_tab[i].value) 5383 printf(" %s", hdac_quirks_tab[i].key); 5384 } 5385 printf("\n"); 5386 } 5387 device_printf(sc->dev, "\n"); 5388 device_printf(sc->dev, "+-------------------+\n"); 5389 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5390 device_printf(sc->dev, "+-------------------+\n"); 5391 hdac_dump_nodes(devinfo); 5392 device_printf(sc->dev, "\n"); 5393 device_printf(sc->dev, "+------------------------+\n"); 5394 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5395 device_printf(sc->dev, "+------------------------+\n"); 5396 device_printf(sc->dev, "\n"); 5397 i = 0; 5398 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5399 device_printf(sc->dev, "%3d: nid=%d", i, 5400 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5401 if (ctl->childwidget != NULL) 5402 printf(" cnid=%d", ctl->childwidget->nid); 5403 printf(" dir=0x%x index=%d " 5404 "ossmask=0x%08x ossdev=%d%s\n", 5405 ctl->dir, ctl->index, 5406 ctl->ossmask, ctl->ossdev, 5407 (ctl->enable == 0) ? " [DISABLED]" : ""); 5408 } 5409 device_printf(sc->dev, "\n"); 5410 device_printf(sc->dev, "+-----------------------------------+\n"); 5411 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5412 device_printf(sc->dev, "+-----------------------------------+\n"); 5413 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5414 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5415 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5416 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5417 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5418 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5419 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5420 hdac_dump_ctls(devinfo, NULL, 0); 5421 hdac_dump_dac(devinfo); 5422 hdac_dump_adc(devinfo); 5423 device_printf(sc->dev, "\n"); 5424 device_printf(sc->dev, "+--------------------------------------+\n"); 5425 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5426 device_printf(sc->dev, "+--------------------------------------+\n"); 5427 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5428 ); 5429 5430 if (sc->polling != 0) { 5431 hdac_lock(sc); 5432 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5433 hdac_unlock(sc); 5434 } 5435 } 5436 5437 /**************************************************************************** 5438 * int hdac_detach(device_t) 5439 * 5440 * Detach and free up resources utilized by the hdac device. 5441 ****************************************************************************/ 5442 static int 5443 hdac_detach(device_t dev) 5444 { 5445 struct hdac_softc *sc = NULL; 5446 struct hdac_devinfo *devinfo = NULL; 5447 int err; 5448 5449 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5450 if (devinfo != NULL && devinfo->codec != NULL) 5451 sc = devinfo->codec->sc; 5452 if (sc == NULL) 5453 return (0); 5454 5455 if (sc->registered > 0) { 5456 err = pcm_unregister(dev); 5457 if (err != 0) 5458 return (err); 5459 } 5460 5461 hdac_release_resources(sc); 5462 5463 return (0); 5464 } 5465 5466 static device_method_t hdac_methods[] = { 5467 /* device interface */ 5468 DEVMETHOD(device_probe, hdac_probe), 5469 DEVMETHOD(device_attach, hdac_attach), 5470 DEVMETHOD(device_detach, hdac_detach), 5471 { 0, 0 } 5472 }; 5473 5474 static driver_t hdac_driver = { 5475 "pcm", 5476 hdac_methods, 5477 PCM_SOFTC_SIZE, 5478 }; 5479 5480 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5481 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5482 MODULE_VERSION(snd_hda, 1); 5483