1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70 #include <dev/sound/pcm/sound.h> 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <sys/ctype.h> 75 #include <sys/taskqueue.h> 76 77 #include <dev/sound/pci/hda/hdac_private.h> 78 #include <dev/sound/pci/hda/hdac_reg.h> 79 #include <dev/sound/pci/hda/hda_reg.h> 80 #include <dev/sound/pci/hda/hdac.h> 81 82 #include "mixer_if.h" 83 84 #define HDA_DRV_TEST_REV "20071129_0050" 85 #define HDA_WIDGET_PARSER_REV 1 86 87 SND_DECLARE_FILE("$FreeBSD$"); 88 89 #define HDA_BOOTVERBOSE(stmt) do { \ 90 if (bootverbose != 0 || snd_verbose > 3) { \ 91 stmt \ 92 } \ 93 } while(0) 94 95 #if 1 96 #undef HDAC_INTR_EXTRA 97 #define HDAC_INTR_EXTRA 1 98 #endif 99 100 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 101 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 102 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 103 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 104 105 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 106 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 107 (fl) == 0xffffffff || \ 108 (((fl) & 0xffff0000) == 0xffff0000 && \ 109 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 110 (((fl) & 0x0000ffff) == 0x0000ffff && \ 111 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 112 #define HDA_MATCH_ALL 0xffffffff 113 #define HDAC_INVALID 0xffffffff 114 115 /* Default controller / jack sense poll: 250ms */ 116 #define HDAC_POLL_INTERVAL max(hz >> 2, 1) 117 118 /* 119 * Make room for possible 4096 playback/record channels, in 100 years to come. 120 */ 121 #define HDAC_TRIGGER_NONE 0x00000000 122 #define HDAC_TRIGGER_PLAY 0x00000fff 123 #define HDAC_TRIGGER_REC 0x00fff000 124 #define HDAC_TRIGGER_UNSOL 0x80000000 125 126 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 127 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 128 129 /* Controller models */ 130 131 /* Intel */ 132 #define INTEL_VENDORID 0x8086 133 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 134 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 135 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 136 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 137 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 138 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 139 140 /* Nvidia */ 141 #define NVIDIA_VENDORID 0x10de 142 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 143 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 144 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 145 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 146 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 147 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 148 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 149 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 150 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 151 152 /* ATI */ 153 #define ATI_VENDORID 0x1002 154 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 155 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 156 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 157 158 /* VIA */ 159 #define VIA_VENDORID 0x1106 160 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 161 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 162 163 /* SiS */ 164 #define SIS_VENDORID 0x1039 165 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 166 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 167 168 /* OEM/subvendors */ 169 170 /* Intel */ 171 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 172 173 /* HP/Compaq */ 174 #define HP_VENDORID 0x103c 175 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 176 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 177 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 178 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 179 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 180 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 181 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 182 #define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 183 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 184 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 185 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 186 #define HP_NX6325_SUBVENDORX 0x103c30b0 187 188 /* Dell */ 189 #define DELL_VENDORID 0x1028 190 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 191 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 192 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 193 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 194 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 195 196 /* Clevo */ 197 #define CLEVO_VENDORID 0x1558 198 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 199 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 200 201 /* Acer */ 202 #define ACER_VENDORID 0x1025 203 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 204 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 205 #define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 206 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 207 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 208 209 /* Asus */ 210 #define ASUS_VENDORID 0x1043 211 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 212 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 213 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 214 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 215 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 216 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 217 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 218 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 219 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 220 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 221 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 222 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 223 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 224 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 225 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 226 227 /* IBM / Lenovo */ 228 #define IBM_VENDORID 0x1014 229 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 230 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 231 232 /* Lenovo */ 233 #define LENOVO_VENDORID 0x17aa 234 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 235 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 236 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 237 238 /* Samsung */ 239 #define SAMSUNG_VENDORID 0x144d 240 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 241 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 242 243 /* Medion ? */ 244 #define MEDION_VENDORID 0x161f 245 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 246 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 247 248 /* Apple Computer Inc. */ 249 #define APPLE_VENDORID 0x106b 250 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 251 252 /* 253 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 254 * instead of their own, which is beyond my comprehension 255 * (see HDA_CODEC_STAC9221 below). 256 */ 257 #define APPLE_INTEL_MAC 0x76808384 258 259 /* LG Electronics */ 260 #define LG_VENDORID 0x1854 261 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 262 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 263 264 /* Fujitsu Siemens */ 265 #define FS_VENDORID 0x1734 266 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 267 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 268 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 269 270 /* Fujitsu Limited */ 271 #define FL_VENDORID 0x10cf 272 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 273 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 274 275 /* Toshiba */ 276 #define TOSHIBA_VENDORID 0x1179 277 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 278 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 279 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 280 281 /* Micro-Star International (MSI) */ 282 #define MSI_VENDORID 0x1462 283 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 284 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 285 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 286 287 /* Giga-Byte Technology */ 288 #define GB_VENDORID 0x1458 289 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 290 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 291 292 /* Uniwill ? */ 293 #define UNIWILL_VENDORID 0x1584 294 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 295 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 296 297 298 /* Misc constants.. */ 299 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 300 #define HDA_AMP_MUTE_NONE (0) 301 #define HDA_AMP_MUTE_LEFT (1 << 0) 302 #define HDA_AMP_MUTE_RIGHT (1 << 1) 303 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 304 305 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 306 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 307 308 #define HDA_DAC_PATH (1 << 0) 309 #define HDA_ADC_PATH (1 << 1) 310 #define HDA_ADC_RECSEL (1 << 2) 311 312 #define HDA_DAC_LOCKED (1 << 3) 313 #define HDA_ADC_LOCKED (1 << 4) 314 315 #define HDA_CTL_OUT (1 << 0) 316 #define HDA_CTL_IN (1 << 1) 317 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 318 319 #define HDA_GPIO_MAX 8 320 /* 0 - 7 = GPIO , 8 = Flush */ 321 #define HDA_QUIRK_GPIO0 (1 << 0) 322 #define HDA_QUIRK_GPIO1 (1 << 1) 323 #define HDA_QUIRK_GPIO2 (1 << 2) 324 #define HDA_QUIRK_GPIO3 (1 << 3) 325 #define HDA_QUIRK_GPIO4 (1 << 4) 326 #define HDA_QUIRK_GPIO5 (1 << 5) 327 #define HDA_QUIRK_GPIO6 (1 << 6) 328 #define HDA_QUIRK_GPIO7 (1 << 7) 329 #define HDA_QUIRK_GPIOFLUSH (1 << 8) 330 331 /* 9 - 25 = anything else */ 332 #define HDA_QUIRK_SOFTPCMVOL (1 << 9) 333 #define HDA_QUIRK_FIXEDRATE (1 << 10) 334 #define HDA_QUIRK_FORCESTEREO (1 << 11) 335 #define HDA_QUIRK_EAPDINV (1 << 12) 336 #define HDA_QUIRK_DMAPOS (1 << 13) 337 338 /* 26 - 31 = vrefs */ 339 #define HDA_QUIRK_IVREF50 (1 << 26) 340 #define HDA_QUIRK_IVREF80 (1 << 27) 341 #define HDA_QUIRK_IVREF100 (1 << 28) 342 #define HDA_QUIRK_OVREF50 (1 << 29) 343 #define HDA_QUIRK_OVREF80 (1 << 30) 344 #define HDA_QUIRK_OVREF100 (1 << 31) 345 346 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 347 HDA_QUIRK_IVREF100) 348 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 349 HDA_QUIRK_OVREF100) 350 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 351 352 #define SOUND_MASK_SKIP (1 << 30) 353 #define SOUND_MASK_DISABLE (1 << 31) 354 355 #if __FreeBSD_version < 600000 356 #define taskqueue_drain(...) 357 #endif 358 359 static const struct { 360 char *key; 361 uint32_t value; 362 } hdac_quirks_tab[] = { 363 { "gpio0", HDA_QUIRK_GPIO0 }, 364 { "gpio1", HDA_QUIRK_GPIO1 }, 365 { "gpio2", HDA_QUIRK_GPIO2 }, 366 { "gpio3", HDA_QUIRK_GPIO3 }, 367 { "gpio4", HDA_QUIRK_GPIO4 }, 368 { "gpio5", HDA_QUIRK_GPIO5 }, 369 { "gpio6", HDA_QUIRK_GPIO6 }, 370 { "gpio7", HDA_QUIRK_GPIO7 }, 371 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 372 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 373 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 374 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 375 { "eapdinv", HDA_QUIRK_EAPDINV }, 376 { "dmapos", HDA_QUIRK_DMAPOS }, 377 { "ivref50", HDA_QUIRK_IVREF50 }, 378 { "ivref80", HDA_QUIRK_IVREF80 }, 379 { "ivref100", HDA_QUIRK_IVREF100 }, 380 { "ovref50", HDA_QUIRK_OVREF50 }, 381 { "ovref80", HDA_QUIRK_OVREF80 }, 382 { "ovref100", HDA_QUIRK_OVREF100 }, 383 { "ivref", HDA_QUIRK_IVREF }, 384 { "ovref", HDA_QUIRK_OVREF }, 385 { "vref", HDA_QUIRK_VREF }, 386 }; 387 #define HDAC_QUIRKS_TAB_LEN \ 388 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 389 390 #define HDA_BDL_MIN 2 391 #define HDA_BDL_MAX 256 392 #define HDA_BDL_DEFAULT HDA_BDL_MIN 393 394 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 395 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 396 397 #define HDA_BUFSZ_MIN 4096 398 #define HDA_BUFSZ_MAX 65536 399 #define HDA_BUFSZ_DEFAULT 16384 400 401 #define HDA_PARSE_MAXDEPTH 10 402 403 #define HDAC_UNSOLTAG_EVENT_HP 0x00 404 #define HDAC_UNSOLTAG_EVENT_TEST 0x01 405 406 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 407 408 enum { 409 HDA_PARSE_MIXER, 410 HDA_PARSE_DIRECT 411 }; 412 413 /* Default */ 414 static uint32_t hdac_fmt[] = { 415 AFMT_STEREO | AFMT_S16_LE, 416 0 417 }; 418 419 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 420 421 static const struct { 422 uint32_t model; 423 char *desc; 424 } hdac_devices[] = { 425 { HDA_INTEL_82801F, "Intel 82801F" }, 426 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 427 { HDA_INTEL_82801G, "Intel 82801G" }, 428 { HDA_INTEL_82801H, "Intel 82801H" }, 429 { HDA_INTEL_82801I, "Intel 82801I" }, 430 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 431 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 432 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 433 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 434 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 435 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 436 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 437 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 438 { HDA_ATI_SB450, "ATI SB450" }, 439 { HDA_ATI_SB600, "ATI SB600" }, 440 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 441 { HDA_SIS_966, "SiS 966" }, 442 /* Unknown */ 443 { HDA_INTEL_ALL, "Intel (Unknown)" }, 444 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 445 { HDA_ATI_ALL, "ATI (Unknown)" }, 446 { HDA_VIA_ALL, "VIA (Unknown)" }, 447 { HDA_SIS_ALL, "SiS (Unknown)" }, 448 }; 449 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 450 451 static const struct { 452 uint16_t vendor; 453 uint8_t reg; 454 uint8_t mask; 455 uint8_t enable; 456 } hdac_pcie_snoop[] = { 457 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 458 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 459 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 460 }; 461 #define HDAC_PCIESNOOP_LEN \ 462 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 463 464 static const struct { 465 uint32_t rate; 466 int valid; 467 uint16_t base; 468 uint16_t mul; 469 uint16_t div; 470 } hda_rate_tab[] = { 471 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 472 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 473 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 474 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 475 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 476 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 477 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 478 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 479 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 480 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 481 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 482 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 483 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 484 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 485 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 486 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 487 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 488 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 489 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 490 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 491 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 492 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 493 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 494 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 495 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 496 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 497 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 498 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 499 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 500 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 501 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 502 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 503 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 504 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 505 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 506 }; 507 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 508 509 /* All codecs you can eat... */ 510 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 511 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 512 513 /* Realtek */ 514 #define REALTEK_VENDORID 0x10ec 515 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 516 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 517 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 518 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 519 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 520 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 521 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 522 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 523 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 524 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 525 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 526 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 527 528 /* Analog Devices */ 529 #define ANALOGDEVICES_VENDORID 0x11d4 530 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 531 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 532 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 533 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 534 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 535 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 536 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 537 538 /* CMedia */ 539 #define CMEDIA_VENDORID 0x434d 540 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 541 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 542 543 /* Sigmatel */ 544 #define SIGMATEL_VENDORID 0x8384 545 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 546 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 547 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 548 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 549 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 550 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 551 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 552 553 /* 554 * Conexant 555 * 556 * Ok, the truth is, I don't have any idea at all whether 557 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 558 * place that tell me it is "Venice" is from its Windows driver INF. 559 * 560 * Venice - CX????? 561 * Waikiki - CX20551-22 562 */ 563 #define CONEXANT_VENDORID 0x14f1 564 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 565 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 566 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 567 568 /* VIA */ 569 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 570 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 571 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 572 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 573 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 574 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 575 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 576 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 577 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 578 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 579 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 580 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 581 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 582 583 584 /* Codecs */ 585 static const struct { 586 uint32_t id; 587 char *name; 588 } hdac_codecs[] = { 589 { HDA_CODEC_ALC260, "Realtek ALC260" }, 590 { HDA_CODEC_ALC262, "Realtek ALC262" }, 591 { HDA_CODEC_ALC268, "Realtek ALC268" }, 592 { HDA_CODEC_ALC660, "Realtek ALC660" }, 593 { HDA_CODEC_ALC861, "Realtek ALC861" }, 594 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 595 { HDA_CODEC_ALC880, "Realtek ALC880" }, 596 { HDA_CODEC_ALC882, "Realtek ALC882" }, 597 { HDA_CODEC_ALC883, "Realtek ALC883" }, 598 { HDA_CODEC_ALC885, "Realtek ALC885" }, 599 { HDA_CODEC_ALC888, "Realtek ALC888" }, 600 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 601 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 602 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 603 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 604 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 605 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 606 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 607 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 608 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 609 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 610 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 611 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 612 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 613 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 614 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 615 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 616 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 617 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 618 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 619 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 620 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 621 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 622 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 623 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 624 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 625 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 626 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 627 /* Unknown codec */ 628 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 629 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 630 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 631 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 632 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 633 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 634 }; 635 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 636 637 enum { 638 HDAC_HP_SWITCH_CTL, 639 HDAC_HP_SWITCH_CTRL, 640 HDAC_HP_SWITCH_DEBUG 641 }; 642 643 static const struct { 644 uint32_t model; 645 uint32_t id; 646 int type; 647 int inverted; 648 int polling; 649 int execsense; 650 nid_t hpnid; 651 nid_t spkrnid[8]; 652 nid_t eapdnid; 653 } hdac_hp_switch[] = { 654 /* Specific OEM models */ 655 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 656 0, 0, -1, 17, { 16, -1 }, 16 }, 657 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 658 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 659 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 660 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */ 661 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 662 0, 0, -1, 6, { 5, -1 }, 5 }, 663 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 664 0, 0, -1, 6, { 5, -1 }, 5 }, 665 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 666 0, 0, -1, 6, { 5, -1 }, 5 }, 667 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL, 668 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */ 669 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 670 0, 0, -1, 6, { 5, -1 }, -1 }, 671 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL, 672 0, 0, -1, 27, { 20, -1 }, -1 }, 673 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 674 0, 0, -1, 13, { 14, -1 }, -1 }, 675 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 676 0, 0, -1, 13, { 14, -1 }, -1 }, 677 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 678 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 679 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL, 680 0, 0, -1, 21, { 20, 22, -1 }, -1 }, 681 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 682 0, 0, -1, 10, { 13, -1 }, -1 }, 683 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 684 1, 0, -1, 26, { 27, -1 }, -1 }, 685 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 686 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */ 687 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 688 0, 0, -1, 27, { 20, -1 }, -1 }, 689 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 690 0, 0, -1, 20, { 21, -1 }, -1 }, 691 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 692 0, 0, -1, 20, { 21, -1 }, -1 }, 693 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 694 0, 0, -1, 20, { 21, -1 }, -1 }, 695 { ACER_A4710_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 696 0, 0, -1, 20, { 21, -1 }, -1 }, 697 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 698 0, 0, -1, 20, { 21, -1 }, -1 }, 699 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 700 0, 0, -1, 20, { 27, -1 }, -1 }, 701 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 702 0, 0, -1, 20, { 27, -1 }, -1 }, 703 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 704 0, 0, -1, 20, { 21, -1 }, -1 }, 705 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 706 0, 0, -1, 20, { 16, -1 }, -1 }, 707 /* 708 * All models that at least come from the same vendor with 709 * simmilar codec. 710 */ 711 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 712 0, 0, -1, 17, { 16, -1 }, 16 }, 713 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 714 0, 0, -1, 6, { 5, -1 }, 5 }, 715 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 716 0, 0, -1, 6, { 5, -1 }, -1 }, 717 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 718 0, 0, -1, 13, { 14, -1 }, -1 }, 719 #if 0 720 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 721 1, 0, -1, 26, { 27, -1 }, -1 }, 722 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 723 0, 0, -1, 20, { 21, -1 }, -1 }, 724 #endif 725 }; 726 #define HDAC_HP_SWITCH_LEN \ 727 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 728 729 static const struct { 730 uint32_t model; 731 uint32_t id; 732 nid_t eapdnid; 733 int hp_switch; 734 } hdac_eapd_switch[] = { 735 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 736 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 737 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 738 }; 739 #define HDAC_EAPD_SWITCH_LEN \ 740 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 741 742 /**************************************************************************** 743 * Function prototypes 744 ****************************************************************************/ 745 static void hdac_intr_handler(void *); 746 static int hdac_reset(struct hdac_softc *); 747 static int hdac_get_capabilities(struct hdac_softc *); 748 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 749 static int hdac_dma_alloc(struct hdac_softc *, 750 struct hdac_dma *, bus_size_t); 751 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 752 static int hdac_mem_alloc(struct hdac_softc *); 753 static void hdac_mem_free(struct hdac_softc *); 754 static int hdac_irq_alloc(struct hdac_softc *); 755 static void hdac_irq_free(struct hdac_softc *); 756 static void hdac_corb_init(struct hdac_softc *); 757 static void hdac_rirb_init(struct hdac_softc *); 758 static void hdac_corb_start(struct hdac_softc *); 759 static void hdac_rirb_start(struct hdac_softc *); 760 static void hdac_scan_codecs(struct hdac_softc *, int); 761 static int hdac_probe_codec(struct hdac_codec *); 762 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 763 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 764 765 static void hdac_attach2(void *); 766 767 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 768 uint32_t, int); 769 static void hdac_command_send_internal(struct hdac_softc *, 770 struct hdac_command_list *, int); 771 772 static int hdac_probe(device_t); 773 static int hdac_attach(device_t); 774 static int hdac_detach(device_t); 775 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 776 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 777 uint32_t, int, int); 778 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 779 nid_t, int, int); 780 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 781 nid_t, nid_t, int, int, int, int, int, int); 782 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 783 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 784 785 static int hdac_rirb_flush(struct hdac_softc *sc); 786 static int hdac_unsolq_flush(struct hdac_softc *sc); 787 788 #define hdac_command(a1, a2, a3) \ 789 hdac_command_sendone_internal(a1, a2, a3) 790 791 #define hdac_codec_id(d) \ 792 ((uint32_t)((d == NULL) ? 0x00000000 : \ 793 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 794 ((uint32_t)(d)->device_id & 0x0000ffff)))) 795 796 static char * 797 hdac_codec_name(struct hdac_devinfo *devinfo) 798 { 799 uint32_t id; 800 int i; 801 802 id = hdac_codec_id(devinfo); 803 804 for (i = 0; i < HDAC_CODECS_LEN; i++) { 805 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 806 return (hdac_codecs[i].name); 807 } 808 809 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 810 } 811 812 static char * 813 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 814 { 815 static char *ossname[] = SOUND_DEVICE_NAMES; 816 static char *unknown = "???"; 817 int i; 818 819 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 820 if (devmask & (1 << i)) 821 return (ossname[i]); 822 } 823 return (unknown); 824 } 825 826 static void 827 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 828 { 829 static char *ossname[] = SOUND_DEVICE_NAMES; 830 int i, first = 1; 831 832 bzero(buf, len); 833 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 834 if (mask & (1 << i)) { 835 if (first == 0) 836 strlcat(buf, ", ", len); 837 strlcat(buf, ossname[i], len); 838 first = 0; 839 } 840 } 841 } 842 843 static struct hdac_audio_ctl * 844 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 845 { 846 if (devinfo == NULL || 847 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 848 index == NULL || devinfo->function.audio.ctl == NULL || 849 devinfo->function.audio.ctlcnt < 1 || 850 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 851 return (NULL); 852 return (&devinfo->function.audio.ctl[(*index)++]); 853 } 854 855 static struct hdac_audio_ctl * 856 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 857 int index, int cnt) 858 { 859 struct hdac_audio_ctl *ctl, *retctl = NULL; 860 int i, at, atindex, found = 0; 861 862 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 863 return (NULL); 864 865 at = cnt; 866 if (at == 0) 867 at = 1; 868 else if (at < 0) 869 at = -1; 870 atindex = index; 871 if (atindex < 0) 872 atindex = -1; 873 874 i = 0; 875 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 876 if (ctl->enable == 0 || ctl->widget == NULL) 877 continue; 878 if (!(ctl->widget->nid == nid && (atindex == -1 || 879 ctl->index == atindex))) 880 continue; 881 found++; 882 if (found == cnt) 883 return (ctl); 884 retctl = ctl; 885 } 886 887 return ((at == -1) ? retctl : NULL); 888 } 889 890 static void 891 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 892 { 893 struct hdac_softc *sc; 894 struct hdac_widget *w; 895 struct hdac_audio_ctl *ctl; 896 uint32_t val, id, res; 897 int i = 0, j, timeout, forcemute; 898 nid_t cad; 899 900 if (devinfo == NULL || devinfo->codec == NULL || 901 devinfo->codec->sc == NULL) 902 return; 903 904 sc = devinfo->codec->sc; 905 cad = devinfo->codec->cad; 906 id = hdac_codec_id(devinfo); 907 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 908 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 909 sc->pci_subvendor) && 910 hdac_hp_switch[i].id == id) 911 break; 912 } 913 914 if (i >= HDAC_HP_SWITCH_LEN) 915 return; 916 917 forcemute = 0; 918 if (hdac_hp_switch[i].eapdnid != -1) { 919 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 920 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 921 forcemute = (w->param.eapdbtl & 922 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 923 } 924 925 if (hdac_hp_switch[i].execsense != -1) 926 hdac_command(sc, 927 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 928 hdac_hp_switch[i].execsense), cad); 929 930 timeout = 10000; 931 do { 932 res = hdac_command(sc, 933 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 934 cad); 935 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 936 break; 937 DELAY(10); 938 } while (--timeout != 0); 939 940 HDA_BOOTVERBOSE( 941 device_printf(sc->dev, 942 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 943 hdac_hp_switch[i].hpnid, timeout, res); 944 ); 945 946 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 947 res ^= hdac_hp_switch[i].inverted; 948 949 switch (hdac_hp_switch[i].type) { 950 case HDAC_HP_SWITCH_CTL: 951 ctl = hdac_audio_ctl_amp_get(devinfo, 952 hdac_hp_switch[i].hpnid, 0, 1); 953 if (ctl != NULL) { 954 val = (res != 0 && forcemute == 0) ? 955 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 956 if (val != ctl->muted) { 957 ctl->muted = val; 958 hdac_audio_ctl_amp_set(ctl, 959 HDA_AMP_MUTE_DEFAULT, ctl->left, 960 ctl->right); 961 } 962 } 963 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 964 ctl = hdac_audio_ctl_amp_get(devinfo, 965 hdac_hp_switch[i].spkrnid[j], 0, 1); 966 if (ctl == NULL) 967 continue; 968 val = (res != 0 || forcemute == 1) ? 969 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 970 if (val == ctl->muted) 971 continue; 972 ctl->muted = val; 973 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 974 ctl->left, ctl->right); 975 } 976 break; 977 case HDAC_HP_SWITCH_CTRL: 978 if (res != 0) { 979 /* HP in */ 980 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 981 if (w != NULL && w->type == 982 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 983 if (forcemute == 0) 984 val = w->wclass.pin.ctrl | 985 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 986 else 987 val = w->wclass.pin.ctrl & 988 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 989 if (val != w->wclass.pin.ctrl) { 990 w->wclass.pin.ctrl = val; 991 hdac_command(sc, 992 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 993 w->nid, w->wclass.pin.ctrl), cad); 994 } 995 } 996 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 997 w = hdac_widget_get(devinfo, 998 hdac_hp_switch[i].spkrnid[j]); 999 if (w == NULL || w->type != 1000 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1001 continue; 1002 val = w->wclass.pin.ctrl & 1003 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1004 if (val == w->wclass.pin.ctrl) 1005 continue; 1006 w->wclass.pin.ctrl = val; 1007 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1008 cad, w->nid, w->wclass.pin.ctrl), cad); 1009 } 1010 } else { 1011 /* HP out */ 1012 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 1013 if (w != NULL && w->type == 1014 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1015 val = w->wclass.pin.ctrl & 1016 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1017 if (val != w->wclass.pin.ctrl) { 1018 w->wclass.pin.ctrl = val; 1019 hdac_command(sc, 1020 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1021 w->nid, w->wclass.pin.ctrl), cad); 1022 } 1023 } 1024 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1025 w = hdac_widget_get(devinfo, 1026 hdac_hp_switch[i].spkrnid[j]); 1027 if (w == NULL || w->type != 1028 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1029 continue; 1030 if (forcemute == 0) 1031 val = w->wclass.pin.ctrl | 1032 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1033 else 1034 val = w->wclass.pin.ctrl & 1035 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1036 if (val == w->wclass.pin.ctrl) 1037 continue; 1038 w->wclass.pin.ctrl = val; 1039 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1040 cad, w->nid, w->wclass.pin.ctrl), cad); 1041 } 1042 } 1043 break; 1044 case HDAC_HP_SWITCH_DEBUG: 1045 if (hdac_hp_switch[i].execsense != -1) 1046 hdac_command(sc, 1047 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 1048 hdac_hp_switch[i].execsense), cad); 1049 res = hdac_command(sc, 1050 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1051 device_printf(sc->dev, 1052 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1053 hdac_hp_switch[i].hpnid, res); 1054 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1055 w = hdac_widget_get(devinfo, 1056 hdac_hp_switch[i].spkrnid[j]); 1057 if (w == NULL || w->type != 1058 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1059 continue; 1060 if (hdac_hp_switch[i].execsense != -1) 1061 hdac_command(sc, 1062 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1063 hdac_hp_switch[i].execsense), cad); 1064 res = hdac_command(sc, 1065 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1066 device_printf(sc->dev, 1067 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1068 j + 1, w->nid, res); 1069 } 1070 break; 1071 default: 1072 break; 1073 } 1074 } 1075 1076 static void 1077 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1078 { 1079 struct hdac_softc *sc; 1080 struct hdac_devinfo *devinfo = NULL; 1081 device_t *devlist = NULL; 1082 int devcount, i; 1083 1084 if (codec == NULL || codec->sc == NULL) 1085 return; 1086 1087 sc = codec->sc; 1088 1089 HDA_BOOTVERBOSE( 1090 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1091 ); 1092 1093 device_get_children(sc->dev, &devlist, &devcount); 1094 for (i = 0; devlist != NULL && i < devcount; i++) { 1095 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1096 if (devinfo != NULL && devinfo->node_type == 1097 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1098 devinfo->codec != NULL && 1099 devinfo->codec->cad == codec->cad) { 1100 break; 1101 } else 1102 devinfo = NULL; 1103 } 1104 if (devlist != NULL) 1105 free(devlist, M_TEMP); 1106 1107 if (devinfo == NULL) 1108 return; 1109 1110 switch (tag) { 1111 case HDAC_UNSOLTAG_EVENT_HP: 1112 hdac_hp_switch_handler(devinfo); 1113 break; 1114 case HDAC_UNSOLTAG_EVENT_TEST: 1115 device_printf(sc->dev, "Unsol Test!\n"); 1116 break; 1117 default: 1118 break; 1119 } 1120 } 1121 1122 static int 1123 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1124 { 1125 /* XXX to be removed */ 1126 #ifdef HDAC_INTR_EXTRA 1127 uint32_t res; 1128 #endif 1129 1130 if (!(ch->flags & HDAC_CHN_RUNNING)) 1131 return (0); 1132 1133 /* XXX to be removed */ 1134 #ifdef HDAC_INTR_EXTRA 1135 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1136 #endif 1137 1138 /* XXX to be removed */ 1139 #ifdef HDAC_INTR_EXTRA 1140 HDA_BOOTVERBOSE( 1141 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1142 device_printf(sc->dev, 1143 "PCMDIR_%s intr triggered beyond stream boundary:" 1144 "%08x\n", 1145 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1146 ); 1147 #endif 1148 1149 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1150 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1151 1152 /* XXX to be removed */ 1153 #ifdef HDAC_INTR_EXTRA 1154 if (res & HDAC_SDSTS_BCIS) { 1155 #endif 1156 return (1); 1157 /* XXX to be removed */ 1158 #ifdef HDAC_INTR_EXTRA 1159 } 1160 #endif 1161 1162 return (0); 1163 } 1164 1165 /**************************************************************************** 1166 * void hdac_intr_handler(void *) 1167 * 1168 * Interrupt handler. Processes interrupts received from the hdac. 1169 ****************************************************************************/ 1170 static void 1171 hdac_intr_handler(void *context) 1172 { 1173 struct hdac_softc *sc; 1174 uint32_t intsts; 1175 uint8_t rirbsts; 1176 struct hdac_rirb *rirb_base; 1177 uint32_t trigger; 1178 1179 sc = (struct hdac_softc *)context; 1180 1181 hdac_lock(sc); 1182 if (sc->polling != 0) { 1183 hdac_unlock(sc); 1184 return; 1185 } 1186 1187 /* Do we have anything to do? */ 1188 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1189 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1190 hdac_unlock(sc); 1191 return; 1192 } 1193 1194 trigger = 0; 1195 1196 /* Was this a controller interrupt? */ 1197 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1198 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1199 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1200 /* Get as many responses that we can */ 1201 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1202 HDAC_WRITE_1(&sc->mem, 1203 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1204 if (hdac_rirb_flush(sc) != 0) 1205 trigger |= HDAC_TRIGGER_UNSOL; 1206 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1207 } 1208 /* XXX to be removed */ 1209 /* Clear interrupt and exit */ 1210 #ifdef HDAC_INTR_EXTRA 1211 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1212 #endif 1213 } 1214 1215 if (intsts & HDAC_INTSTS_SIS_MASK) { 1216 if ((intsts & (1 << sc->num_iss)) && 1217 hdac_stream_intr(sc, &sc->play) != 0) 1218 trigger |= HDAC_TRIGGER_PLAY; 1219 if ((intsts & (1 << 0)) && 1220 hdac_stream_intr(sc, &sc->rec) != 0) 1221 trigger |= HDAC_TRIGGER_REC; 1222 /* XXX to be removed */ 1223 #ifdef HDAC_INTR_EXTRA 1224 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1225 HDAC_INTSTS_SIS_MASK); 1226 #endif 1227 } 1228 1229 hdac_unlock(sc); 1230 1231 if (trigger & HDAC_TRIGGER_PLAY) 1232 chn_intr(sc->play.c); 1233 if (trigger & HDAC_TRIGGER_REC) 1234 chn_intr(sc->rec.c); 1235 if (trigger & HDAC_TRIGGER_UNSOL) 1236 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1237 } 1238 1239 /**************************************************************************** 1240 * int hdac_reset(hdac_softc *) 1241 * 1242 * Reset the hdac to a quiescent and known state. 1243 ****************************************************************************/ 1244 static int 1245 hdac_reset(struct hdac_softc *sc) 1246 { 1247 uint32_t gctl; 1248 int count, i; 1249 1250 /* 1251 * Stop all Streams DMA engine 1252 */ 1253 for (i = 0; i < sc->num_iss; i++) 1254 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1255 for (i = 0; i < sc->num_oss; i++) 1256 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1257 for (i = 0; i < sc->num_bss; i++) 1258 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1259 1260 /* 1261 * Stop Control DMA engines. 1262 */ 1263 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1264 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1265 1266 /* 1267 * Reset DMA position buffer. 1268 */ 1269 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1270 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1271 1272 /* 1273 * Reset the controller. The reset must remain asserted for 1274 * a minimum of 100us. 1275 */ 1276 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1277 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1278 count = 10000; 1279 do { 1280 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1281 if (!(gctl & HDAC_GCTL_CRST)) 1282 break; 1283 DELAY(10); 1284 } while (--count); 1285 if (gctl & HDAC_GCTL_CRST) { 1286 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1287 return (ENXIO); 1288 } 1289 DELAY(100); 1290 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1291 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1292 count = 10000; 1293 do { 1294 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1295 if (gctl & HDAC_GCTL_CRST) 1296 break; 1297 DELAY(10); 1298 } while (--count); 1299 if (!(gctl & HDAC_GCTL_CRST)) { 1300 device_printf(sc->dev, "Device stuck in reset\n"); 1301 return (ENXIO); 1302 } 1303 1304 /* 1305 * Wait for codecs to finish their own reset sequence. The delay here 1306 * should be of 250us but for some reasons, on it's not enough on my 1307 * computer. Let's use twice as much as necessary to make sure that 1308 * it's reset properly. 1309 */ 1310 DELAY(1000); 1311 1312 return (0); 1313 } 1314 1315 1316 /**************************************************************************** 1317 * int hdac_get_capabilities(struct hdac_softc *); 1318 * 1319 * Retreive the general capabilities of the hdac; 1320 * Number of Input Streams 1321 * Number of Output Streams 1322 * Number of bidirectional Streams 1323 * 64bit ready 1324 * CORB and RIRB sizes 1325 ****************************************************************************/ 1326 static int 1327 hdac_get_capabilities(struct hdac_softc *sc) 1328 { 1329 uint16_t gcap; 1330 uint8_t corbsize, rirbsize; 1331 1332 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1333 sc->num_iss = HDAC_GCAP_ISS(gcap); 1334 sc->num_oss = HDAC_GCAP_OSS(gcap); 1335 sc->num_bss = HDAC_GCAP_BSS(gcap); 1336 1337 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1338 1339 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1340 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1341 HDAC_CORBSIZE_CORBSZCAP_256) 1342 sc->corb_size = 256; 1343 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1344 HDAC_CORBSIZE_CORBSZCAP_16) 1345 sc->corb_size = 16; 1346 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1347 HDAC_CORBSIZE_CORBSZCAP_2) 1348 sc->corb_size = 2; 1349 else { 1350 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1351 __func__, corbsize); 1352 return (ENXIO); 1353 } 1354 1355 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1356 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1357 HDAC_RIRBSIZE_RIRBSZCAP_256) 1358 sc->rirb_size = 256; 1359 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1360 HDAC_RIRBSIZE_RIRBSZCAP_16) 1361 sc->rirb_size = 16; 1362 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1363 HDAC_RIRBSIZE_RIRBSZCAP_2) 1364 sc->rirb_size = 2; 1365 else { 1366 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1367 __func__, rirbsize); 1368 return (ENXIO); 1369 } 1370 1371 return (0); 1372 } 1373 1374 1375 /**************************************************************************** 1376 * void hdac_dma_cb 1377 * 1378 * This function is called by bus_dmamap_load when the mapping has been 1379 * established. We just record the physical address of the mapping into 1380 * the struct hdac_dma passed in. 1381 ****************************************************************************/ 1382 static void 1383 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1384 { 1385 struct hdac_dma *dma; 1386 1387 if (error == 0) { 1388 dma = (struct hdac_dma *)callback_arg; 1389 dma->dma_paddr = segs[0].ds_addr; 1390 } 1391 } 1392 1393 1394 /**************************************************************************** 1395 * int hdac_dma_alloc 1396 * 1397 * This function allocate and setup a dma region (struct hdac_dma). 1398 * It must be freed by a corresponding hdac_dma_free. 1399 ****************************************************************************/ 1400 static int 1401 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1402 { 1403 bus_size_t roundsz; 1404 int result; 1405 int lowaddr; 1406 1407 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1408 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1409 BUS_SPACE_MAXADDR_32BIT; 1410 bzero(dma, sizeof(*dma)); 1411 1412 /* 1413 * Create a DMA tag 1414 */ 1415 result = bus_dma_tag_create(NULL, /* parent */ 1416 HDAC_DMA_ALIGNMENT, /* alignment */ 1417 0, /* boundary */ 1418 lowaddr, /* lowaddr */ 1419 BUS_SPACE_MAXADDR, /* highaddr */ 1420 NULL, /* filtfunc */ 1421 NULL, /* fistfuncarg */ 1422 roundsz, /* maxsize */ 1423 1, /* nsegments */ 1424 roundsz, /* maxsegsz */ 1425 0, /* flags */ 1426 NULL, /* lockfunc */ 1427 NULL, /* lockfuncarg */ 1428 &dma->dma_tag); /* dmat */ 1429 if (result != 0) { 1430 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1431 __func__, result); 1432 goto hdac_dma_alloc_fail; 1433 } 1434 1435 /* 1436 * Allocate DMA memory 1437 */ 1438 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1439 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1440 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1441 &dma->dma_map); 1442 if (result != 0) { 1443 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1444 __func__, result); 1445 goto hdac_dma_alloc_fail; 1446 } 1447 1448 dma->dma_size = roundsz; 1449 1450 /* 1451 * Map the memory 1452 */ 1453 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1454 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1455 if (result != 0 || dma->dma_paddr == 0) { 1456 if (result == 0) 1457 result = ENOMEM; 1458 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1459 __func__, result); 1460 goto hdac_dma_alloc_fail; 1461 } 1462 1463 HDA_BOOTVERBOSE( 1464 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1465 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1466 ); 1467 1468 return (0); 1469 1470 hdac_dma_alloc_fail: 1471 hdac_dma_free(sc, dma); 1472 1473 return (result); 1474 } 1475 1476 1477 /**************************************************************************** 1478 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1479 * 1480 * Free a struct dhac_dma that has been previously allocated via the 1481 * hdac_dma_alloc function. 1482 ****************************************************************************/ 1483 static void 1484 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1485 { 1486 if (dma->dma_map != NULL) { 1487 #if 0 1488 /* Flush caches */ 1489 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1490 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1491 #endif 1492 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1493 } 1494 if (dma->dma_vaddr != NULL) { 1495 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1496 dma->dma_vaddr = NULL; 1497 } 1498 dma->dma_map = NULL; 1499 if (dma->dma_tag != NULL) { 1500 bus_dma_tag_destroy(dma->dma_tag); 1501 dma->dma_tag = NULL; 1502 } 1503 dma->dma_size = 0; 1504 } 1505 1506 /**************************************************************************** 1507 * int hdac_mem_alloc(struct hdac_softc *) 1508 * 1509 * Allocate all the bus resources necessary to speak with the physical 1510 * controller. 1511 ****************************************************************************/ 1512 static int 1513 hdac_mem_alloc(struct hdac_softc *sc) 1514 { 1515 struct hdac_mem *mem; 1516 1517 mem = &sc->mem; 1518 mem->mem_rid = PCIR_BAR(0); 1519 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1520 &mem->mem_rid, RF_ACTIVE); 1521 if (mem->mem_res == NULL) { 1522 device_printf(sc->dev, 1523 "%s: Unable to allocate memory resource\n", __func__); 1524 return (ENOMEM); 1525 } 1526 mem->mem_tag = rman_get_bustag(mem->mem_res); 1527 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1528 1529 return (0); 1530 } 1531 1532 /**************************************************************************** 1533 * void hdac_mem_free(struct hdac_softc *) 1534 * 1535 * Free up resources previously allocated by hdac_mem_alloc. 1536 ****************************************************************************/ 1537 static void 1538 hdac_mem_free(struct hdac_softc *sc) 1539 { 1540 struct hdac_mem *mem; 1541 1542 mem = &sc->mem; 1543 if (mem->mem_res != NULL) 1544 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1545 mem->mem_res); 1546 mem->mem_res = NULL; 1547 } 1548 1549 /**************************************************************************** 1550 * int hdac_irq_alloc(struct hdac_softc *) 1551 * 1552 * Allocate and setup the resources necessary for interrupt handling. 1553 ****************************************************************************/ 1554 static int 1555 hdac_irq_alloc(struct hdac_softc *sc) 1556 { 1557 struct hdac_irq *irq; 1558 int result; 1559 1560 irq = &sc->irq; 1561 irq->irq_rid = 0x0; 1562 1563 #if __FreeBSD_version >= 602106 1564 if ((sc->flags & HDAC_F_MSI) && 1565 (result = pci_msi_count(sc->dev)) == 1 && 1566 pci_alloc_msi(sc->dev, &result) == 0) 1567 irq->irq_rid = 0x1; 1568 else 1569 #endif 1570 sc->flags &= ~HDAC_F_MSI; 1571 1572 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1573 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1574 if (irq->irq_res == NULL) { 1575 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1576 __func__); 1577 goto hdac_irq_alloc_fail; 1578 } 1579 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1580 hdac_intr_handler, sc, &irq->irq_handle); 1581 if (result != 0) { 1582 device_printf(sc->dev, 1583 "%s: Unable to setup interrupt handler (%x)\n", 1584 __func__, result); 1585 goto hdac_irq_alloc_fail; 1586 } 1587 1588 return (0); 1589 1590 hdac_irq_alloc_fail: 1591 hdac_irq_free(sc); 1592 1593 return (ENXIO); 1594 } 1595 1596 /**************************************************************************** 1597 * void hdac_irq_free(struct hdac_softc *) 1598 * 1599 * Free up resources previously allocated by hdac_irq_alloc. 1600 ****************************************************************************/ 1601 static void 1602 hdac_irq_free(struct hdac_softc *sc) 1603 { 1604 struct hdac_irq *irq; 1605 1606 irq = &sc->irq; 1607 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1608 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1609 if (irq->irq_res != NULL) 1610 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1611 irq->irq_res); 1612 #if __FreeBSD_version >= 602106 1613 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1614 pci_release_msi(sc->dev); 1615 #endif 1616 irq->irq_handle = NULL; 1617 irq->irq_res = NULL; 1618 irq->irq_rid = 0x0; 1619 } 1620 1621 /**************************************************************************** 1622 * void hdac_corb_init(struct hdac_softc *) 1623 * 1624 * Initialize the corb registers for operations but do not start it up yet. 1625 * The CORB engine must not be running when this function is called. 1626 ****************************************************************************/ 1627 static void 1628 hdac_corb_init(struct hdac_softc *sc) 1629 { 1630 uint8_t corbsize; 1631 uint64_t corbpaddr; 1632 1633 /* Setup the CORB size. */ 1634 switch (sc->corb_size) { 1635 case 256: 1636 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1637 break; 1638 case 16: 1639 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1640 break; 1641 case 2: 1642 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1643 break; 1644 default: 1645 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1646 } 1647 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1648 1649 /* Setup the CORB Address in the hdac */ 1650 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1651 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1652 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1653 1654 /* Set the WP and RP */ 1655 sc->corb_wp = 0; 1656 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1657 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1658 /* 1659 * The HDA specification indicates that the CORBRPRST bit will always 1660 * read as zero. Unfortunately, it seems that at least the 82801G 1661 * doesn't reset the bit to zero, which stalls the corb engine. 1662 * manually reset the bit to zero before continuing. 1663 */ 1664 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1665 1666 /* Enable CORB error reporting */ 1667 #if 0 1668 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1669 #endif 1670 } 1671 1672 /**************************************************************************** 1673 * void hdac_rirb_init(struct hdac_softc *) 1674 * 1675 * Initialize the rirb registers for operations but do not start it up yet. 1676 * The RIRB engine must not be running when this function is called. 1677 ****************************************************************************/ 1678 static void 1679 hdac_rirb_init(struct hdac_softc *sc) 1680 { 1681 uint8_t rirbsize; 1682 uint64_t rirbpaddr; 1683 1684 /* Setup the RIRB size. */ 1685 switch (sc->rirb_size) { 1686 case 256: 1687 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1688 break; 1689 case 16: 1690 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1691 break; 1692 case 2: 1693 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1694 break; 1695 default: 1696 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1697 } 1698 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1699 1700 /* Setup the RIRB Address in the hdac */ 1701 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1702 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1703 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1704 1705 /* Setup the WP and RP */ 1706 sc->rirb_rp = 0; 1707 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1708 1709 if (sc->polling == 0) { 1710 /* Setup the interrupt threshold */ 1711 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1712 1713 /* Enable Overrun and response received reporting */ 1714 #if 0 1715 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1716 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1717 #else 1718 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1719 #endif 1720 } 1721 1722 #if 0 1723 /* 1724 * Make sure that the Host CPU cache doesn't contain any dirty 1725 * cache lines that falls in the rirb. If I understood correctly, it 1726 * should be sufficient to do this only once as the rirb is purely 1727 * read-only from now on. 1728 */ 1729 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1730 BUS_DMASYNC_PREREAD); 1731 #endif 1732 } 1733 1734 /**************************************************************************** 1735 * void hdac_corb_start(hdac_softc *) 1736 * 1737 * Startup the corb DMA engine 1738 ****************************************************************************/ 1739 static void 1740 hdac_corb_start(struct hdac_softc *sc) 1741 { 1742 uint32_t corbctl; 1743 1744 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1745 corbctl |= HDAC_CORBCTL_CORBRUN; 1746 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1747 } 1748 1749 /**************************************************************************** 1750 * void hdac_rirb_start(hdac_softc *) 1751 * 1752 * Startup the rirb DMA engine 1753 ****************************************************************************/ 1754 static void 1755 hdac_rirb_start(struct hdac_softc *sc) 1756 { 1757 uint32_t rirbctl; 1758 1759 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1760 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1761 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1762 } 1763 1764 1765 /**************************************************************************** 1766 * void hdac_scan_codecs(struct hdac_softc *, int) 1767 * 1768 * Scan the bus for available codecs, starting with num. 1769 ****************************************************************************/ 1770 static void 1771 hdac_scan_codecs(struct hdac_softc *sc, int num) 1772 { 1773 struct hdac_codec *codec; 1774 int i; 1775 uint16_t statests; 1776 1777 if (num < 0) 1778 num = 0; 1779 if (num >= HDAC_CODEC_MAX) 1780 num = HDAC_CODEC_MAX - 1; 1781 1782 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1783 for (i = num; i < HDAC_CODEC_MAX; i++) { 1784 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1785 /* We have found a codec. */ 1786 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1787 M_HDAC, M_ZERO | M_NOWAIT); 1788 if (codec == NULL) { 1789 device_printf(sc->dev, 1790 "Unable to allocate memory for codec\n"); 1791 continue; 1792 } 1793 codec->commands = NULL; 1794 codec->responses_received = 0; 1795 codec->verbs_sent = 0; 1796 codec->sc = sc; 1797 codec->cad = i; 1798 sc->codecs[i] = codec; 1799 if (hdac_probe_codec(codec) != 0) 1800 break; 1801 } 1802 } 1803 /* All codecs have been probed, now try to attach drivers to them */ 1804 /* bus_generic_attach(sc->dev); */ 1805 } 1806 1807 /**************************************************************************** 1808 * void hdac_probe_codec(struct hdac_softc *, int) 1809 * 1810 * Probe a the given codec_id for available function groups. 1811 ****************************************************************************/ 1812 static int 1813 hdac_probe_codec(struct hdac_codec *codec) 1814 { 1815 struct hdac_softc *sc = codec->sc; 1816 struct hdac_devinfo *devinfo; 1817 uint32_t vendorid, revisionid, subnode; 1818 int startnode; 1819 int endnode; 1820 int i; 1821 nid_t cad = codec->cad; 1822 1823 HDA_BOOTVERBOSE( 1824 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1825 ); 1826 vendorid = hdac_command(sc, 1827 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1828 cad); 1829 revisionid = hdac_command(sc, 1830 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1831 cad); 1832 subnode = hdac_command(sc, 1833 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1834 cad); 1835 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1836 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1837 1838 HDA_BOOTVERBOSE( 1839 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1840 startnode, endnode); 1841 ); 1842 for (i = startnode; i < endnode; i++) { 1843 devinfo = hdac_probe_function(codec, i); 1844 if (devinfo != NULL) { 1845 /* XXX Ignore other FG. */ 1846 devinfo->vendor_id = 1847 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1848 devinfo->device_id = 1849 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1850 devinfo->revision_id = 1851 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1852 devinfo->stepping_id = 1853 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1854 HDA_BOOTVERBOSE( 1855 device_printf(sc->dev, 1856 "HDA_DEBUG: \tFound AFG nid=%d " 1857 "[startnode=%d endnode=%d]\n", 1858 devinfo->nid, startnode, endnode); 1859 ); 1860 return (1); 1861 } 1862 } 1863 1864 HDA_BOOTVERBOSE( 1865 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1866 ); 1867 return (0); 1868 } 1869 1870 static struct hdac_devinfo * 1871 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1872 { 1873 struct hdac_softc *sc = codec->sc; 1874 struct hdac_devinfo *devinfo; 1875 uint32_t fctgrptype; 1876 nid_t cad = codec->cad; 1877 1878 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1879 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1880 1881 /* XXX For now, ignore other FG. */ 1882 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1883 return (NULL); 1884 1885 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1886 M_NOWAIT | M_ZERO); 1887 if (devinfo == NULL) { 1888 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1889 __func__); 1890 return (NULL); 1891 } 1892 1893 devinfo->nid = nid; 1894 devinfo->node_type = fctgrptype; 1895 devinfo->codec = codec; 1896 1897 hdac_add_child(sc, devinfo); 1898 1899 return (devinfo); 1900 } 1901 1902 static void 1903 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1904 { 1905 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1906 device_set_ivars(devinfo->dev, (void *)devinfo); 1907 /* XXX - Print more information when booting verbose??? */ 1908 } 1909 1910 static void 1911 hdac_widget_connection_parse(struct hdac_widget *w) 1912 { 1913 struct hdac_softc *sc = w->devinfo->codec->sc; 1914 uint32_t res; 1915 int i, j, max, ents, entnum; 1916 nid_t cad = w->devinfo->codec->cad; 1917 nid_t nid = w->nid; 1918 nid_t cnid, addcnid, prevcnid; 1919 1920 w->nconns = 0; 1921 1922 res = hdac_command(sc, 1923 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1924 1925 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1926 1927 if (ents < 1) 1928 return; 1929 1930 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1931 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1932 prevcnid = 0; 1933 1934 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1935 #define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1936 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1937 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1938 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1939 1940 for (i = 0; i < ents; i += entnum) { 1941 res = hdac_command(sc, 1942 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1943 for (j = 0; j < entnum; j++) { 1944 cnid = CONN_CNID(res, entnum, j); 1945 if (cnid == 0) { 1946 if (w->nconns < ents) 1947 device_printf(sc->dev, 1948 "%s: nid=%d WARNING: zero cnid " 1949 "entnum=%d j=%d index=%d " 1950 "entries=%d found=%d res=0x%08x\n", 1951 __func__, nid, entnum, j, i, 1952 ents, w->nconns, res); 1953 else 1954 goto getconns_out; 1955 } 1956 if (cnid < w->devinfo->startnode || 1957 cnid >= w->devinfo->endnode) { 1958 HDA_BOOTVERBOSE( 1959 device_printf(sc->dev, 1960 "%s: GHOST: nid=%d j=%d " 1961 "entnum=%d index=%d res=0x%08x\n", 1962 __func__, nid, j, entnum, i, res); 1963 ); 1964 } 1965 if (CONN_RANGE(res, entnum, j) == 0) 1966 addcnid = cnid; 1967 else if (prevcnid == 0 || prevcnid >= cnid) { 1968 device_printf(sc->dev, 1969 "%s: WARNING: Invalid child range " 1970 "nid=%d index=%d j=%d entnum=%d " 1971 "prevcnid=%d cnid=%d res=0x%08x\n", 1972 __func__, nid, i, j, entnum, prevcnid, 1973 cnid, res); 1974 addcnid = cnid; 1975 } else 1976 addcnid = prevcnid + 1; 1977 while (addcnid <= cnid) { 1978 if (w->nconns > max) { 1979 device_printf(sc->dev, 1980 "%s: nid=%d: Adding %d: " 1981 "Max connection reached! max=%d\n", 1982 __func__, nid, addcnid, max + 1); 1983 goto getconns_out; 1984 } 1985 w->conns[w->nconns++] = addcnid++; 1986 } 1987 prevcnid = cnid; 1988 } 1989 } 1990 1991 getconns_out: 1992 HDA_BOOTVERBOSE( 1993 device_printf(sc->dev, 1994 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1995 __func__, nid, ents, w->nconns); 1996 ); 1997 return; 1998 } 1999 2000 static uint32_t 2001 hdac_widget_pin_getconfig(struct hdac_widget *w) 2002 { 2003 struct hdac_softc *sc; 2004 uint32_t config, orig, id; 2005 nid_t cad, nid; 2006 2007 sc = w->devinfo->codec->sc; 2008 cad = w->devinfo->codec->cad; 2009 nid = w->nid; 2010 id = hdac_codec_id(w->devinfo); 2011 2012 config = hdac_command(sc, 2013 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2014 cad); 2015 orig = config; 2016 2017 /* 2018 * XXX REWRITE!!!! Don't argue! 2019 */ 2020 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2021 switch (nid) { 2022 case 26: 2023 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2024 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2025 break; 2026 case 27: 2027 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2028 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2029 break; 2030 default: 2031 break; 2032 } 2033 } else if (id == HDA_CODEC_ALC880 && 2034 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2035 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2036 /* 2037 * Super broken BIOS 2038 */ 2039 switch (nid) { 2040 case 20: 2041 break; 2042 case 21: 2043 break; 2044 case 22: 2045 break; 2046 case 23: 2047 break; 2048 case 24: /* MIC1 */ 2049 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2050 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2051 break; 2052 case 25: /* XXX MIC2 */ 2053 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2054 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2055 break; 2056 case 26: /* LINE1 */ 2057 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2058 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2059 break; 2060 case 27: /* XXX LINE2 */ 2061 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2062 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2063 break; 2064 case 28: /* CD */ 2065 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2066 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2067 break; 2068 case 30: 2069 break; 2070 case 31: 2071 break; 2072 default: 2073 break; 2074 } 2075 } else if (id == HDA_CODEC_ALC883 && 2076 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2077 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2078 switch (nid) { 2079 case 25: 2080 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2081 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2082 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2083 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2084 break; 2085 case 28: 2086 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2087 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2088 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2089 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2090 break; 2091 default: 2092 break; 2093 } 2094 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2095 HP_V3000_SUBVENDOR) { 2096 switch (nid) { 2097 case 18: 2098 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2099 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2100 break; 2101 case 20: 2102 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2103 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2104 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2105 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2106 break; 2107 case 21: 2108 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2109 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2110 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2111 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2112 break; 2113 default: 2114 break; 2115 } 2116 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2117 HP_DV5000_SUBVENDOR) { 2118 switch (nid) { 2119 case 20: 2120 case 21: 2121 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2122 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2123 break; 2124 default: 2125 break; 2126 } 2127 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2128 ASUS_W6F_SUBVENDOR) { 2129 switch (nid) { 2130 case 11: 2131 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2132 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2133 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2134 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2135 break; 2136 case 15: 2137 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2138 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2139 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2140 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2141 break; 2142 default: 2143 break; 2144 } 2145 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2146 UNIWILL_9075_SUBVENDOR) { 2147 switch (nid) { 2148 case 15: 2149 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2150 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2151 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2152 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2153 break; 2154 default: 2155 break; 2156 } 2157 } else if (id == HDA_CODEC_AD1986A && 2158 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2159 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2160 switch (nid) { 2161 case 28: /* LINE */ 2162 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2163 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2164 break; 2165 case 29: /* MIC */ 2166 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2167 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2168 break; 2169 default: 2170 break; 2171 } 2172 } else if (id == HDA_CODEC_ALC268 && 2173 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2174 switch (nid) { 2175 case 28: 2176 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2177 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2178 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2179 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2180 break; 2181 default: 2182 break; 2183 } 2184 } 2185 2186 HDA_BOOTVERBOSE( 2187 if (config != orig) 2188 device_printf(sc->dev, 2189 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2190 nid, orig, config); 2191 ); 2192 2193 return (config); 2194 } 2195 2196 static uint32_t 2197 hdac_widget_pin_getcaps(struct hdac_widget *w) 2198 { 2199 struct hdac_softc *sc; 2200 uint32_t caps, orig, id; 2201 nid_t cad, nid; 2202 2203 sc = w->devinfo->codec->sc; 2204 cad = w->devinfo->codec->cad; 2205 nid = w->nid; 2206 id = hdac_codec_id(w->devinfo); 2207 2208 caps = hdac_command(sc, 2209 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2210 orig = caps; 2211 2212 HDA_BOOTVERBOSE( 2213 if (caps != orig) 2214 device_printf(sc->dev, 2215 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2216 nid, orig, caps); 2217 ); 2218 2219 return (caps); 2220 } 2221 2222 static void 2223 hdac_widget_pin_parse(struct hdac_widget *w) 2224 { 2225 struct hdac_softc *sc = w->devinfo->codec->sc; 2226 uint32_t config, pincap; 2227 char *devstr, *connstr; 2228 nid_t cad = w->devinfo->codec->cad; 2229 nid_t nid = w->nid; 2230 2231 config = hdac_widget_pin_getconfig(w); 2232 w->wclass.pin.config = config; 2233 2234 pincap = hdac_widget_pin_getcaps(w); 2235 w->wclass.pin.cap = pincap; 2236 2237 w->wclass.pin.ctrl = hdac_command(sc, 2238 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2239 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2240 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2241 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2242 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2243 2244 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2245 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2246 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2247 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2248 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2249 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2250 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2251 w->param.eapdbtl = hdac_command(sc, 2252 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2253 w->param.eapdbtl &= 0x7; 2254 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2255 } else 2256 w->param.eapdbtl = HDAC_INVALID; 2257 2258 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2259 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2260 devstr = "line out"; 2261 break; 2262 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2263 devstr = "speaker"; 2264 break; 2265 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2266 devstr = "headphones out"; 2267 break; 2268 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2269 devstr = "CD"; 2270 break; 2271 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2272 devstr = "SPDIF out"; 2273 break; 2274 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2275 devstr = "digital (other) out"; 2276 break; 2277 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2278 devstr = "modem, line side"; 2279 break; 2280 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2281 devstr = "modem, handset side"; 2282 break; 2283 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2284 devstr = "line in"; 2285 break; 2286 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2287 devstr = "AUX"; 2288 break; 2289 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2290 devstr = "Mic in"; 2291 break; 2292 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2293 devstr = "telephony"; 2294 break; 2295 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2296 devstr = "SPDIF in"; 2297 break; 2298 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2299 devstr = "digital (other) in"; 2300 break; 2301 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2302 devstr = "other"; 2303 break; 2304 default: 2305 devstr = "unknown"; 2306 break; 2307 } 2308 2309 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2310 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2311 connstr = "jack"; 2312 break; 2313 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2314 connstr = "none"; 2315 break; 2316 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2317 connstr = "fixed"; 2318 break; 2319 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2320 connstr = "jack / fixed"; 2321 break; 2322 default: 2323 connstr = "unknown"; 2324 break; 2325 } 2326 2327 strlcat(w->name, ": ", sizeof(w->name)); 2328 strlcat(w->name, devstr, sizeof(w->name)); 2329 strlcat(w->name, " (", sizeof(w->name)); 2330 strlcat(w->name, connstr, sizeof(w->name)); 2331 strlcat(w->name, ")", sizeof(w->name)); 2332 } 2333 2334 static void 2335 hdac_widget_parse(struct hdac_widget *w) 2336 { 2337 struct hdac_softc *sc = w->devinfo->codec->sc; 2338 uint32_t wcap, cap; 2339 char *typestr; 2340 nid_t cad = w->devinfo->codec->cad; 2341 nid_t nid = w->nid; 2342 2343 wcap = hdac_command(sc, 2344 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2345 cad); 2346 w->param.widget_cap = wcap; 2347 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2348 2349 switch (w->type) { 2350 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2351 typestr = "audio output"; 2352 break; 2353 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2354 typestr = "audio input"; 2355 break; 2356 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2357 typestr = "audio mixer"; 2358 break; 2359 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2360 typestr = "audio selector"; 2361 break; 2362 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2363 typestr = "pin"; 2364 break; 2365 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2366 typestr = "power widget"; 2367 break; 2368 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2369 typestr = "volume widget"; 2370 break; 2371 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2372 typestr = "beep widget"; 2373 break; 2374 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2375 typestr = "vendor widget"; 2376 break; 2377 default: 2378 typestr = "unknown type"; 2379 break; 2380 } 2381 2382 strlcpy(w->name, typestr, sizeof(w->name)); 2383 2384 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2385 hdac_command(sc, 2386 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2387 cad); 2388 DELAY(1000); 2389 } 2390 2391 hdac_widget_connection_parse(w); 2392 2393 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2394 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2395 w->param.outamp_cap = 2396 hdac_command(sc, 2397 HDA_CMD_GET_PARAMETER(cad, nid, 2398 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2399 else 2400 w->param.outamp_cap = 2401 w->devinfo->function.audio.outamp_cap; 2402 } else 2403 w->param.outamp_cap = 0; 2404 2405 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2406 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2407 w->param.inamp_cap = 2408 hdac_command(sc, 2409 HDA_CMD_GET_PARAMETER(cad, nid, 2410 HDA_PARAM_INPUT_AMP_CAP), cad); 2411 else 2412 w->param.inamp_cap = 2413 w->devinfo->function.audio.inamp_cap; 2414 } else 2415 w->param.inamp_cap = 0; 2416 2417 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2418 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2419 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2420 cap = hdac_command(sc, 2421 HDA_CMD_GET_PARAMETER(cad, nid, 2422 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2423 w->param.supp_stream_formats = (cap != 0) ? cap : 2424 w->devinfo->function.audio.supp_stream_formats; 2425 cap = hdac_command(sc, 2426 HDA_CMD_GET_PARAMETER(cad, nid, 2427 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2428 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2429 w->devinfo->function.audio.supp_pcm_size_rate; 2430 } else { 2431 w->param.supp_stream_formats = 2432 w->devinfo->function.audio.supp_stream_formats; 2433 w->param.supp_pcm_size_rate = 2434 w->devinfo->function.audio.supp_pcm_size_rate; 2435 } 2436 } else { 2437 w->param.supp_stream_formats = 0; 2438 w->param.supp_pcm_size_rate = 0; 2439 } 2440 2441 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2442 hdac_widget_pin_parse(w); 2443 } 2444 2445 static struct hdac_widget * 2446 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2447 { 2448 if (devinfo == NULL || devinfo->widget == NULL || 2449 nid < devinfo->startnode || nid >= devinfo->endnode) 2450 return (NULL); 2451 return (&devinfo->widget[nid - devinfo->startnode]); 2452 } 2453 2454 static __inline int 2455 hda_poll_channel(struct hdac_chan *ch) 2456 { 2457 uint32_t sz, delta; 2458 volatile uint32_t ptr; 2459 2460 if (!(ch->flags & HDAC_CHN_RUNNING)) 2461 return (0); 2462 2463 sz = ch->blksz * ch->blkcnt; 2464 if (ch->dmapos != NULL) 2465 ptr = *(ch->dmapos); 2466 else 2467 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2468 ch->off + HDAC_SDLPIB); 2469 ch->ptr = ptr; 2470 ptr %= sz; 2471 ptr &= ~(ch->blksz - 1); 2472 delta = (sz + ptr - ch->prevptr) % sz; 2473 2474 if (delta < ch->blksz) 2475 return (0); 2476 2477 ch->prevptr = ptr; 2478 2479 return (1); 2480 } 2481 2482 #define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \ 2483 HDAC_CHN_RUNNING) 2484 2485 static void 2486 hda_poll_callback(void *arg) 2487 { 2488 struct hdac_softc *sc = arg; 2489 uint32_t trigger; 2490 2491 if (sc == NULL) 2492 return; 2493 2494 hdac_lock(sc); 2495 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2496 hdac_unlock(sc); 2497 return; 2498 } 2499 2500 trigger = 0; 2501 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2502 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2503 2504 /* XXX */ 2505 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2506 hda_poll_callback, sc); 2507 2508 hdac_unlock(sc); 2509 2510 if (trigger & HDAC_TRIGGER_PLAY) 2511 chn_intr(sc->play.c); 2512 if (trigger & HDAC_TRIGGER_REC) 2513 chn_intr(sc->rec.c); 2514 } 2515 2516 static int 2517 hdac_rirb_flush(struct hdac_softc *sc) 2518 { 2519 struct hdac_rirb *rirb_base, *rirb; 2520 struct hdac_codec *codec; 2521 struct hdac_command_list *commands; 2522 nid_t cad; 2523 uint32_t resp; 2524 uint8_t rirbwp; 2525 int ret; 2526 2527 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2528 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2529 #if 0 2530 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2531 BUS_DMASYNC_POSTREAD); 2532 #endif 2533 2534 ret = 0; 2535 2536 while (sc->rirb_rp != rirbwp) { 2537 sc->rirb_rp++; 2538 sc->rirb_rp %= sc->rirb_size; 2539 rirb = &rirb_base[sc->rirb_rp]; 2540 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2541 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2542 sc->codecs[cad] == NULL) 2543 continue; 2544 resp = rirb->response; 2545 codec = sc->codecs[cad]; 2546 commands = codec->commands; 2547 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2548 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2549 ((resp >> 26) & 0xffff); 2550 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2551 } else if (commands != NULL && commands->num_commands > 0 && 2552 codec->responses_received < commands->num_commands) 2553 commands->responses[codec->responses_received++] = 2554 resp; 2555 ret++; 2556 } 2557 2558 return (ret); 2559 } 2560 2561 static int 2562 hdac_unsolq_flush(struct hdac_softc *sc) 2563 { 2564 nid_t cad; 2565 uint32_t tag; 2566 int ret = 0; 2567 2568 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2569 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2570 while (sc->unsolq_rp != sc->unsolq_wp) { 2571 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2572 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2573 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2574 hdac_unsolicited_handler(sc->codecs[cad], tag); 2575 ret++; 2576 } 2577 sc->unsolq_st = HDAC_UNSOLQ_READY; 2578 } 2579 2580 return (ret); 2581 } 2582 2583 static void 2584 hdac_poll_callback(void *arg) 2585 { 2586 struct hdac_softc *sc = arg; 2587 if (sc == NULL) 2588 return; 2589 2590 hdac_lock(sc); 2591 if (sc->polling == 0 || sc->poll_ival == 0) { 2592 hdac_unlock(sc); 2593 return; 2594 } 2595 if (hdac_rirb_flush(sc) != 0) 2596 hdac_unsolq_flush(sc); 2597 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2598 hdac_unlock(sc); 2599 } 2600 2601 static void 2602 hdac_stream_stop(struct hdac_chan *ch) 2603 { 2604 struct hdac_softc *sc = ch->devinfo->codec->sc; 2605 uint32_t ctl; 2606 2607 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2608 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2609 HDAC_SDCTL_RUN); 2610 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2611 2612 ch->flags &= ~HDAC_CHN_RUNNING; 2613 2614 if (sc->polling != 0) { 2615 int pollticks; 2616 2617 if (hda_chan_active(sc) == 0) { 2618 callout_stop(&sc->poll_hda); 2619 sc->poll_ticks = 1; 2620 } else { 2621 if (sc->play.flags & HDAC_CHN_RUNNING) 2622 ch = &sc->play; 2623 else 2624 ch = &sc->rec; 2625 pollticks = ((uint64_t)hz * ch->blksz) / 2626 ((uint64_t)sndbuf_getbps(ch->b) * 2627 sndbuf_getspd(ch->b)); 2628 pollticks >>= 2; 2629 if (pollticks > hz) 2630 pollticks = hz; 2631 if (pollticks < 1) { 2632 HDA_BOOTVERBOSE( 2633 device_printf(sc->dev, 2634 "%s: pollticks=%d < 1 !\n", 2635 __func__, pollticks); 2636 ); 2637 pollticks = 1; 2638 } 2639 if (pollticks > sc->poll_ticks) { 2640 HDA_BOOTVERBOSE( 2641 device_printf(sc->dev, 2642 "%s: pollticks %d -> %d\n", 2643 __func__, sc->poll_ticks, 2644 pollticks); 2645 ); 2646 sc->poll_ticks = pollticks; 2647 callout_reset(&sc->poll_hda, 1, 2648 hda_poll_callback, sc); 2649 } 2650 } 2651 } else { 2652 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2653 ctl &= ~(1 << (ch->off >> 5)); 2654 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2655 } 2656 } 2657 2658 static void 2659 hdac_stream_start(struct hdac_chan *ch) 2660 { 2661 struct hdac_softc *sc = ch->devinfo->codec->sc; 2662 uint32_t ctl; 2663 2664 if (sc->polling != 0) { 2665 int pollticks; 2666 2667 pollticks = ((uint64_t)hz * ch->blksz) / 2668 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2669 pollticks >>= 2; 2670 if (pollticks > hz) 2671 pollticks = hz; 2672 if (pollticks < 1) { 2673 HDA_BOOTVERBOSE( 2674 device_printf(sc->dev, 2675 "%s: pollticks=%d < 1 !\n", 2676 __func__, pollticks); 2677 ); 2678 pollticks = 1; 2679 } 2680 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2681 HDA_BOOTVERBOSE( 2682 if (hda_chan_active(sc) == 0) { 2683 device_printf(sc->dev, 2684 "%s: pollticks=%d\n", 2685 __func__, pollticks); 2686 } else { 2687 device_printf(sc->dev, 2688 "%s: pollticks %d -> %d\n", 2689 __func__, sc->poll_ticks, 2690 pollticks); 2691 } 2692 ); 2693 sc->poll_ticks = pollticks; 2694 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2695 sc); 2696 } 2697 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2698 ctl |= HDAC_SDCTL_RUN; 2699 } else { 2700 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2701 ctl |= 1 << (ch->off >> 5); 2702 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2703 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2704 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2705 HDAC_SDCTL_RUN; 2706 } 2707 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2708 2709 ch->flags |= HDAC_CHN_RUNNING; 2710 } 2711 2712 static void 2713 hdac_stream_reset(struct hdac_chan *ch) 2714 { 2715 struct hdac_softc *sc = ch->devinfo->codec->sc; 2716 int timeout = 1000; 2717 int to = timeout; 2718 uint32_t ctl; 2719 2720 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2721 ctl |= HDAC_SDCTL_SRST; 2722 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2723 do { 2724 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2725 if (ctl & HDAC_SDCTL_SRST) 2726 break; 2727 DELAY(10); 2728 } while (--to); 2729 if (!(ctl & HDAC_SDCTL_SRST)) { 2730 device_printf(sc->dev, "timeout in reset\n"); 2731 } 2732 ctl &= ~HDAC_SDCTL_SRST; 2733 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2734 to = timeout; 2735 do { 2736 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2737 if (!(ctl & HDAC_SDCTL_SRST)) 2738 break; 2739 DELAY(10); 2740 } while (--to); 2741 if (ctl & HDAC_SDCTL_SRST) 2742 device_printf(sc->dev, "can't reset!\n"); 2743 } 2744 2745 static void 2746 hdac_stream_setid(struct hdac_chan *ch) 2747 { 2748 struct hdac_softc *sc = ch->devinfo->codec->sc; 2749 uint32_t ctl; 2750 2751 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2752 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2753 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2754 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2755 } 2756 2757 static void 2758 hdac_bdl_setup(struct hdac_chan *ch) 2759 { 2760 struct hdac_softc *sc = ch->devinfo->codec->sc; 2761 struct hdac_bdle *bdle; 2762 uint64_t addr; 2763 uint32_t blksz, blkcnt; 2764 int i; 2765 2766 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2767 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2768 2769 if (sc->polling != 0) { 2770 blksz = ch->blksz * ch->blkcnt; 2771 blkcnt = 1; 2772 } else { 2773 blksz = ch->blksz; 2774 blkcnt = ch->blkcnt; 2775 } 2776 2777 for (i = 0; i < blkcnt; i++, bdle++) { 2778 bdle->addrl = (uint32_t)addr; 2779 bdle->addrh = (uint32_t)(addr >> 32); 2780 bdle->len = blksz; 2781 bdle->ioc = 1 ^ sc->polling; 2782 addr += blksz; 2783 } 2784 2785 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2786 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2787 addr = ch->bdl_dma.dma_paddr; 2788 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2789 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2790 if (ch->dmapos != NULL && 2791 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2792 addr = sc->pos_dma.dma_paddr; 2793 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2794 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2795 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2796 } 2797 } 2798 2799 static int 2800 hdac_bdl_alloc(struct hdac_chan *ch) 2801 { 2802 struct hdac_softc *sc = ch->devinfo->codec->sc; 2803 int rc; 2804 2805 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2806 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2807 if (rc) { 2808 device_printf(sc->dev, "can't alloc bdl\n"); 2809 return (rc); 2810 } 2811 2812 return (0); 2813 } 2814 2815 static void 2816 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2817 int index, int lmute, int rmute, 2818 int left, int right, int dir) 2819 { 2820 uint16_t v = 0; 2821 2822 if (sc == NULL) 2823 return; 2824 2825 if (left != right || lmute != rmute) { 2826 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2827 (lmute << 7) | left; 2828 hdac_command(sc, 2829 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2830 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2831 (rmute << 7) | right; 2832 } else 2833 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2834 (lmute << 7) | left; 2835 2836 hdac_command(sc, 2837 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2838 } 2839 2840 static void 2841 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2842 int left, int right) 2843 { 2844 struct hdac_softc *sc; 2845 nid_t nid, cad; 2846 int lmute, rmute; 2847 2848 if (ctl == NULL || ctl->widget == NULL || 2849 ctl->widget->devinfo == NULL || 2850 ctl->widget->devinfo->codec == NULL || 2851 ctl->widget->devinfo->codec->sc == NULL) 2852 return; 2853 2854 sc = ctl->widget->devinfo->codec->sc; 2855 cad = ctl->widget->devinfo->codec->cad; 2856 nid = ctl->widget->nid; 2857 2858 if (mute == HDA_AMP_MUTE_DEFAULT) { 2859 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2860 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2861 } else { 2862 lmute = HDA_AMP_LEFT_MUTED(mute); 2863 rmute = HDA_AMP_RIGHT_MUTED(mute); 2864 } 2865 2866 if (ctl->dir & HDA_CTL_OUT) 2867 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2868 lmute, rmute, left, right, 0); 2869 if (ctl->dir & HDA_CTL_IN) 2870 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2871 lmute, rmute, left, right, 1); 2872 ctl->left = left; 2873 ctl->right = right; 2874 } 2875 2876 static void 2877 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2878 { 2879 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2880 return; 2881 hdac_command(w->devinfo->codec->sc, 2882 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2883 w->nid, index), w->devinfo->codec->cad); 2884 w->selconn = index; 2885 } 2886 2887 2888 /**************************************************************************** 2889 * uint32_t hdac_command_sendone_internal 2890 * 2891 * Wrapper function that sends only one command to a given codec 2892 ****************************************************************************/ 2893 static uint32_t 2894 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2895 { 2896 struct hdac_command_list cl; 2897 uint32_t response = HDAC_INVALID; 2898 2899 if (!hdac_lockowned(sc)) 2900 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2901 cl.num_commands = 1; 2902 cl.verbs = &verb; 2903 cl.responses = &response; 2904 2905 hdac_command_send_internal(sc, &cl, cad); 2906 2907 return (response); 2908 } 2909 2910 /**************************************************************************** 2911 * hdac_command_send_internal 2912 * 2913 * Send a command list to the codec via the corb. We queue as much verbs as 2914 * we can and msleep on the codec. When the interrupt get the responses 2915 * back from the rirb, it will wake us up so we can queue the remaining verbs 2916 * if any. 2917 ****************************************************************************/ 2918 static void 2919 hdac_command_send_internal(struct hdac_softc *sc, 2920 struct hdac_command_list *commands, nid_t cad) 2921 { 2922 struct hdac_codec *codec; 2923 int corbrp; 2924 uint32_t *corb; 2925 int timeout; 2926 int retry = 10; 2927 struct hdac_rirb *rirb_base; 2928 2929 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2930 commands->num_commands < 1) 2931 return; 2932 2933 codec = sc->codecs[cad]; 2934 codec->commands = commands; 2935 codec->responses_received = 0; 2936 codec->verbs_sent = 0; 2937 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2938 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2939 2940 do { 2941 if (codec->verbs_sent != commands->num_commands) { 2942 /* Queue as many verbs as possible */ 2943 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2944 #if 0 2945 bus_dmamap_sync(sc->corb_dma.dma_tag, 2946 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2947 #endif 2948 while (codec->verbs_sent != commands->num_commands && 2949 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2950 sc->corb_wp++; 2951 sc->corb_wp %= sc->corb_size; 2952 corb[sc->corb_wp] = 2953 commands->verbs[codec->verbs_sent++]; 2954 } 2955 2956 /* Send the verbs to the codecs */ 2957 #if 0 2958 bus_dmamap_sync(sc->corb_dma.dma_tag, 2959 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2960 #endif 2961 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2962 } 2963 2964 timeout = 1000; 2965 while (hdac_rirb_flush(sc) == 0 && --timeout) 2966 DELAY(10); 2967 } while ((codec->verbs_sent != commands->num_commands || 2968 codec->responses_received != commands->num_commands) && --retry); 2969 2970 if (retry == 0) 2971 device_printf(sc->dev, 2972 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2973 __func__, commands->num_commands, codec->verbs_sent, 2974 codec->responses_received); 2975 2976 codec->commands = NULL; 2977 codec->responses_received = 0; 2978 codec->verbs_sent = 0; 2979 2980 hdac_unsolq_flush(sc); 2981 } 2982 2983 2984 /**************************************************************************** 2985 * Device Methods 2986 ****************************************************************************/ 2987 2988 /**************************************************************************** 2989 * int hdac_probe(device_t) 2990 * 2991 * Probe for the presence of an hdac. If none is found, check for a generic 2992 * match using the subclass of the device. 2993 ****************************************************************************/ 2994 static int 2995 hdac_probe(device_t dev) 2996 { 2997 int i, result; 2998 uint32_t model; 2999 uint16_t class, subclass; 3000 char desc[64]; 3001 3002 model = (uint32_t)pci_get_device(dev) << 16; 3003 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3004 class = pci_get_class(dev); 3005 subclass = pci_get_subclass(dev); 3006 3007 bzero(desc, sizeof(desc)); 3008 result = ENXIO; 3009 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3010 if (hdac_devices[i].model == model) { 3011 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3012 result = BUS_PROBE_DEFAULT; 3013 break; 3014 } 3015 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3016 class == PCIC_MULTIMEDIA && 3017 subclass == PCIS_MULTIMEDIA_HDA) { 3018 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3019 result = BUS_PROBE_GENERIC; 3020 break; 3021 } 3022 } 3023 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3024 subclass == PCIS_MULTIMEDIA_HDA) { 3025 strlcpy(desc, "Generic", sizeof(desc)); 3026 result = BUS_PROBE_GENERIC; 3027 } 3028 if (result != ENXIO) { 3029 strlcat(desc, " High Definition Audio Controller", 3030 sizeof(desc)); 3031 device_set_desc_copy(dev, desc); 3032 } 3033 3034 return (result); 3035 } 3036 3037 static void * 3038 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3039 struct pcm_channel *c, int dir) 3040 { 3041 struct hdac_devinfo *devinfo = data; 3042 struct hdac_softc *sc = devinfo->codec->sc; 3043 struct hdac_chan *ch; 3044 3045 hdac_lock(sc); 3046 if (dir == PCMDIR_PLAY) { 3047 ch = &sc->play; 3048 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 3049 devinfo->function.audio.playcnt++; 3050 } else { 3051 ch = &sc->rec; 3052 ch->off = devinfo->function.audio.reccnt << 5; 3053 devinfo->function.audio.reccnt++; 3054 } 3055 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3056 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3057 ch->pcmrates[0] = 48000; 3058 ch->pcmrates[1] = 0; 3059 } 3060 if (sc->pos_dma.dma_vaddr != NULL) 3061 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3062 (sc->streamcnt * 8)); 3063 else 3064 ch->dmapos = NULL; 3065 ch->sid = ++sc->streamcnt; 3066 ch->dir = dir; 3067 ch->b = b; 3068 ch->c = c; 3069 ch->devinfo = devinfo; 3070 ch->blksz = sc->chan_size / sc->chan_blkcnt; 3071 ch->blkcnt = sc->chan_blkcnt; 3072 hdac_unlock(sc); 3073 3074 if (hdac_bdl_alloc(ch) != 0) { 3075 ch->blkcnt = 0; 3076 return (NULL); 3077 } 3078 3079 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3080 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3081 sc->chan_size) != 0) 3082 return (NULL); 3083 3084 return (ch); 3085 } 3086 3087 static int 3088 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3089 { 3090 struct hdac_chan *ch = data; 3091 int i; 3092 3093 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3094 if (format == ch->caps.fmtlist[i]) { 3095 ch->fmt = format; 3096 return (0); 3097 } 3098 } 3099 3100 return (EINVAL); 3101 } 3102 3103 static int 3104 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3105 { 3106 struct hdac_chan *ch = data; 3107 uint32_t spd = 0, threshold; 3108 int i; 3109 3110 for (i = 0; ch->pcmrates[i] != 0; i++) { 3111 spd = ch->pcmrates[i]; 3112 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3113 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3114 if (speed < threshold) 3115 break; 3116 } 3117 3118 if (spd == 0) /* impossible */ 3119 ch->spd = 48000; 3120 else 3121 ch->spd = spd; 3122 3123 return (ch->spd); 3124 } 3125 3126 static void 3127 hdac_stream_setup(struct hdac_chan *ch) 3128 { 3129 struct hdac_softc *sc = ch->devinfo->codec->sc; 3130 struct hdac_widget *w; 3131 int i, chn, totalchn; 3132 nid_t cad = ch->devinfo->codec->cad; 3133 uint16_t fmt; 3134 3135 fmt = 0; 3136 if (ch->fmt & AFMT_S16_LE) 3137 fmt |= ch->bit16 << 4; 3138 else if (ch->fmt & AFMT_S32_LE) 3139 fmt |= ch->bit32 << 4; 3140 else 3141 fmt |= 1 << 4; 3142 3143 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3144 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3145 fmt |= hda_rate_tab[i].base; 3146 fmt |= hda_rate_tab[i].mul; 3147 fmt |= hda_rate_tab[i].div; 3148 break; 3149 } 3150 } 3151 3152 if (ch->fmt & AFMT_STEREO) { 3153 fmt |= 1; 3154 totalchn = 2; 3155 } else 3156 totalchn = 1; 3157 3158 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3159 3160 chn = 0; 3161 for (i = 0; ch->io[i] != -1; i++) { 3162 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3163 if (w == NULL) 3164 continue; 3165 HDA_BOOTVERBOSE( 3166 device_printf(sc->dev, 3167 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3168 "fmt=0x%08x\n", 3169 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3170 ch->io[i], fmt); 3171 ); 3172 hdac_command(sc, 3173 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3174 if (ch->dir == PCMDIR_REC) 3175 hdac_command(sc, 3176 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3177 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0), 3178 cad); 3179 else 3180 hdac_command(sc, 3181 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3182 ch->sid << 4), cad); 3183 chn += 3184 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3185 2 : 1; 3186 } 3187 } 3188 3189 static int 3190 hdac_channel_setfragments(kobj_t obj, void *data, 3191 uint32_t blksz, uint32_t blkcnt) 3192 { 3193 struct hdac_chan *ch = data; 3194 struct hdac_softc *sc = ch->devinfo->codec->sc; 3195 3196 blksz &= HDA_BLK_ALIGN; 3197 3198 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3199 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3200 if (blksz < HDA_BLK_MIN) 3201 blksz = HDA_BLK_MIN; 3202 if (blkcnt > HDA_BDL_MAX) 3203 blkcnt = HDA_BDL_MAX; 3204 if (blkcnt < HDA_BDL_MIN) 3205 blkcnt = HDA_BDL_MIN; 3206 3207 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3208 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3209 blkcnt >>= 1; 3210 else if ((blksz >> 1) >= HDA_BLK_MIN) 3211 blksz >>= 1; 3212 else 3213 break; 3214 } 3215 3216 if ((sndbuf_getblksz(ch->b) != blksz || 3217 sndbuf_getblkcnt(ch->b) != blkcnt) && 3218 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3219 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3220 __func__, blksz, blkcnt); 3221 3222 ch->blksz = sndbuf_getblksz(ch->b); 3223 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3224 3225 return (1); 3226 } 3227 3228 static int 3229 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3230 { 3231 struct hdac_chan *ch = data; 3232 struct hdac_softc *sc = ch->devinfo->codec->sc; 3233 3234 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3235 3236 return (ch->blksz); 3237 } 3238 3239 static void 3240 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3241 { 3242 struct hdac_devinfo *devinfo = ch->devinfo; 3243 nid_t cad = devinfo->codec->cad; 3244 int i; 3245 3246 hdac_stream_stop(ch); 3247 3248 for (i = 0; ch->io[i] != -1; i++) { 3249 hdac_command(sc, 3250 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3251 0), cad); 3252 } 3253 } 3254 3255 static void 3256 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3257 { 3258 ch->ptr = 0; 3259 ch->prevptr = 0; 3260 hdac_stream_stop(ch); 3261 hdac_stream_reset(ch); 3262 hdac_bdl_setup(ch); 3263 hdac_stream_setid(ch); 3264 hdac_stream_setup(ch); 3265 hdac_stream_start(ch); 3266 } 3267 3268 static int 3269 hdac_channel_trigger(kobj_t obj, void *data, int go) 3270 { 3271 struct hdac_chan *ch = data; 3272 struct hdac_softc *sc = ch->devinfo->codec->sc; 3273 3274 if (!PCMTRIG_COMMON(go)) 3275 return (0); 3276 3277 hdac_lock(sc); 3278 switch (go) { 3279 case PCMTRIG_START: 3280 hdac_channel_start(sc, ch); 3281 break; 3282 case PCMTRIG_STOP: 3283 case PCMTRIG_ABORT: 3284 hdac_channel_stop(sc, ch); 3285 break; 3286 default: 3287 break; 3288 } 3289 hdac_unlock(sc); 3290 3291 return (0); 3292 } 3293 3294 static int 3295 hdac_channel_getptr(kobj_t obj, void *data) 3296 { 3297 struct hdac_chan *ch = data; 3298 struct hdac_softc *sc = ch->devinfo->codec->sc; 3299 uint32_t ptr; 3300 3301 hdac_lock(sc); 3302 if (sc->polling != 0) 3303 ptr = ch->ptr; 3304 else if (ch->dmapos != NULL) 3305 ptr = *(ch->dmapos); 3306 else 3307 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3308 hdac_unlock(sc); 3309 3310 /* 3311 * Round to available space and force 128 bytes aligment. 3312 */ 3313 ptr %= ch->blksz * ch->blkcnt; 3314 ptr &= HDA_BLK_ALIGN; 3315 3316 return (ptr); 3317 } 3318 3319 static struct pcmchan_caps * 3320 hdac_channel_getcaps(kobj_t obj, void *data) 3321 { 3322 return (&((struct hdac_chan *)data)->caps); 3323 } 3324 3325 static kobj_method_t hdac_channel_methods[] = { 3326 KOBJMETHOD(channel_init, hdac_channel_init), 3327 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3328 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3329 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3330 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3331 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3332 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3333 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3334 { 0, 0 } 3335 }; 3336 CHANNEL_DECLARE(hdac_channel); 3337 3338 static void 3339 hdac_jack_poll_callback(void *arg) 3340 { 3341 struct hdac_devinfo *devinfo = arg; 3342 struct hdac_softc *sc; 3343 3344 if (devinfo == NULL || devinfo->codec == NULL || 3345 devinfo->codec->sc == NULL) 3346 return; 3347 sc = devinfo->codec->sc; 3348 hdac_lock(sc); 3349 if (sc->poll_ival == 0) { 3350 hdac_unlock(sc); 3351 return; 3352 } 3353 hdac_hp_switch_handler(devinfo); 3354 callout_reset(&sc->poll_jack, sc->poll_ival, 3355 hdac_jack_poll_callback, devinfo); 3356 hdac_unlock(sc); 3357 } 3358 3359 static int 3360 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3361 { 3362 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3363 struct hdac_softc *sc = devinfo->codec->sc; 3364 struct hdac_widget *w, *cw; 3365 struct hdac_audio_ctl *ctl; 3366 uint32_t mask, recmask, id; 3367 int i, j, softpcmvol; 3368 nid_t cad; 3369 3370 hdac_lock(sc); 3371 3372 mask = 0; 3373 recmask = 0; 3374 3375 id = hdac_codec_id(devinfo); 3376 cad = devinfo->codec->cad; 3377 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3378 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3379 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3380 continue; 3381 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3382 if (w == NULL || w->enable == 0 || w->type != 3383 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3384 continue; 3385 if (hdac_hp_switch[i].polling != 0) 3386 callout_reset(&sc->poll_jack, 1, 3387 hdac_jack_poll_callback, devinfo); 3388 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3389 hdac_command(sc, 3390 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3391 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3392 HDAC_UNSOLTAG_EVENT_HP), cad); 3393 else 3394 continue; 3395 hdac_hp_switch_handler(devinfo); 3396 HDA_BOOTVERBOSE( 3397 device_printf(sc->dev, 3398 "HDA_DEBUG: Enabling headphone/speaker " 3399 "audio routing switching:\n"); 3400 device_printf(sc->dev, 3401 "HDA_DEBUG: \tindex=%d nid=%d " 3402 "pci_subvendor=0x%08x " 3403 "codec=0x%08x [%s]\n", 3404 i, w->nid, sc->pci_subvendor, id, 3405 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3406 "UNSOL"); 3407 ); 3408 break; 3409 } 3410 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3411 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3412 sc->pci_subvendor) && 3413 hdac_eapd_switch[i].id == id)) 3414 continue; 3415 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3416 if (w == NULL || w->enable == 0) 3417 break; 3418 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3419 w->param.eapdbtl == HDAC_INVALID) 3420 break; 3421 mask |= SOUND_MASK_OGAIN; 3422 break; 3423 } 3424 3425 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3426 w = hdac_widget_get(devinfo, i); 3427 if (w == NULL || w->enable == 0) 3428 continue; 3429 mask |= w->ctlflags; 3430 if (!(w->pflags & HDA_ADC_RECSEL)) 3431 continue; 3432 for (j = 0; j < w->nconns; j++) { 3433 cw = hdac_widget_get(devinfo, w->conns[j]); 3434 if (cw == NULL || cw->enable == 0) 3435 continue; 3436 recmask |= cw->ctlflags; 3437 } 3438 } 3439 3440 if (!(mask & SOUND_MASK_PCM)) { 3441 softpcmvol = 1; 3442 mask |= SOUND_MASK_PCM; 3443 } else 3444 softpcmvol = (devinfo->function.audio.quirks & 3445 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3446 3447 i = 0; 3448 ctl = NULL; 3449 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3450 if (ctl->widget == NULL || ctl->enable == 0) 3451 continue; 3452 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3453 continue; 3454 if (ctl->step > 0) 3455 break; 3456 } 3457 3458 if (softpcmvol == 1 || ctl == NULL) { 3459 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3460 HDA_BOOTVERBOSE( 3461 device_printf(sc->dev, 3462 "HDA_DEBUG: %s Soft PCM volume\n", 3463 (softpcmvol == 1) ? 3464 "Forcing" : "Enabling"); 3465 ); 3466 i = 0; 3467 /* 3468 * XXX Temporary quirk for STAC9220, until the parser 3469 * become smarter. 3470 */ 3471 if (id == HDA_CODEC_STAC9220) { 3472 mask |= SOUND_MASK_VOLUME; 3473 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3474 NULL) { 3475 if (ctl->widget == NULL || ctl->enable == 0) 3476 continue; 3477 if (ctl->widget->nid == 11 && ctl->index == 0) { 3478 ctl->ossmask = SOUND_MASK_VOLUME; 3479 ctl->ossval = 100 | (100 << 8); 3480 } else 3481 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3482 } 3483 } else if (id == HDA_CODEC_STAC9221) { 3484 mask |= SOUND_MASK_VOLUME; 3485 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3486 NULL) { 3487 if (ctl->widget == NULL) 3488 continue; 3489 if (ctl->widget->type == 3490 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3491 ctl->index == 0 && (ctl->widget->nid == 2 || 3492 ctl->widget->enable != 0)) { 3493 ctl->enable = 1; 3494 ctl->ossmask = SOUND_MASK_VOLUME; 3495 ctl->ossval = 100 | (100 << 8); 3496 } else if (ctl->enable == 0) 3497 continue; 3498 else 3499 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3500 } 3501 } else { 3502 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3503 SOUND_MASK_PCM); 3504 if (!(mask & SOUND_MASK_VOLUME)) 3505 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3506 SOUND_MIXER_NONE); 3507 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3508 NULL) { 3509 if (ctl->widget == NULL || ctl->enable == 0) 3510 continue; 3511 if (!HDA_FLAG_MATCH(ctl->ossmask, 3512 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3513 continue; 3514 if (!(ctl->mute == 1 && ctl->step == 0)) 3515 ctl->enable = 0; 3516 } 3517 } 3518 } 3519 3520 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3521 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3522 SOUND_MASK_OGAIN); 3523 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3524 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3525 3526 mix_setrecdevs(m, recmask); 3527 mix_setdevs(m, mask); 3528 3529 hdac_unlock(sc); 3530 3531 return (0); 3532 } 3533 3534 static int 3535 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3536 unsigned left, unsigned right) 3537 { 3538 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3539 struct hdac_softc *sc = devinfo->codec->sc; 3540 struct hdac_widget *w; 3541 struct hdac_audio_ctl *ctl; 3542 uint32_t id, mute; 3543 int lvol, rvol, mlvol, mrvol; 3544 int i = 0; 3545 3546 hdac_lock(sc); 3547 if (dev == SOUND_MIXER_OGAIN) { 3548 uint32_t orig; 3549 /*if (left != right || !(left == 0 || left == 1)) { 3550 hdac_unlock(sc); 3551 return (-1); 3552 }*/ 3553 id = hdac_codec_id(devinfo); 3554 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3555 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3556 sc->pci_subvendor) && 3557 hdac_eapd_switch[i].id == id) 3558 break; 3559 } 3560 if (i >= HDAC_EAPD_SWITCH_LEN) { 3561 hdac_unlock(sc); 3562 return (-1); 3563 } 3564 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3565 if (w == NULL || 3566 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3567 w->param.eapdbtl == HDAC_INVALID) { 3568 hdac_unlock(sc); 3569 return (-1); 3570 } 3571 orig = w->param.eapdbtl; 3572 if (left == 0) 3573 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3574 else 3575 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3576 if (orig != w->param.eapdbtl) { 3577 uint32_t val; 3578 3579 if (hdac_eapd_switch[i].hp_switch != 0) 3580 hdac_hp_switch_handler(devinfo); 3581 val = w->param.eapdbtl; 3582 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3583 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3584 hdac_command(sc, 3585 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3586 w->nid, val), devinfo->codec->cad); 3587 } 3588 hdac_unlock(sc); 3589 return (left | (left << 8)); 3590 } 3591 if (dev == SOUND_MIXER_VOLUME) 3592 devinfo->function.audio.mvol = left | (right << 8); 3593 3594 mlvol = devinfo->function.audio.mvol & 0x7f; 3595 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3596 lvol = 0; 3597 rvol = 0; 3598 3599 i = 0; 3600 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3601 if (ctl->widget == NULL || ctl->enable == 0 || 3602 !(ctl->ossmask & (1 << dev))) 3603 continue; 3604 switch (dev) { 3605 case SOUND_MIXER_VOLUME: 3606 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3607 lvol = (lvol * ctl->step) / 100; 3608 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3609 rvol = (rvol * ctl->step) / 100; 3610 break; 3611 default: 3612 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3613 lvol = (left * mlvol) / 100; 3614 lvol = (lvol * ctl->step) / 100; 3615 rvol = (right * mrvol) / 100; 3616 rvol = (rvol * ctl->step) / 100; 3617 } else { 3618 lvol = (left * ctl->step) / 100; 3619 rvol = (right * ctl->step) / 100; 3620 } 3621 ctl->ossval = left | (right << 8); 3622 break; 3623 } 3624 mute = 0; 3625 if (ctl->step < 1) { 3626 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3627 (ctl->muted & HDA_AMP_MUTE_LEFT); 3628 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3629 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3630 } else { 3631 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3632 (ctl->muted & HDA_AMP_MUTE_LEFT); 3633 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3634 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3635 } 3636 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3637 } 3638 hdac_unlock(sc); 3639 3640 return (left | (right << 8)); 3641 } 3642 3643 static int 3644 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3645 { 3646 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3647 struct hdac_widget *w, *cw; 3648 struct hdac_softc *sc = devinfo->codec->sc; 3649 uint32_t ret = src, target; 3650 int i, j; 3651 3652 target = 0; 3653 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3654 if (src & (1 << i)) { 3655 target = 1 << i; 3656 break; 3657 } 3658 } 3659 3660 hdac_lock(sc); 3661 3662 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3663 w = hdac_widget_get(devinfo, i); 3664 if (w == NULL || w->enable == 0) 3665 continue; 3666 if (!(w->pflags & HDA_ADC_RECSEL)) 3667 continue; 3668 for (j = 0; j < w->nconns; j++) { 3669 cw = hdac_widget_get(devinfo, w->conns[j]); 3670 if (cw == NULL || cw->enable == 0) 3671 continue; 3672 if ((target == SOUND_MASK_VOLUME && 3673 cw->type != 3674 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3675 (target != SOUND_MASK_VOLUME && 3676 cw->type == 3677 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3678 continue; 3679 if (cw->ctlflags & target) { 3680 if (!(w->pflags & HDA_ADC_LOCKED)) 3681 hdac_widget_connection_select(w, j); 3682 ret = target; 3683 j += w->nconns; 3684 } 3685 } 3686 } 3687 3688 hdac_unlock(sc); 3689 3690 return (ret); 3691 } 3692 3693 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3694 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3695 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3696 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3697 { 0, 0 } 3698 }; 3699 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3700 3701 static void 3702 hdac_unsolq_task(void *context, int pending) 3703 { 3704 struct hdac_softc *sc; 3705 3706 sc = (struct hdac_softc *)context; 3707 3708 hdac_lock(sc); 3709 hdac_unsolq_flush(sc); 3710 hdac_unlock(sc); 3711 } 3712 3713 /**************************************************************************** 3714 * int hdac_attach(device_t) 3715 * 3716 * Attach the device into the kernel. Interrupts usually won't be enabled 3717 * when this function is called. Setup everything that doesn't require 3718 * interrupts and defer probing of codecs until interrupts are enabled. 3719 ****************************************************************************/ 3720 static int 3721 hdac_attach(device_t dev) 3722 { 3723 struct hdac_softc *sc; 3724 int result; 3725 int i; 3726 uint16_t vendor; 3727 uint8_t v; 3728 3729 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3730 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3731 sc->dev = dev; 3732 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3733 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3734 vendor = pci_get_vendor(dev); 3735 3736 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3737 /* Screw nx6325 - subdevice/subvendor swapped */ 3738 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3739 } 3740 3741 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3742 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3743 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3744 3745 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3746 3747 sc->poll_ticks = 1; 3748 sc->poll_ival = HDAC_POLL_INTERVAL; 3749 if (resource_int_value(device_get_name(dev), 3750 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3751 sc->polling = 1; 3752 else 3753 sc->polling = 0; 3754 3755 sc->chan_size = pcm_getbuffersize(dev, 3756 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3757 3758 if (resource_int_value(device_get_name(dev), 3759 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3760 i &= HDA_BLK_ALIGN; 3761 if (i < HDA_BLK_MIN) 3762 i = HDA_BLK_MIN; 3763 sc->chan_blkcnt = sc->chan_size / i; 3764 i = 0; 3765 while (sc->chan_blkcnt >> i) 3766 i++; 3767 sc->chan_blkcnt = 1 << (i - 1); 3768 if (sc->chan_blkcnt < HDA_BDL_MIN) 3769 sc->chan_blkcnt = HDA_BDL_MIN; 3770 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3771 sc->chan_blkcnt = HDA_BDL_MAX; 3772 } else 3773 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3774 3775 result = bus_dma_tag_create(NULL, /* parent */ 3776 HDAC_DMA_ALIGNMENT, /* alignment */ 3777 0, /* boundary */ 3778 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3779 BUS_SPACE_MAXADDR, /* highaddr */ 3780 NULL, /* filtfunc */ 3781 NULL, /* fistfuncarg */ 3782 sc->chan_size, /* maxsize */ 3783 1, /* nsegments */ 3784 sc->chan_size, /* maxsegsz */ 3785 0, /* flags */ 3786 NULL, /* lockfunc */ 3787 NULL, /* lockfuncarg */ 3788 &sc->chan_dmat); /* dmat */ 3789 if (result != 0) { 3790 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3791 __func__, result); 3792 snd_mtxfree(sc->lock); 3793 free(sc, M_DEVBUF); 3794 return (ENXIO); 3795 } 3796 3797 3798 sc->hdabus = NULL; 3799 for (i = 0; i < HDAC_CODEC_MAX; i++) 3800 sc->codecs[i] = NULL; 3801 3802 pci_enable_busmaster(dev); 3803 3804 if (vendor == INTEL_VENDORID) { 3805 /* TCSEL -> TC0 */ 3806 v = pci_read_config(dev, 0x44, 1); 3807 pci_write_config(dev, 0x44, v & 0xf8, 1); 3808 HDA_BOOTVERBOSE( 3809 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3810 pci_read_config(dev, 0x44, 1)); 3811 ); 3812 } 3813 3814 #if __FreeBSD_version >= 602106 3815 if (resource_int_value(device_get_name(dev), 3816 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3817 pci_msi_count(dev) == 1) 3818 sc->flags |= HDAC_F_MSI; 3819 else 3820 #endif 3821 sc->flags &= ~HDAC_F_MSI; 3822 3823 #if defined(__i386__) || defined(__amd64__) 3824 sc->flags |= HDAC_F_DMA_NOCACHE; 3825 3826 if (resource_int_value(device_get_name(dev), 3827 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3828 #else 3829 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3830 #endif 3831 /* 3832 * Try to enable PCIe snoop to avoid messing around with 3833 * uncacheable DMA attribute. Since PCIe snoop register 3834 * config is pretty much vendor specific, there are no 3835 * general solutions on how to enable it, forcing us (even 3836 * Microsoft) to enable uncacheable or write combined DMA 3837 * by default. 3838 * 3839 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3840 */ 3841 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3842 if (hdac_pcie_snoop[i].vendor != vendor) 3843 continue; 3844 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3845 if (hdac_pcie_snoop[i].reg == 0x00) 3846 break; 3847 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3848 if ((v & hdac_pcie_snoop[i].enable) == 3849 hdac_pcie_snoop[i].enable) 3850 break; 3851 v &= hdac_pcie_snoop[i].mask; 3852 v |= hdac_pcie_snoop[i].enable; 3853 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3854 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3855 if ((v & hdac_pcie_snoop[i].enable) != 3856 hdac_pcie_snoop[i].enable) { 3857 HDA_BOOTVERBOSE( 3858 device_printf(dev, 3859 "WARNING: Failed to enable PCIe " 3860 "snoop!\n"); 3861 ); 3862 #if defined(__i386__) || defined(__amd64__) 3863 sc->flags |= HDAC_F_DMA_NOCACHE; 3864 #endif 3865 } 3866 break; 3867 } 3868 #if defined(__i386__) || defined(__amd64__) 3869 } 3870 #endif 3871 3872 HDA_BOOTVERBOSE( 3873 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3874 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3875 "Uncacheable" : "PCIe snoop", vendor); 3876 ); 3877 3878 /* Allocate resources */ 3879 result = hdac_mem_alloc(sc); 3880 if (result != 0) 3881 goto hdac_attach_fail; 3882 result = hdac_irq_alloc(sc); 3883 if (result != 0) 3884 goto hdac_attach_fail; 3885 3886 /* Get Capabilities */ 3887 result = hdac_get_capabilities(sc); 3888 if (result != 0) 3889 goto hdac_attach_fail; 3890 3891 /* Allocate CORB and RIRB dma memory */ 3892 result = hdac_dma_alloc(sc, &sc->corb_dma, 3893 sc->corb_size * sizeof(uint32_t)); 3894 if (result != 0) 3895 goto hdac_attach_fail; 3896 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3897 sc->rirb_size * sizeof(struct hdac_rirb)); 3898 if (result != 0) 3899 goto hdac_attach_fail; 3900 3901 /* Quiesce everything */ 3902 hdac_reset(sc); 3903 3904 /* Initialize the CORB and RIRB */ 3905 hdac_corb_init(sc); 3906 hdac_rirb_init(sc); 3907 3908 /* Defer remaining of initialization until interrupts are enabled */ 3909 sc->intrhook.ich_func = hdac_attach2; 3910 sc->intrhook.ich_arg = (void *)sc; 3911 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3912 sc->intrhook.ich_func = NULL; 3913 hdac_attach2((void *)sc); 3914 } 3915 3916 return (0); 3917 3918 hdac_attach_fail: 3919 hdac_irq_free(sc); 3920 hdac_dma_free(sc, &sc->rirb_dma); 3921 hdac_dma_free(sc, &sc->corb_dma); 3922 hdac_mem_free(sc); 3923 snd_mtxfree(sc->lock); 3924 free(sc, M_DEVBUF); 3925 3926 return (ENXIO); 3927 } 3928 3929 static void 3930 hdac_audio_parse(struct hdac_devinfo *devinfo) 3931 { 3932 struct hdac_softc *sc = devinfo->codec->sc; 3933 struct hdac_widget *w; 3934 uint32_t res; 3935 int i; 3936 nid_t cad, nid; 3937 3938 cad = devinfo->codec->cad; 3939 nid = devinfo->nid; 3940 3941 hdac_command(sc, 3942 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3943 3944 DELAY(100); 3945 3946 res = hdac_command(sc, 3947 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3948 3949 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3950 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3951 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3952 3953 res = hdac_command(sc, 3954 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3955 devinfo->function.audio.gpio = res; 3956 3957 HDA_BOOTVERBOSE( 3958 device_printf(sc->dev, " Vendor: 0x%08x\n", 3959 devinfo->vendor_id); 3960 device_printf(sc->dev, " Device: 0x%08x\n", 3961 devinfo->device_id); 3962 device_printf(sc->dev, " Revision: 0x%08x\n", 3963 devinfo->revision_id); 3964 device_printf(sc->dev, " Stepping: 0x%08x\n", 3965 devinfo->stepping_id); 3966 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3967 sc->pci_subvendor); 3968 device_printf(sc->dev, " Nodes: start=%d " 3969 "endnode=%d total=%d\n", 3970 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3971 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3972 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3973 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3974 sc->num_iss, sc->num_oss, sc->num_bss); 3975 device_printf(sc->dev, " GPIO: 0x%08x\n", 3976 devinfo->function.audio.gpio); 3977 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3978 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3979 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3980 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3981 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3982 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3983 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3984 ); 3985 3986 res = hdac_command(sc, 3987 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3988 cad); 3989 devinfo->function.audio.supp_stream_formats = res; 3990 3991 res = hdac_command(sc, 3992 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3993 cad); 3994 devinfo->function.audio.supp_pcm_size_rate = res; 3995 3996 res = hdac_command(sc, 3997 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3998 cad); 3999 devinfo->function.audio.outamp_cap = res; 4000 4001 res = hdac_command(sc, 4002 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4003 cad); 4004 devinfo->function.audio.inamp_cap = res; 4005 4006 if (devinfo->nodecnt > 0) 4007 devinfo->widget = (struct hdac_widget *)malloc( 4008 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 4009 M_NOWAIT | M_ZERO); 4010 else 4011 devinfo->widget = NULL; 4012 4013 if (devinfo->widget == NULL) { 4014 device_printf(sc->dev, "unable to allocate widgets!\n"); 4015 devinfo->endnode = devinfo->startnode; 4016 devinfo->nodecnt = 0; 4017 return; 4018 } 4019 4020 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4021 w = hdac_widget_get(devinfo, i); 4022 if (w == NULL) 4023 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4024 else { 4025 w->devinfo = devinfo; 4026 w->nid = i; 4027 w->enable = 1; 4028 w->selconn = -1; 4029 w->pflags = 0; 4030 w->ctlflags = 0; 4031 w->param.eapdbtl = HDAC_INVALID; 4032 hdac_widget_parse(w); 4033 } 4034 } 4035 } 4036 4037 static void 4038 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4039 { 4040 struct hdac_softc *sc = devinfo->codec->sc; 4041 struct hdac_audio_ctl *ctls; 4042 struct hdac_widget *w, *cw; 4043 int i, j, cnt, max, ocap, icap; 4044 int mute, offset, step, size; 4045 4046 /* XXX This is redundant */ 4047 max = 0; 4048 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4049 w = hdac_widget_get(devinfo, i); 4050 if (w == NULL || w->enable == 0) 4051 continue; 4052 if (w->param.outamp_cap != 0) 4053 max++; 4054 if (w->param.inamp_cap != 0) { 4055 switch (w->type) { 4056 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4057 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4058 for (j = 0; j < w->nconns; j++) { 4059 cw = hdac_widget_get(devinfo, 4060 w->conns[j]); 4061 if (cw == NULL || cw->enable == 0) 4062 continue; 4063 max++; 4064 } 4065 break; 4066 default: 4067 max++; 4068 break; 4069 } 4070 } 4071 } 4072 4073 devinfo->function.audio.ctlcnt = max; 4074 4075 if (max < 1) 4076 return; 4077 4078 ctls = (struct hdac_audio_ctl *)malloc( 4079 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4080 4081 if (ctls == NULL) { 4082 /* Blekh! */ 4083 device_printf(sc->dev, "unable to allocate ctls!\n"); 4084 devinfo->function.audio.ctlcnt = 0; 4085 return; 4086 } 4087 4088 cnt = 0; 4089 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4090 if (cnt >= max) { 4091 device_printf(sc->dev, "%s: Ctl overflow!\n", 4092 __func__); 4093 break; 4094 } 4095 w = hdac_widget_get(devinfo, i); 4096 if (w == NULL || w->enable == 0) 4097 continue; 4098 ocap = w->param.outamp_cap; 4099 icap = w->param.inamp_cap; 4100 if (ocap != 0) { 4101 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4102 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4103 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4104 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4105 /*if (offset > step) { 4106 HDA_BOOTVERBOSE( 4107 device_printf(sc->dev, 4108 "HDA_DEBUG: BUGGY outamp: nid=%d " 4109 "[offset=%d > step=%d]\n", 4110 w->nid, offset, step); 4111 ); 4112 offset = step; 4113 }*/ 4114 ctls[cnt].enable = 1; 4115 ctls[cnt].widget = w; 4116 ctls[cnt].mute = mute; 4117 ctls[cnt].step = step; 4118 ctls[cnt].size = size; 4119 ctls[cnt].offset = offset; 4120 ctls[cnt].left = offset; 4121 ctls[cnt].right = offset; 4122 ctls[cnt++].dir = HDA_CTL_OUT; 4123 } 4124 4125 if (icap != 0) { 4126 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4127 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4128 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4129 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4130 /*if (offset > step) { 4131 HDA_BOOTVERBOSE( 4132 device_printf(sc->dev, 4133 "HDA_DEBUG: BUGGY inamp: nid=%d " 4134 "[offset=%d > step=%d]\n", 4135 w->nid, offset, step); 4136 ); 4137 offset = step; 4138 }*/ 4139 switch (w->type) { 4140 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4141 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4142 for (j = 0; j < w->nconns; j++) { 4143 if (cnt >= max) { 4144 device_printf(sc->dev, 4145 "%s: Ctl overflow!\n", 4146 __func__); 4147 break; 4148 } 4149 cw = hdac_widget_get(devinfo, 4150 w->conns[j]); 4151 if (cw == NULL || cw->enable == 0) 4152 continue; 4153 ctls[cnt].enable = 1; 4154 ctls[cnt].widget = w; 4155 ctls[cnt].childwidget = cw; 4156 ctls[cnt].index = j; 4157 ctls[cnt].mute = mute; 4158 ctls[cnt].step = step; 4159 ctls[cnt].size = size; 4160 ctls[cnt].offset = offset; 4161 ctls[cnt].left = offset; 4162 ctls[cnt].right = offset; 4163 ctls[cnt++].dir = HDA_CTL_IN; 4164 } 4165 break; 4166 default: 4167 if (cnt >= max) { 4168 device_printf(sc->dev, 4169 "%s: Ctl overflow!\n", 4170 __func__); 4171 break; 4172 } 4173 ctls[cnt].enable = 1; 4174 ctls[cnt].widget = w; 4175 ctls[cnt].mute = mute; 4176 ctls[cnt].step = step; 4177 ctls[cnt].size = size; 4178 ctls[cnt].offset = offset; 4179 ctls[cnt].left = offset; 4180 ctls[cnt].right = offset; 4181 ctls[cnt++].dir = HDA_CTL_IN; 4182 break; 4183 } 4184 } 4185 } 4186 4187 devinfo->function.audio.ctl = ctls; 4188 } 4189 4190 static const struct { 4191 uint32_t model; 4192 uint32_t id; 4193 uint32_t set, unset; 4194 } hdac_quirks[] = { 4195 /* 4196 * XXX Force stereo quirk. Monoural recording / playback 4197 * on few codecs (especially ALC880) seems broken or 4198 * perhaps unsupported. 4199 */ 4200 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4201 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4202 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4203 HDA_QUIRK_GPIO0, 0 }, 4204 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4205 HDA_QUIRK_GPIO0, 0 }, 4206 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4207 HDA_QUIRK_GPIO0, 0 }, 4208 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4209 HDA_QUIRK_GPIO0, 0 }, 4210 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4211 HDA_QUIRK_GPIO0, 0 }, 4212 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4213 HDA_QUIRK_EAPDINV, 0 }, 4214 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4215 HDA_QUIRK_EAPDINV, 0 }, 4216 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4217 HDA_QUIRK_OVREF, 0 }, 4218 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4219 HDA_QUIRK_OVREF, 0 }, 4220 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4221 HDA_QUIRK_OVREF, 0 }, 4222 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4223 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4224 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4225 HDA_QUIRK_GPIO1, 0 }, 4226 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4227 HDA_QUIRK_EAPDINV, 0 }, 4228 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4229 HDA_QUIRK_EAPDINV, 0 }, 4230 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4231 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4232 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4233 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4234 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4235 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4236 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4237 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4238 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4239 0, HDA_QUIRK_FORCESTEREO }, 4240 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4241 HDA_QUIRK_SOFTPCMVOL, 0 } 4242 }; 4243 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4244 4245 static void 4246 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4247 { 4248 struct hdac_widget *w; 4249 struct hdac_audio_ctl *ctl; 4250 uint32_t id, subvendor; 4251 int i; 4252 4253 id = hdac_codec_id(devinfo); 4254 subvendor = devinfo->codec->sc->pci_subvendor; 4255 4256 /* 4257 * Quirks 4258 */ 4259 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4260 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4261 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4262 continue; 4263 if (hdac_quirks[i].set != 0) 4264 devinfo->function.audio.quirks |= 4265 hdac_quirks[i].set; 4266 if (hdac_quirks[i].unset != 0) 4267 devinfo->function.audio.quirks &= 4268 ~(hdac_quirks[i].unset); 4269 } 4270 4271 switch (id) { 4272 case HDA_CODEC_ALC260: 4273 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4274 w = hdac_widget_get(devinfo, i); 4275 if (w == NULL || w->enable == 0) 4276 continue; 4277 if (w->type != 4278 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4279 continue; 4280 if (w->nid != 5) 4281 w->enable = 0; 4282 } 4283 if (subvendor == HP_XW4300_SUBVENDOR) { 4284 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4285 if (ctl != NULL && ctl->widget != NULL) { 4286 ctl->ossmask = SOUND_MASK_SPEAKER; 4287 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4288 } 4289 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4290 if (ctl != NULL && ctl->widget != NULL) { 4291 ctl->ossmask = SOUND_MASK_SPEAKER; 4292 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4293 } 4294 } else if (subvendor == HP_3010_SUBVENDOR) { 4295 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4296 if (ctl != NULL && ctl->widget != NULL) { 4297 ctl->ossmask = SOUND_MASK_SPEAKER; 4298 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4299 } 4300 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4301 if (ctl != NULL && ctl->widget != NULL) { 4302 ctl->ossmask = SOUND_MASK_SPEAKER; 4303 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4304 } 4305 } 4306 break; 4307 case HDA_CODEC_ALC262: 4308 if (subvendor == HP_DC7700S_SUBVENDOR) { 4309 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4310 if (ctl != NULL && ctl->widget != NULL) { 4311 ctl->ossmask = SOUND_MASK_PHONEOUT; 4312 ctl->widget->ctlflags |= SOUND_MASK_PHONEOUT; 4313 } 4314 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4315 if (ctl != NULL && ctl->widget != NULL) { 4316 ctl->ossmask = SOUND_MASK_SPEAKER; 4317 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4318 } 4319 } else if (subvendor == HP_DC7700_SUBVENDOR) { 4320 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4321 if (ctl != NULL && ctl->widget != NULL) { 4322 ctl->ossmask = SOUND_MASK_SPEAKER; 4323 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4324 } 4325 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1); 4326 if (ctl != NULL && ctl->widget != NULL) { 4327 ctl->ossmask = SOUND_MASK_SPEAKER; 4328 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4329 } 4330 } 4331 break; 4332 case HDA_CODEC_ALC268: 4333 if (HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, subvendor)) { 4334 w = hdac_widget_get(devinfo, 29); 4335 if (w != NULL) { 4336 w->enable = 1; 4337 w->type = 4338 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4339 w->param.widget_cap &= 4340 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4341 w->param.widget_cap |= 4342 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4343 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4344 strlcpy(w->name, "beep widget", sizeof(w->name)); 4345 } 4346 } 4347 break; 4348 case HDA_CODEC_ALC861: 4349 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4350 if (ctl != NULL) 4351 ctl->muted = HDA_AMP_MUTE_ALL; 4352 break; 4353 case HDA_CODEC_ALC880: 4354 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4355 w = hdac_widget_get(devinfo, i); 4356 if (w == NULL || w->enable == 0) 4357 continue; 4358 if (w->type == 4359 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4360 w->nid != 9 && w->nid != 29) { 4361 w->enable = 0; 4362 } else if (w->type != 4363 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4364 w->nid == 29) { 4365 w->type = 4366 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4367 w->param.widget_cap &= 4368 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4369 w->param.widget_cap |= 4370 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4371 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4372 strlcpy(w->name, "beep widget", sizeof(w->name)); 4373 } 4374 } 4375 break; 4376 case HDA_CODEC_ALC883: 4377 /* 4378 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4379 * Clear vref cap for jack connectivity. 4380 */ 4381 w = hdac_widget_get(devinfo, 24); 4382 if (w != NULL && w->enable != 0 && w->type == 4383 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4384 (w->wclass.pin.config & 4385 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4386 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4387 w->wclass.pin.cap &= ~( 4388 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4389 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4390 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4391 w = hdac_widget_get(devinfo, 25); 4392 if (w != NULL && w->enable != 0 && w->type == 4393 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4394 (w->wclass.pin.config & 4395 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4396 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4397 w->wclass.pin.cap &= ~( 4398 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4399 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4400 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4401 /* 4402 * nid: 26 = Line-in, leave it alone. 4403 */ 4404 break; 4405 case HDA_CODEC_AD1981HD: 4406 w = hdac_widget_get(devinfo, 11); 4407 if (w != NULL && w->enable != 0 && w->nconns > 3) 4408 w->selconn = 3; 4409 if (subvendor == IBM_M52_SUBVENDOR) { 4410 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4411 if (ctl != NULL) 4412 ctl->ossmask = SOUND_MASK_SPEAKER; 4413 } 4414 break; 4415 case HDA_CODEC_AD1986A: 4416 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4417 w = hdac_widget_get(devinfo, i); 4418 if (w == NULL || w->enable == 0) 4419 continue; 4420 if (w->type != 4421 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4422 continue; 4423 if (w->nid != 3) 4424 w->enable = 0; 4425 } 4426 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4427 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4428 /* nid 28 is mic, nid 29 is line-in */ 4429 w = hdac_widget_get(devinfo, 15); 4430 if (w != NULL) 4431 w->selconn = 2; 4432 w = hdac_widget_get(devinfo, 16); 4433 if (w != NULL) 4434 w->selconn = 1; 4435 } 4436 break; 4437 case HDA_CODEC_AD1988: 4438 case HDA_CODEC_AD1988B: 4439 /*w = hdac_widget_get(devinfo, 12); 4440 if (w != NULL) { 4441 w->selconn = 1; 4442 w->pflags |= HDA_ADC_LOCKED; 4443 } 4444 w = hdac_widget_get(devinfo, 13); 4445 if (w != NULL) { 4446 w->selconn = 4; 4447 w->pflags |= HDA_ADC_LOCKED; 4448 } 4449 w = hdac_widget_get(devinfo, 14); 4450 if (w != NULL) { 4451 w->selconn = 2; 4452 w->pflags |= HDA_ADC_LOCKED; 4453 }*/ 4454 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4455 if (ctl != NULL) { 4456 ctl->ossmask = SOUND_MASK_IGAIN; 4457 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4458 } 4459 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4460 if (ctl != NULL) { 4461 ctl->ossmask = SOUND_MASK_IGAIN; 4462 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4463 } 4464 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4465 if (ctl != NULL) { 4466 ctl->ossmask = SOUND_MASK_IGAIN; 4467 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4468 } 4469 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4470 if (ctl != NULL) { 4471 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4472 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4473 } 4474 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4475 if (ctl != NULL) { 4476 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4477 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4478 } 4479 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4480 if (ctl != NULL) { 4481 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4482 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4483 } 4484 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4485 if (ctl != NULL) { 4486 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4487 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4488 } 4489 break; 4490 case HDA_CODEC_STAC9221: 4491 /* 4492 * Dell XPS M1210 need all DACs for each output jacks 4493 */ 4494 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4495 break; 4496 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4497 w = hdac_widget_get(devinfo, i); 4498 if (w == NULL || w->enable == 0) 4499 continue; 4500 if (w->type != 4501 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4502 continue; 4503 if (w->nid != 2) 4504 w->enable = 0; 4505 } 4506 break; 4507 case HDA_CODEC_STAC9221D: 4508 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4509 w = hdac_widget_get(devinfo, i); 4510 if (w == NULL || w->enable == 0) 4511 continue; 4512 if (w->type == 4513 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4514 w->nid != 6) 4515 w->enable = 0; 4516 4517 } 4518 break; 4519 case HDA_CODEC_STAC9227: 4520 w = hdac_widget_get(devinfo, 8); 4521 if (w != NULL) 4522 w->enable = 0; 4523 w = hdac_widget_get(devinfo, 9); 4524 if (w != NULL) 4525 w->enable = 0; 4526 break; 4527 case HDA_CODEC_CXWAIKIKI: 4528 if (subvendor == HP_DV5000_SUBVENDOR) { 4529 w = hdac_widget_get(devinfo, 27); 4530 if (w != NULL) 4531 w->enable = 0; 4532 } 4533 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4534 if (ctl != NULL) 4535 ctl->ossmask = SOUND_MASK_SKIP; 4536 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4537 if (ctl != NULL && ctl->childwidget != NULL && 4538 ctl->childwidget->enable != 0) { 4539 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4540 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4541 } 4542 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4543 if (ctl != NULL && ctl->childwidget != NULL && 4544 ctl->childwidget->enable != 0) { 4545 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4546 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4547 } 4548 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4549 if (ctl != NULL && ctl->childwidget != NULL && 4550 ctl->childwidget->enable != 0) { 4551 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4552 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4553 } 4554 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4555 if (ctl != NULL) { 4556 ctl->ossmask = SOUND_MASK_SKIP; 4557 /* XXX mixer \=rec mic broken.. why?!? */ 4558 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4559 } 4560 break; 4561 default: 4562 break; 4563 } 4564 } 4565 4566 static int 4567 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4568 { 4569 int *dev = &devinfo->function.audio.ossidx; 4570 4571 while (*dev < SOUND_MIXER_NRDEVICES) { 4572 switch (*dev) { 4573 case SOUND_MIXER_VOLUME: 4574 case SOUND_MIXER_BASS: 4575 case SOUND_MIXER_TREBLE: 4576 case SOUND_MIXER_PCM: 4577 case SOUND_MIXER_SPEAKER: 4578 case SOUND_MIXER_LINE: 4579 case SOUND_MIXER_MIC: 4580 case SOUND_MIXER_CD: 4581 case SOUND_MIXER_RECLEV: 4582 case SOUND_MIXER_IGAIN: 4583 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4584 (*dev)++; 4585 break; 4586 default: 4587 return (*dev)++; 4588 break; 4589 } 4590 } 4591 4592 return (-1); 4593 } 4594 4595 static int 4596 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4597 { 4598 struct hdac_widget *w; 4599 int i, ret = 0; 4600 4601 if (depth > HDA_PARSE_MAXDEPTH) 4602 return (0); 4603 w = hdac_widget_get(devinfo, nid); 4604 if (w == NULL || w->enable == 0) 4605 return (0); 4606 switch (w->type) { 4607 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4608 w->pflags |= HDA_DAC_PATH; 4609 ret = 1; 4610 break; 4611 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4612 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4613 for (i = 0; i < w->nconns; i++) { 4614 if (hdac_widget_find_dac_path(devinfo, 4615 w->conns[i], depth + 1) != 0) { 4616 if (w->selconn == -1) 4617 w->selconn = i; 4618 ret = 1; 4619 w->pflags |= HDA_DAC_PATH; 4620 } 4621 } 4622 break; 4623 default: 4624 break; 4625 } 4626 return (ret); 4627 } 4628 4629 static int 4630 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4631 { 4632 struct hdac_widget *w; 4633 int i, conndev, ret = 0; 4634 4635 if (depth > HDA_PARSE_MAXDEPTH) 4636 return (0); 4637 w = hdac_widget_get(devinfo, nid); 4638 if (w == NULL || w->enable == 0) 4639 return (0); 4640 switch (w->type) { 4641 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4642 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4643 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4644 for (i = 0; i < w->nconns; i++) { 4645 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4646 depth + 1) != 0) { 4647 if (w->selconn == -1) 4648 w->selconn = i; 4649 w->pflags |= HDA_ADC_PATH; 4650 ret = 1; 4651 } 4652 } 4653 break; 4654 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4655 conndev = w->wclass.pin.config & 4656 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4657 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4658 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4659 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4660 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4661 w->pflags |= HDA_ADC_PATH; 4662 ret = 1; 4663 } 4664 break; 4665 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4666 if (w->pflags & HDA_DAC_PATH) { 4667 w->pflags |= HDA_ADC_PATH; 4668 ret = 1; 4669 } 4670 break;*/ 4671 default: 4672 break; 4673 } 4674 return (ret); 4675 } 4676 4677 static uint32_t 4678 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4679 nid_t nid, nid_t pnid, int index, int depth) 4680 { 4681 struct hdac_widget *w, *pw; 4682 struct hdac_audio_ctl *ctl; 4683 uint32_t fl = 0; 4684 int i, ossdev, conndev, strategy; 4685 4686 if (depth > HDA_PARSE_MAXDEPTH) 4687 return (0); 4688 4689 w = hdac_widget_get(devinfo, nid); 4690 if (w == NULL || w->enable == 0) 4691 return (0); 4692 4693 pw = hdac_widget_get(devinfo, pnid); 4694 strategy = devinfo->function.audio.parsing_strategy; 4695 4696 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4697 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4698 for (i = 0; i < w->nconns; i++) { 4699 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4700 w->nid, i, depth + 1); 4701 } 4702 w->ctlflags |= fl; 4703 return (fl); 4704 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4705 (w->pflags & HDA_DAC_PATH)) { 4706 i = 0; 4707 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4708 if (ctl->enable == 0 || ctl->widget == NULL) 4709 continue; 4710 /* XXX This should be compressed! */ 4711 if (((ctl->widget->nid == w->nid) || 4712 (ctl->widget->nid == pnid && ctl->index == index && 4713 (ctl->dir & HDA_CTL_IN)) || 4714 (ctl->widget->nid == pnid && pw != NULL && 4715 pw->type == 4716 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4717 (pw->nconns < 2 || pw->selconn == index || 4718 pw->selconn == -1) && 4719 (ctl->dir & HDA_CTL_OUT)) || 4720 (strategy == HDA_PARSE_DIRECT && 4721 ctl->widget->nid == w->nid)) && 4722 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4723 /*if (pw != NULL && pw->selconn == -1) 4724 pw->selconn = index; 4725 fl |= SOUND_MASK_VOLUME; 4726 fl |= SOUND_MASK_PCM; 4727 ctl->ossmask |= SOUND_MASK_VOLUME; 4728 ctl->ossmask |= SOUND_MASK_PCM; 4729 ctl->ossdev = SOUND_MIXER_PCM;*/ 4730 if (!(w->ctlflags & SOUND_MASK_PCM) || 4731 (pw != NULL && 4732 !(pw->ctlflags & SOUND_MASK_PCM))) { 4733 fl |= SOUND_MASK_VOLUME; 4734 fl |= SOUND_MASK_PCM; 4735 ctl->ossmask |= SOUND_MASK_VOLUME; 4736 ctl->ossmask |= SOUND_MASK_PCM; 4737 ctl->ossdev = SOUND_MIXER_PCM; 4738 w->ctlflags |= SOUND_MASK_VOLUME; 4739 w->ctlflags |= SOUND_MASK_PCM; 4740 if (pw != NULL) { 4741 if (pw->selconn == -1) 4742 pw->selconn = index; 4743 pw->ctlflags |= 4744 SOUND_MASK_VOLUME; 4745 pw->ctlflags |= 4746 SOUND_MASK_PCM; 4747 } 4748 } 4749 } 4750 } 4751 w->ctlflags |= fl; 4752 return (fl); 4753 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4754 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4755 (w->pflags & HDA_ADC_PATH)) { 4756 conndev = w->wclass.pin.config & 4757 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4758 i = 0; 4759 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4760 if (ctl->enable == 0 || ctl->widget == NULL) 4761 continue; 4762 /* XXX This should be compressed! */ 4763 if (((ctl->widget->nid == pnid && ctl->index == index && 4764 (ctl->dir & HDA_CTL_IN)) || 4765 (ctl->widget->nid == pnid && pw != NULL && 4766 pw->type == 4767 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4768 (pw->nconns < 2 || pw->selconn == index || 4769 pw->selconn == -1) && 4770 (ctl->dir & HDA_CTL_OUT)) || 4771 (strategy == HDA_PARSE_DIRECT && 4772 ctl->widget->nid == w->nid)) && 4773 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4774 if (pw != NULL && pw->selconn == -1) 4775 pw->selconn = index; 4776 ossdev = 0; 4777 switch (conndev) { 4778 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4779 ossdev = SOUND_MIXER_MIC; 4780 break; 4781 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4782 ossdev = SOUND_MIXER_LINE; 4783 break; 4784 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4785 ossdev = SOUND_MIXER_CD; 4786 break; 4787 default: 4788 ossdev = 4789 hdac_audio_ctl_ossmixer_getnextdev( 4790 devinfo); 4791 if (ossdev < 0) 4792 ossdev = 0; 4793 break; 4794 } 4795 if (strategy == HDA_PARSE_MIXER) { 4796 fl |= SOUND_MASK_VOLUME; 4797 ctl->ossmask |= SOUND_MASK_VOLUME; 4798 } 4799 fl |= 1 << ossdev; 4800 ctl->ossmask |= 1 << ossdev; 4801 ctl->ossdev = ossdev; 4802 } 4803 } 4804 w->ctlflags |= fl; 4805 return (fl); 4806 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4807 i = 0; 4808 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4809 if (ctl->enable == 0 || ctl->widget == NULL) 4810 continue; 4811 /* XXX This should be compressed! */ 4812 if (((ctl->widget->nid == pnid && ctl->index == index && 4813 (ctl->dir & HDA_CTL_IN)) || 4814 (ctl->widget->nid == pnid && pw != NULL && 4815 pw->type == 4816 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4817 (pw->nconns < 2 || pw->selconn == index || 4818 pw->selconn == -1) && 4819 (ctl->dir & HDA_CTL_OUT)) || 4820 (strategy == HDA_PARSE_DIRECT && 4821 ctl->widget->nid == w->nid)) && 4822 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4823 if (pw != NULL && pw->selconn == -1) 4824 pw->selconn = index; 4825 fl |= SOUND_MASK_VOLUME; 4826 fl |= SOUND_MASK_SPEAKER; 4827 ctl->ossmask |= SOUND_MASK_VOLUME; 4828 ctl->ossmask |= SOUND_MASK_SPEAKER; 4829 ctl->ossdev = SOUND_MIXER_SPEAKER; 4830 } 4831 } 4832 w->ctlflags |= fl; 4833 return (fl); 4834 } 4835 return (0); 4836 } 4837 4838 static uint32_t 4839 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4840 { 4841 struct hdac_widget *w, *cw; 4842 struct hdac_audio_ctl *ctl; 4843 uint32_t fl; 4844 int i; 4845 4846 if (depth > HDA_PARSE_MAXDEPTH) 4847 return (0); 4848 4849 w = hdac_widget_get(devinfo, nid); 4850 if (w == NULL || w->enable == 0) 4851 return (0); 4852 /*if (!(w->pflags & HDA_ADC_PATH)) 4853 return (0); 4854 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4855 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4856 return (0);*/ 4857 i = 0; 4858 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4859 if (ctl->enable == 0 || ctl->widget == NULL) 4860 continue; 4861 if (ctl->widget->nid == nid) { 4862 ctl->ossmask |= SOUND_MASK_RECLEV; 4863 w->ctlflags |= SOUND_MASK_RECLEV; 4864 return (SOUND_MASK_RECLEV); 4865 } 4866 } 4867 for (i = 0; i < w->nconns; i++) { 4868 cw = hdac_widget_get(devinfo, w->conns[i]); 4869 if (cw == NULL || cw->enable == 0) 4870 continue; 4871 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4872 continue; 4873 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4874 if (fl != 0) { 4875 cw->ctlflags |= fl; 4876 w->ctlflags |= fl; 4877 return (fl); 4878 } 4879 } 4880 return (0); 4881 } 4882 4883 static int 4884 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4885 { 4886 struct hdac_widget *w, *cw; 4887 int i, child = 0; 4888 4889 if (depth > HDA_PARSE_MAXDEPTH) 4890 return (0); 4891 4892 w = hdac_widget_get(devinfo, nid); 4893 if (w == NULL || w->enable == 0) 4894 return (0); 4895 /*if (!(w->pflags & HDA_ADC_PATH)) 4896 return (0); 4897 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4898 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4899 return (0);*/ 4900 /* XXX weak! */ 4901 for (i = 0; i < w->nconns; i++) { 4902 cw = hdac_widget_get(devinfo, w->conns[i]); 4903 if (cw == NULL) 4904 continue; 4905 if (++child > 1) { 4906 w->pflags |= HDA_ADC_RECSEL; 4907 return (1); 4908 } 4909 } 4910 for (i = 0; i < w->nconns; i++) { 4911 if (hdac_audio_ctl_recsel_build(devinfo, 4912 w->conns[i], depth + 1) != 0) 4913 return (1); 4914 } 4915 return (0); 4916 } 4917 4918 static int 4919 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4920 { 4921 struct hdac_widget *w, *cw; 4922 int i, j, conndev, found_dac = 0; 4923 int strategy; 4924 4925 strategy = devinfo->function.audio.parsing_strategy; 4926 4927 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4928 w = hdac_widget_get(devinfo, i); 4929 if (w == NULL || w->enable == 0) 4930 continue; 4931 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4932 continue; 4933 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4934 continue; 4935 conndev = w->wclass.pin.config & 4936 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4937 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4938 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4939 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4940 continue; 4941 for (j = 0; j < w->nconns; j++) { 4942 cw = hdac_widget_get(devinfo, w->conns[j]); 4943 if (cw == NULL || cw->enable == 0) 4944 continue; 4945 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4946 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4947 cw->type == 4948 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4949 continue; 4950 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4951 != 0) { 4952 if (w->selconn == -1) 4953 w->selconn = j; 4954 w->pflags |= HDA_DAC_PATH; 4955 found_dac++; 4956 } 4957 } 4958 } 4959 4960 return (found_dac); 4961 } 4962 4963 static void 4964 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4965 { 4966 struct hdac_widget *w; 4967 struct hdac_audio_ctl *ctl; 4968 int i, j, dacs, strategy; 4969 4970 /* Construct DAC path */ 4971 strategy = HDA_PARSE_MIXER; 4972 devinfo->function.audio.parsing_strategy = strategy; 4973 HDA_BOOTVERBOSE( 4974 device_printf(devinfo->codec->sc->dev, 4975 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4976 HDA_WIDGET_PARSER_REV); 4977 ); 4978 dacs = hdac_audio_build_tree_strategy(devinfo); 4979 if (dacs == 0) { 4980 HDA_BOOTVERBOSE( 4981 device_printf(devinfo->codec->sc->dev, 4982 "HDA_DEBUG: HWiP: 0 DAC path found! " 4983 "Retrying parser " 4984 "using HDA_PARSE_DIRECT strategy.\n"); 4985 ); 4986 strategy = HDA_PARSE_DIRECT; 4987 devinfo->function.audio.parsing_strategy = strategy; 4988 dacs = hdac_audio_build_tree_strategy(devinfo); 4989 } 4990 4991 HDA_BOOTVERBOSE( 4992 device_printf(devinfo->codec->sc->dev, 4993 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4994 "strategy.\n", 4995 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4996 ); 4997 4998 /* Construct ADC path */ 4999 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5000 w = hdac_widget_get(devinfo, i); 5001 if (w == NULL || w->enable == 0) 5002 continue; 5003 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5004 continue; 5005 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 5006 } 5007 5008 /* Output mixers */ 5009 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5010 w = hdac_widget_get(devinfo, i); 5011 if (w == NULL || w->enable == 0) 5012 continue; 5013 if ((strategy == HDA_PARSE_MIXER && 5014 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 5015 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 5016 && (w->pflags & HDA_DAC_PATH)) || 5017 (strategy == HDA_PARSE_DIRECT && (w->pflags & 5018 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 5019 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 5020 w->nid, devinfo->startnode - 1, 0, 0); 5021 } else if (w->type == 5022 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 5023 j = 0; 5024 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 5025 NULL) { 5026 if (ctl->enable == 0 || ctl->widget == NULL) 5027 continue; 5028 if (ctl->widget->nid != w->nid) 5029 continue; 5030 ctl->ossmask |= SOUND_MASK_VOLUME; 5031 ctl->ossmask |= SOUND_MASK_SPEAKER; 5032 ctl->ossdev = SOUND_MIXER_SPEAKER; 5033 w->ctlflags |= SOUND_MASK_VOLUME; 5034 w->ctlflags |= SOUND_MASK_SPEAKER; 5035 } 5036 } 5037 } 5038 5039 /* Input mixers (rec) */ 5040 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5041 w = hdac_widget_get(devinfo, i); 5042 if (w == NULL || w->enable == 0) 5043 continue; 5044 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 5045 w->pflags & HDA_ADC_PATH)) 5046 continue; 5047 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 5048 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 5049 } 5050 } 5051 5052 #define HDA_COMMIT_CONN (1 << 0) 5053 #define HDA_COMMIT_CTRL (1 << 1) 5054 #define HDA_COMMIT_EAPD (1 << 2) 5055 #define HDA_COMMIT_GPIO (1 << 3) 5056 #define HDA_COMMIT_MISC (1 << 4) 5057 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 5058 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 5059 5060 static void 5061 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 5062 { 5063 struct hdac_softc *sc = devinfo->codec->sc; 5064 struct hdac_widget *w; 5065 nid_t cad; 5066 int i; 5067 5068 if (!(cfl & HDA_COMMIT_ALL)) 5069 return; 5070 5071 cad = devinfo->codec->cad; 5072 5073 if ((cfl & HDA_COMMIT_MISC)) { 5074 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5075 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5076 0x7e7, 0), cad); 5077 } 5078 5079 if (cfl & HDA_COMMIT_GPIO) { 5080 uint32_t gdata, gmask, gdir; 5081 int commitgpio, numgpio; 5082 5083 gdata = 0; 5084 gmask = 0; 5085 gdir = 0; 5086 commitgpio = 0; 5087 5088 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5089 devinfo->function.audio.gpio); 5090 5091 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5092 commitgpio = (numgpio > 0) ? 1 : 0; 5093 else { 5094 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5095 if (!(devinfo->function.audio.quirks & 5096 (1 << i))) 5097 continue; 5098 if (commitgpio == 0) { 5099 commitgpio = 1; 5100 HDA_BOOTVERBOSE( 5101 gdata = hdac_command(sc, 5102 HDA_CMD_GET_GPIO_DATA(cad, 5103 devinfo->nid), cad); 5104 gmask = hdac_command(sc, 5105 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5106 devinfo->nid), cad); 5107 gdir = hdac_command(sc, 5108 HDA_CMD_GET_GPIO_DIRECTION(cad, 5109 devinfo->nid), cad); 5110 device_printf(sc->dev, 5111 "GPIO init: data=0x%08x " 5112 "mask=0x%08x dir=0x%08x\n", 5113 gdata, gmask, gdir); 5114 gdata = 0; 5115 gmask = 0; 5116 gdir = 0; 5117 ); 5118 } 5119 gdata |= 1 << i; 5120 gmask |= 1 << i; 5121 gdir |= 1 << i; 5122 } 5123 } 5124 5125 if (commitgpio != 0) { 5126 HDA_BOOTVERBOSE( 5127 device_printf(sc->dev, 5128 "GPIO commit: data=0x%08x mask=0x%08x " 5129 "dir=0x%08x\n", 5130 gdata, gmask, gdir); 5131 ); 5132 hdac_command(sc, 5133 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5134 gmask), cad); 5135 hdac_command(sc, 5136 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5137 gdir), cad); 5138 hdac_command(sc, 5139 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5140 gdata), cad); 5141 } 5142 } 5143 5144 for (i = 0; i < devinfo->nodecnt; i++) { 5145 w = &devinfo->widget[i]; 5146 if (w == NULL || w->enable == 0) 5147 continue; 5148 if (cfl & HDA_COMMIT_CONN) { 5149 if (w->selconn == -1) 5150 w->selconn = 0; 5151 if (w->nconns > 0) 5152 hdac_widget_connection_select(w, w->selconn); 5153 } 5154 if ((cfl & HDA_COMMIT_CTRL) && 5155 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5156 uint32_t pincap; 5157 5158 pincap = w->wclass.pin.cap; 5159 5160 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5161 (HDA_DAC_PATH | HDA_ADC_PATH)) 5162 device_printf(sc->dev, "WARNING: node %d " 5163 "participate both for DAC/ADC!\n", w->nid); 5164 if (w->pflags & HDA_DAC_PATH) { 5165 w->wclass.pin.ctrl &= 5166 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5167 if ((w->wclass.pin.config & 5168 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5169 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5170 w->wclass.pin.ctrl &= 5171 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5172 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5173 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5174 w->wclass.pin.ctrl |= 5175 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5176 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5177 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5178 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5179 w->wclass.pin.ctrl |= 5180 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5181 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5182 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5183 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5184 w->wclass.pin.ctrl |= 5185 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5186 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5187 } else if (w->pflags & HDA_ADC_PATH) { 5188 w->wclass.pin.ctrl &= 5189 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5190 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5191 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5192 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5193 w->wclass.pin.ctrl |= 5194 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5195 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5196 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5197 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5198 w->wclass.pin.ctrl |= 5199 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5200 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5201 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5202 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5203 w->wclass.pin.ctrl |= 5204 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5205 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5206 } else 5207 w->wclass.pin.ctrl &= ~( 5208 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5209 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5210 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5211 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5212 hdac_command(sc, 5213 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5214 w->wclass.pin.ctrl), cad); 5215 } 5216 if ((cfl & HDA_COMMIT_EAPD) && 5217 w->param.eapdbtl != HDAC_INVALID) { 5218 uint32_t val; 5219 5220 val = w->param.eapdbtl; 5221 if (devinfo->function.audio.quirks & 5222 HDA_QUIRK_EAPDINV) 5223 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5224 hdac_command(sc, 5225 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5226 val), cad); 5227 5228 } 5229 DELAY(1000); 5230 } 5231 } 5232 5233 static void 5234 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5235 { 5236 struct hdac_softc *sc = devinfo->codec->sc; 5237 struct hdac_audio_ctl *ctl; 5238 int i; 5239 5240 devinfo->function.audio.mvol = 100 | (100 << 8); 5241 i = 0; 5242 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5243 if (ctl->enable == 0 || ctl->widget == NULL) { 5244 HDA_BOOTVERBOSE( 5245 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5246 i, (ctl->widget != NULL) ? 5247 ctl->widget->nid : -1); 5248 if (ctl->childwidget != NULL) 5249 printf(" childnid=%d", 5250 ctl->childwidget->nid); 5251 if (ctl->widget == NULL) 5252 printf(" NULL WIDGET!"); 5253 printf(" DISABLED\n"); 5254 ); 5255 continue; 5256 } 5257 HDA_BOOTVERBOSE( 5258 if (ctl->ossmask == 0) { 5259 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5260 i, ctl->widget->nid); 5261 if (ctl->childwidget != NULL) 5262 printf(" childnid=%d", 5263 ctl->childwidget->nid); 5264 printf(" Bind to NONE\n"); 5265 } 5266 ); 5267 if (ctl->step > 0) { 5268 ctl->ossval = (ctl->left * 100) / ctl->step; 5269 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5270 } else 5271 ctl->ossval = 0; 5272 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5273 ctl->left, ctl->right); 5274 } 5275 } 5276 5277 static int 5278 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5279 { 5280 struct hdac_chan *ch; 5281 struct hdac_widget *w; 5282 uint32_t cap, fmtcap, pcmcap, path; 5283 int i, type, ret, max; 5284 5285 if (dir == PCMDIR_PLAY) { 5286 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5287 ch = &devinfo->codec->sc->play; 5288 path = HDA_DAC_PATH; 5289 } else { 5290 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5291 ch = &devinfo->codec->sc->rec; 5292 path = HDA_ADC_PATH; 5293 } 5294 5295 ch->caps = hdac_caps; 5296 ch->caps.fmtlist = ch->fmtlist; 5297 ch->bit16 = 1; 5298 ch->bit32 = 0; 5299 ch->pcmrates[0] = 48000; 5300 ch->pcmrates[1] = 0; 5301 5302 ret = 0; 5303 fmtcap = devinfo->function.audio.supp_stream_formats; 5304 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5305 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5306 5307 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5308 w = hdac_widget_get(devinfo, i); 5309 if (w == NULL || w->enable == 0 || w->type != type || 5310 !(w->pflags & path)) 5311 continue; 5312 cap = w->param.widget_cap; 5313 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5314 continue;*/ 5315 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5316 continue; 5317 cap = w->param.supp_stream_formats; 5318 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5319 } 5320 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5321 }*/ 5322 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5323 continue; 5324 if (ret == 0) { 5325 fmtcap = w->param.supp_stream_formats; 5326 pcmcap = w->param.supp_pcm_size_rate; 5327 } else { 5328 fmtcap &= w->param.supp_stream_formats; 5329 pcmcap &= w->param.supp_pcm_size_rate; 5330 } 5331 ch->io[ret++] = i; 5332 } 5333 ch->io[ret] = -1; 5334 5335 ch->supp_stream_formats = fmtcap; 5336 ch->supp_pcm_size_rate = pcmcap; 5337 5338 /* 5339 * 8bit = 0 5340 * 16bit = 1 5341 * 20bit = 2 5342 * 24bit = 3 5343 * 32bit = 4 5344 */ 5345 if (ret > 0) { 5346 cap = pcmcap; 5347 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5348 ch->bit16 = 1; 5349 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5350 ch->bit16 = 0; 5351 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5352 ch->bit32 = 4; 5353 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5354 ch->bit32 = 3; 5355 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5356 ch->bit32 = 2; 5357 i = 0; 5358 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5359 ch->fmtlist[i++] = AFMT_S16_LE; 5360 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5361 if (ch->bit32 > 0) { 5362 if (!(devinfo->function.audio.quirks & 5363 HDA_QUIRK_FORCESTEREO)) 5364 ch->fmtlist[i++] = AFMT_S32_LE; 5365 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5366 } 5367 ch->fmtlist[i] = 0; 5368 i = 0; 5369 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5370 ch->pcmrates[i++] = 8000; 5371 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5372 ch->pcmrates[i++] = 11025; 5373 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5374 ch->pcmrates[i++] = 16000; 5375 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5376 ch->pcmrates[i++] = 22050; 5377 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5378 ch->pcmrates[i++] = 32000; 5379 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5380 ch->pcmrates[i++] = 44100; 5381 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5382 ch->pcmrates[i++] = 48000; 5383 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5384 ch->pcmrates[i++] = 88200; 5385 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5386 ch->pcmrates[i++] = 96000; 5387 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5388 ch->pcmrates[i++] = 176400; 5389 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5390 ch->pcmrates[i++] = 192000; 5391 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5392 ch->pcmrates[i] = 0; 5393 if (i > 0) { 5394 ch->caps.minspeed = ch->pcmrates[0]; 5395 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5396 } 5397 } 5398 5399 return (ret); 5400 } 5401 5402 static void 5403 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5404 { 5405 struct hdac_audio_ctl *ctl; 5406 struct hdac_softc *sc = devinfo->codec->sc; 5407 int i; 5408 uint32_t fl = 0; 5409 5410 5411 if (flag == 0) { 5412 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5413 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5414 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5415 } 5416 5417 i = 0; 5418 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5419 if (ctl->enable == 0 || ctl->widget == NULL || 5420 ctl->widget->enable == 0 || (ctl->ossmask & 5421 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5422 continue; 5423 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5424 (flag != 0 && (ctl->ossmask & flag))) { 5425 if (banner != NULL) { 5426 device_printf(sc->dev, "\n"); 5427 device_printf(sc->dev, "%s\n", banner); 5428 } 5429 goto hdac_ctl_dump_it_all; 5430 } 5431 } 5432 5433 return; 5434 5435 hdac_ctl_dump_it_all: 5436 i = 0; 5437 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5438 if (ctl->enable == 0 || ctl->widget == NULL || 5439 ctl->widget->enable == 0) 5440 continue; 5441 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5442 (flag != 0 && (ctl->ossmask & flag)))) 5443 continue; 5444 if (flag == 0) { 5445 device_printf(sc->dev, "\n"); 5446 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5447 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5448 } 5449 device_printf(sc->dev, " |\n"); 5450 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5451 ctl->widget->nid, ctl->index); 5452 if (ctl->childwidget != NULL) 5453 printf("(nid: %2d) ", ctl->childwidget->nid); 5454 else 5455 printf(" "); 5456 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5457 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5458 ctl->ossmask); 5459 } 5460 } 5461 5462 static void 5463 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5464 { 5465 uint32_t cap; 5466 5467 cap = fcap; 5468 if (cap != 0) { 5469 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5470 device_printf(sc->dev, " Format:"); 5471 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5472 printf(" AC3"); 5473 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5474 printf(" FLOAT32"); 5475 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5476 printf(" PCM"); 5477 printf("\n"); 5478 } 5479 cap = pcmcap; 5480 if (cap != 0) { 5481 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5482 device_printf(sc->dev, " PCM size:"); 5483 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5484 printf(" 8"); 5485 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5486 printf(" 16"); 5487 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5488 printf(" 20"); 5489 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5490 printf(" 24"); 5491 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5492 printf(" 32"); 5493 printf("\n"); 5494 device_printf(sc->dev, " PCM rate:"); 5495 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5496 printf(" 8"); 5497 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5498 printf(" 11"); 5499 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5500 printf(" 16"); 5501 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5502 printf(" 22"); 5503 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5504 printf(" 32"); 5505 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5506 printf(" 44"); 5507 printf(" 48"); 5508 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5509 printf(" 88"); 5510 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5511 printf(" 96"); 5512 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5513 printf(" 176"); 5514 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5515 printf(" 192"); 5516 printf("\n"); 5517 } 5518 } 5519 5520 static void 5521 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5522 { 5523 uint32_t pincap, wcap; 5524 5525 pincap = w->wclass.pin.cap; 5526 wcap = w->param.widget_cap; 5527 5528 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5529 device_printf(sc->dev, " "); 5530 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5531 printf(" ISC"); 5532 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5533 printf(" TRQD"); 5534 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5535 printf(" PDC"); 5536 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5537 printf(" HP"); 5538 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5539 printf(" OUT"); 5540 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5541 printf(" IN"); 5542 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5543 printf(" BAL"); 5544 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5545 printf(" VREF["); 5546 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5547 printf(" 50"); 5548 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5549 printf(" 80"); 5550 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5551 printf(" 100"); 5552 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5553 printf(" GROUND"); 5554 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5555 printf(" HIZ"); 5556 printf(" ]"); 5557 } 5558 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5559 printf(" EAPD"); 5560 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5561 printf(" : UNSOL"); 5562 printf("\n"); 5563 device_printf(sc->dev, " Pin config: 0x%08x\n", 5564 w->wclass.pin.config); 5565 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5566 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5567 printf(" HP"); 5568 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5569 printf(" IN"); 5570 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5571 printf(" OUT"); 5572 printf("\n"); 5573 } 5574 5575 static void 5576 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5577 { 5578 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5579 device_printf(sc->dev, " " 5580 "mute=%d step=%d size=%d offset=%d\n", 5581 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5582 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5583 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5584 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5585 } 5586 5587 static void 5588 hdac_dump_nodes(struct hdac_devinfo *devinfo) 5589 { 5590 struct hdac_softc *sc = devinfo->codec->sc; 5591 struct hdac_widget *w, *cw; 5592 int i, j; 5593 5594 device_printf(sc->dev, "\n"); 5595 device_printf(sc->dev, "Default Parameter\n"); 5596 device_printf(sc->dev, "-----------------\n"); 5597 hdac_dump_audio_formats(sc, 5598 devinfo->function.audio.supp_stream_formats, 5599 devinfo->function.audio.supp_pcm_size_rate); 5600 device_printf(sc->dev, " IN amp: 0x%08x\n", 5601 devinfo->function.audio.inamp_cap); 5602 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5603 devinfo->function.audio.outamp_cap); 5604 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5605 w = hdac_widget_get(devinfo, i); 5606 if (w == NULL) { 5607 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5608 continue; 5609 } 5610 device_printf(sc->dev, "\n"); 5611 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5612 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5613 "DIGITAL" : "ANALOG", 5614 (w->enable == 0) ? " [DISABLED]" : ""); 5615 device_printf(sc->dev, " name: %s\n", w->name); 5616 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5617 w->param.widget_cap); 5618 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5619 w->pflags); 5620 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5621 w->ctlflags); 5622 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5623 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5624 hdac_dump_audio_formats(sc, 5625 w->param.supp_stream_formats, 5626 w->param.supp_pcm_size_rate); 5627 } else if (w->type == 5628 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5629 hdac_dump_pin(sc, w); 5630 if (w->param.eapdbtl != HDAC_INVALID) 5631 device_printf(sc->dev, " EAPD: 0x%08x\n", 5632 w->param.eapdbtl); 5633 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5634 w->param.outamp_cap != 0) 5635 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5636 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5637 w->param.inamp_cap != 0) 5638 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5639 device_printf(sc->dev, " connections: %d\n", w->nconns); 5640 for (j = 0; j < w->nconns; j++) { 5641 cw = hdac_widget_get(devinfo, w->conns[j]); 5642 device_printf(sc->dev, " |\n"); 5643 device_printf(sc->dev, " + <- nid=%d [%s]", 5644 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5645 if (cw == NULL) 5646 printf(" [UNKNOWN]"); 5647 else if (cw->enable == 0) 5648 printf(" [DISABLED]"); 5649 if (w->nconns > 1 && w->selconn == j && w->type != 5650 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5651 printf(" (selected)"); 5652 printf("\n"); 5653 } 5654 } 5655 5656 } 5657 5658 static int 5659 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5660 { 5661 struct hdac_widget *w, *cw; 5662 struct hdac_softc *sc = devinfo->codec->sc; 5663 int i; 5664 5665 if (depth > HDA_PARSE_MAXDEPTH) 5666 return (0); 5667 5668 w = hdac_widget_get(devinfo, nid); 5669 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5670 return (0); 5671 5672 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5673 device_printf(sc->dev, "\n"); 5674 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5675 device_printf(sc->dev, " ^\n"); 5676 device_printf(sc->dev, " |\n"); 5677 device_printf(sc->dev, " +-----<------+\n"); 5678 } else { 5679 device_printf(sc->dev, " ^\n"); 5680 device_printf(sc->dev, " |\n"); 5681 device_printf(sc->dev, " "); 5682 printf(" nid=%d [%s]\n", w->nid, w->name); 5683 } 5684 5685 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5686 return (1); 5687 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5688 for (i = 0; i < w->nconns; i++) { 5689 cw = hdac_widget_get(devinfo, w->conns[i]); 5690 if (cw == NULL || cw->enable == 0 || cw->type == 5691 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5692 continue; 5693 if (hdac_dump_dac_internal(devinfo, cw->nid, 5694 depth + 1) != 0) 5695 return (1); 5696 } 5697 } else if ((w->type == 5698 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5699 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5700 w->selconn > -1 && w->selconn < w->nconns) { 5701 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5702 depth + 1) != 0) 5703 return (1); 5704 } 5705 5706 return (0); 5707 } 5708 5709 static void 5710 hdac_dump_dac(struct hdac_devinfo *devinfo) 5711 { 5712 struct hdac_widget *w; 5713 struct hdac_softc *sc = devinfo->codec->sc; 5714 int i, printed = 0; 5715 5716 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5717 w = hdac_widget_get(devinfo, i); 5718 if (w == NULL || w->enable == 0) 5719 continue; 5720 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5721 !(w->pflags & HDA_DAC_PATH)) 5722 continue; 5723 if (printed == 0) { 5724 printed = 1; 5725 device_printf(sc->dev, "\n"); 5726 device_printf(sc->dev, "Playback path:\n"); 5727 } 5728 hdac_dump_dac_internal(devinfo, w->nid, 0); 5729 } 5730 } 5731 5732 static void 5733 hdac_dump_adc(struct hdac_devinfo *devinfo) 5734 { 5735 struct hdac_widget *w, *cw; 5736 struct hdac_softc *sc = devinfo->codec->sc; 5737 int i, j; 5738 int printed = 0; 5739 char ossdevs[256]; 5740 5741 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5742 w = hdac_widget_get(devinfo, i); 5743 if (w == NULL || w->enable == 0) 5744 continue; 5745 if (!(w->pflags & HDA_ADC_RECSEL)) 5746 continue; 5747 if (printed == 0) { 5748 printed = 1; 5749 device_printf(sc->dev, "\n"); 5750 device_printf(sc->dev, "Recording sources:\n"); 5751 } 5752 device_printf(sc->dev, "\n"); 5753 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5754 for (j = 0; j < w->nconns; j++) { 5755 cw = hdac_widget_get(devinfo, w->conns[j]); 5756 if (cw == NULL || cw->enable == 0) 5757 continue; 5758 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5759 ossdevs, sizeof(ossdevs)); 5760 device_printf(sc->dev, " |\n"); 5761 device_printf(sc->dev, " + <- nid=%d [%s]", 5762 cw->nid, cw->name); 5763 if (strlen(ossdevs) > 0) { 5764 printf(" [recsrc: %s]", ossdevs); 5765 } 5766 printf("\n"); 5767 } 5768 } 5769 } 5770 5771 static void 5772 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5773 { 5774 nid_t *nids; 5775 5776 if (pcnt > 0) { 5777 device_printf(sc->dev, "\n"); 5778 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5779 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5780 sc->play.supp_pcm_size_rate); 5781 device_printf(sc->dev, " DAC:"); 5782 for (nids = sc->play.io; *nids != -1; nids++) 5783 printf(" %d", *nids); 5784 printf("\n"); 5785 } 5786 5787 if (rcnt > 0) { 5788 device_printf(sc->dev, "\n"); 5789 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5790 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5791 sc->rec.supp_pcm_size_rate); 5792 device_printf(sc->dev, " ADC:"); 5793 for (nids = sc->rec.io; *nids != -1; nids++) 5794 printf(" %d", *nids); 5795 printf("\n"); 5796 } 5797 } 5798 5799 static void 5800 hdac_release_resources(struct hdac_softc *sc) 5801 { 5802 struct hdac_devinfo *devinfo = NULL; 5803 device_t *devlist = NULL; 5804 int i, devcount; 5805 5806 if (sc == NULL) 5807 return; 5808 5809 hdac_lock(sc); 5810 sc->polling = 0; 5811 sc->poll_ival = 0; 5812 callout_stop(&sc->poll_hda); 5813 callout_stop(&sc->poll_hdac); 5814 callout_stop(&sc->poll_jack); 5815 hdac_reset(sc); 5816 hdac_unlock(sc); 5817 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5818 callout_drain(&sc->poll_hda); 5819 callout_drain(&sc->poll_hdac); 5820 callout_drain(&sc->poll_jack); 5821 5822 hdac_irq_free(sc); 5823 5824 device_get_children(sc->dev, &devlist, &devcount); 5825 for (i = 0; devlist != NULL && i < devcount; i++) { 5826 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5827 if (devinfo == NULL) 5828 continue; 5829 if (devinfo->widget != NULL) 5830 free(devinfo->widget, M_HDAC); 5831 if (devinfo->node_type == 5832 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5833 devinfo->function.audio.ctl != NULL) 5834 free(devinfo->function.audio.ctl, M_HDAC); 5835 free(devinfo, M_HDAC); 5836 device_delete_child(sc->dev, devlist[i]); 5837 } 5838 if (devlist != NULL) 5839 free(devlist, M_TEMP); 5840 5841 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5842 if (sc->codecs[i] != NULL) 5843 free(sc->codecs[i], M_HDAC); 5844 sc->codecs[i] = NULL; 5845 } 5846 5847 hdac_dma_free(sc, &sc->pos_dma); 5848 hdac_dma_free(sc, &sc->rirb_dma); 5849 hdac_dma_free(sc, &sc->corb_dma); 5850 if (sc->play.blkcnt > 0) 5851 hdac_dma_free(sc, &sc->play.bdl_dma); 5852 if (sc->rec.blkcnt > 0) 5853 hdac_dma_free(sc, &sc->rec.bdl_dma); 5854 if (sc->chan_dmat != NULL) { 5855 bus_dma_tag_destroy(sc->chan_dmat); 5856 sc->chan_dmat = NULL; 5857 } 5858 hdac_mem_free(sc); 5859 snd_mtxfree(sc->lock); 5860 free(sc, M_DEVBUF); 5861 } 5862 5863 /* This function surely going to make its way into upper level someday. */ 5864 static void 5865 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5866 { 5867 const char *res = NULL; 5868 int i = 0, j, k, len, inv; 5869 5870 if (on != NULL) 5871 *on = 0; 5872 if (off != NULL) 5873 *off = 0; 5874 if (sc == NULL) 5875 return; 5876 if (resource_string_value(device_get_name(sc->dev), 5877 device_get_unit(sc->dev), "config", &res) != 0) 5878 return; 5879 if (!(res != NULL && strlen(res) > 0)) 5880 return; 5881 HDA_BOOTVERBOSE( 5882 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5883 ); 5884 for (;;) { 5885 while (res[i] != '\0' && 5886 (res[i] == ',' || isspace(res[i]) != 0)) 5887 i++; 5888 if (res[i] == '\0') { 5889 HDA_BOOTVERBOSE( 5890 printf("\n"); 5891 ); 5892 return; 5893 } 5894 j = i; 5895 while (res[j] != '\0' && 5896 !(res[j] == ',' || isspace(res[j]) != 0)) 5897 j++; 5898 len = j - i; 5899 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5900 inv = 2; 5901 else 5902 inv = 0; 5903 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5904 if (strncmp(res + i + inv, 5905 hdac_quirks_tab[k].key, len - inv) != 0) 5906 continue; 5907 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5908 break; 5909 HDA_BOOTVERBOSE( 5910 printf(" %s%s", (inv != 0) ? "no" : "", 5911 hdac_quirks_tab[k].key); 5912 ); 5913 if (inv == 0 && on != NULL) 5914 *on |= hdac_quirks_tab[k].value; 5915 else if (inv != 0 && off != NULL) 5916 *off |= hdac_quirks_tab[k].value; 5917 break; 5918 } 5919 i = j; 5920 } 5921 } 5922 5923 #ifdef SND_DYNSYSCTL 5924 static int 5925 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5926 { 5927 struct hdac_softc *sc; 5928 struct hdac_devinfo *devinfo; 5929 device_t dev; 5930 uint32_t ctl; 5931 int err, val; 5932 5933 dev = oidp->oid_arg1; 5934 devinfo = pcm_getdevinfo(dev); 5935 if (devinfo == NULL || devinfo->codec == NULL || 5936 devinfo->codec->sc == NULL) 5937 return (EINVAL); 5938 sc = devinfo->codec->sc; 5939 hdac_lock(sc); 5940 val = sc->polling; 5941 hdac_unlock(sc); 5942 err = sysctl_handle_int(oidp, &val, 0, req); 5943 5944 if (err != 0 || req->newptr == NULL) 5945 return (err); 5946 if (val < 0 || val > 1) 5947 return (EINVAL); 5948 5949 hdac_lock(sc); 5950 if (val != sc->polling) { 5951 if (hda_chan_active(sc) != 0) 5952 err = EBUSY; 5953 else if (val == 0) { 5954 callout_stop(&sc->poll_hdac); 5955 hdac_unlock(sc); 5956 callout_drain(&sc->poll_hdac); 5957 hdac_lock(sc); 5958 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5959 sc->rirb_size / 2); 5960 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5961 ctl |= HDAC_RIRBCTL_RINTCTL; 5962 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5963 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5964 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5965 sc->polling = 0; 5966 DELAY(1000); 5967 } else { 5968 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5969 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5970 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5971 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5972 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5973 hdac_unlock(sc); 5974 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5975 hdac_lock(sc); 5976 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5977 sc); 5978 sc->polling = 1; 5979 DELAY(1000); 5980 } 5981 } 5982 hdac_unlock(sc); 5983 5984 return (err); 5985 } 5986 5987 static int 5988 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5989 { 5990 struct hdac_softc *sc; 5991 struct hdac_devinfo *devinfo; 5992 device_t dev; 5993 int err, val; 5994 5995 dev = oidp->oid_arg1; 5996 devinfo = pcm_getdevinfo(dev); 5997 if (devinfo == NULL || devinfo->codec == NULL || 5998 devinfo->codec->sc == NULL) 5999 return (EINVAL); 6000 sc = devinfo->codec->sc; 6001 hdac_lock(sc); 6002 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6003 hdac_unlock(sc); 6004 err = sysctl_handle_int(oidp, &val, 0, req); 6005 6006 if (err != 0 || req->newptr == NULL) 6007 return (err); 6008 6009 if (val < 1) 6010 val = 1; 6011 if (val > 5000) 6012 val = 5000; 6013 val = ((uint64_t)val * hz) / 1000; 6014 if (val < 1) 6015 val = 1; 6016 if (val > (hz * 5)) 6017 val = hz * 5; 6018 6019 hdac_lock(sc); 6020 sc->poll_ival = val; 6021 hdac_unlock(sc); 6022 6023 return (err); 6024 } 6025 6026 #ifdef SND_DEBUG 6027 static int 6028 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6029 { 6030 struct hdac_softc *sc; 6031 struct hdac_devinfo *devinfo; 6032 struct hdac_widget *w; 6033 device_t dev; 6034 uint32_t res, pincap, timeout; 6035 int i, err, val; 6036 nid_t cad; 6037 6038 dev = oidp->oid_arg1; 6039 devinfo = pcm_getdevinfo(dev); 6040 if (devinfo == NULL || devinfo->codec == NULL || 6041 devinfo->codec->sc == NULL) 6042 return (EINVAL); 6043 val = 0; 6044 err = sysctl_handle_int(oidp, &val, 0, req); 6045 if (err != 0 || req->newptr == NULL || val == 0) 6046 return (err); 6047 sc = devinfo->codec->sc; 6048 cad = devinfo->codec->cad; 6049 hdac_lock(sc); 6050 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 6051 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6052 w = hdac_widget_get(devinfo, i); 6053 if (w == NULL || w->type != 6054 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6055 continue; 6056 pincap = w->wclass.pin.cap; 6057 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6058 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 6059 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6060 timeout = 10000; 6061 hdac_command(sc, 6062 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6063 do { 6064 res = hdac_command(sc, 6065 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6066 if (res != 0x7fffffff) 6067 break; 6068 DELAY(10); 6069 } while (--timeout != 0); 6070 } else { 6071 timeout = -1; 6072 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6073 w->nid), cad); 6074 } 6075 device_printf(dev, 6076 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 6077 w->nid, timeout, res, 6078 (w->enable == 0) ? "DISABLED" : "ENABLED"); 6079 } 6080 device_printf(dev, 6081 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6082 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6083 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6084 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6085 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6086 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6087 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6088 device_printf(dev, " GPI:"); 6089 res = hdac_command(sc, 6090 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6091 printf(" data=0x%08x", res); 6092 res = hdac_command(sc, 6093 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6094 cad); 6095 printf(" wake=0x%08x", res); 6096 res = hdac_command(sc, 6097 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6098 cad); 6099 printf(" unsol=0x%08x", res); 6100 res = hdac_command(sc, 6101 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6102 printf(" sticky=0x%08x\n", res); 6103 } 6104 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6105 device_printf(dev, " GPO:"); 6106 res = hdac_command(sc, 6107 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6108 printf(" data=0x%08x\n", res); 6109 } 6110 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6111 device_printf(dev, "GPI0:"); 6112 res = hdac_command(sc, 6113 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6114 printf(" data=0x%08x", res); 6115 res = hdac_command(sc, 6116 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6117 printf(" enable=0x%08x", res); 6118 res = hdac_command(sc, 6119 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6120 printf(" direction=0x%08x\n", res); 6121 res = hdac_command(sc, 6122 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6123 device_printf(dev, " wake=0x%08x", res); 6124 res = hdac_command(sc, 6125 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6126 cad); 6127 printf(" unsol=0x%08x", res); 6128 res = hdac_command(sc, 6129 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6130 printf(" sticky=0x%08x\n", res); 6131 } 6132 hdac_unlock(sc); 6133 return (0); 6134 } 6135 #endif 6136 #endif 6137 6138 static void 6139 hdac_attach2(void *arg) 6140 { 6141 struct hdac_softc *sc; 6142 struct hdac_widget *w; 6143 struct hdac_audio_ctl *ctl; 6144 uint32_t quirks_on, quirks_off; 6145 int pcnt, rcnt, codec_index; 6146 int i; 6147 char status[SND_STATUSLEN]; 6148 device_t *devlist = NULL; 6149 int devcount; 6150 struct hdac_devinfo *devinfo = NULL; 6151 6152 sc = (struct hdac_softc *)arg; 6153 6154 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6155 6156 HDA_BOOTVERBOSE( 6157 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6158 quirks_on, quirks_off); 6159 ); 6160 6161 if (resource_int_value(device_get_name(sc->dev), 6162 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) { 6163 switch (sc->pci_subvendor) { 6164 case GB_G33S2H_SUBVENDOR: 6165 codec_index = 2; 6166 break; 6167 default: 6168 codec_index = 0; 6169 break; 6170 } 6171 } 6172 6173 hdac_lock(sc); 6174 6175 /* Remove ourselves from the config hooks */ 6176 if (sc->intrhook.ich_func != NULL) { 6177 config_intrhook_disestablish(&sc->intrhook); 6178 sc->intrhook.ich_func = NULL; 6179 } 6180 6181 /* Start the corb and rirb engines */ 6182 HDA_BOOTVERBOSE( 6183 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6184 ); 6185 hdac_corb_start(sc); 6186 HDA_BOOTVERBOSE( 6187 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6188 ); 6189 hdac_rirb_start(sc); 6190 6191 HDA_BOOTVERBOSE( 6192 device_printf(sc->dev, 6193 "HDA_DEBUG: Enabling controller interrupt...\n"); 6194 ); 6195 if (sc->polling == 0) 6196 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6197 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6198 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6199 HDAC_GCTL_UNSOL); 6200 6201 DELAY(1000); 6202 6203 HDA_BOOTVERBOSE( 6204 device_printf(sc->dev, 6205 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n", 6206 codec_index); 6207 ); 6208 hdac_scan_codecs(sc, codec_index); 6209 6210 device_get_children(sc->dev, &devlist, &devcount); 6211 for (i = 0; devlist != NULL && i < devcount; i++) { 6212 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6213 if (devinfo != NULL && devinfo->node_type == 6214 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6215 break; 6216 } else 6217 devinfo = NULL; 6218 } 6219 if (devlist != NULL) 6220 free(devlist, M_TEMP); 6221 6222 if (devinfo == NULL) { 6223 hdac_unlock(sc); 6224 device_printf(sc->dev, "Audio Function Group not found!\n"); 6225 hdac_release_resources(sc); 6226 return; 6227 } 6228 6229 HDA_BOOTVERBOSE( 6230 device_printf(sc->dev, 6231 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6232 devinfo->nid, devinfo->codec->cad); 6233 ); 6234 hdac_audio_parse(devinfo); 6235 HDA_BOOTVERBOSE( 6236 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6237 ); 6238 hdac_audio_ctl_parse(devinfo); 6239 HDA_BOOTVERBOSE( 6240 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6241 ); 6242 hdac_vendor_patch_parse(devinfo); 6243 if (quirks_on != 0) 6244 devinfo->function.audio.quirks |= quirks_on; 6245 if (quirks_off != 0) 6246 devinfo->function.audio.quirks &= ~quirks_off; 6247 6248 /* XXX Disable all DIGITAL path. */ 6249 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6250 w = hdac_widget_get(devinfo, i); 6251 if (w == NULL) 6252 continue; 6253 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6254 w->enable = 0; 6255 continue; 6256 } 6257 /* XXX Disable useless pin ? */ 6258 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6259 (w->wclass.pin.config & 6260 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6261 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6262 w->enable = 0; 6263 } 6264 i = 0; 6265 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6266 if (ctl->widget == NULL) 6267 continue; 6268 if (ctl->ossmask & SOUND_MASK_DISABLE) 6269 ctl->enable = 0; 6270 w = ctl->widget; 6271 if (w->enable == 0 || 6272 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6273 ctl->enable = 0; 6274 w = ctl->childwidget; 6275 if (w == NULL) 6276 continue; 6277 if (w->enable == 0 || 6278 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6279 ctl->enable = 0; 6280 } 6281 6282 HDA_BOOTVERBOSE( 6283 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6284 ); 6285 hdac_audio_build_tree(devinfo); 6286 6287 i = 0; 6288 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6289 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6290 ctl->ossmask = 0; 6291 } 6292 HDA_BOOTVERBOSE( 6293 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6294 ); 6295 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6296 HDA_BOOTVERBOSE( 6297 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6298 ); 6299 hdac_audio_ctl_commit(devinfo); 6300 6301 HDA_BOOTVERBOSE( 6302 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6303 ); 6304 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6305 HDA_BOOTVERBOSE( 6306 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6307 ); 6308 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6309 6310 hdac_unlock(sc); 6311 HDA_BOOTVERBOSE( 6312 device_printf(sc->dev, 6313 "HDA_DEBUG: OSS mixer initialization...\n"); 6314 ); 6315 6316 /* 6317 * There is no point of return after this. If the driver failed, 6318 * so be it. Let the detach procedure do all the cleanup. 6319 */ 6320 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6321 device_printf(sc->dev, "Can't register mixer\n"); 6322 6323 if (pcnt > 0) 6324 pcnt = 1; 6325 if (rcnt > 0) 6326 rcnt = 1; 6327 6328 HDA_BOOTVERBOSE( 6329 device_printf(sc->dev, 6330 "HDA_DEBUG: Registering PCM channels...\n"); 6331 ); 6332 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6333 device_printf(sc->dev, "Can't register PCM\n"); 6334 6335 sc->registered++; 6336 6337 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6338 hdac_dma_alloc(sc, &sc->pos_dma, 6339 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6340 HDA_BOOTVERBOSE( 6341 device_printf(sc->dev, 6342 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6343 ); 6344 } 6345 6346 for (i = 0; i < pcnt; i++) 6347 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6348 for (i = 0; i < rcnt; i++) 6349 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6350 6351 #ifdef SND_DYNSYSCTL 6352 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6353 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6354 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6355 sysctl_hdac_polling, "I", "Enable polling mode"); 6356 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6357 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6358 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6359 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6360 "Controller/Jack Sense polling interval (1-1000 ms)"); 6361 #ifdef SND_DEBUG 6362 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6363 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6364 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6365 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6366 #endif 6367 #endif 6368 6369 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6370 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6371 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6372 pcm_setstatus(sc->dev, status); 6373 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6374 HDA_BOOTVERBOSE( 6375 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6376 hdac_codec_id(devinfo)); 6377 ); 6378 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6379 HDA_DRV_TEST_REV); 6380 6381 HDA_BOOTVERBOSE( 6382 if (devinfo->function.audio.quirks != 0) { 6383 device_printf(sc->dev, "\n"); 6384 device_printf(sc->dev, "HDA config/quirks:"); 6385 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6386 if ((devinfo->function.audio.quirks & 6387 hdac_quirks_tab[i].value) == 6388 hdac_quirks_tab[i].value) 6389 printf(" %s", hdac_quirks_tab[i].key); 6390 } 6391 printf("\n"); 6392 } 6393 device_printf(sc->dev, "\n"); 6394 device_printf(sc->dev, "+-------------------+\n"); 6395 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6396 device_printf(sc->dev, "+-------------------+\n"); 6397 hdac_dump_nodes(devinfo); 6398 device_printf(sc->dev, "\n"); 6399 device_printf(sc->dev, "+------------------------+\n"); 6400 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6401 device_printf(sc->dev, "+------------------------+\n"); 6402 device_printf(sc->dev, "\n"); 6403 i = 0; 6404 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6405 device_printf(sc->dev, "%3d: nid=%d", i, 6406 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6407 if (ctl->childwidget != NULL) 6408 printf(" cnid=%d", ctl->childwidget->nid); 6409 printf(" dir=0x%x index=%d " 6410 "ossmask=0x%08x ossdev=%d%s\n", 6411 ctl->dir, ctl->index, 6412 ctl->ossmask, ctl->ossdev, 6413 (ctl->enable == 0) ? " [DISABLED]" : ""); 6414 } 6415 device_printf(sc->dev, "\n"); 6416 device_printf(sc->dev, "+-----------------------------------+\n"); 6417 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6418 device_printf(sc->dev, "+-----------------------------------+\n"); 6419 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6420 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6421 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6422 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6423 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6424 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6425 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6426 hdac_dump_ctls(devinfo, NULL, 0); 6427 hdac_dump_dac(devinfo); 6428 hdac_dump_adc(devinfo); 6429 device_printf(sc->dev, "\n"); 6430 device_printf(sc->dev, "+--------------------------------------+\n"); 6431 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6432 device_printf(sc->dev, "+--------------------------------------+\n"); 6433 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6434 ); 6435 6436 if (sc->polling != 0) { 6437 hdac_lock(sc); 6438 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6439 hdac_unlock(sc); 6440 } 6441 } 6442 6443 /**************************************************************************** 6444 * int hdac_detach(device_t) 6445 * 6446 * Detach and free up resources utilized by the hdac device. 6447 ****************************************************************************/ 6448 static int 6449 hdac_detach(device_t dev) 6450 { 6451 struct hdac_softc *sc = NULL; 6452 struct hdac_devinfo *devinfo = NULL; 6453 int err; 6454 6455 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6456 if (devinfo != NULL && devinfo->codec != NULL) 6457 sc = devinfo->codec->sc; 6458 if (sc == NULL) 6459 return (0); 6460 6461 if (sc->registered > 0) { 6462 err = pcm_unregister(dev); 6463 if (err != 0) 6464 return (err); 6465 } 6466 6467 hdac_release_resources(sc); 6468 6469 return (0); 6470 } 6471 6472 static device_method_t hdac_methods[] = { 6473 /* device interface */ 6474 DEVMETHOD(device_probe, hdac_probe), 6475 DEVMETHOD(device_attach, hdac_attach), 6476 DEVMETHOD(device_detach, hdac_detach), 6477 { 0, 0 } 6478 }; 6479 6480 static driver_t hdac_driver = { 6481 "pcm", 6482 hdac_methods, 6483 PCM_SOFTC_SIZE, 6484 }; 6485 6486 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6487 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6488 MODULE_VERSION(snd_hda, 1); 6489