1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 5 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Intel High Definition Audio (Controller) driver for FreeBSD. 33 */ 34 35 #ifdef HAVE_KERNEL_OPTION_HEADERS 36 #include "opt_snd.h" 37 #endif 38 39 #include <dev/sound/pcm/sound.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 43 #include <sys/ctype.h> 44 #include <sys/endian.h> 45 #include <sys/taskqueue.h> 46 47 #include <dev/sound/pci/hda/hdac_private.h> 48 #include <dev/sound/pci/hda/hdac_reg.h> 49 #include <dev/sound/pci/hda/hda_reg.h> 50 #include <dev/sound/pci/hda/hdac.h> 51 52 #define HDA_DRV_TEST_REV "20120126_0002" 53 54 SND_DECLARE_FILE("$FreeBSD$"); 55 56 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 57 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 58 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 59 60 #define HDAC_QUIRK_64BIT (1 << 0) 61 #define HDAC_QUIRK_DMAPOS (1 << 1) 62 #define HDAC_QUIRK_MSI (1 << 2) 63 64 static const struct { 65 const char *key; 66 uint32_t value; 67 } hdac_quirks_tab[] = { 68 { "64bit", HDAC_QUIRK_DMAPOS }, 69 { "dmapos", HDAC_QUIRK_DMAPOS }, 70 { "msi", HDAC_QUIRK_MSI }, 71 }; 72 73 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 74 75 static const struct { 76 uint32_t model; 77 const char *desc; 78 char quirks_on; 79 char quirks_off; 80 } hdac_devices[] = { 81 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 }, 82 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 }, 83 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 }, 84 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 }, 85 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 }, 86 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 }, 87 { HDA_INTEL_BDW2, "Intel Broadwell", 0, 0 }, 88 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 89 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 90 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 91 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 }, 92 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 }, 93 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 }, 94 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 }, 95 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 }, 96 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 }, 97 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 }, 98 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 }, 99 { HDA_INTEL_KBLKLP, "Intel Kaby Lake-LP", 0, 0 }, 100 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 }, 101 { HDA_INTEL_KBLK, "Intel Kaby Lake", 0, 0 }, 102 { HDA_INTEL_KBLKH, "Intel Kaby Lake-H", 0, 0 }, 103 { HDA_INTEL_CFLK, "Intel Coffee Lake", 0, 0 }, 104 { HDA_INTEL_CNLK, "Intel Cannon Lake", 0, 0 }, 105 { HDA_INTEL_ICLK, "Intel Ice Lake", 0, 0 }, 106 { HDA_INTEL_CMLKLP, "Intel Comet Lake-LP", 0, 0 }, 107 { HDA_INTEL_CMLKH, "Intel Comet Lake-H", 0, 0 }, 108 { HDA_INTEL_TGLK, "Intel Tiger Lake", 0, 0 }, 109 { HDA_INTEL_GMLK, "Intel Gemini Lake", 0, 0 }, 110 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 111 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 112 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 113 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 114 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 115 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 116 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 117 { HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 }, 118 { HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 }, 119 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 120 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 121 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 122 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 123 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 124 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 125 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 126 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 127 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 128 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 129 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 130 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 131 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 132 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 133 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 134 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 135 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 136 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 137 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 138 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 139 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 140 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 141 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 142 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 143 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 144 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 145 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 146 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 147 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 148 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 149 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 150 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 151 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 152 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 153 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 154 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 155 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 156 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 157 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 158 { HDA_ATI_R600, "ATI R600", 0, 0 }, 159 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 160 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 161 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 162 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 163 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 164 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 165 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 166 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 167 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 168 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 169 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 170 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 171 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 172 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 173 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 174 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 175 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 176 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 }, 177 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 178 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 179 { HDA_SIS_966, "SiS 966/968", 0, 0 }, 180 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 181 /* Unknown */ 182 { HDA_INTEL_ALL, "Intel", 0, 0 }, 183 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 184 { HDA_ATI_ALL, "ATI", 0, 0 }, 185 { HDA_AMD_ALL, "AMD", 0, 0 }, 186 { HDA_CREATIVE_ALL, "Creative", 0, 0 }, 187 { HDA_VIA_ALL, "VIA", 0, 0 }, 188 { HDA_SIS_ALL, "SiS", 0, 0 }, 189 { HDA_ULI_ALL, "ULI", 0, 0 }, 190 }; 191 192 static const struct { 193 uint16_t vendor; 194 uint8_t reg; 195 uint8_t mask; 196 uint8_t enable; 197 } hdac_pcie_snoop[] = { 198 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 199 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 200 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 201 }; 202 203 /**************************************************************************** 204 * Function prototypes 205 ****************************************************************************/ 206 static void hdac_intr_handler(void *); 207 static int hdac_reset(struct hdac_softc *, int); 208 static int hdac_get_capabilities(struct hdac_softc *); 209 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 210 static int hdac_dma_alloc(struct hdac_softc *, 211 struct hdac_dma *, bus_size_t); 212 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 213 static int hdac_mem_alloc(struct hdac_softc *); 214 static void hdac_mem_free(struct hdac_softc *); 215 static int hdac_irq_alloc(struct hdac_softc *); 216 static void hdac_irq_free(struct hdac_softc *); 217 static void hdac_corb_init(struct hdac_softc *); 218 static void hdac_rirb_init(struct hdac_softc *); 219 static void hdac_corb_start(struct hdac_softc *); 220 static void hdac_rirb_start(struct hdac_softc *); 221 222 static void hdac_attach2(void *); 223 224 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 225 226 static int hdac_probe(device_t); 227 static int hdac_attach(device_t); 228 static int hdac_detach(device_t); 229 static int hdac_suspend(device_t); 230 static int hdac_resume(device_t); 231 232 static int hdac_rirb_flush(struct hdac_softc *sc); 233 static int hdac_unsolq_flush(struct hdac_softc *sc); 234 235 #define hdac_command(a1, a2, a3) \ 236 hdac_send_command(a1, a3, a2) 237 238 /* This function surely going to make its way into upper level someday. */ 239 static void 240 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 241 { 242 const char *res = NULL; 243 int i = 0, j, k, len, inv; 244 245 if (resource_string_value(device_get_name(sc->dev), 246 device_get_unit(sc->dev), "config", &res) != 0) 247 return; 248 if (!(res != NULL && strlen(res) > 0)) 249 return; 250 HDA_BOOTVERBOSE( 251 device_printf(sc->dev, "Config options:"); 252 ); 253 for (;;) { 254 while (res[i] != '\0' && 255 (res[i] == ',' || isspace(res[i]) != 0)) 256 i++; 257 if (res[i] == '\0') { 258 HDA_BOOTVERBOSE( 259 printf("\n"); 260 ); 261 return; 262 } 263 j = i; 264 while (res[j] != '\0' && 265 !(res[j] == ',' || isspace(res[j]) != 0)) 266 j++; 267 len = j - i; 268 if (len > 2 && strncmp(res + i, "no", 2) == 0) 269 inv = 2; 270 else 271 inv = 0; 272 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) { 273 if (strncmp(res + i + inv, 274 hdac_quirks_tab[k].key, len - inv) != 0) 275 continue; 276 if (len - inv != strlen(hdac_quirks_tab[k].key)) 277 continue; 278 HDA_BOOTVERBOSE( 279 printf(" %s%s", (inv != 0) ? "no" : "", 280 hdac_quirks_tab[k].key); 281 ); 282 if (inv == 0) { 283 *on |= hdac_quirks_tab[k].value; 284 *on &= ~hdac_quirks_tab[k].value; 285 } else if (inv != 0) { 286 *off |= hdac_quirks_tab[k].value; 287 *off &= ~hdac_quirks_tab[k].value; 288 } 289 break; 290 } 291 i = j; 292 } 293 } 294 295 /**************************************************************************** 296 * void hdac_intr_handler(void *) 297 * 298 * Interrupt handler. Processes interrupts received from the hdac. 299 ****************************************************************************/ 300 static void 301 hdac_intr_handler(void *context) 302 { 303 struct hdac_softc *sc; 304 device_t dev; 305 uint32_t intsts; 306 uint8_t rirbsts; 307 int i; 308 309 sc = (struct hdac_softc *)context; 310 hdac_lock(sc); 311 312 /* Do we have anything to do? */ 313 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 314 if ((intsts & HDAC_INTSTS_GIS) == 0) { 315 hdac_unlock(sc); 316 return; 317 } 318 319 /* Was this a controller interrupt? */ 320 if (intsts & HDAC_INTSTS_CIS) { 321 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 322 /* Get as many responses that we can */ 323 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 324 HDAC_WRITE_1(&sc->mem, 325 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 326 hdac_rirb_flush(sc); 327 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 328 } 329 if (sc->unsolq_rp != sc->unsolq_wp) 330 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 331 } 332 333 if (intsts & HDAC_INTSTS_SIS_MASK) { 334 for (i = 0; i < sc->num_ss; i++) { 335 if ((intsts & (1 << i)) == 0) 336 continue; 337 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 338 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 339 if ((dev = sc->streams[i].dev) != NULL) { 340 HDAC_STREAM_INTR(dev, 341 sc->streams[i].dir, sc->streams[i].stream); 342 } 343 } 344 } 345 346 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 347 hdac_unlock(sc); 348 } 349 350 static void 351 hdac_poll_callback(void *arg) 352 { 353 struct hdac_softc *sc = arg; 354 355 if (sc == NULL) 356 return; 357 358 hdac_lock(sc); 359 if (sc->polling == 0) { 360 hdac_unlock(sc); 361 return; 362 } 363 callout_reset(&sc->poll_callout, sc->poll_ival, hdac_poll_callback, sc); 364 hdac_unlock(sc); 365 366 hdac_intr_handler(sc); 367 } 368 369 /**************************************************************************** 370 * int hdac_reset(hdac_softc *, int) 371 * 372 * Reset the hdac to a quiescent and known state. 373 ****************************************************************************/ 374 static int 375 hdac_reset(struct hdac_softc *sc, int wakeup) 376 { 377 uint32_t gctl; 378 int count, i; 379 380 /* 381 * Stop all Streams DMA engine 382 */ 383 for (i = 0; i < sc->num_iss; i++) 384 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 385 for (i = 0; i < sc->num_oss; i++) 386 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 387 for (i = 0; i < sc->num_bss; i++) 388 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 389 390 /* 391 * Stop Control DMA engines. 392 */ 393 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 394 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 395 396 /* 397 * Reset DMA position buffer. 398 */ 399 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 400 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 401 402 /* 403 * Reset the controller. The reset must remain asserted for 404 * a minimum of 100us. 405 */ 406 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 407 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 408 count = 10000; 409 do { 410 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 411 if (!(gctl & HDAC_GCTL_CRST)) 412 break; 413 DELAY(10); 414 } while (--count); 415 if (gctl & HDAC_GCTL_CRST) { 416 device_printf(sc->dev, "Unable to put hdac in reset\n"); 417 return (ENXIO); 418 } 419 420 /* If wakeup is not requested - leave the controller in reset state. */ 421 if (!wakeup) 422 return (0); 423 424 DELAY(100); 425 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 426 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 427 count = 10000; 428 do { 429 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 430 if (gctl & HDAC_GCTL_CRST) 431 break; 432 DELAY(10); 433 } while (--count); 434 if (!(gctl & HDAC_GCTL_CRST)) { 435 device_printf(sc->dev, "Device stuck in reset\n"); 436 return (ENXIO); 437 } 438 439 /* 440 * Wait for codecs to finish their own reset sequence. The delay here 441 * must be at least 521us (HDA 1.0a section 4.3 Codec Discovery). 442 */ 443 DELAY(1000); 444 445 return (0); 446 } 447 448 /**************************************************************************** 449 * int hdac_get_capabilities(struct hdac_softc *); 450 * 451 * Retreive the general capabilities of the hdac; 452 * Number of Input Streams 453 * Number of Output Streams 454 * Number of bidirectional Streams 455 * 64bit ready 456 * CORB and RIRB sizes 457 ****************************************************************************/ 458 static int 459 hdac_get_capabilities(struct hdac_softc *sc) 460 { 461 uint16_t gcap; 462 uint8_t corbsize, rirbsize; 463 464 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 465 sc->num_iss = HDAC_GCAP_ISS(gcap); 466 sc->num_oss = HDAC_GCAP_OSS(gcap); 467 sc->num_bss = HDAC_GCAP_BSS(gcap); 468 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 469 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 470 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 471 if (sc->quirks_on & HDAC_QUIRK_64BIT) 472 sc->support_64bit = 1; 473 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 474 sc->support_64bit = 0; 475 476 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 477 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 478 HDAC_CORBSIZE_CORBSZCAP_256) 479 sc->corb_size = 256; 480 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 481 HDAC_CORBSIZE_CORBSZCAP_16) 482 sc->corb_size = 16; 483 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 484 HDAC_CORBSIZE_CORBSZCAP_2) 485 sc->corb_size = 2; 486 else { 487 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 488 __func__, corbsize); 489 return (ENXIO); 490 } 491 492 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 493 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 494 HDAC_RIRBSIZE_RIRBSZCAP_256) 495 sc->rirb_size = 256; 496 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 497 HDAC_RIRBSIZE_RIRBSZCAP_16) 498 sc->rirb_size = 16; 499 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 500 HDAC_RIRBSIZE_RIRBSZCAP_2) 501 sc->rirb_size = 2; 502 else { 503 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 504 __func__, rirbsize); 505 return (ENXIO); 506 } 507 508 HDA_BOOTVERBOSE( 509 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 510 "NSDO %d%s, CORB %d, RIRB %d\n", 511 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 512 sc->support_64bit ? ", 64bit" : "", 513 sc->corb_size, sc->rirb_size); 514 ); 515 516 return (0); 517 } 518 519 520 /**************************************************************************** 521 * void hdac_dma_cb 522 * 523 * This function is called by bus_dmamap_load when the mapping has been 524 * established. We just record the physical address of the mapping into 525 * the struct hdac_dma passed in. 526 ****************************************************************************/ 527 static void 528 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 529 { 530 struct hdac_dma *dma; 531 532 if (error == 0) { 533 dma = (struct hdac_dma *)callback_arg; 534 dma->dma_paddr = segs[0].ds_addr; 535 } 536 } 537 538 539 /**************************************************************************** 540 * int hdac_dma_alloc 541 * 542 * This function allocate and setup a dma region (struct hdac_dma). 543 * It must be freed by a corresponding hdac_dma_free. 544 ****************************************************************************/ 545 static int 546 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 547 { 548 bus_size_t roundsz; 549 int result; 550 551 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 552 bzero(dma, sizeof(*dma)); 553 554 /* 555 * Create a DMA tag 556 */ 557 result = bus_dma_tag_create( 558 bus_get_dma_tag(sc->dev), /* parent */ 559 HDA_DMA_ALIGNMENT, /* alignment */ 560 0, /* boundary */ 561 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 562 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 563 BUS_SPACE_MAXADDR, /* highaddr */ 564 NULL, /* filtfunc */ 565 NULL, /* fistfuncarg */ 566 roundsz, /* maxsize */ 567 1, /* nsegments */ 568 roundsz, /* maxsegsz */ 569 0, /* flags */ 570 NULL, /* lockfunc */ 571 NULL, /* lockfuncarg */ 572 &dma->dma_tag); /* dmat */ 573 if (result != 0) { 574 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%d)\n", 575 __func__, result); 576 goto hdac_dma_alloc_fail; 577 } 578 579 /* 580 * Allocate DMA memory 581 */ 582 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 583 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 584 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 585 BUS_DMA_COHERENT), 586 &dma->dma_map); 587 if (result != 0) { 588 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%d)\n", 589 __func__, result); 590 goto hdac_dma_alloc_fail; 591 } 592 593 dma->dma_size = roundsz; 594 595 /* 596 * Map the memory 597 */ 598 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 599 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 600 if (result != 0 || dma->dma_paddr == 0) { 601 if (result == 0) 602 result = ENOMEM; 603 device_printf(sc->dev, "%s: bus_dmamem_load failed (%d)\n", 604 __func__, result); 605 goto hdac_dma_alloc_fail; 606 } 607 608 HDA_BOOTHVERBOSE( 609 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 610 __func__, (uintmax_t)size, (uintmax_t)roundsz); 611 ); 612 613 return (0); 614 615 hdac_dma_alloc_fail: 616 hdac_dma_free(sc, dma); 617 618 return (result); 619 } 620 621 /**************************************************************************** 622 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 623 * 624 * Free a struct hdac_dma that has been previously allocated via the 625 * hdac_dma_alloc function. 626 ****************************************************************************/ 627 static void 628 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 629 { 630 if (dma->dma_paddr != 0) { 631 /* Flush caches */ 632 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 633 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 634 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 635 dma->dma_paddr = 0; 636 } 637 if (dma->dma_vaddr != NULL) { 638 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 639 dma->dma_vaddr = NULL; 640 } 641 if (dma->dma_tag != NULL) { 642 bus_dma_tag_destroy(dma->dma_tag); 643 dma->dma_tag = NULL; 644 } 645 dma->dma_size = 0; 646 } 647 648 /**************************************************************************** 649 * int hdac_mem_alloc(struct hdac_softc *) 650 * 651 * Allocate all the bus resources necessary to speak with the physical 652 * controller. 653 ****************************************************************************/ 654 static int 655 hdac_mem_alloc(struct hdac_softc *sc) 656 { 657 struct hdac_mem *mem; 658 659 mem = &sc->mem; 660 mem->mem_rid = PCIR_BAR(0); 661 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 662 &mem->mem_rid, RF_ACTIVE); 663 if (mem->mem_res == NULL) { 664 device_printf(sc->dev, 665 "%s: Unable to allocate memory resource\n", __func__); 666 return (ENOMEM); 667 } 668 mem->mem_tag = rman_get_bustag(mem->mem_res); 669 mem->mem_handle = rman_get_bushandle(mem->mem_res); 670 671 return (0); 672 } 673 674 /**************************************************************************** 675 * void hdac_mem_free(struct hdac_softc *) 676 * 677 * Free up resources previously allocated by hdac_mem_alloc. 678 ****************************************************************************/ 679 static void 680 hdac_mem_free(struct hdac_softc *sc) 681 { 682 struct hdac_mem *mem; 683 684 mem = &sc->mem; 685 if (mem->mem_res != NULL) 686 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 687 mem->mem_res); 688 mem->mem_res = NULL; 689 } 690 691 /**************************************************************************** 692 * int hdac_irq_alloc(struct hdac_softc *) 693 * 694 * Allocate and setup the resources necessary for interrupt handling. 695 ****************************************************************************/ 696 static int 697 hdac_irq_alloc(struct hdac_softc *sc) 698 { 699 struct hdac_irq *irq; 700 int result; 701 702 irq = &sc->irq; 703 irq->irq_rid = 0x0; 704 705 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 706 (result = pci_msi_count(sc->dev)) == 1 && 707 pci_alloc_msi(sc->dev, &result) == 0) 708 irq->irq_rid = 0x1; 709 710 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 711 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 712 if (irq->irq_res == NULL) { 713 device_printf(sc->dev, "%s: Unable to allocate irq\n", 714 __func__); 715 goto hdac_irq_alloc_fail; 716 } 717 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 718 NULL, hdac_intr_handler, sc, &irq->irq_handle); 719 if (result != 0) { 720 device_printf(sc->dev, 721 "%s: Unable to setup interrupt handler (%d)\n", 722 __func__, result); 723 goto hdac_irq_alloc_fail; 724 } 725 726 return (0); 727 728 hdac_irq_alloc_fail: 729 hdac_irq_free(sc); 730 731 return (ENXIO); 732 } 733 734 /**************************************************************************** 735 * void hdac_irq_free(struct hdac_softc *) 736 * 737 * Free up resources previously allocated by hdac_irq_alloc. 738 ****************************************************************************/ 739 static void 740 hdac_irq_free(struct hdac_softc *sc) 741 { 742 struct hdac_irq *irq; 743 744 irq = &sc->irq; 745 if (irq->irq_res != NULL && irq->irq_handle != NULL) 746 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 747 if (irq->irq_res != NULL) 748 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 749 irq->irq_res); 750 if (irq->irq_rid == 0x1) 751 pci_release_msi(sc->dev); 752 irq->irq_handle = NULL; 753 irq->irq_res = NULL; 754 irq->irq_rid = 0x0; 755 } 756 757 /**************************************************************************** 758 * void hdac_corb_init(struct hdac_softc *) 759 * 760 * Initialize the corb registers for operations but do not start it up yet. 761 * The CORB engine must not be running when this function is called. 762 ****************************************************************************/ 763 static void 764 hdac_corb_init(struct hdac_softc *sc) 765 { 766 uint8_t corbsize; 767 uint64_t corbpaddr; 768 769 /* Setup the CORB size. */ 770 switch (sc->corb_size) { 771 case 256: 772 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 773 break; 774 case 16: 775 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 776 break; 777 case 2: 778 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 779 break; 780 default: 781 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 782 } 783 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 784 785 /* Setup the CORB Address in the hdac */ 786 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 787 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 788 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 789 790 /* Set the WP and RP */ 791 sc->corb_wp = 0; 792 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 793 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 794 /* 795 * The HDA specification indicates that the CORBRPRST bit will always 796 * read as zero. Unfortunately, it seems that at least the 82801G 797 * doesn't reset the bit to zero, which stalls the corb engine. 798 * manually reset the bit to zero before continuing. 799 */ 800 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 801 802 /* Enable CORB error reporting */ 803 #if 0 804 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 805 #endif 806 } 807 808 /**************************************************************************** 809 * void hdac_rirb_init(struct hdac_softc *) 810 * 811 * Initialize the rirb registers for operations but do not start it up yet. 812 * The RIRB engine must not be running when this function is called. 813 ****************************************************************************/ 814 static void 815 hdac_rirb_init(struct hdac_softc *sc) 816 { 817 uint8_t rirbsize; 818 uint64_t rirbpaddr; 819 820 /* Setup the RIRB size. */ 821 switch (sc->rirb_size) { 822 case 256: 823 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 824 break; 825 case 16: 826 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 827 break; 828 case 2: 829 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 830 break; 831 default: 832 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 833 } 834 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 835 836 /* Setup the RIRB Address in the hdac */ 837 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 838 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 839 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 840 841 /* Setup the WP and RP */ 842 sc->rirb_rp = 0; 843 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 844 845 /* Setup the interrupt threshold */ 846 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 847 848 /* Enable Overrun and response received reporting */ 849 #if 0 850 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 851 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 852 #else 853 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 854 #endif 855 856 /* 857 * Make sure that the Host CPU cache doesn't contain any dirty 858 * cache lines that falls in the rirb. If I understood correctly, it 859 * should be sufficient to do this only once as the rirb is purely 860 * read-only from now on. 861 */ 862 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 863 BUS_DMASYNC_PREREAD); 864 } 865 866 /**************************************************************************** 867 * void hdac_corb_start(hdac_softc *) 868 * 869 * Startup the corb DMA engine 870 ****************************************************************************/ 871 static void 872 hdac_corb_start(struct hdac_softc *sc) 873 { 874 uint32_t corbctl; 875 876 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 877 corbctl |= HDAC_CORBCTL_CORBRUN; 878 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 879 } 880 881 /**************************************************************************** 882 * void hdac_rirb_start(hdac_softc *) 883 * 884 * Startup the rirb DMA engine 885 ****************************************************************************/ 886 static void 887 hdac_rirb_start(struct hdac_softc *sc) 888 { 889 uint32_t rirbctl; 890 891 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 892 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 893 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 894 } 895 896 static int 897 hdac_rirb_flush(struct hdac_softc *sc) 898 { 899 struct hdac_rirb *rirb_base, *rirb; 900 nid_t cad; 901 uint32_t resp, resp_ex; 902 uint8_t rirbwp; 903 int ret; 904 905 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 906 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 907 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 908 BUS_DMASYNC_POSTREAD); 909 910 ret = 0; 911 while (sc->rirb_rp != rirbwp) { 912 sc->rirb_rp++; 913 sc->rirb_rp %= sc->rirb_size; 914 rirb = &rirb_base[sc->rirb_rp]; 915 resp = le32toh(rirb->response); 916 resp_ex = le32toh(rirb->response_ex); 917 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(resp_ex); 918 if (resp_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 919 sc->unsolq[sc->unsolq_wp++] = resp; 920 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 921 sc->unsolq[sc->unsolq_wp++] = cad; 922 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 923 } else if (sc->codecs[cad].pending <= 0) { 924 device_printf(sc->dev, "Unexpected unsolicited " 925 "response from address %d: %08x\n", cad, resp); 926 } else { 927 sc->codecs[cad].response = resp; 928 sc->codecs[cad].pending--; 929 } 930 ret++; 931 } 932 933 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 934 BUS_DMASYNC_PREREAD); 935 return (ret); 936 } 937 938 static int 939 hdac_unsolq_flush(struct hdac_softc *sc) 940 { 941 device_t child; 942 nid_t cad; 943 uint32_t resp; 944 int ret = 0; 945 946 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 947 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 948 while (sc->unsolq_rp != sc->unsolq_wp) { 949 resp = sc->unsolq[sc->unsolq_rp++]; 950 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 951 cad = sc->unsolq[sc->unsolq_rp++]; 952 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 953 if ((child = sc->codecs[cad].dev) != NULL) 954 HDAC_UNSOL_INTR(child, resp); 955 ret++; 956 } 957 sc->unsolq_st = HDAC_UNSOLQ_READY; 958 } 959 960 return (ret); 961 } 962 963 /**************************************************************************** 964 * uint32_t hdac_send_command 965 * 966 * Wrapper function that sends only one command to a given codec 967 ****************************************************************************/ 968 static uint32_t 969 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 970 { 971 int timeout; 972 uint32_t *corb; 973 974 hdac_lockassert(sc); 975 verb &= ~HDA_CMD_CAD_MASK; 976 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 977 sc->codecs[cad].response = HDA_INVALID; 978 979 sc->codecs[cad].pending++; 980 sc->corb_wp++; 981 sc->corb_wp %= sc->corb_size; 982 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 983 bus_dmamap_sync(sc->corb_dma.dma_tag, 984 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 985 corb[sc->corb_wp] = htole32(verb); 986 bus_dmamap_sync(sc->corb_dma.dma_tag, 987 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 988 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 989 990 timeout = 10000; 991 do { 992 if (hdac_rirb_flush(sc) == 0) 993 DELAY(10); 994 } while (sc->codecs[cad].pending != 0 && --timeout); 995 996 if (sc->codecs[cad].pending != 0) { 997 device_printf(sc->dev, "Command 0x%08x timeout on address %d\n", 998 verb, cad); 999 sc->codecs[cad].pending = 0; 1000 } 1001 1002 if (sc->unsolq_rp != sc->unsolq_wp) 1003 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1004 return (sc->codecs[cad].response); 1005 } 1006 1007 /**************************************************************************** 1008 * Device Methods 1009 ****************************************************************************/ 1010 1011 /**************************************************************************** 1012 * int hdac_probe(device_t) 1013 * 1014 * Probe for the presence of an hdac. If none is found, check for a generic 1015 * match using the subclass of the device. 1016 ****************************************************************************/ 1017 static int 1018 hdac_probe(device_t dev) 1019 { 1020 int i, result; 1021 uint32_t model; 1022 uint16_t class, subclass; 1023 char desc[64]; 1024 1025 model = (uint32_t)pci_get_device(dev) << 16; 1026 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1027 class = pci_get_class(dev); 1028 subclass = pci_get_subclass(dev); 1029 1030 bzero(desc, sizeof(desc)); 1031 result = ENXIO; 1032 for (i = 0; i < nitems(hdac_devices); i++) { 1033 if (hdac_devices[i].model == model) { 1034 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1035 result = BUS_PROBE_DEFAULT; 1036 break; 1037 } 1038 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1039 class == PCIC_MULTIMEDIA && 1040 subclass == PCIS_MULTIMEDIA_HDA) { 1041 snprintf(desc, sizeof(desc), "%s (0x%04x)", 1042 hdac_devices[i].desc, pci_get_device(dev)); 1043 result = BUS_PROBE_GENERIC; 1044 break; 1045 } 1046 } 1047 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1048 subclass == PCIS_MULTIMEDIA_HDA) { 1049 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1050 result = BUS_PROBE_GENERIC; 1051 } 1052 if (result != ENXIO) { 1053 strlcat(desc, " HDA Controller", sizeof(desc)); 1054 device_set_desc_copy(dev, desc); 1055 } 1056 1057 return (result); 1058 } 1059 1060 static void 1061 hdac_unsolq_task(void *context, int pending) 1062 { 1063 struct hdac_softc *sc; 1064 1065 sc = (struct hdac_softc *)context; 1066 1067 hdac_lock(sc); 1068 hdac_unsolq_flush(sc); 1069 hdac_unlock(sc); 1070 } 1071 1072 /**************************************************************************** 1073 * int hdac_attach(device_t) 1074 * 1075 * Attach the device into the kernel. Interrupts usually won't be enabled 1076 * when this function is called. Setup everything that doesn't require 1077 * interrupts and defer probing of codecs until interrupts are enabled. 1078 ****************************************************************************/ 1079 static int 1080 hdac_attach(device_t dev) 1081 { 1082 struct hdac_softc *sc; 1083 int result; 1084 int i, devid = -1; 1085 uint32_t model; 1086 uint16_t class, subclass; 1087 uint16_t vendor; 1088 uint8_t v; 1089 1090 sc = device_get_softc(dev); 1091 HDA_BOOTVERBOSE( 1092 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n", 1093 pci_get_subvendor(dev), pci_get_subdevice(dev)); 1094 device_printf(dev, "HDA Driver Revision: %s\n", 1095 HDA_DRV_TEST_REV); 1096 ); 1097 1098 model = (uint32_t)pci_get_device(dev) << 16; 1099 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1100 class = pci_get_class(dev); 1101 subclass = pci_get_subclass(dev); 1102 1103 for (i = 0; i < nitems(hdac_devices); i++) { 1104 if (hdac_devices[i].model == model) { 1105 devid = i; 1106 break; 1107 } 1108 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1109 class == PCIC_MULTIMEDIA && 1110 subclass == PCIS_MULTIMEDIA_HDA) { 1111 devid = i; 1112 break; 1113 } 1114 } 1115 1116 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1117 sc->dev = dev; 1118 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1119 callout_init(&sc->poll_callout, 1); 1120 for (i = 0; i < HDAC_CODEC_MAX; i++) 1121 sc->codecs[i].dev = NULL; 1122 if (devid >= 0) { 1123 sc->quirks_on = hdac_devices[devid].quirks_on; 1124 sc->quirks_off = hdac_devices[devid].quirks_off; 1125 } else { 1126 sc->quirks_on = 0; 1127 sc->quirks_off = 0; 1128 } 1129 if (resource_int_value(device_get_name(dev), 1130 device_get_unit(dev), "msi", &i) == 0) { 1131 if (i == 0) 1132 sc->quirks_off |= HDAC_QUIRK_MSI; 1133 else { 1134 sc->quirks_on |= HDAC_QUIRK_MSI; 1135 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1136 } 1137 } 1138 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1139 HDA_BOOTVERBOSE( 1140 device_printf(sc->dev, 1141 "Config options: on=0x%08x off=0x%08x\n", 1142 sc->quirks_on, sc->quirks_off); 1143 ); 1144 sc->poll_ival = hz; 1145 if (resource_int_value(device_get_name(dev), 1146 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1147 sc->polling = 1; 1148 else 1149 sc->polling = 0; 1150 1151 pci_enable_busmaster(dev); 1152 1153 vendor = pci_get_vendor(dev); 1154 if (vendor == INTEL_VENDORID) { 1155 /* TCSEL -> TC0 */ 1156 v = pci_read_config(dev, 0x44, 1); 1157 pci_write_config(dev, 0x44, v & 0xf8, 1); 1158 HDA_BOOTHVERBOSE( 1159 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1160 pci_read_config(dev, 0x44, 1)); 1161 ); 1162 } 1163 1164 #if defined(__i386__) || defined(__amd64__) 1165 sc->flags |= HDAC_F_DMA_NOCACHE; 1166 1167 if (resource_int_value(device_get_name(dev), 1168 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 1169 #else 1170 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1171 #endif 1172 /* 1173 * Try to enable PCIe snoop to avoid messing around with 1174 * uncacheable DMA attribute. Since PCIe snoop register 1175 * config is pretty much vendor specific, there are no 1176 * general solutions on how to enable it, forcing us (even 1177 * Microsoft) to enable uncacheable or write combined DMA 1178 * by default. 1179 * 1180 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 1181 */ 1182 for (i = 0; i < nitems(hdac_pcie_snoop); i++) { 1183 if (hdac_pcie_snoop[i].vendor != vendor) 1184 continue; 1185 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1186 if (hdac_pcie_snoop[i].reg == 0x00) 1187 break; 1188 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1189 if ((v & hdac_pcie_snoop[i].enable) == 1190 hdac_pcie_snoop[i].enable) 1191 break; 1192 v &= hdac_pcie_snoop[i].mask; 1193 v |= hdac_pcie_snoop[i].enable; 1194 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 1195 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1196 if ((v & hdac_pcie_snoop[i].enable) != 1197 hdac_pcie_snoop[i].enable) { 1198 HDA_BOOTVERBOSE( 1199 device_printf(dev, 1200 "WARNING: Failed to enable PCIe " 1201 "snoop!\n"); 1202 ); 1203 #if defined(__i386__) || defined(__amd64__) 1204 sc->flags |= HDAC_F_DMA_NOCACHE; 1205 #endif 1206 } 1207 break; 1208 } 1209 #if defined(__i386__) || defined(__amd64__) 1210 } 1211 #endif 1212 1213 HDA_BOOTHVERBOSE( 1214 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1215 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1216 "Uncacheable" : "PCIe snoop", vendor); 1217 ); 1218 1219 /* Allocate resources */ 1220 result = hdac_mem_alloc(sc); 1221 if (result != 0) 1222 goto hdac_attach_fail; 1223 result = hdac_irq_alloc(sc); 1224 if (result != 0) 1225 goto hdac_attach_fail; 1226 1227 /* Get Capabilities */ 1228 result = hdac_get_capabilities(sc); 1229 if (result != 0) 1230 goto hdac_attach_fail; 1231 1232 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1233 result = hdac_dma_alloc(sc, &sc->corb_dma, 1234 sc->corb_size * sizeof(uint32_t)); 1235 if (result != 0) 1236 goto hdac_attach_fail; 1237 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1238 sc->rirb_size * sizeof(struct hdac_rirb)); 1239 if (result != 0) 1240 goto hdac_attach_fail; 1241 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, 1242 M_HDAC, M_ZERO | M_WAITOK); 1243 for (i = 0; i < sc->num_ss; i++) { 1244 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1245 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1246 if (result != 0) 1247 goto hdac_attach_fail; 1248 } 1249 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1250 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1251 HDA_BOOTVERBOSE( 1252 device_printf(dev, "Failed to " 1253 "allocate DMA pos buffer " 1254 "(non-fatal)\n"); 1255 ); 1256 } else { 1257 uint64_t addr = sc->pos_dma.dma_paddr; 1258 1259 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1260 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1261 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1262 HDAC_DPLBASE_DPLBASE_DMAPBE); 1263 } 1264 } 1265 1266 result = bus_dma_tag_create( 1267 bus_get_dma_tag(sc->dev), /* parent */ 1268 HDA_DMA_ALIGNMENT, /* alignment */ 1269 0, /* boundary */ 1270 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1271 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1272 BUS_SPACE_MAXADDR, /* highaddr */ 1273 NULL, /* filtfunc */ 1274 NULL, /* fistfuncarg */ 1275 HDA_BUFSZ_MAX, /* maxsize */ 1276 1, /* nsegments */ 1277 HDA_BUFSZ_MAX, /* maxsegsz */ 1278 0, /* flags */ 1279 NULL, /* lockfunc */ 1280 NULL, /* lockfuncarg */ 1281 &sc->chan_dmat); /* dmat */ 1282 if (result != 0) { 1283 device_printf(dev, "%s: bus_dma_tag_create failed (%d)\n", 1284 __func__, result); 1285 goto hdac_attach_fail; 1286 } 1287 1288 /* Quiesce everything */ 1289 HDA_BOOTHVERBOSE( 1290 device_printf(dev, "Reset controller...\n"); 1291 ); 1292 hdac_reset(sc, 1); 1293 1294 /* Initialize the CORB and RIRB */ 1295 hdac_corb_init(sc); 1296 hdac_rirb_init(sc); 1297 1298 /* Defer remaining of initialization until interrupts are enabled */ 1299 sc->intrhook.ich_func = hdac_attach2; 1300 sc->intrhook.ich_arg = (void *)sc; 1301 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1302 sc->intrhook.ich_func = NULL; 1303 hdac_attach2((void *)sc); 1304 } 1305 1306 return (0); 1307 1308 hdac_attach_fail: 1309 hdac_irq_free(sc); 1310 if (sc->streams != NULL) 1311 for (i = 0; i < sc->num_ss; i++) 1312 hdac_dma_free(sc, &sc->streams[i].bdl); 1313 free(sc->streams, M_HDAC); 1314 hdac_dma_free(sc, &sc->rirb_dma); 1315 hdac_dma_free(sc, &sc->corb_dma); 1316 hdac_mem_free(sc); 1317 snd_mtxfree(sc->lock); 1318 1319 return (ENXIO); 1320 } 1321 1322 static int 1323 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1324 { 1325 struct hdac_softc *sc; 1326 device_t *devlist; 1327 device_t dev; 1328 int devcount, i, err, val; 1329 1330 dev = oidp->oid_arg1; 1331 sc = device_get_softc(dev); 1332 if (sc == NULL) 1333 return (EINVAL); 1334 val = 0; 1335 err = sysctl_handle_int(oidp, &val, 0, req); 1336 if (err != 0 || req->newptr == NULL || val == 0) 1337 return (err); 1338 1339 /* XXX: Temporary. For debugging. */ 1340 if (val == 100) { 1341 hdac_suspend(dev); 1342 return (0); 1343 } else if (val == 101) { 1344 hdac_resume(dev); 1345 return (0); 1346 } 1347 1348 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1349 return (err); 1350 hdac_lock(sc); 1351 for (i = 0; i < devcount; i++) 1352 HDAC_PINDUMP(devlist[i]); 1353 hdac_unlock(sc); 1354 free(devlist, M_TEMP); 1355 return (0); 1356 } 1357 1358 static int 1359 hdac_mdata_rate(uint16_t fmt) 1360 { 1361 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1362 int rate, bits; 1363 1364 if (fmt & (1 << 14)) 1365 rate = 44100; 1366 else 1367 rate = 48000; 1368 rate *= ((fmt >> 11) & 0x07) + 1; 1369 rate /= ((fmt >> 8) & 0x07) + 1; 1370 bits = mbits[(fmt >> 4) & 0x03]; 1371 bits *= (fmt & 0x0f) + 1; 1372 return (rate * bits); 1373 } 1374 1375 static int 1376 hdac_bdata_rate(uint16_t fmt, int output) 1377 { 1378 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1379 int rate, bits; 1380 1381 rate = 48000; 1382 rate *= ((fmt >> 11) & 0x07) + 1; 1383 bits = bbits[(fmt >> 4) & 0x03]; 1384 bits *= (fmt & 0x0f) + 1; 1385 if (!output) 1386 bits = ((bits + 7) & ~0x07) + 10; 1387 return (rate * bits); 1388 } 1389 1390 static void 1391 hdac_poll_reinit(struct hdac_softc *sc) 1392 { 1393 int i, pollticks, min = 1000000; 1394 struct hdac_stream *s; 1395 1396 if (sc->polling == 0) 1397 return; 1398 if (sc->unsol_registered > 0) 1399 min = hz / 2; 1400 for (i = 0; i < sc->num_ss; i++) { 1401 s = &sc->streams[i]; 1402 if (s->running == 0) 1403 continue; 1404 pollticks = ((uint64_t)hz * s->blksz) / 1405 (hdac_mdata_rate(s->format) / 8); 1406 pollticks >>= 1; 1407 if (pollticks > hz) 1408 pollticks = hz; 1409 if (pollticks < 1) 1410 pollticks = 1; 1411 if (min > pollticks) 1412 min = pollticks; 1413 } 1414 sc->poll_ival = min; 1415 if (min == 1000000) 1416 callout_stop(&sc->poll_callout); 1417 else 1418 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1419 } 1420 1421 static int 1422 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1423 { 1424 struct hdac_softc *sc; 1425 device_t dev; 1426 uint32_t ctl; 1427 int err, val; 1428 1429 dev = oidp->oid_arg1; 1430 sc = device_get_softc(dev); 1431 if (sc == NULL) 1432 return (EINVAL); 1433 hdac_lock(sc); 1434 val = sc->polling; 1435 hdac_unlock(sc); 1436 err = sysctl_handle_int(oidp, &val, 0, req); 1437 1438 if (err != 0 || req->newptr == NULL) 1439 return (err); 1440 if (val < 0 || val > 1) 1441 return (EINVAL); 1442 1443 hdac_lock(sc); 1444 if (val != sc->polling) { 1445 if (val == 0) { 1446 callout_stop(&sc->poll_callout); 1447 hdac_unlock(sc); 1448 callout_drain(&sc->poll_callout); 1449 hdac_lock(sc); 1450 sc->polling = 0; 1451 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1452 ctl |= HDAC_INTCTL_GIE; 1453 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1454 } else { 1455 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1456 ctl &= ~HDAC_INTCTL_GIE; 1457 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1458 sc->polling = 1; 1459 hdac_poll_reinit(sc); 1460 } 1461 } 1462 hdac_unlock(sc); 1463 1464 return (err); 1465 } 1466 1467 static void 1468 hdac_attach2(void *arg) 1469 { 1470 struct hdac_softc *sc; 1471 device_t child; 1472 uint32_t vendorid, revisionid; 1473 int i; 1474 uint16_t statests; 1475 1476 sc = (struct hdac_softc *)arg; 1477 1478 hdac_lock(sc); 1479 1480 /* Remove ourselves from the config hooks */ 1481 if (sc->intrhook.ich_func != NULL) { 1482 config_intrhook_disestablish(&sc->intrhook); 1483 sc->intrhook.ich_func = NULL; 1484 } 1485 1486 HDA_BOOTHVERBOSE( 1487 device_printf(sc->dev, "Starting CORB Engine...\n"); 1488 ); 1489 hdac_corb_start(sc); 1490 HDA_BOOTHVERBOSE( 1491 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1492 ); 1493 hdac_rirb_start(sc); 1494 HDA_BOOTHVERBOSE( 1495 device_printf(sc->dev, 1496 "Enabling controller interrupt...\n"); 1497 ); 1498 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1499 HDAC_GCTL_UNSOL); 1500 if (sc->polling == 0) { 1501 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1502 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1503 } 1504 DELAY(1000); 1505 1506 HDA_BOOTHVERBOSE( 1507 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1508 ); 1509 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1510 hdac_unlock(sc); 1511 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1512 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1513 HDA_BOOTHVERBOSE( 1514 device_printf(sc->dev, 1515 "Found CODEC at address %d\n", i); 1516 ); 1517 hdac_lock(sc); 1518 vendorid = hdac_send_command(sc, i, 1519 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1520 revisionid = hdac_send_command(sc, i, 1521 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1522 hdac_unlock(sc); 1523 if (vendorid == HDA_INVALID && 1524 revisionid == HDA_INVALID) { 1525 device_printf(sc->dev, 1526 "CODEC at address %d not responding!\n", i); 1527 continue; 1528 } 1529 sc->codecs[i].vendor_id = 1530 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1531 sc->codecs[i].device_id = 1532 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1533 sc->codecs[i].revision_id = 1534 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1535 sc->codecs[i].stepping_id = 1536 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1537 child = device_add_child(sc->dev, "hdacc", -1); 1538 if (child == NULL) { 1539 device_printf(sc->dev, 1540 "Failed to add CODEC device\n"); 1541 continue; 1542 } 1543 device_set_ivars(child, (void *)(intptr_t)i); 1544 sc->codecs[i].dev = child; 1545 } 1546 } 1547 bus_generic_attach(sc->dev); 1548 1549 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1550 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1551 "pindump", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc->dev, 1552 sizeof(sc->dev), sysctl_hdac_pindump, "I", "Dump pin states/data"); 1553 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1554 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1555 "polling", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc->dev, 1556 sizeof(sc->dev), sysctl_hdac_polling, "I", "Enable polling mode"); 1557 } 1558 1559 /**************************************************************************** 1560 * int hdac_suspend(device_t) 1561 * 1562 * Suspend and power down HDA bus and codecs. 1563 ****************************************************************************/ 1564 static int 1565 hdac_suspend(device_t dev) 1566 { 1567 struct hdac_softc *sc = device_get_softc(dev); 1568 1569 HDA_BOOTHVERBOSE( 1570 device_printf(dev, "Suspend...\n"); 1571 ); 1572 bus_generic_suspend(dev); 1573 1574 hdac_lock(sc); 1575 HDA_BOOTHVERBOSE( 1576 device_printf(dev, "Reset controller...\n"); 1577 ); 1578 callout_stop(&sc->poll_callout); 1579 hdac_reset(sc, 0); 1580 hdac_unlock(sc); 1581 callout_drain(&sc->poll_callout); 1582 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1583 HDA_BOOTHVERBOSE( 1584 device_printf(dev, "Suspend done\n"); 1585 ); 1586 return (0); 1587 } 1588 1589 /**************************************************************************** 1590 * int hdac_resume(device_t) 1591 * 1592 * Powerup and restore HDA bus and codecs state. 1593 ****************************************************************************/ 1594 static int 1595 hdac_resume(device_t dev) 1596 { 1597 struct hdac_softc *sc = device_get_softc(dev); 1598 int error; 1599 1600 HDA_BOOTHVERBOSE( 1601 device_printf(dev, "Resume...\n"); 1602 ); 1603 hdac_lock(sc); 1604 1605 /* Quiesce everything */ 1606 HDA_BOOTHVERBOSE( 1607 device_printf(dev, "Reset controller...\n"); 1608 ); 1609 hdac_reset(sc, 1); 1610 1611 /* Initialize the CORB and RIRB */ 1612 hdac_corb_init(sc); 1613 hdac_rirb_init(sc); 1614 1615 HDA_BOOTHVERBOSE( 1616 device_printf(dev, "Starting CORB Engine...\n"); 1617 ); 1618 hdac_corb_start(sc); 1619 HDA_BOOTHVERBOSE( 1620 device_printf(dev, "Starting RIRB Engine...\n"); 1621 ); 1622 hdac_rirb_start(sc); 1623 HDA_BOOTHVERBOSE( 1624 device_printf(dev, "Enabling controller interrupt...\n"); 1625 ); 1626 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1627 HDAC_GCTL_UNSOL); 1628 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1629 DELAY(1000); 1630 hdac_poll_reinit(sc); 1631 hdac_unlock(sc); 1632 1633 error = bus_generic_resume(dev); 1634 HDA_BOOTHVERBOSE( 1635 device_printf(dev, "Resume done\n"); 1636 ); 1637 return (error); 1638 } 1639 1640 /**************************************************************************** 1641 * int hdac_detach(device_t) 1642 * 1643 * Detach and free up resources utilized by the hdac device. 1644 ****************************************************************************/ 1645 static int 1646 hdac_detach(device_t dev) 1647 { 1648 struct hdac_softc *sc = device_get_softc(dev); 1649 device_t *devlist; 1650 int cad, i, devcount, error; 1651 1652 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1653 return (error); 1654 for (i = 0; i < devcount; i++) { 1655 cad = (intptr_t)device_get_ivars(devlist[i]); 1656 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1657 free(devlist, M_TEMP); 1658 return (error); 1659 } 1660 sc->codecs[cad].dev = NULL; 1661 } 1662 free(devlist, M_TEMP); 1663 1664 hdac_lock(sc); 1665 hdac_reset(sc, 0); 1666 hdac_unlock(sc); 1667 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1668 hdac_irq_free(sc); 1669 1670 for (i = 0; i < sc->num_ss; i++) 1671 hdac_dma_free(sc, &sc->streams[i].bdl); 1672 free(sc->streams, M_HDAC); 1673 hdac_dma_free(sc, &sc->pos_dma); 1674 hdac_dma_free(sc, &sc->rirb_dma); 1675 hdac_dma_free(sc, &sc->corb_dma); 1676 if (sc->chan_dmat != NULL) { 1677 bus_dma_tag_destroy(sc->chan_dmat); 1678 sc->chan_dmat = NULL; 1679 } 1680 hdac_mem_free(sc); 1681 snd_mtxfree(sc->lock); 1682 return (0); 1683 } 1684 1685 static bus_dma_tag_t 1686 hdac_get_dma_tag(device_t dev, device_t child) 1687 { 1688 struct hdac_softc *sc = device_get_softc(dev); 1689 1690 return (sc->chan_dmat); 1691 } 1692 1693 static int 1694 hdac_print_child(device_t dev, device_t child) 1695 { 1696 int retval; 1697 1698 retval = bus_print_child_header(dev, child); 1699 retval += printf(" at cad %d", (int)(intptr_t)device_get_ivars(child)); 1700 retval += bus_print_child_footer(dev, child); 1701 1702 return (retval); 1703 } 1704 1705 static int 1706 hdac_child_location_str(device_t dev, device_t child, char *buf, size_t buflen) 1707 { 1708 1709 snprintf(buf, buflen, "cad=%d", (int)(intptr_t)device_get_ivars(child)); 1710 return (0); 1711 } 1712 1713 static int 1714 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1715 size_t buflen) 1716 { 1717 struct hdac_softc *sc = device_get_softc(dev); 1718 nid_t cad = (uintptr_t)device_get_ivars(child); 1719 1720 snprintf(buf, buflen, 1721 "vendor=0x%04x device=0x%04x revision=0x%02x stepping=0x%02x", 1722 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1723 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1724 return (0); 1725 } 1726 1727 static int 1728 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1729 { 1730 struct hdac_softc *sc = device_get_softc(dev); 1731 nid_t cad = (uintptr_t)device_get_ivars(child); 1732 1733 switch (which) { 1734 case HDA_IVAR_CODEC_ID: 1735 *result = cad; 1736 break; 1737 case HDA_IVAR_VENDOR_ID: 1738 *result = sc->codecs[cad].vendor_id; 1739 break; 1740 case HDA_IVAR_DEVICE_ID: 1741 *result = sc->codecs[cad].device_id; 1742 break; 1743 case HDA_IVAR_REVISION_ID: 1744 *result = sc->codecs[cad].revision_id; 1745 break; 1746 case HDA_IVAR_STEPPING_ID: 1747 *result = sc->codecs[cad].stepping_id; 1748 break; 1749 case HDA_IVAR_SUBVENDOR_ID: 1750 *result = pci_get_subvendor(dev); 1751 break; 1752 case HDA_IVAR_SUBDEVICE_ID: 1753 *result = pci_get_subdevice(dev); 1754 break; 1755 case HDA_IVAR_DMA_NOCACHE: 1756 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1757 break; 1758 case HDA_IVAR_STRIPES_MASK: 1759 *result = (1 << (1 << sc->num_sdo)) - 1; 1760 break; 1761 default: 1762 return (ENOENT); 1763 } 1764 return (0); 1765 } 1766 1767 static struct mtx * 1768 hdac_get_mtx(device_t dev, device_t child) 1769 { 1770 struct hdac_softc *sc = device_get_softc(dev); 1771 1772 return (sc->lock); 1773 } 1774 1775 static uint32_t 1776 hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1777 { 1778 1779 return (hdac_send_command(device_get_softc(dev), 1780 (intptr_t)device_get_ivars(child), verb)); 1781 } 1782 1783 static int 1784 hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1785 { 1786 int i, ss; 1787 1788 ss = -1; 1789 /* Allocate ISS/OSS first. */ 1790 if (dir == 0) { 1791 for (i = 0; i < sc->num_iss; i++) { 1792 if (sc->streams[i].stream == stream) { 1793 ss = i; 1794 break; 1795 } 1796 } 1797 } else { 1798 for (i = 0; i < sc->num_oss; i++) { 1799 if (sc->streams[i + sc->num_iss].stream == stream) { 1800 ss = i + sc->num_iss; 1801 break; 1802 } 1803 } 1804 } 1805 /* Fallback to BSS. */ 1806 if (ss == -1) { 1807 for (i = 0; i < sc->num_bss; i++) { 1808 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1809 == stream) { 1810 ss = i + sc->num_iss + sc->num_oss; 1811 break; 1812 } 1813 } 1814 } 1815 return (ss); 1816 } 1817 1818 static int 1819 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1820 uint32_t **dmapos) 1821 { 1822 struct hdac_softc *sc = device_get_softc(dev); 1823 nid_t cad = (uintptr_t)device_get_ivars(child); 1824 int stream, ss, bw, maxbw, prevbw; 1825 1826 /* Look for empty stream. */ 1827 ss = hdac_find_stream(sc, dir, 0); 1828 1829 /* Return if found nothing. */ 1830 if (ss < 0) 1831 return (0); 1832 1833 /* Check bus bandwidth. */ 1834 bw = hdac_bdata_rate(format, dir); 1835 if (dir == 1) { 1836 bw *= 1 << (sc->num_sdo - stripe); 1837 prevbw = sc->sdo_bw_used; 1838 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1839 } else { 1840 prevbw = sc->codecs[cad].sdi_bw_used; 1841 maxbw = 48000 * 464; 1842 } 1843 HDA_BOOTHVERBOSE( 1844 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1845 (bw + prevbw) / 1000, maxbw / 1000, 1846 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1847 ); 1848 if (bw + prevbw > maxbw) 1849 return (0); 1850 if (dir == 1) 1851 sc->sdo_bw_used += bw; 1852 else 1853 sc->codecs[cad].sdi_bw_used += bw; 1854 1855 /* Allocate stream number */ 1856 if (ss >= sc->num_iss + sc->num_oss) 1857 stream = 15 - (ss - sc->num_iss - sc->num_oss); 1858 else if (ss >= sc->num_iss) 1859 stream = ss - sc->num_iss + 1; 1860 else 1861 stream = ss + 1; 1862 1863 sc->streams[ss].dev = child; 1864 sc->streams[ss].dir = dir; 1865 sc->streams[ss].stream = stream; 1866 sc->streams[ss].bw = bw; 1867 sc->streams[ss].format = format; 1868 sc->streams[ss].stripe = stripe; 1869 if (dmapos != NULL) { 1870 if (sc->pos_dma.dma_vaddr != NULL) 1871 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1872 else 1873 *dmapos = NULL; 1874 } 1875 return (stream); 1876 } 1877 1878 static void 1879 hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1880 { 1881 struct hdac_softc *sc = device_get_softc(dev); 1882 nid_t cad = (uintptr_t)device_get_ivars(child); 1883 int ss; 1884 1885 ss = hdac_find_stream(sc, dir, stream); 1886 KASSERT(ss >= 0, 1887 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1888 if (dir == 1) 1889 sc->sdo_bw_used -= sc->streams[ss].bw; 1890 else 1891 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1892 sc->streams[ss].stream = 0; 1893 sc->streams[ss].dev = NULL; 1894 } 1895 1896 static int 1897 hdac_stream_start(device_t dev, device_t child, int dir, int stream, 1898 bus_addr_t buf, int blksz, int blkcnt) 1899 { 1900 struct hdac_softc *sc = device_get_softc(dev); 1901 struct hdac_bdle *bdle; 1902 uint64_t addr; 1903 int i, ss, off; 1904 uint32_t ctl; 1905 1906 ss = hdac_find_stream(sc, dir, stream); 1907 KASSERT(ss >= 0, 1908 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1909 1910 addr = (uint64_t)buf; 1911 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1912 for (i = 0; i < blkcnt; i++, bdle++) { 1913 bdle->addrl = htole32((uint32_t)addr); 1914 bdle->addrh = htole32((uint32_t)(addr >> 32)); 1915 bdle->len = htole32(blksz); 1916 bdle->ioc = htole32(1); 1917 addr += blksz; 1918 } 1919 1920 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag, 1921 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_PREWRITE); 1922 1923 off = ss << 5; 1924 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1925 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1926 addr = sc->streams[ss].bdl.dma_paddr; 1927 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1928 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1929 1930 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1931 if (dir) 1932 ctl |= HDAC_SDCTL2_DIR; 1933 else 1934 ctl &= ~HDAC_SDCTL2_DIR; 1935 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1936 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1937 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1938 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1939 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1940 1941 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1942 1943 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1944 ctl |= 1 << ss; 1945 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1946 1947 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 1948 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 1949 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1950 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1951 HDAC_SDCTL_RUN; 1952 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1953 1954 sc->streams[ss].blksz = blksz; 1955 sc->streams[ss].running = 1; 1956 hdac_poll_reinit(sc); 1957 return (0); 1958 } 1959 1960 static void 1961 hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1962 { 1963 struct hdac_softc *sc = device_get_softc(dev); 1964 int ss, off; 1965 uint32_t ctl; 1966 1967 ss = hdac_find_stream(sc, dir, stream); 1968 KASSERT(ss >= 0, 1969 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1970 1971 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag, 1972 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_POSTWRITE); 1973 1974 off = ss << 5; 1975 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1976 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1977 HDAC_SDCTL_RUN); 1978 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1979 1980 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1981 ctl &= ~(1 << ss); 1982 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1983 1984 sc->streams[ss].running = 0; 1985 hdac_poll_reinit(sc); 1986 } 1987 1988 static void 1989 hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 1990 { 1991 struct hdac_softc *sc = device_get_softc(dev); 1992 int timeout = 1000; 1993 int to = timeout; 1994 int ss, off; 1995 uint32_t ctl; 1996 1997 ss = hdac_find_stream(sc, dir, stream); 1998 KASSERT(ss >= 0, 1999 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2000 2001 off = ss << 5; 2002 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2003 ctl |= HDAC_SDCTL_SRST; 2004 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2005 do { 2006 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2007 if (ctl & HDAC_SDCTL_SRST) 2008 break; 2009 DELAY(10); 2010 } while (--to); 2011 if (!(ctl & HDAC_SDCTL_SRST)) 2012 device_printf(dev, "Reset setting timeout\n"); 2013 ctl &= ~HDAC_SDCTL_SRST; 2014 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2015 to = timeout; 2016 do { 2017 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2018 if (!(ctl & HDAC_SDCTL_SRST)) 2019 break; 2020 DELAY(10); 2021 } while (--to); 2022 if (ctl & HDAC_SDCTL_SRST) 2023 device_printf(dev, "Reset timeout!\n"); 2024 } 2025 2026 static uint32_t 2027 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2028 { 2029 struct hdac_softc *sc = device_get_softc(dev); 2030 int ss, off; 2031 2032 ss = hdac_find_stream(sc, dir, stream); 2033 KASSERT(ss >= 0, 2034 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2035 2036 off = ss << 5; 2037 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2038 } 2039 2040 static int 2041 hdac_unsol_alloc(device_t dev, device_t child, int tag) 2042 { 2043 struct hdac_softc *sc = device_get_softc(dev); 2044 2045 sc->unsol_registered++; 2046 hdac_poll_reinit(sc); 2047 return (tag); 2048 } 2049 2050 static void 2051 hdac_unsol_free(device_t dev, device_t child, int tag) 2052 { 2053 struct hdac_softc *sc = device_get_softc(dev); 2054 2055 sc->unsol_registered--; 2056 hdac_poll_reinit(sc); 2057 } 2058 2059 static device_method_t hdac_methods[] = { 2060 /* device interface */ 2061 DEVMETHOD(device_probe, hdac_probe), 2062 DEVMETHOD(device_attach, hdac_attach), 2063 DEVMETHOD(device_detach, hdac_detach), 2064 DEVMETHOD(device_suspend, hdac_suspend), 2065 DEVMETHOD(device_resume, hdac_resume), 2066 /* Bus interface */ 2067 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2068 DEVMETHOD(bus_print_child, hdac_print_child), 2069 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2070 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2071 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2072 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2073 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2074 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2075 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2076 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2077 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2078 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2079 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2080 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2081 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2082 DEVMETHOD_END 2083 }; 2084 2085 static driver_t hdac_driver = { 2086 "hdac", 2087 hdac_methods, 2088 sizeof(struct hdac_softc), 2089 }; 2090 2091 static devclass_t hdac_devclass; 2092 2093 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL); 2094