1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70 #include <sys/ctype.h> 71 72 #include <dev/sound/pcm/sound.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 76 #include <dev/sound/pci/hda/hdac_private.h> 77 #include <dev/sound/pci/hda/hdac_reg.h> 78 #include <dev/sound/pci/hda/hda_reg.h> 79 #include <dev/sound/pci/hda/hdac.h> 80 81 #include "mixer_if.h" 82 83 #define HDA_DRV_TEST_REV "20061210_0037" 84 #define HDA_WIDGET_PARSER_REV 1 85 86 SND_DECLARE_FILE("$FreeBSD$"); 87 88 #undef HDA_DEBUG_ENABLED 89 #define HDA_DEBUG_ENABLED 1 90 91 #ifdef HDA_DEBUG_ENABLED 92 #define HDA_DEBUG(stmt) do { \ 93 stmt \ 94 } while(0) 95 #else 96 #define HDA_DEBUG(stmt) 97 #endif 98 99 #define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103 } while(0) 104 105 #if 1 106 #undef HDAC_INTR_EXTRA 107 #define HDAC_INTR_EXTRA 1 108 #endif 109 110 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 111 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113 #define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122 #define HDA_MATCH_ALL 0xffffffff 123 #define HDAC_INVALID 0xffffffff 124 125 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128 /* Controller models */ 129 130 /* Intel */ 131 #define INTEL_VENDORID 0x8086 132 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138 /* Nvidia */ 139 #define NVIDIA_VENDORID 0x10de 140 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142 #define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143 #define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144 #define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145 #define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148 /* ATI */ 149 #define ATI_VENDORID 0x1002 150 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154 /* VIA */ 155 #define VIA_VENDORID 0x1106 156 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159 /* SiS */ 160 #define SIS_VENDORID 0x1039 161 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164 /* OEM/subvendors */ 165 166 /* Intel */ 167 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 168 169 /* HP/Compaq */ 170 #define HP_VENDORID 0x103c 171 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 172 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 173 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 174 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 175 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 176 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 177 #define HP_NX6325_SUBVENDORX 0x103c30b0 178 179 /* Dell */ 180 #define DELL_VENDORID 0x1028 181 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 182 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 183 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 184 185 /* Clevo */ 186 #define CLEVO_VENDORID 0x1558 187 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 188 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 189 190 /* Acer */ 191 #define ACER_VENDORID 0x1025 192 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 193 194 /* Asus */ 195 #define ASUS_VENDORID 0x1043 196 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 197 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 198 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 199 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 200 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 201 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 202 203 /* IBM / Lenovo */ 204 #define IBM_VENDORID 0x1014 205 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 206 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 207 208 /* Lenovo */ 209 #define LENOVO_VENDORID 0x17aa 210 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 211 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 212 213 /* Samsung */ 214 #define SAMSUNG_VENDORID 0x144d 215 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 216 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 217 218 /* Medion ? */ 219 #define MEDION_VENDORID 0x161f 220 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 221 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 222 223 /* 224 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 225 * instead of their own, which is beyond my comprehension 226 * (see HDA_CODEC_STAC9221 below). 227 */ 228 #define APPLE_INTEL_MAC 0x76808384 229 230 /* LG Electronics */ 231 #define LG_VENDORID 0x1854 232 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 233 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 234 235 /* Fujitsu Siemens */ 236 #define FS_VENDORID 0x1734 237 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 238 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 239 240 /* Misc constants.. */ 241 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 242 #define HDA_AMP_MUTE_NONE (0) 243 #define HDA_AMP_MUTE_LEFT (1 << 0) 244 #define HDA_AMP_MUTE_RIGHT (1 << 1) 245 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 246 247 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 248 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 249 250 #define HDA_DAC_PATH (1 << 0) 251 #define HDA_ADC_PATH (1 << 1) 252 #define HDA_ADC_RECSEL (1 << 2) 253 254 #define HDA_CTL_OUT (1 << 0) 255 #define HDA_CTL_IN (1 << 1) 256 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 257 258 #define HDA_GPIO_MAX 15 259 /* 0 - 14 = GPIO */ 260 #define HDA_QUIRK_GPIO0 (1 << 0) 261 #define HDA_QUIRK_GPIO1 (1 << 1) 262 #define HDA_QUIRK_GPIO2 (1 << 2) 263 #define HDA_QUIRK_GPIOFLUSH (1 << 15) 264 #define HDA_QUIRK_SOFTPCMVOL (1 << 16) 265 #define HDA_QUIRK_FIXEDRATE (1 << 17) 266 #define HDA_QUIRK_FORCESTEREO (1 << 18) 267 #define HDA_QUIRK_EAPDINV (1 << 19) 268 #define HDA_QUIRK_VREF (1 << 20) 269 270 static const struct { 271 char *key; 272 uint32_t value; 273 } hdac_quirks_tab[] = { 274 { "gpio0", HDA_QUIRK_GPIO0 }, 275 { "gpio1", HDA_QUIRK_GPIO1 }, 276 { "gpio2", HDA_QUIRK_GPIO2 }, 277 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 278 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 279 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 280 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 281 { "eapdinv", HDA_QUIRK_EAPDINV }, 282 { "vref", HDA_QUIRK_VREF }, 283 }; 284 #define HDAC_QUIRKS_TAB_LEN \ 285 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 286 287 #define HDA_BDL_MIN 2 288 #define HDA_BDL_MAX 256 289 #define HDA_BDL_DEFAULT HDA_BDL_MIN 290 291 #define HDA_BUFSZ_MIN 4096 292 #define HDA_BUFSZ_MAX 65536 293 #define HDA_BUFSZ_DEFAULT 16384 294 295 #define HDA_PARSE_MAXDEPTH 10 296 297 #define HDAC_UNSOLTAG_EVENT_HP 0x00 298 299 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 300 301 enum { 302 HDA_PARSE_MIXER, 303 HDA_PARSE_DIRECT 304 }; 305 306 /* Default */ 307 static uint32_t hdac_fmt[] = { 308 AFMT_STEREO | AFMT_S16_LE, 309 0 310 }; 311 312 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 313 314 static const struct { 315 uint32_t model; 316 char *desc; 317 } hdac_devices[] = { 318 { HDA_INTEL_82801F, "Intel 82801F" }, 319 { HDA_INTEL_82801G, "Intel 82801G" }, 320 { HDA_INTEL_82801H, "Intel 82801H" }, 321 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 322 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 323 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 324 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 325 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 326 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 327 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 328 { HDA_ATI_SB450, "ATI SB450" }, 329 { HDA_ATI_SB600, "ATI SB600" }, 330 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 331 { HDA_SIS_966, "SiS 966" }, 332 /* Unknown */ 333 { HDA_INTEL_ALL, "Intel (Unknown)" }, 334 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 335 { HDA_ATI_ALL, "ATI (Unknown)" }, 336 { HDA_VIA_ALL, "VIA (Unknown)" }, 337 { HDA_SIS_ALL, "SiS (Unknown)" }, 338 }; 339 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 340 341 static const struct { 342 uint32_t rate; 343 int valid; 344 uint16_t base; 345 uint16_t mul; 346 uint16_t div; 347 } hda_rate_tab[] = { 348 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 349 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 350 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 351 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 352 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 353 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 354 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 355 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 356 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 357 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 358 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 359 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 360 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 361 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 362 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 363 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 364 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 365 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 366 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 367 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 368 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 369 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 370 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 371 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 372 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 373 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 374 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 375 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 376 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 377 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 378 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 379 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 380 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 381 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 382 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 383 }; 384 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 385 386 /* All codecs you can eat... */ 387 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 388 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 389 390 /* Realtek */ 391 #define REALTEK_VENDORID 0x10ec 392 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 393 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 394 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 395 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 396 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 397 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 398 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 399 400 /* Analog Device */ 401 #define ANALOGDEVICE_VENDORID 0x11d4 402 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 403 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 404 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 405 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 406 407 /* CMedia */ 408 #define CMEDIA_VENDORID 0x434d 409 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 410 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 411 412 /* Sigmatel */ 413 #define SIGMATEL_VENDORID 0x8384 414 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 415 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 416 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 417 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 418 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 419 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 420 421 /* 422 * Conexant 423 * 424 * Ok, the truth is, I don't have any idea at all whether 425 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 426 * place that tell me it is "Venice" is from its Windows driver INF. 427 * 428 * Venice - CX????? 429 * Waikiki - CX20551-22 430 */ 431 #define CONEXANT_VENDORID 0x14f1 432 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 433 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 434 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 435 436 437 /* Codecs */ 438 static const struct { 439 uint32_t id; 440 char *name; 441 } hdac_codecs[] = { 442 { HDA_CODEC_ALC260, "Realtek ALC260" }, 443 { HDA_CODEC_ALC861, "Realtek ALC861" }, 444 { HDA_CODEC_ALC880, "Realtek ALC880" }, 445 { HDA_CODEC_ALC882, "Realtek ALC882" }, 446 { HDA_CODEC_ALC883, "Realtek ALC883" }, 447 { HDA_CODEC_ALC888, "Realtek ALC888" }, 448 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 449 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 450 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 451 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 452 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 453 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 454 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 455 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 456 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 457 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 458 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 459 /* Unknown codec */ 460 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 461 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 462 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 463 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 464 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 465 }; 466 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 467 468 enum { 469 HDAC_HP_SWITCH_CTL, 470 HDAC_HP_SWITCH_CTRL 471 }; 472 473 static const struct { 474 uint32_t model; 475 uint32_t id; 476 int type; 477 int inverted; 478 nid_t hpnid; 479 nid_t spkrnid[8]; 480 nid_t eapdnid; 481 } hdac_hp_switch[] = { 482 /* Specific OEM models */ 483 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 484 17, { 16, -1 }, 16 }, 485 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 486 6, { 5, -1 }, 5 }, 487 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 488 6, { 5, -1 }, 5 }, 489 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 490 6, { 5, -1 }, 5 }, 491 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 492 13, { 14, -1 }, -1 }, 493 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 494 13, { 14, -1 }, -1 }, 495 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 496 10, { 13, -1 }, -1 }, 497 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 498 26, { 27, -1 }, -1 }, 499 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 500 27, { 20, -1 }, -1 }, 501 /* 502 * All models that at least come from the same vendor with 503 * simmilar codec. 504 */ 505 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 506 17, { 16, -1 }, 16 }, 507 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 508 6, { 5, -1 }, 5 }, 509 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 510 13, { 14, -1 }, -1 }, 511 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 512 26, { 27, -1 }, -1 }, 513 }; 514 #define HDAC_HP_SWITCH_LEN \ 515 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 516 517 static const struct { 518 uint32_t model; 519 uint32_t id; 520 nid_t eapdnid; 521 int hp_switch; 522 } hdac_eapd_switch[] = { 523 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 524 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 525 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 526 }; 527 #define HDAC_EAPD_SWITCH_LEN \ 528 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 529 530 /**************************************************************************** 531 * Function prototypes 532 ****************************************************************************/ 533 static void hdac_intr_handler(void *); 534 static int hdac_reset(struct hdac_softc *); 535 static int hdac_get_capabilities(struct hdac_softc *); 536 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 537 static int hdac_dma_alloc(struct hdac_softc *, 538 struct hdac_dma *, bus_size_t); 539 static void hdac_dma_free(struct hdac_dma *); 540 static int hdac_mem_alloc(struct hdac_softc *); 541 static void hdac_mem_free(struct hdac_softc *); 542 static int hdac_irq_alloc(struct hdac_softc *); 543 static void hdac_irq_free(struct hdac_softc *); 544 static void hdac_corb_init(struct hdac_softc *); 545 static void hdac_rirb_init(struct hdac_softc *); 546 static void hdac_corb_start(struct hdac_softc *); 547 static void hdac_rirb_start(struct hdac_softc *); 548 static void hdac_scan_codecs(struct hdac_softc *); 549 static int hdac_probe_codec(struct hdac_codec *); 550 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 551 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 552 553 static void hdac_attach2(void *); 554 555 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 556 uint32_t, int); 557 static void hdac_command_send_internal(struct hdac_softc *, 558 struct hdac_command_list *, int); 559 560 static int hdac_probe(device_t); 561 static int hdac_attach(device_t); 562 static int hdac_detach(device_t); 563 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 564 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 565 uint32_t, int, int); 566 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 567 nid_t, int, int); 568 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 569 nid_t, nid_t, int, int, int, int, int, int); 570 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 571 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 572 573 static int hdac_rirb_flush(struct hdac_softc *sc); 574 static int hdac_unsolq_flush(struct hdac_softc *sc); 575 576 #define hdac_command(a1, a2, a3) \ 577 hdac_command_sendone_internal(a1, a2, a3) 578 579 #define hdac_codec_id(d) \ 580 ((uint32_t)((d == NULL) ? 0x00000000 : \ 581 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 582 ((uint32_t)(d)->device_id & 0x0000ffff)))) 583 584 static char * 585 hdac_codec_name(struct hdac_devinfo *devinfo) 586 { 587 uint32_t id; 588 int i; 589 590 id = hdac_codec_id(devinfo); 591 592 for (i = 0; i < HDAC_CODECS_LEN; i++) { 593 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 594 return (hdac_codecs[i].name); 595 } 596 597 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 598 } 599 600 static char * 601 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 602 { 603 static char *ossname[] = SOUND_DEVICE_NAMES; 604 static char *unknown = "???"; 605 int i; 606 607 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 608 if (devmask & (1 << i)) 609 return (ossname[i]); 610 } 611 return (unknown); 612 } 613 614 static void 615 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 616 { 617 static char *ossname[] = SOUND_DEVICE_NAMES; 618 int i, first = 1; 619 620 bzero(buf, len); 621 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 622 if (mask & (1 << i)) { 623 if (first == 0) 624 strlcat(buf, ", ", len); 625 strlcat(buf, ossname[i], len); 626 first = 0; 627 } 628 } 629 } 630 631 static struct hdac_audio_ctl * 632 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 633 { 634 if (devinfo == NULL || 635 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 636 index == NULL || devinfo->function.audio.ctl == NULL || 637 devinfo->function.audio.ctlcnt < 1 || 638 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 639 return (NULL); 640 return (&devinfo->function.audio.ctl[(*index)++]); 641 } 642 643 static struct hdac_audio_ctl * 644 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 645 int index, int cnt) 646 { 647 struct hdac_audio_ctl *ctl, *retctl = NULL; 648 int i, at, atindex, found = 0; 649 650 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 651 return (NULL); 652 653 at = cnt; 654 if (at == 0) 655 at = 1; 656 else if (at < 0) 657 at = -1; 658 atindex = index; 659 if (atindex < 0) 660 atindex = -1; 661 662 i = 0; 663 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 664 if (ctl->enable == 0 || ctl->widget == NULL) 665 continue; 666 if (!(ctl->widget->nid == nid && (atindex == -1 || 667 ctl->index == atindex))) 668 continue; 669 found++; 670 if (found == cnt) 671 return (ctl); 672 retctl = ctl; 673 } 674 675 return ((at == -1) ? retctl : NULL); 676 } 677 678 static void 679 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 680 { 681 struct hdac_softc *sc; 682 struct hdac_widget *w; 683 struct hdac_audio_ctl *ctl; 684 uint32_t id, res; 685 int i = 0, j, forcemute; 686 nid_t cad; 687 688 if (devinfo == NULL || devinfo->codec == NULL || 689 devinfo->codec->sc == NULL) 690 return; 691 692 sc = devinfo->codec->sc; 693 cad = devinfo->codec->cad; 694 id = hdac_codec_id(devinfo); 695 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 696 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 697 sc->pci_subvendor) && 698 hdac_hp_switch[i].id == id) 699 break; 700 } 701 702 if (i >= HDAC_HP_SWITCH_LEN) 703 return; 704 705 forcemute = 0; 706 if (hdac_hp_switch[i].eapdnid != -1) { 707 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 708 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 709 forcemute = (w->param.eapdbtl & 710 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 711 } 712 713 res = hdac_command(sc, 714 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 715 HDA_BOOTVERBOSE( 716 device_printf(sc->dev, 717 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 718 hdac_hp_switch[i].hpnid, res); 719 ); 720 res >>= 31; 721 res ^= hdac_hp_switch[i].inverted; 722 723 switch (hdac_hp_switch[i].type) { 724 case HDAC_HP_SWITCH_CTL: 725 ctl = hdac_audio_ctl_amp_get(devinfo, 726 hdac_hp_switch[i].hpnid, 0, 1); 727 if (ctl != NULL) { 728 ctl->muted = (res != 0 && forcemute == 0) ? 729 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 730 hdac_audio_ctl_amp_set(ctl, 731 HDA_AMP_MUTE_DEFAULT, ctl->left, 732 ctl->right); 733 } 734 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 735 ctl = hdac_audio_ctl_amp_get(devinfo, 736 hdac_hp_switch[i].spkrnid[j], 0, 1); 737 if (ctl != NULL) { 738 ctl->muted = (res != 0 || forcemute == 1) ? 739 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 740 hdac_audio_ctl_amp_set(ctl, 741 HDA_AMP_MUTE_DEFAULT, ctl->left, 742 ctl->right); 743 } 744 } 745 break; 746 case HDAC_HP_SWITCH_CTRL: 747 if (res != 0) { 748 /* HP in */ 749 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 750 if (w != NULL && w->type == 751 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 752 if (forcemute == 0) 753 w->wclass.pin.ctrl |= 754 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 755 else 756 w->wclass.pin.ctrl &= 757 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 758 hdac_command(sc, 759 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 760 w->wclass.pin.ctrl), cad); 761 } 762 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 763 w = hdac_widget_get(devinfo, 764 hdac_hp_switch[i].spkrnid[j]); 765 if (w != NULL && w->type == 766 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 767 w->wclass.pin.ctrl &= 768 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 769 hdac_command(sc, 770 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 771 w->nid, 772 w->wclass.pin.ctrl), cad); 773 } 774 } 775 } else { 776 /* HP out */ 777 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 778 if (w != NULL && w->type == 779 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 780 w->wclass.pin.ctrl &= 781 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 782 hdac_command(sc, 783 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 784 w->wclass.pin.ctrl), cad); 785 } 786 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 787 w = hdac_widget_get(devinfo, 788 hdac_hp_switch[i].spkrnid[j]); 789 if (w != NULL && w->type == 790 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 791 if (forcemute == 0) 792 w->wclass.pin.ctrl |= 793 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 794 else 795 w->wclass.pin.ctrl &= 796 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 797 hdac_command(sc, 798 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 799 w->nid, 800 w->wclass.pin.ctrl), cad); 801 } 802 } 803 } 804 break; 805 default: 806 break; 807 } 808 } 809 810 static void 811 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 812 { 813 struct hdac_softc *sc; 814 struct hdac_devinfo *devinfo = NULL; 815 device_t *devlist = NULL; 816 int devcount, i; 817 818 if (codec == NULL || codec->sc == NULL) 819 return; 820 821 sc = codec->sc; 822 823 HDA_BOOTVERBOSE( 824 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 825 ); 826 827 device_get_children(sc->dev, &devlist, &devcount); 828 for (i = 0; devlist != NULL && i < devcount; i++) { 829 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 830 if (devinfo != NULL && devinfo->node_type == 831 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 832 devinfo->codec != NULL && 833 devinfo->codec->cad == codec->cad) { 834 break; 835 } else 836 devinfo = NULL; 837 } 838 if (devlist != NULL) 839 free(devlist, M_TEMP); 840 841 if (devinfo == NULL) 842 return; 843 844 switch (tag) { 845 case HDAC_UNSOLTAG_EVENT_HP: 846 hdac_hp_switch_handler(devinfo); 847 break; 848 default: 849 break; 850 } 851 } 852 853 static int 854 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 855 { 856 /* XXX to be removed */ 857 #ifdef HDAC_INTR_EXTRA 858 uint32_t res; 859 #endif 860 861 if (ch->blkcnt == 0) 862 return (0); 863 864 /* XXX to be removed */ 865 #ifdef HDAC_INTR_EXTRA 866 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 867 #endif 868 869 /* XXX to be removed */ 870 #ifdef HDAC_INTR_EXTRA 871 HDA_BOOTVERBOSE( 872 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 873 device_printf(sc->dev, 874 "PCMDIR_%s intr triggered beyond stream boundary:" 875 "%08x\n", 876 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 877 ); 878 #endif 879 880 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 881 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 882 883 /* XXX to be removed */ 884 #ifdef HDAC_INTR_EXTRA 885 if (res & HDAC_SDSTS_BCIS) { 886 #endif 887 return (1); 888 /* XXX to be removed */ 889 #ifdef HDAC_INTR_EXTRA 890 } 891 #endif 892 893 return (0); 894 } 895 896 /**************************************************************************** 897 * void hdac_intr_handler(void *) 898 * 899 * Interrupt handler. Processes interrupts received from the hdac. 900 ****************************************************************************/ 901 static void 902 hdac_intr_handler(void *context) 903 { 904 struct hdac_softc *sc; 905 uint32_t intsts; 906 uint8_t rirbsts; 907 struct hdac_rirb *rirb_base; 908 uint32_t trigger = 0; 909 910 sc = (struct hdac_softc *)context; 911 912 hdac_lock(sc); 913 if (sc->polling != 0) { 914 hdac_unlock(sc); 915 return; 916 } 917 /* Do we have anything to do? */ 918 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 919 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 920 hdac_unlock(sc); 921 return; 922 } 923 924 /* Was this a controller interrupt? */ 925 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 926 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 927 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 928 /* Get as many responses that we can */ 929 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 930 HDAC_WRITE_1(&sc->mem, 931 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 932 hdac_rirb_flush(sc); 933 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 934 } 935 /* XXX to be removed */ 936 /* Clear interrupt and exit */ 937 #ifdef HDAC_INTR_EXTRA 938 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 939 #endif 940 } 941 942 hdac_unsolq_flush(sc); 943 944 if (intsts & HDAC_INTSTS_SIS_MASK) { 945 if ((intsts & (1 << sc->num_iss)) && 946 hdac_stream_intr(sc, &sc->play) != 0) 947 trigger |= 1; 948 if ((intsts & (1 << 0)) && 949 hdac_stream_intr(sc, &sc->rec) != 0) 950 trigger |= 2; 951 /* XXX to be removed */ 952 #ifdef HDAC_INTR_EXTRA 953 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 954 HDAC_INTSTS_SIS_MASK); 955 #endif 956 } 957 958 hdac_unlock(sc); 959 960 if (trigger & 1) 961 chn_intr(sc->play.c); 962 if (trigger & 2) 963 chn_intr(sc->rec.c); 964 } 965 966 /**************************************************************************** 967 * int hdac_reset(hdac_softc *) 968 * 969 * Reset the hdac to a quiescent and known state. 970 ****************************************************************************/ 971 static int 972 hdac_reset(struct hdac_softc *sc) 973 { 974 uint32_t gctl; 975 int count, i; 976 977 /* 978 * Stop all Streams DMA engine 979 */ 980 for (i = 0; i < sc->num_iss; i++) 981 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 982 for (i = 0; i < sc->num_oss; i++) 983 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 984 for (i = 0; i < sc->num_bss; i++) 985 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 986 987 /* 988 * Stop Control DMA engines 989 */ 990 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 991 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 992 993 /* 994 * Reset the controller. The reset must remain asserted for 995 * a minimum of 100us. 996 */ 997 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 998 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 999 count = 10000; 1000 do { 1001 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1002 if (!(gctl & HDAC_GCTL_CRST)) 1003 break; 1004 DELAY(10); 1005 } while (--count); 1006 if (gctl & HDAC_GCTL_CRST) { 1007 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1008 return (ENXIO); 1009 } 1010 DELAY(100); 1011 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1012 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1013 count = 10000; 1014 do { 1015 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1016 if (gctl & HDAC_GCTL_CRST) 1017 break; 1018 DELAY(10); 1019 } while (--count); 1020 if (!(gctl & HDAC_GCTL_CRST)) { 1021 device_printf(sc->dev, "Device stuck in reset\n"); 1022 return (ENXIO); 1023 } 1024 1025 /* 1026 * Wait for codecs to finish their own reset sequence. The delay here 1027 * should be of 250us but for some reasons, on it's not enough on my 1028 * computer. Let's use twice as much as necessary to make sure that 1029 * it's reset properly. 1030 */ 1031 DELAY(1000); 1032 1033 return (0); 1034 } 1035 1036 1037 /**************************************************************************** 1038 * int hdac_get_capabilities(struct hdac_softc *); 1039 * 1040 * Retreive the general capabilities of the hdac; 1041 * Number of Input Streams 1042 * Number of Output Streams 1043 * Number of bidirectional Streams 1044 * 64bit ready 1045 * CORB and RIRB sizes 1046 ****************************************************************************/ 1047 static int 1048 hdac_get_capabilities(struct hdac_softc *sc) 1049 { 1050 uint16_t gcap; 1051 uint8_t corbsize, rirbsize; 1052 1053 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1054 sc->num_iss = HDAC_GCAP_ISS(gcap); 1055 sc->num_oss = HDAC_GCAP_OSS(gcap); 1056 sc->num_bss = HDAC_GCAP_BSS(gcap); 1057 1058 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1059 1060 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1061 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1062 HDAC_CORBSIZE_CORBSZCAP_256) 1063 sc->corb_size = 256; 1064 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1065 HDAC_CORBSIZE_CORBSZCAP_16) 1066 sc->corb_size = 16; 1067 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1068 HDAC_CORBSIZE_CORBSZCAP_2) 1069 sc->corb_size = 2; 1070 else { 1071 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1072 __func__, corbsize); 1073 return (ENXIO); 1074 } 1075 1076 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1077 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1078 HDAC_RIRBSIZE_RIRBSZCAP_256) 1079 sc->rirb_size = 256; 1080 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1081 HDAC_RIRBSIZE_RIRBSZCAP_16) 1082 sc->rirb_size = 16; 1083 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1084 HDAC_RIRBSIZE_RIRBSZCAP_2) 1085 sc->rirb_size = 2; 1086 else { 1087 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1088 __func__, rirbsize); 1089 return (ENXIO); 1090 } 1091 1092 return (0); 1093 } 1094 1095 1096 /**************************************************************************** 1097 * void hdac_dma_cb 1098 * 1099 * This function is called by bus_dmamap_load when the mapping has been 1100 * established. We just record the physical address of the mapping into 1101 * the struct hdac_dma passed in. 1102 ****************************************************************************/ 1103 static void 1104 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1105 { 1106 struct hdac_dma *dma; 1107 1108 if (error == 0) { 1109 dma = (struct hdac_dma *)callback_arg; 1110 dma->dma_paddr = segs[0].ds_addr; 1111 } 1112 } 1113 1114 static void 1115 hdac_dma_nocache(void *ptr) 1116 { 1117 #if defined(__i386__) || defined(__amd64__) 1118 pt_entry_t *pte; 1119 vm_offset_t va; 1120 1121 va = (vm_offset_t)ptr; 1122 pte = vtopte(va); 1123 if (pte) { 1124 *pte |= PG_N; 1125 invltlb(); 1126 } 1127 #endif 1128 } 1129 1130 /**************************************************************************** 1131 * int hdac_dma_alloc 1132 * 1133 * This function allocate and setup a dma region (struct hdac_dma). 1134 * It must be freed by a corresponding hdac_dma_free. 1135 ****************************************************************************/ 1136 static int 1137 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1138 { 1139 int result; 1140 int lowaddr; 1141 1142 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1143 BUS_SPACE_MAXADDR_32BIT; 1144 bzero(dma, sizeof(*dma)); 1145 1146 /* 1147 * Create a DMA tag 1148 */ 1149 result = bus_dma_tag_create(NULL, /* parent */ 1150 HDAC_DMA_ALIGNMENT, /* alignment */ 1151 0, /* boundary */ 1152 lowaddr, /* lowaddr */ 1153 BUS_SPACE_MAXADDR, /* highaddr */ 1154 NULL, /* filtfunc */ 1155 NULL, /* fistfuncarg */ 1156 size, /* maxsize */ 1157 1, /* nsegments */ 1158 size, /* maxsegsz */ 1159 0, /* flags */ 1160 NULL, /* lockfunc */ 1161 NULL, /* lockfuncarg */ 1162 &dma->dma_tag); /* dmat */ 1163 if (result != 0) { 1164 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1165 __func__, result); 1166 goto fail; 1167 } 1168 1169 /* 1170 * Allocate DMA memory 1171 */ 1172 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1173 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1174 if (result != 0) { 1175 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1176 __func__, result); 1177 goto fail; 1178 } 1179 1180 /* 1181 * Map the memory 1182 */ 1183 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1184 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1185 BUS_DMA_NOWAIT); 1186 if (result != 0 || dma->dma_paddr == 0) { 1187 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1188 __func__, result); 1189 goto fail; 1190 } 1191 bzero((void *)dma->dma_vaddr, size); 1192 hdac_dma_nocache(dma->dma_vaddr); 1193 1194 return (0); 1195 fail: 1196 if (dma->dma_map != NULL) 1197 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1198 if (dma->dma_tag != NULL) 1199 bus_dma_tag_destroy(dma->dma_tag); 1200 return (result); 1201 } 1202 1203 1204 /**************************************************************************** 1205 * void hdac_dma_free(struct hdac_dma *) 1206 * 1207 * Free a struct dhac_dma that has been previously allocated via the 1208 * hdac_dma_alloc function. 1209 ****************************************************************************/ 1210 static void 1211 hdac_dma_free(struct hdac_dma *dma) 1212 { 1213 if (dma->dma_tag != NULL) { 1214 /* Flush caches */ 1215 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1216 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1217 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1218 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1219 bus_dma_tag_destroy(dma->dma_tag); 1220 } 1221 } 1222 1223 /**************************************************************************** 1224 * int hdac_mem_alloc(struct hdac_softc *) 1225 * 1226 * Allocate all the bus resources necessary to speak with the physical 1227 * controller. 1228 ****************************************************************************/ 1229 static int 1230 hdac_mem_alloc(struct hdac_softc *sc) 1231 { 1232 struct hdac_mem *mem; 1233 1234 mem = &sc->mem; 1235 mem->mem_rid = PCIR_BAR(0); 1236 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1237 &mem->mem_rid, RF_ACTIVE); 1238 if (mem->mem_res == NULL) { 1239 device_printf(sc->dev, 1240 "%s: Unable to allocate memory resource\n", __func__); 1241 return (ENOMEM); 1242 } 1243 mem->mem_tag = rman_get_bustag(mem->mem_res); 1244 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1245 1246 return (0); 1247 } 1248 1249 /**************************************************************************** 1250 * void hdac_mem_free(struct hdac_softc *) 1251 * 1252 * Free up resources previously allocated by hdac_mem_alloc. 1253 ****************************************************************************/ 1254 static void 1255 hdac_mem_free(struct hdac_softc *sc) 1256 { 1257 struct hdac_mem *mem; 1258 1259 mem = &sc->mem; 1260 if (mem->mem_res != NULL) 1261 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1262 mem->mem_res); 1263 mem->mem_res = NULL; 1264 } 1265 1266 /**************************************************************************** 1267 * int hdac_irq_alloc(struct hdac_softc *) 1268 * 1269 * Allocate and setup the resources necessary for interrupt handling. 1270 ****************************************************************************/ 1271 static int 1272 hdac_irq_alloc(struct hdac_softc *sc) 1273 { 1274 struct hdac_irq *irq; 1275 int result; 1276 1277 irq = &sc->irq; 1278 irq->irq_rid = 0x0; 1279 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1280 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1281 if (irq->irq_res == NULL) { 1282 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1283 __func__); 1284 goto fail; 1285 } 1286 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1287 hdac_intr_handler, sc, &irq->irq_handle); 1288 if (result != 0) { 1289 device_printf(sc->dev, 1290 "%s: Unable to setup interrupt handler (%x)\n", 1291 __func__, result); 1292 goto fail; 1293 } 1294 1295 return (0); 1296 1297 fail: 1298 hdac_irq_free(sc); 1299 1300 return (ENXIO); 1301 } 1302 1303 /**************************************************************************** 1304 * void hdac_irq_free(struct hdac_softc *) 1305 * 1306 * Free up resources previously allocated by hdac_irq_alloc. 1307 ****************************************************************************/ 1308 static void 1309 hdac_irq_free(struct hdac_softc *sc) 1310 { 1311 struct hdac_irq *irq; 1312 1313 irq = &sc->irq; 1314 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1315 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1316 if (irq->irq_res != NULL) 1317 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1318 irq->irq_res); 1319 irq->irq_handle = NULL; 1320 irq->irq_res = NULL; 1321 } 1322 1323 /**************************************************************************** 1324 * void hdac_corb_init(struct hdac_softc *) 1325 * 1326 * Initialize the corb registers for operations but do not start it up yet. 1327 * The CORB engine must not be running when this function is called. 1328 ****************************************************************************/ 1329 static void 1330 hdac_corb_init(struct hdac_softc *sc) 1331 { 1332 uint8_t corbsize; 1333 uint64_t corbpaddr; 1334 1335 /* Setup the CORB size. */ 1336 switch (sc->corb_size) { 1337 case 256: 1338 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1339 break; 1340 case 16: 1341 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1342 break; 1343 case 2: 1344 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1345 break; 1346 default: 1347 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1348 } 1349 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1350 1351 /* Setup the CORB Address in the hdac */ 1352 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1353 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1354 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1355 1356 /* Set the WP and RP */ 1357 sc->corb_wp = 0; 1358 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1359 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1360 /* 1361 * The HDA specification indicates that the CORBRPRST bit will always 1362 * read as zero. Unfortunately, it seems that at least the 82801G 1363 * doesn't reset the bit to zero, which stalls the corb engine. 1364 * manually reset the bit to zero before continuing. 1365 */ 1366 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1367 1368 /* Enable CORB error reporting */ 1369 #if 0 1370 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1371 #endif 1372 } 1373 1374 /**************************************************************************** 1375 * void hdac_rirb_init(struct hdac_softc *) 1376 * 1377 * Initialize the rirb registers for operations but do not start it up yet. 1378 * The RIRB engine must not be running when this function is called. 1379 ****************************************************************************/ 1380 static void 1381 hdac_rirb_init(struct hdac_softc *sc) 1382 { 1383 uint8_t rirbsize; 1384 uint64_t rirbpaddr; 1385 1386 /* Setup the RIRB size. */ 1387 switch (sc->rirb_size) { 1388 case 256: 1389 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1390 break; 1391 case 16: 1392 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1393 break; 1394 case 2: 1395 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1396 break; 1397 default: 1398 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1399 } 1400 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1401 1402 /* Setup the RIRB Address in the hdac */ 1403 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1404 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1405 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1406 1407 /* Setup the WP and RP */ 1408 sc->rirb_rp = 0; 1409 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1410 1411 if (sc->polling == 0) { 1412 /* Setup the interrupt threshold */ 1413 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1414 1415 /* Enable Overrun and response received reporting */ 1416 #if 0 1417 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1418 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1419 #else 1420 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1421 #endif 1422 } 1423 1424 /* 1425 * Make sure that the Host CPU cache doesn't contain any dirty 1426 * cache lines that falls in the rirb. If I understood correctly, it 1427 * should be sufficient to do this only once as the rirb is purely 1428 * read-only from now on. 1429 */ 1430 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1431 BUS_DMASYNC_PREREAD); 1432 } 1433 1434 /**************************************************************************** 1435 * void hdac_corb_start(hdac_softc *) 1436 * 1437 * Startup the corb DMA engine 1438 ****************************************************************************/ 1439 static void 1440 hdac_corb_start(struct hdac_softc *sc) 1441 { 1442 uint32_t corbctl; 1443 1444 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1445 corbctl |= HDAC_CORBCTL_CORBRUN; 1446 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1447 } 1448 1449 /**************************************************************************** 1450 * void hdac_rirb_start(hdac_softc *) 1451 * 1452 * Startup the rirb DMA engine 1453 ****************************************************************************/ 1454 static void 1455 hdac_rirb_start(struct hdac_softc *sc) 1456 { 1457 uint32_t rirbctl; 1458 1459 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1460 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1461 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1462 } 1463 1464 1465 /**************************************************************************** 1466 * void hdac_scan_codecs(struct hdac_softc *) 1467 * 1468 * Scan the bus for available codecs. 1469 ****************************************************************************/ 1470 static void 1471 hdac_scan_codecs(struct hdac_softc *sc) 1472 { 1473 struct hdac_codec *codec; 1474 int i; 1475 uint16_t statests; 1476 1477 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1478 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1479 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1480 /* We have found a codec. */ 1481 hdac_unlock(sc); 1482 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1483 M_HDAC, M_ZERO | M_NOWAIT); 1484 hdac_lock(sc); 1485 if (codec == NULL) { 1486 device_printf(sc->dev, 1487 "Unable to allocate memory for codec\n"); 1488 continue; 1489 } 1490 codec->commands = NULL; 1491 codec->responses_received = 0; 1492 codec->verbs_sent = 0; 1493 codec->sc = sc; 1494 codec->cad = i; 1495 sc->codecs[i] = codec; 1496 if (hdac_probe_codec(codec) != 0) 1497 break; 1498 } 1499 } 1500 /* All codecs have been probed, now try to attach drivers to them */ 1501 /* bus_generic_attach(sc->dev); */ 1502 } 1503 1504 /**************************************************************************** 1505 * void hdac_probe_codec(struct hdac_softc *, int) 1506 * 1507 * Probe a the given codec_id for available function groups. 1508 ****************************************************************************/ 1509 static int 1510 hdac_probe_codec(struct hdac_codec *codec) 1511 { 1512 struct hdac_softc *sc = codec->sc; 1513 struct hdac_devinfo *devinfo; 1514 uint32_t vendorid, revisionid, subnode; 1515 int startnode; 1516 int endnode; 1517 int i; 1518 nid_t cad = codec->cad; 1519 1520 HDA_BOOTVERBOSE( 1521 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1522 ); 1523 vendorid = hdac_command(sc, 1524 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1525 cad); 1526 revisionid = hdac_command(sc, 1527 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1528 cad); 1529 subnode = hdac_command(sc, 1530 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1531 cad); 1532 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1533 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1534 1535 HDA_BOOTVERBOSE( 1536 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1537 startnode, endnode); 1538 ); 1539 for (i = startnode; i < endnode; i++) { 1540 devinfo = hdac_probe_function(codec, i); 1541 if (devinfo != NULL) { 1542 /* XXX Ignore other FG. */ 1543 devinfo->vendor_id = 1544 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1545 devinfo->device_id = 1546 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1547 devinfo->revision_id = 1548 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1549 devinfo->stepping_id = 1550 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1551 HDA_BOOTVERBOSE( 1552 device_printf(sc->dev, 1553 "HDA_DEBUG: \tFound AFG nid=%d " 1554 "[startnode=%d endnode=%d]\n", 1555 devinfo->nid, startnode, endnode); 1556 ); 1557 return (1); 1558 } 1559 } 1560 1561 HDA_BOOTVERBOSE( 1562 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1563 ); 1564 return (0); 1565 } 1566 1567 static struct hdac_devinfo * 1568 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1569 { 1570 struct hdac_softc *sc = codec->sc; 1571 struct hdac_devinfo *devinfo; 1572 uint32_t fctgrptype; 1573 nid_t cad = codec->cad; 1574 1575 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1576 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1577 1578 /* XXX For now, ignore other FG. */ 1579 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1580 return (NULL); 1581 1582 hdac_unlock(sc); 1583 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1584 M_NOWAIT | M_ZERO); 1585 hdac_lock(sc); 1586 if (devinfo == NULL) { 1587 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1588 __func__); 1589 return (NULL); 1590 } 1591 1592 devinfo->nid = nid; 1593 devinfo->node_type = fctgrptype; 1594 devinfo->codec = codec; 1595 1596 hdac_add_child(sc, devinfo); 1597 1598 return (devinfo); 1599 } 1600 1601 static void 1602 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1603 { 1604 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1605 device_set_ivars(devinfo->dev, (void *)devinfo); 1606 /* XXX - Print more information when booting verbose??? */ 1607 } 1608 1609 static void 1610 hdac_widget_connection_parse(struct hdac_widget *w) 1611 { 1612 struct hdac_softc *sc = w->devinfo->codec->sc; 1613 uint32_t res; 1614 int i, j, max, found, entnum, cnid; 1615 nid_t cad = w->devinfo->codec->cad; 1616 nid_t nid = w->nid; 1617 1618 res = hdac_command(sc, 1619 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1620 1621 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1622 1623 if (w->nconns < 1) 1624 return; 1625 1626 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1627 res = 0; 1628 i = 0; 1629 found = 0; 1630 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1631 1632 while (i < w->nconns) { 1633 res = hdac_command(sc, 1634 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1635 for (j = 0; j < entnum; j++) { 1636 cnid = res; 1637 cnid >>= (32 / entnum) * j; 1638 cnid &= (1 << (32 / entnum)) - 1; 1639 if (cnid == 0) 1640 continue; 1641 if (found > max) { 1642 device_printf(sc->dev, 1643 "node %d: Adding %d: " 1644 "Max connection reached!\n", 1645 nid, cnid); 1646 continue; 1647 } 1648 w->conns[found++] = cnid; 1649 } 1650 i += entnum; 1651 } 1652 1653 HDA_BOOTVERBOSE( 1654 if (w->nconns != found) { 1655 device_printf(sc->dev, 1656 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1657 "length=%d != found=%d\n", 1658 nid, w->nconns, found); 1659 } 1660 ); 1661 } 1662 1663 static uint32_t 1664 hdac_widget_pin_getconfig(struct hdac_widget *w) 1665 { 1666 struct hdac_softc *sc; 1667 uint32_t config, id; 1668 nid_t cad, nid; 1669 1670 sc = w->devinfo->codec->sc; 1671 cad = w->devinfo->codec->cad; 1672 nid = w->nid; 1673 id = hdac_codec_id(w->devinfo); 1674 1675 config = hdac_command(sc, 1676 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1677 cad); 1678 /* 1679 * XXX REWRITE!!!! Don't argue! 1680 */ 1681 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1682 switch (nid) { 1683 case 26: 1684 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1685 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1686 break; 1687 case 27: 1688 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1689 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1690 break; 1691 } 1692 } else if (id == HDA_CODEC_ALC880 && 1693 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1694 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1695 /* 1696 * Super broken BIOS 1697 */ 1698 switch (nid) { 1699 case 20: 1700 break; 1701 case 21: 1702 break; 1703 case 22: 1704 break; 1705 case 23: 1706 break; 1707 case 24: /* MIC1 */ 1708 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1709 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1710 break; 1711 case 25: /* XXX MIC2 */ 1712 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1713 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1714 break; 1715 case 26: /* LINE1 */ 1716 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1717 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1718 break; 1719 case 27: /* XXX LINE2 */ 1720 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1721 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1722 break; 1723 case 28: /* CD */ 1724 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1725 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1726 break; 1727 case 30: 1728 break; 1729 case 31: 1730 break; 1731 default: 1732 break; 1733 } 1734 } 1735 1736 return (config); 1737 } 1738 1739 static void 1740 hdac_widget_pin_parse(struct hdac_widget *w) 1741 { 1742 struct hdac_softc *sc = w->devinfo->codec->sc; 1743 uint32_t config, pincap; 1744 char *devstr, *connstr; 1745 nid_t cad = w->devinfo->codec->cad; 1746 nid_t nid = w->nid; 1747 1748 config = hdac_widget_pin_getconfig(w); 1749 w->wclass.pin.config = config; 1750 1751 pincap = hdac_command(sc, 1752 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1753 w->wclass.pin.cap = pincap; 1754 1755 w->wclass.pin.ctrl = hdac_command(sc, 1756 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1757 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1758 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1759 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1760 1761 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1762 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1763 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1764 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1765 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1766 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1767 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1768 w->param.eapdbtl = hdac_command(sc, 1769 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1770 w->param.eapdbtl &= 0x7; 1771 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1772 } else 1773 w->param.eapdbtl = HDAC_INVALID; 1774 1775 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1776 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1777 devstr = "line out"; 1778 break; 1779 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1780 devstr = "speaker"; 1781 break; 1782 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1783 devstr = "headphones out"; 1784 break; 1785 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1786 devstr = "CD"; 1787 break; 1788 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1789 devstr = "SPDIF out"; 1790 break; 1791 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1792 devstr = "digital (other) out"; 1793 break; 1794 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1795 devstr = "modem, line side"; 1796 break; 1797 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1798 devstr = "modem, handset side"; 1799 break; 1800 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1801 devstr = "line in"; 1802 break; 1803 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1804 devstr = "AUX"; 1805 break; 1806 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1807 devstr = "Mic in"; 1808 break; 1809 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1810 devstr = "telephony"; 1811 break; 1812 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1813 devstr = "SPDIF in"; 1814 break; 1815 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1816 devstr = "digital (other) in"; 1817 break; 1818 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1819 devstr = "other"; 1820 break; 1821 default: 1822 devstr = "unknown"; 1823 break; 1824 } 1825 1826 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1827 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1828 connstr = "jack"; 1829 break; 1830 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1831 connstr = "none"; 1832 break; 1833 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1834 connstr = "fixed"; 1835 break; 1836 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1837 connstr = "jack / fixed"; 1838 break; 1839 default: 1840 connstr = "unknown"; 1841 break; 1842 } 1843 1844 strlcat(w->name, ": ", sizeof(w->name)); 1845 strlcat(w->name, devstr, sizeof(w->name)); 1846 strlcat(w->name, " (", sizeof(w->name)); 1847 strlcat(w->name, connstr, sizeof(w->name)); 1848 strlcat(w->name, ")", sizeof(w->name)); 1849 } 1850 1851 static void 1852 hdac_widget_parse(struct hdac_widget *w) 1853 { 1854 struct hdac_softc *sc = w->devinfo->codec->sc; 1855 uint32_t wcap, cap; 1856 char *typestr; 1857 nid_t cad = w->devinfo->codec->cad; 1858 nid_t nid = w->nid; 1859 1860 wcap = hdac_command(sc, 1861 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1862 cad); 1863 w->param.widget_cap = wcap; 1864 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1865 1866 switch (w->type) { 1867 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1868 typestr = "audio output"; 1869 break; 1870 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1871 typestr = "audio input"; 1872 break; 1873 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1874 typestr = "audio mixer"; 1875 break; 1876 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1877 typestr = "audio selector"; 1878 break; 1879 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1880 typestr = "pin"; 1881 break; 1882 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1883 typestr = "power widget"; 1884 break; 1885 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1886 typestr = "volume widget"; 1887 break; 1888 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1889 typestr = "beep widget"; 1890 break; 1891 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1892 typestr = "vendor widget"; 1893 break; 1894 default: 1895 typestr = "unknown type"; 1896 break; 1897 } 1898 1899 strlcpy(w->name, typestr, sizeof(w->name)); 1900 1901 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1902 hdac_command(sc, 1903 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1904 cad); 1905 DELAY(1000); 1906 } 1907 1908 hdac_widget_connection_parse(w); 1909 1910 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1911 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1912 w->param.outamp_cap = 1913 hdac_command(sc, 1914 HDA_CMD_GET_PARAMETER(cad, nid, 1915 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1916 else 1917 w->param.outamp_cap = 1918 w->devinfo->function.audio.outamp_cap; 1919 } else 1920 w->param.outamp_cap = 0; 1921 1922 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1923 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1924 w->param.inamp_cap = 1925 hdac_command(sc, 1926 HDA_CMD_GET_PARAMETER(cad, nid, 1927 HDA_PARAM_INPUT_AMP_CAP), cad); 1928 else 1929 w->param.inamp_cap = 1930 w->devinfo->function.audio.inamp_cap; 1931 } else 1932 w->param.inamp_cap = 0; 1933 1934 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1935 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1936 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1937 cap = hdac_command(sc, 1938 HDA_CMD_GET_PARAMETER(cad, nid, 1939 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1940 w->param.supp_stream_formats = (cap != 0) ? cap : 1941 w->devinfo->function.audio.supp_stream_formats; 1942 cap = hdac_command(sc, 1943 HDA_CMD_GET_PARAMETER(cad, nid, 1944 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1945 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1946 w->devinfo->function.audio.supp_pcm_size_rate; 1947 } else { 1948 w->param.supp_stream_formats = 1949 w->devinfo->function.audio.supp_stream_formats; 1950 w->param.supp_pcm_size_rate = 1951 w->devinfo->function.audio.supp_pcm_size_rate; 1952 } 1953 } else { 1954 w->param.supp_stream_formats = 0; 1955 w->param.supp_pcm_size_rate = 0; 1956 } 1957 1958 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1959 hdac_widget_pin_parse(w); 1960 } 1961 1962 static struct hdac_widget * 1963 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1964 { 1965 if (devinfo == NULL || devinfo->widget == NULL || 1966 nid < devinfo->startnode || nid >= devinfo->endnode) 1967 return (NULL); 1968 return (&devinfo->widget[nid - devinfo->startnode]); 1969 } 1970 1971 static __inline int 1972 hda_poll_channel(struct hdac_chan *ch) 1973 { 1974 uint32_t sz, delta; 1975 volatile uint32_t ptr; 1976 1977 if (ch->active == 0) 1978 return (0); 1979 1980 sz = ch->blksz * ch->blkcnt; 1981 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 1982 ch->ptr = ptr; 1983 ptr %= sz; 1984 ptr &= ~(ch->blksz - 1); 1985 delta = (sz + ptr - ch->prevptr) % sz; 1986 1987 if (delta < ch->blksz) 1988 return (0); 1989 1990 ch->prevptr = ptr; 1991 1992 return (1); 1993 } 1994 1995 #define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 1996 1997 static void 1998 hda_poll_callback(void *arg) 1999 { 2000 struct hdac_softc *sc = arg; 2001 uint32_t trigger = 0; 2002 2003 if (sc == NULL) 2004 return; 2005 2006 hdac_lock(sc); 2007 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2008 hdac_unlock(sc); 2009 return; 2010 } 2011 2012 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2013 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2014 2015 /* XXX */ 2016 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2017 hda_poll_callback, sc); 2018 2019 hdac_unlock(sc); 2020 2021 if (trigger & 1) 2022 chn_intr(sc->play.c); 2023 if (trigger & 2) 2024 chn_intr(sc->rec.c); 2025 } 2026 2027 static int 2028 hdac_rirb_flush(struct hdac_softc *sc) 2029 { 2030 struct hdac_rirb *rirb_base, *rirb; 2031 struct hdac_codec *codec; 2032 struct hdac_command_list *commands; 2033 nid_t cad; 2034 uint32_t resp; 2035 uint8_t rirbwp; 2036 int ret = 0; 2037 2038 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2039 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2040 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2041 BUS_DMASYNC_POSTREAD); 2042 2043 while (sc->rirb_rp != rirbwp) { 2044 sc->rirb_rp++; 2045 sc->rirb_rp %= sc->rirb_size; 2046 rirb = &rirb_base[sc->rirb_rp]; 2047 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2048 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2049 sc->codecs[cad] == NULL) 2050 continue; 2051 resp = rirb->response; 2052 codec = sc->codecs[cad]; 2053 commands = codec->commands; 2054 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2055 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2056 ((resp >> 26) & 0xffff); 2057 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2058 } else if (commands != NULL && commands->num_commands > 0 && 2059 codec->responses_received < commands->num_commands) 2060 commands->responses[codec->responses_received++] = 2061 resp; 2062 ret++; 2063 } 2064 2065 return (ret); 2066 } 2067 2068 static int 2069 hdac_unsolq_flush(struct hdac_softc *sc) 2070 { 2071 nid_t cad; 2072 uint32_t tag; 2073 int ret = 0; 2074 2075 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2076 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2077 while (sc->unsolq_rp != sc->unsolq_wp) { 2078 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2079 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2080 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2081 hdac_unsolicited_handler(sc->codecs[cad], tag); 2082 ret++; 2083 } 2084 sc->unsolq_st = HDAC_UNSOLQ_READY; 2085 } 2086 2087 return (ret); 2088 } 2089 2090 static void 2091 hdac_poll_callback(void *arg) 2092 { 2093 struct hdac_softc *sc = arg; 2094 if (sc == NULL) 2095 return; 2096 2097 hdac_lock(sc); 2098 if (sc->polling == 0) { 2099 hdac_unlock(sc); 2100 return; 2101 } 2102 hdac_rirb_flush(sc); 2103 hdac_unsolq_flush(sc); 2104 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2105 hdac_poll_callback, sc); 2106 hdac_unlock(sc); 2107 } 2108 2109 static void 2110 hdac_stream_stop(struct hdac_chan *ch) 2111 { 2112 struct hdac_softc *sc = ch->devinfo->codec->sc; 2113 uint32_t ctl; 2114 2115 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2116 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2117 HDAC_SDCTL_RUN); 2118 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2119 2120 ch->active = 0; 2121 2122 if (sc->polling != 0) { 2123 int pollticks; 2124 2125 if (hda_chan_active(sc) == 0) { 2126 callout_stop(&sc->poll_hda); 2127 sc->poll_ticks = 1; 2128 } else { 2129 if (sc->play.active != 0) 2130 ch = &sc->play; 2131 else 2132 ch = &sc->rec; 2133 pollticks = ((uint64_t)hz * ch->blksz) / 2134 ((uint64_t)sndbuf_getbps(ch->b) * 2135 sndbuf_getspd(ch->b)); 2136 pollticks >>= 2; 2137 if (pollticks > hz) 2138 pollticks = hz; 2139 if (pollticks < 1) { 2140 HDA_BOOTVERBOSE( 2141 device_printf(sc->dev, 2142 "%s: pollticks=%d < 1 !\n", 2143 __func__, pollticks); 2144 ); 2145 pollticks = 1; 2146 } 2147 if (pollticks > sc->poll_ticks) { 2148 HDA_BOOTVERBOSE( 2149 device_printf(sc->dev, 2150 "%s: pollticks %d -> %d\n", 2151 __func__, sc->poll_ticks, 2152 pollticks); 2153 ); 2154 sc->poll_ticks = pollticks; 2155 callout_reset(&sc->poll_hda, 1, 2156 hda_poll_callback, sc); 2157 } 2158 } 2159 } else { 2160 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2161 ctl &= ~(1 << (ch->off >> 5)); 2162 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2163 } 2164 } 2165 2166 static void 2167 hdac_stream_start(struct hdac_chan *ch) 2168 { 2169 struct hdac_softc *sc = ch->devinfo->codec->sc; 2170 uint32_t ctl; 2171 2172 if (sc->polling != 0) { 2173 int pollticks; 2174 2175 pollticks = ((uint64_t)hz * ch->blksz) / 2176 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2177 pollticks >>= 2; 2178 if (pollticks > hz) 2179 pollticks = hz; 2180 if (pollticks < 1) { 2181 HDA_BOOTVERBOSE( 2182 device_printf(sc->dev, 2183 "%s: pollticks=%d < 1 !\n", 2184 __func__, pollticks); 2185 ); 2186 pollticks = 1; 2187 } 2188 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2189 HDA_BOOTVERBOSE( 2190 if (hda_chan_active(sc) == 0) { 2191 device_printf(sc->dev, 2192 "%s: pollticks=%d\n", 2193 __func__, pollticks); 2194 } else { 2195 device_printf(sc->dev, 2196 "%s: pollticks %d -> %d\n", 2197 __func__, sc->poll_ticks, 2198 pollticks); 2199 } 2200 ); 2201 sc->poll_ticks = pollticks; 2202 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2203 sc); 2204 } 2205 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2206 ctl |= HDAC_SDCTL_RUN; 2207 } else { 2208 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2209 ctl |= 1 << (ch->off >> 5); 2210 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2211 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2212 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2213 HDAC_SDCTL_RUN; 2214 } 2215 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2216 2217 ch->active = 1; 2218 } 2219 2220 static void 2221 hdac_stream_reset(struct hdac_chan *ch) 2222 { 2223 struct hdac_softc *sc = ch->devinfo->codec->sc; 2224 int timeout = 1000; 2225 int to = timeout; 2226 uint32_t ctl; 2227 2228 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2229 ctl |= HDAC_SDCTL_SRST; 2230 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2231 do { 2232 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2233 if (ctl & HDAC_SDCTL_SRST) 2234 break; 2235 DELAY(10); 2236 } while (--to); 2237 if (!(ctl & HDAC_SDCTL_SRST)) { 2238 device_printf(sc->dev, "timeout in reset\n"); 2239 } 2240 ctl &= ~HDAC_SDCTL_SRST; 2241 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2242 to = timeout; 2243 do { 2244 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2245 if (!(ctl & HDAC_SDCTL_SRST)) 2246 break; 2247 DELAY(10); 2248 } while (--to); 2249 if (ctl & HDAC_SDCTL_SRST) 2250 device_printf(sc->dev, "can't reset!\n"); 2251 } 2252 2253 static void 2254 hdac_stream_setid(struct hdac_chan *ch) 2255 { 2256 struct hdac_softc *sc = ch->devinfo->codec->sc; 2257 uint32_t ctl; 2258 2259 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2260 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2261 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2262 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2263 } 2264 2265 static void 2266 hdac_bdl_setup(struct hdac_chan *ch) 2267 { 2268 struct hdac_softc *sc = ch->devinfo->codec->sc; 2269 struct hdac_bdle *bdle; 2270 uint64_t addr; 2271 uint32_t blksz, blkcnt; 2272 int i; 2273 2274 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2275 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2276 2277 if (sc->polling != 0) { 2278 blksz = ch->blksz * ch->blkcnt; 2279 blkcnt = 1; 2280 } else { 2281 blksz = ch->blksz; 2282 blkcnt = ch->blkcnt; 2283 } 2284 2285 for (i = 0; i < blkcnt; i++, bdle++) { 2286 bdle->addrl = (uint32_t)addr; 2287 bdle->addrh = (uint32_t)(addr >> 32); 2288 bdle->len = blksz; 2289 bdle->ioc = 1 ^ sc->polling; 2290 addr += blksz; 2291 } 2292 2293 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2294 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2295 addr = ch->bdl_dma.dma_paddr; 2296 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2297 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2298 } 2299 2300 static int 2301 hdac_bdl_alloc(struct hdac_chan *ch) 2302 { 2303 struct hdac_softc *sc = ch->devinfo->codec->sc; 2304 int rc; 2305 2306 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2307 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2308 if (rc) { 2309 device_printf(sc->dev, "can't alloc bdl\n"); 2310 return (rc); 2311 } 2312 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2313 2314 return (0); 2315 } 2316 2317 static void 2318 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2319 int index, int lmute, int rmute, 2320 int left, int right, int dir) 2321 { 2322 uint16_t v = 0; 2323 2324 if (sc == NULL) 2325 return; 2326 2327 if (left != right || lmute != rmute) { 2328 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2329 (lmute << 7) | left; 2330 hdac_command(sc, 2331 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2332 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2333 (rmute << 7) | right; 2334 } else 2335 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2336 (lmute << 7) | left; 2337 2338 hdac_command(sc, 2339 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2340 } 2341 2342 static void 2343 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2344 int left, int right) 2345 { 2346 struct hdac_softc *sc; 2347 nid_t nid, cad; 2348 int lmute, rmute; 2349 2350 if (ctl == NULL || ctl->widget == NULL || 2351 ctl->widget->devinfo == NULL || 2352 ctl->widget->devinfo->codec == NULL || 2353 ctl->widget->devinfo->codec->sc == NULL) 2354 return; 2355 2356 sc = ctl->widget->devinfo->codec->sc; 2357 cad = ctl->widget->devinfo->codec->cad; 2358 nid = ctl->widget->nid; 2359 2360 if (mute == HDA_AMP_MUTE_DEFAULT) { 2361 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2362 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2363 } else { 2364 lmute = HDA_AMP_LEFT_MUTED(mute); 2365 rmute = HDA_AMP_RIGHT_MUTED(mute); 2366 } 2367 2368 if (ctl->dir & HDA_CTL_OUT) 2369 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2370 lmute, rmute, left, right, 0); 2371 if (ctl->dir & HDA_CTL_IN) 2372 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2373 lmute, rmute, left, right, 1); 2374 ctl->left = left; 2375 ctl->right = right; 2376 } 2377 2378 static void 2379 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2380 { 2381 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2382 return; 2383 hdac_command(w->devinfo->codec->sc, 2384 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2385 w->nid, index), w->devinfo->codec->cad); 2386 w->selconn = index; 2387 } 2388 2389 2390 /**************************************************************************** 2391 * uint32_t hdac_command_sendone_internal 2392 * 2393 * Wrapper function that sends only one command to a given codec 2394 ****************************************************************************/ 2395 static uint32_t 2396 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2397 { 2398 struct hdac_command_list cl; 2399 uint32_t response = HDAC_INVALID; 2400 2401 if (!hdac_lockowned(sc)) 2402 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2403 cl.num_commands = 1; 2404 cl.verbs = &verb; 2405 cl.responses = &response; 2406 2407 hdac_command_send_internal(sc, &cl, cad); 2408 2409 return (response); 2410 } 2411 2412 /**************************************************************************** 2413 * hdac_command_send_internal 2414 * 2415 * Send a command list to the codec via the corb. We queue as much verbs as 2416 * we can and msleep on the codec. When the interrupt get the responses 2417 * back from the rirb, it will wake us up so we can queue the remaining verbs 2418 * if any. 2419 ****************************************************************************/ 2420 static void 2421 hdac_command_send_internal(struct hdac_softc *sc, 2422 struct hdac_command_list *commands, nid_t cad) 2423 { 2424 struct hdac_codec *codec; 2425 int corbrp; 2426 uint32_t *corb; 2427 int timeout; 2428 int retry = 10; 2429 struct hdac_rirb *rirb_base; 2430 2431 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2432 commands->num_commands < 1) 2433 return; 2434 2435 codec = sc->codecs[cad]; 2436 codec->commands = commands; 2437 codec->responses_received = 0; 2438 codec->verbs_sent = 0; 2439 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2440 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2441 2442 do { 2443 if (codec->verbs_sent != commands->num_commands) { 2444 /* Queue as many verbs as possible */ 2445 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2446 bus_dmamap_sync(sc->corb_dma.dma_tag, 2447 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2448 while (codec->verbs_sent != commands->num_commands && 2449 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2450 sc->corb_wp++; 2451 sc->corb_wp %= sc->corb_size; 2452 corb[sc->corb_wp] = 2453 commands->verbs[codec->verbs_sent++]; 2454 } 2455 2456 /* Send the verbs to the codecs */ 2457 bus_dmamap_sync(sc->corb_dma.dma_tag, 2458 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2459 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2460 } 2461 2462 timeout = 1000; 2463 while (hdac_rirb_flush(sc) == 0 && --timeout) 2464 DELAY(10); 2465 } while ((codec->verbs_sent != commands->num_commands || 2466 codec->responses_received != commands->num_commands) && --retry); 2467 2468 if (retry == 0) 2469 device_printf(sc->dev, 2470 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2471 __func__, commands->num_commands, codec->verbs_sent, 2472 codec->responses_received); 2473 2474 codec->commands = NULL; 2475 codec->responses_received = 0; 2476 codec->verbs_sent = 0; 2477 2478 hdac_unsolq_flush(sc); 2479 } 2480 2481 2482 /**************************************************************************** 2483 * Device Methods 2484 ****************************************************************************/ 2485 2486 /**************************************************************************** 2487 * int hdac_probe(device_t) 2488 * 2489 * Probe for the presence of an hdac. If none is found, check for a generic 2490 * match using the subclass of the device. 2491 ****************************************************************************/ 2492 static int 2493 hdac_probe(device_t dev) 2494 { 2495 int i, result; 2496 uint32_t model; 2497 uint16_t class, subclass; 2498 char desc[64]; 2499 2500 model = (uint32_t)pci_get_device(dev) << 16; 2501 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2502 class = pci_get_class(dev); 2503 subclass = pci_get_subclass(dev); 2504 2505 bzero(desc, sizeof(desc)); 2506 result = ENXIO; 2507 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2508 if (hdac_devices[i].model == model) { 2509 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2510 result = BUS_PROBE_DEFAULT; 2511 break; 2512 } 2513 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2514 class == PCIC_MULTIMEDIA && 2515 subclass == PCIS_MULTIMEDIA_HDA) { 2516 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2517 result = BUS_PROBE_GENERIC; 2518 break; 2519 } 2520 } 2521 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2522 subclass == PCIS_MULTIMEDIA_HDA) { 2523 strlcpy(desc, "Generic", sizeof(desc)); 2524 result = BUS_PROBE_GENERIC; 2525 } 2526 if (result != ENXIO) { 2527 strlcat(desc, " High Definition Audio Controller", 2528 sizeof(desc)); 2529 device_set_desc_copy(dev, desc); 2530 } 2531 2532 return (result); 2533 } 2534 2535 static void * 2536 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2537 struct pcm_channel *c, int dir) 2538 { 2539 struct hdac_devinfo *devinfo = data; 2540 struct hdac_softc *sc = devinfo->codec->sc; 2541 struct hdac_chan *ch; 2542 2543 hdac_lock(sc); 2544 if (dir == PCMDIR_PLAY) { 2545 ch = &sc->play; 2546 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2547 ch->dir = PCMDIR_PLAY; 2548 ch->sid = ++sc->streamcnt; 2549 devinfo->function.audio.playcnt++; 2550 } else { 2551 ch = &sc->rec; 2552 ch->off = devinfo->function.audio.reccnt << 5; 2553 ch->dir = PCMDIR_REC; 2554 ch->sid = ++sc->streamcnt; 2555 devinfo->function.audio.reccnt++; 2556 } 2557 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2558 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2559 ch->pcmrates[0] = 48000; 2560 ch->pcmrates[1] = 0; 2561 } 2562 ch->b = b; 2563 ch->c = c; 2564 ch->devinfo = devinfo; 2565 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2566 ch->blkcnt = sc->chan_blkcnt; 2567 hdac_unlock(sc); 2568 2569 if (hdac_bdl_alloc(ch) != 0) { 2570 ch->blkcnt = 0; 2571 return (NULL); 2572 } 2573 2574 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2575 return (NULL); 2576 2577 hdac_dma_nocache(ch->b->buf); 2578 2579 return (ch); 2580 } 2581 2582 static int 2583 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2584 { 2585 struct hdac_chan *ch = data; 2586 int i; 2587 2588 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2589 if (format == ch->caps.fmtlist[i]) { 2590 ch->fmt = format; 2591 return (0); 2592 } 2593 } 2594 2595 return (EINVAL); 2596 } 2597 2598 static int 2599 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2600 { 2601 struct hdac_chan *ch = data; 2602 uint32_t spd = 0, threshold; 2603 int i; 2604 2605 for (i = 0; ch->pcmrates[i] != 0; i++) { 2606 spd = ch->pcmrates[i]; 2607 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2608 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2609 if (speed < threshold) 2610 break; 2611 } 2612 2613 if (spd == 0) /* impossible */ 2614 ch->spd = 48000; 2615 else 2616 ch->spd = spd; 2617 2618 return (ch->spd); 2619 } 2620 2621 static void 2622 hdac_stream_setup(struct hdac_chan *ch) 2623 { 2624 struct hdac_softc *sc = ch->devinfo->codec->sc; 2625 int i; 2626 nid_t cad = ch->devinfo->codec->cad; 2627 uint16_t fmt; 2628 2629 fmt = 0; 2630 if (ch->fmt & AFMT_S16_LE) 2631 fmt |= ch->bit16 << 4; 2632 else if (ch->fmt & AFMT_S32_LE) 2633 fmt |= ch->bit32 << 4; 2634 else 2635 fmt |= 1 << 4; 2636 2637 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2638 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2639 fmt |= hda_rate_tab[i].base; 2640 fmt |= hda_rate_tab[i].mul; 2641 fmt |= hda_rate_tab[i].div; 2642 break; 2643 } 2644 } 2645 2646 if (ch->fmt & AFMT_STEREO) 2647 fmt |= 1; 2648 2649 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2650 2651 for (i = 0; ch->io[i] != -1; i++) { 2652 HDA_BOOTVERBOSE( 2653 device_printf(sc->dev, 2654 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2655 "fmt=0x%08x\n", 2656 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2657 ch->io[i], fmt); 2658 ); 2659 hdac_command(sc, 2660 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2661 hdac_command(sc, 2662 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2663 ch->sid << 4), cad); 2664 } 2665 } 2666 2667 static int 2668 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2669 { 2670 struct hdac_chan *ch = data; 2671 struct hdac_softc *sc = ch->devinfo->codec->sc; 2672 2673 blksz &= ~0x7f; 2674 if (blksz < 0x80) 2675 blksz = 0x80; 2676 2677 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2678 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2679 2680 if ((sndbuf_getblksz(ch->b) != blksz || 2681 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2682 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2683 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2684 __func__, blksz, ch->blkcnt); 2685 2686 ch->blksz = sndbuf_getblksz(ch->b); 2687 2688 return (ch->blksz); 2689 } 2690 2691 static void 2692 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2693 { 2694 struct hdac_devinfo *devinfo = ch->devinfo; 2695 nid_t cad = devinfo->codec->cad; 2696 int i; 2697 2698 hdac_stream_stop(ch); 2699 2700 for (i = 0; ch->io[i] != -1; i++) { 2701 hdac_command(sc, 2702 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2703 0), cad); 2704 } 2705 } 2706 2707 static void 2708 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2709 { 2710 ch->ptr = 0; 2711 ch->prevptr = 0; 2712 hdac_stream_stop(ch); 2713 hdac_stream_reset(ch); 2714 hdac_bdl_setup(ch); 2715 hdac_stream_setid(ch); 2716 hdac_stream_setup(ch); 2717 hdac_stream_start(ch); 2718 } 2719 2720 static int 2721 hdac_channel_trigger(kobj_t obj, void *data, int go) 2722 { 2723 struct hdac_chan *ch = data; 2724 struct hdac_softc *sc = ch->devinfo->codec->sc; 2725 2726 hdac_lock(sc); 2727 switch (go) { 2728 case PCMTRIG_START: 2729 hdac_channel_start(sc, ch); 2730 break; 2731 case PCMTRIG_STOP: 2732 case PCMTRIG_ABORT: 2733 hdac_channel_stop(sc, ch); 2734 break; 2735 } 2736 hdac_unlock(sc); 2737 2738 return (0); 2739 } 2740 2741 static int 2742 hdac_channel_getptr(kobj_t obj, void *data) 2743 { 2744 struct hdac_chan *ch = data; 2745 struct hdac_softc *sc = ch->devinfo->codec->sc; 2746 uint32_t ptr; 2747 2748 hdac_lock(sc); 2749 if (sc->polling != 0) 2750 ptr = ch->ptr; 2751 else 2752 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2753 hdac_unlock(sc); 2754 2755 /* 2756 * Round to available space and force 128 bytes aligment. 2757 */ 2758 ptr %= ch->blksz * ch->blkcnt; 2759 ptr &= ~0x7f; 2760 2761 return (ptr); 2762 } 2763 2764 static struct pcmchan_caps * 2765 hdac_channel_getcaps(kobj_t obj, void *data) 2766 { 2767 return (&((struct hdac_chan *)data)->caps); 2768 } 2769 2770 static kobj_method_t hdac_channel_methods[] = { 2771 KOBJMETHOD(channel_init, hdac_channel_init), 2772 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2773 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2774 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2775 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2776 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2777 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2778 { 0, 0 } 2779 }; 2780 CHANNEL_DECLARE(hdac_channel); 2781 2782 static int 2783 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2784 { 2785 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2786 struct hdac_softc *sc = devinfo->codec->sc; 2787 struct hdac_widget *w, *cw; 2788 struct hdac_audio_ctl *ctl; 2789 uint32_t mask, recmask, id; 2790 int i, j, softpcmvol; 2791 nid_t cad; 2792 2793 hdac_lock(sc); 2794 2795 mask = 0; 2796 recmask = 0; 2797 2798 id = hdac_codec_id(devinfo); 2799 cad = devinfo->codec->cad; 2800 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2801 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2802 sc->pci_subvendor) && 2803 hdac_hp_switch[i].id == id)) 2804 continue; 2805 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2806 if (w != NULL && w->enable != 0 2807 && w->type == 2808 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2809 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2810 hdac_command(sc, 2811 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2812 w->nid, 2813 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2814 HDAC_UNSOLTAG_EVENT_HP), cad); 2815 hdac_hp_switch_handler(devinfo); 2816 HDA_BOOTVERBOSE( 2817 device_printf(sc->dev, 2818 "HDA_DEBUG: Enabling headphone/speaker " 2819 "audio routing switching:\n"); 2820 device_printf(sc->dev, 2821 "HDA_DEBUG: \tindex=%d nid=%d " 2822 "pci_subvendor=0x%08x " 2823 "codec=0x%08x\n", 2824 i, w->nid, sc->pci_subvendor, id); 2825 ); 2826 } 2827 break; 2828 } 2829 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2830 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2831 sc->pci_subvendor) && 2832 hdac_eapd_switch[i].id == id)) 2833 continue; 2834 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2835 if (w == NULL || w->enable == 0) 2836 break; 2837 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2838 w->param.eapdbtl == HDAC_INVALID) 2839 break; 2840 mask |= SOUND_MASK_OGAIN; 2841 break; 2842 } 2843 2844 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2845 w = hdac_widget_get(devinfo, i); 2846 if (w == NULL || w->enable == 0) 2847 continue; 2848 mask |= w->ctlflags; 2849 if (!(w->pflags & HDA_ADC_RECSEL)) 2850 continue; 2851 for (j = 0; j < w->nconns; j++) { 2852 cw = hdac_widget_get(devinfo, w->conns[j]); 2853 if (cw == NULL || cw->enable == 0) 2854 continue; 2855 recmask |= cw->ctlflags; 2856 } 2857 } 2858 2859 if (!(mask & SOUND_MASK_PCM)) { 2860 softpcmvol = 1; 2861 mask |= SOUND_MASK_PCM; 2862 } else 2863 softpcmvol = (devinfo->function.audio.quirks & 2864 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2865 2866 i = 0; 2867 ctl = NULL; 2868 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2869 if (ctl->widget == NULL || ctl->enable == 0) 2870 continue; 2871 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2872 continue; 2873 if (ctl->step > 0) 2874 break; 2875 } 2876 2877 if (softpcmvol == 1 || ctl == NULL) { 2878 struct snddev_info *d = NULL; 2879 d = device_get_softc(sc->dev); 2880 if (d != NULL) { 2881 d->flags |= SD_F_SOFTPCMVOL; 2882 HDA_BOOTVERBOSE( 2883 device_printf(sc->dev, 2884 "HDA_DEBUG: %s Soft PCM volume\n", 2885 (softpcmvol == 1) ? 2886 "Forcing" : "Enabling"); 2887 ); 2888 } 2889 i = 0; 2890 /* 2891 * XXX Temporary quirk for STAC9220, until the parser 2892 * become smarter. 2893 */ 2894 if (id == HDA_CODEC_STAC9220) { 2895 mask |= SOUND_MASK_VOLUME; 2896 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2897 NULL) { 2898 if (ctl->widget == NULL || ctl->enable == 0) 2899 continue; 2900 if (ctl->widget->nid == 11 && ctl->index == 0) { 2901 ctl->ossmask = SOUND_MASK_VOLUME; 2902 ctl->ossval = 100 | (100 << 8); 2903 } else 2904 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2905 } 2906 } else { 2907 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2908 SOUND_MASK_PCM); 2909 if (!(mask & SOUND_MASK_VOLUME)) 2910 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2911 SOUND_MIXER_NONE); 2912 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2913 NULL) { 2914 if (ctl->widget == NULL || ctl->enable == 0) 2915 continue; 2916 if (!HDA_FLAG_MATCH(ctl->ossmask, 2917 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2918 continue; 2919 if (!(ctl->mute == 1 && ctl->step == 0)) 2920 ctl->enable = 0; 2921 } 2922 } 2923 } 2924 2925 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2926 2927 mix_setrecdevs(m, recmask); 2928 mix_setdevs(m, mask); 2929 2930 hdac_unlock(sc); 2931 2932 return (0); 2933 } 2934 2935 static int 2936 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2937 unsigned left, unsigned right) 2938 { 2939 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2940 struct hdac_softc *sc = devinfo->codec->sc; 2941 struct hdac_widget *w; 2942 struct hdac_audio_ctl *ctl; 2943 uint32_t id, mute; 2944 int lvol, rvol, mlvol, mrvol; 2945 int i = 0; 2946 2947 hdac_lock(sc); 2948 if (dev == SOUND_MIXER_OGAIN) { 2949 uint32_t orig; 2950 /*if (left != right || !(left == 0 || left == 1)) { 2951 hdac_unlock(sc); 2952 return (-1); 2953 }*/ 2954 id = hdac_codec_id(devinfo); 2955 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2956 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2957 sc->pci_subvendor) && 2958 hdac_eapd_switch[i].id == id) 2959 break; 2960 } 2961 if (i >= HDAC_EAPD_SWITCH_LEN) { 2962 hdac_unlock(sc); 2963 return (-1); 2964 } 2965 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2966 if (w == NULL || 2967 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2968 w->param.eapdbtl == HDAC_INVALID) { 2969 hdac_unlock(sc); 2970 return (-1); 2971 } 2972 orig = w->param.eapdbtl; 2973 if (left == 0) 2974 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2975 else 2976 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2977 if (orig != w->param.eapdbtl) { 2978 uint32_t val; 2979 2980 if (hdac_eapd_switch[i].hp_switch != 0) 2981 hdac_hp_switch_handler(devinfo); 2982 val = w->param.eapdbtl; 2983 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2984 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2985 hdac_command(sc, 2986 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2987 w->nid, val), devinfo->codec->cad); 2988 } 2989 hdac_unlock(sc); 2990 return (left | (left << 8)); 2991 } 2992 if (dev == SOUND_MIXER_VOLUME) 2993 devinfo->function.audio.mvol = left | (right << 8); 2994 2995 mlvol = devinfo->function.audio.mvol & 0x7f; 2996 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2997 lvol = 0; 2998 rvol = 0; 2999 3000 i = 0; 3001 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3002 if (ctl->widget == NULL || ctl->enable == 0 || 3003 !(ctl->ossmask & (1 << dev))) 3004 continue; 3005 switch (dev) { 3006 case SOUND_MIXER_VOLUME: 3007 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3008 lvol = (lvol * ctl->step) / 100; 3009 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3010 rvol = (rvol * ctl->step) / 100; 3011 break; 3012 default: 3013 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3014 lvol = (left * mlvol) / 100; 3015 lvol = (lvol * ctl->step) / 100; 3016 rvol = (right * mrvol) / 100; 3017 rvol = (rvol * ctl->step) / 100; 3018 } else { 3019 lvol = (left * ctl->step) / 100; 3020 rvol = (right * ctl->step) / 100; 3021 } 3022 ctl->ossval = left | (right << 8); 3023 break; 3024 } 3025 mute = 0; 3026 if (ctl->step < 1) { 3027 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3028 (ctl->muted & HDA_AMP_MUTE_LEFT); 3029 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3030 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3031 } else { 3032 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3033 (ctl->muted & HDA_AMP_MUTE_LEFT); 3034 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3035 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3036 } 3037 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3038 } 3039 hdac_unlock(sc); 3040 3041 return (left | (right << 8)); 3042 } 3043 3044 static int 3045 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3046 { 3047 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3048 struct hdac_widget *w, *cw; 3049 struct hdac_softc *sc = devinfo->codec->sc; 3050 uint32_t ret = src, target; 3051 int i, j; 3052 3053 target = 0; 3054 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3055 if (src & (1 << i)) { 3056 target = 1 << i; 3057 break; 3058 } 3059 } 3060 3061 hdac_lock(sc); 3062 3063 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3064 w = hdac_widget_get(devinfo, i); 3065 if (w == NULL || w->enable == 0) 3066 continue; 3067 if (!(w->pflags & HDA_ADC_RECSEL)) 3068 continue; 3069 for (j = 0; j < w->nconns; j++) { 3070 cw = hdac_widget_get(devinfo, w->conns[j]); 3071 if (cw == NULL || cw->enable == 0) 3072 continue; 3073 if ((target == SOUND_MASK_VOLUME && 3074 cw->type != 3075 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3076 (target != SOUND_MASK_VOLUME && 3077 cw->type == 3078 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3079 continue; 3080 if (cw->ctlflags & target) { 3081 hdac_widget_connection_select(w, j); 3082 ret = target; 3083 j += w->nconns; 3084 } 3085 } 3086 } 3087 3088 hdac_unlock(sc); 3089 3090 return (ret); 3091 } 3092 3093 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3094 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3095 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3096 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3097 { 0, 0 } 3098 }; 3099 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3100 3101 /**************************************************************************** 3102 * int hdac_attach(device_t) 3103 * 3104 * Attach the device into the kernel. Interrupts usually won't be enabled 3105 * when this function is called. Setup everything that doesn't require 3106 * interrupts and defer probing of codecs until interrupts are enabled. 3107 ****************************************************************************/ 3108 static int 3109 hdac_attach(device_t dev) 3110 { 3111 struct hdac_softc *sc; 3112 int result; 3113 int i = 0; 3114 3115 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3116 if (sc == NULL) { 3117 device_printf(dev, "cannot allocate softc\n"); 3118 return (ENOMEM); 3119 } 3120 3121 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3122 if (sc->lock == NULL) { 3123 device_printf(dev, "mutex creation failed\n"); 3124 free(sc, M_DEVBUF); 3125 return (ENOMEM); 3126 } 3127 3128 sc->dev = dev; 3129 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3130 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3131 3132 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3133 /* Screw nx6325 - subdevice/subvendor swapped */ 3134 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3135 } 3136 3137 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3138 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3139 3140 sc->poll_ticks = 1; 3141 if (resource_int_value(device_get_name(sc->dev), 3142 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3143 sc->polling = 1; 3144 else 3145 sc->polling = 0; 3146 3147 sc->chan_size = pcm_getbuffersize(dev, 3148 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3149 3150 if (resource_int_value(device_get_name(sc->dev), 3151 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3152 i &= ~0x7f; 3153 if (i < 0x80) 3154 i = 0x80; 3155 sc->chan_blkcnt = sc->chan_size / i; 3156 i = 0; 3157 while (sc->chan_blkcnt >> i) 3158 i++; 3159 sc->chan_blkcnt = 1 << (i - 1); 3160 if (sc->chan_blkcnt < HDA_BDL_MIN) 3161 sc->chan_blkcnt = HDA_BDL_MIN; 3162 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3163 sc->chan_blkcnt = HDA_BDL_MAX; 3164 } else 3165 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3166 3167 result = bus_dma_tag_create(NULL, /* parent */ 3168 HDAC_DMA_ALIGNMENT, /* alignment */ 3169 0, /* boundary */ 3170 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3171 BUS_SPACE_MAXADDR, /* highaddr */ 3172 NULL, /* filtfunc */ 3173 NULL, /* fistfuncarg */ 3174 sc->chan_size, /* maxsize */ 3175 1, /* nsegments */ 3176 sc->chan_size, /* maxsegsz */ 3177 0, /* flags */ 3178 NULL, /* lockfunc */ 3179 NULL, /* lockfuncarg */ 3180 &sc->chan_dmat); /* dmat */ 3181 if (result != 0) { 3182 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3183 __func__, result); 3184 snd_mtxfree(sc->lock); 3185 free(sc, M_DEVBUF); 3186 return (ENXIO); 3187 } 3188 3189 3190 sc->hdabus = NULL; 3191 for (i = 0; i < HDAC_CODEC_MAX; i++) 3192 sc->codecs[i] = NULL; 3193 3194 pci_enable_busmaster(dev); 3195 3196 /* Allocate resources */ 3197 result = hdac_mem_alloc(sc); 3198 if (result != 0) 3199 goto hdac_attach_fail; 3200 result = hdac_irq_alloc(sc); 3201 if (result != 0) 3202 goto hdac_attach_fail; 3203 3204 /* Get Capabilities */ 3205 result = hdac_get_capabilities(sc); 3206 if (result != 0) 3207 goto hdac_attach_fail; 3208 3209 /* Allocate CORB and RIRB dma memory */ 3210 result = hdac_dma_alloc(sc, &sc->corb_dma, 3211 sc->corb_size * sizeof(uint32_t)); 3212 if (result != 0) 3213 goto hdac_attach_fail; 3214 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3215 sc->rirb_size * sizeof(struct hdac_rirb)); 3216 if (result != 0) 3217 goto hdac_attach_fail; 3218 3219 /* Quiesce everything */ 3220 hdac_reset(sc); 3221 3222 /* Disable PCI-Express QOS */ 3223 pci_write_config(sc->dev, 0x44, 3224 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3225 3226 /* Initialize the CORB and RIRB */ 3227 hdac_corb_init(sc); 3228 hdac_rirb_init(sc); 3229 3230 /* Defer remaining of initialization until interrupts are enabled */ 3231 sc->intrhook.ich_func = hdac_attach2; 3232 sc->intrhook.ich_arg = (void *)sc; 3233 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3234 sc->intrhook.ich_func = NULL; 3235 hdac_attach2((void *)sc); 3236 } 3237 3238 return (0); 3239 3240 hdac_attach_fail: 3241 hdac_dma_free(&sc->rirb_dma); 3242 hdac_dma_free(&sc->corb_dma); 3243 hdac_irq_free(sc); 3244 hdac_mem_free(sc); 3245 snd_mtxfree(sc->lock); 3246 free(sc, M_DEVBUF); 3247 3248 return (ENXIO); 3249 } 3250 3251 static void 3252 hdac_audio_parse(struct hdac_devinfo *devinfo) 3253 { 3254 struct hdac_softc *sc = devinfo->codec->sc; 3255 struct hdac_widget *w; 3256 uint32_t res; 3257 int i; 3258 nid_t cad, nid; 3259 3260 cad = devinfo->codec->cad; 3261 nid = devinfo->nid; 3262 3263 hdac_command(sc, 3264 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3265 3266 DELAY(100); 3267 3268 res = hdac_command(sc, 3269 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3270 3271 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3272 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3273 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3274 3275 HDA_BOOTVERBOSE( 3276 device_printf(sc->dev, " Vendor: 0x%08x\n", 3277 devinfo->vendor_id); 3278 device_printf(sc->dev, " Device: 0x%08x\n", 3279 devinfo->device_id); 3280 device_printf(sc->dev, " Revision: 0x%08x\n", 3281 devinfo->revision_id); 3282 device_printf(sc->dev, " Stepping: 0x%08x\n", 3283 devinfo->stepping_id); 3284 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3285 sc->pci_subvendor); 3286 device_printf(sc->dev, " Nodes: start=%d " 3287 "endnode=%d total=%d\n", 3288 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3289 ); 3290 3291 res = hdac_command(sc, 3292 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3293 cad); 3294 devinfo->function.audio.supp_stream_formats = res; 3295 3296 res = hdac_command(sc, 3297 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3298 cad); 3299 devinfo->function.audio.supp_pcm_size_rate = res; 3300 3301 res = hdac_command(sc, 3302 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3303 cad); 3304 devinfo->function.audio.outamp_cap = res; 3305 3306 res = hdac_command(sc, 3307 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3308 cad); 3309 devinfo->function.audio.inamp_cap = res; 3310 3311 if (devinfo->nodecnt > 0) { 3312 hdac_unlock(sc); 3313 devinfo->widget = (struct hdac_widget *)malloc( 3314 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3315 M_NOWAIT | M_ZERO); 3316 hdac_lock(sc); 3317 } else 3318 devinfo->widget = NULL; 3319 3320 if (devinfo->widget == NULL) { 3321 device_printf(sc->dev, "unable to allocate widgets!\n"); 3322 devinfo->endnode = devinfo->startnode; 3323 devinfo->nodecnt = 0; 3324 return; 3325 } 3326 3327 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3328 w = hdac_widget_get(devinfo, i); 3329 if (w == NULL) 3330 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3331 else { 3332 w->devinfo = devinfo; 3333 w->nid = i; 3334 w->enable = 1; 3335 w->selconn = -1; 3336 w->pflags = 0; 3337 w->ctlflags = 0; 3338 w->param.eapdbtl = HDAC_INVALID; 3339 hdac_widget_parse(w); 3340 } 3341 } 3342 } 3343 3344 static void 3345 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3346 { 3347 struct hdac_softc *sc = devinfo->codec->sc; 3348 struct hdac_audio_ctl *ctls; 3349 struct hdac_widget *w, *cw; 3350 int i, j, cnt, max, ocap, icap; 3351 int mute, offset, step, size; 3352 3353 /* XXX This is redundant */ 3354 max = 0; 3355 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3356 w = hdac_widget_get(devinfo, i); 3357 if (w == NULL || w->enable == 0) 3358 continue; 3359 if (w->param.outamp_cap != 0) 3360 max++; 3361 if (w->param.inamp_cap != 0) { 3362 switch (w->type) { 3363 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3364 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3365 for (j = 0; j < w->nconns; j++) { 3366 cw = hdac_widget_get(devinfo, 3367 w->conns[j]); 3368 if (cw == NULL || cw->enable == 0) 3369 continue; 3370 max++; 3371 } 3372 break; 3373 default: 3374 max++; 3375 break; 3376 } 3377 } 3378 } 3379 3380 devinfo->function.audio.ctlcnt = max; 3381 3382 if (max < 1) 3383 return; 3384 3385 hdac_unlock(sc); 3386 ctls = (struct hdac_audio_ctl *)malloc( 3387 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3388 hdac_lock(sc); 3389 3390 if (ctls == NULL) { 3391 /* Blekh! */ 3392 device_printf(sc->dev, "unable to allocate ctls!\n"); 3393 devinfo->function.audio.ctlcnt = 0; 3394 return; 3395 } 3396 3397 cnt = 0; 3398 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3399 if (cnt >= max) { 3400 device_printf(sc->dev, "%s: Ctl overflow!\n", 3401 __func__); 3402 break; 3403 } 3404 w = hdac_widget_get(devinfo, i); 3405 if (w == NULL || w->enable == 0) 3406 continue; 3407 ocap = w->param.outamp_cap; 3408 icap = w->param.inamp_cap; 3409 if (ocap != 0) { 3410 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3411 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3412 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3413 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3414 /*if (offset > step) { 3415 HDA_BOOTVERBOSE( 3416 device_printf(sc->dev, 3417 "HDA_DEBUG: BUGGY outamp: nid=%d " 3418 "[offset=%d > step=%d]\n", 3419 w->nid, offset, step); 3420 ); 3421 offset = step; 3422 }*/ 3423 ctls[cnt].enable = 1; 3424 ctls[cnt].widget = w; 3425 ctls[cnt].mute = mute; 3426 ctls[cnt].step = step; 3427 ctls[cnt].size = size; 3428 ctls[cnt].offset = offset; 3429 ctls[cnt].left = offset; 3430 ctls[cnt].right = offset; 3431 ctls[cnt++].dir = HDA_CTL_OUT; 3432 } 3433 3434 if (icap != 0) { 3435 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3436 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3437 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3438 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3439 /*if (offset > step) { 3440 HDA_BOOTVERBOSE( 3441 device_printf(sc->dev, 3442 "HDA_DEBUG: BUGGY inamp: nid=%d " 3443 "[offset=%d > step=%d]\n", 3444 w->nid, offset, step); 3445 ); 3446 offset = step; 3447 }*/ 3448 switch (w->type) { 3449 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3450 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3451 for (j = 0; j < w->nconns; j++) { 3452 if (cnt >= max) { 3453 device_printf(sc->dev, 3454 "%s: Ctl overflow!\n", 3455 __func__); 3456 break; 3457 } 3458 cw = hdac_widget_get(devinfo, 3459 w->conns[j]); 3460 if (cw == NULL || cw->enable == 0) 3461 continue; 3462 ctls[cnt].enable = 1; 3463 ctls[cnt].widget = w; 3464 ctls[cnt].childwidget = cw; 3465 ctls[cnt].index = j; 3466 ctls[cnt].mute = mute; 3467 ctls[cnt].step = step; 3468 ctls[cnt].size = size; 3469 ctls[cnt].offset = offset; 3470 ctls[cnt].left = offset; 3471 ctls[cnt].right = offset; 3472 ctls[cnt++].dir = HDA_CTL_IN; 3473 } 3474 break; 3475 default: 3476 if (cnt >= max) { 3477 device_printf(sc->dev, 3478 "%s: Ctl overflow!\n", 3479 __func__); 3480 break; 3481 } 3482 ctls[cnt].enable = 1; 3483 ctls[cnt].widget = w; 3484 ctls[cnt].mute = mute; 3485 ctls[cnt].step = step; 3486 ctls[cnt].size = size; 3487 ctls[cnt].offset = offset; 3488 ctls[cnt].left = offset; 3489 ctls[cnt].right = offset; 3490 ctls[cnt++].dir = HDA_CTL_IN; 3491 break; 3492 } 3493 } 3494 } 3495 3496 devinfo->function.audio.ctl = ctls; 3497 } 3498 3499 static const struct { 3500 uint32_t model; 3501 uint32_t id; 3502 uint32_t set, unset; 3503 } hdac_quirks[] = { 3504 /* 3505 * XXX Force stereo quirk. Monoural recording / playback 3506 * on few codecs (especially ALC880) seems broken or 3507 * perhaps unsupported. 3508 */ 3509 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3510 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3511 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3512 HDA_QUIRK_GPIO0, 0 }, 3513 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3514 HDA_QUIRK_GPIO0, 0 }, 3515 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3516 HDA_QUIRK_GPIO0, 0 }, 3517 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3518 HDA_QUIRK_EAPDINV, 0 }, 3519 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3520 HDA_QUIRK_EAPDINV, 0 }, 3521 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3522 HDA_QUIRK_GPIO1, 0 }, 3523 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3524 HDA_QUIRK_EAPDINV, 0 }, 3525 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3526 HDA_QUIRK_EAPDINV, 0 }, 3527 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3528 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3529 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3530 0, HDA_QUIRK_FORCESTEREO }, 3531 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3532 HDA_QUIRK_SOFTPCMVOL, 0 } 3533 }; 3534 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3535 3536 static void 3537 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3538 { 3539 struct hdac_widget *w; 3540 struct hdac_audio_ctl *ctl; 3541 uint32_t id, subvendor; 3542 int i; 3543 3544 id = hdac_codec_id(devinfo); 3545 subvendor = devinfo->codec->sc->pci_subvendor; 3546 3547 /* 3548 * Quirks 3549 */ 3550 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3551 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3552 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3553 continue; 3554 if (hdac_quirks[i].set != 0) 3555 devinfo->function.audio.quirks |= 3556 hdac_quirks[i].set; 3557 if (hdac_quirks[i].unset != 0) 3558 devinfo->function.audio.quirks &= 3559 ~(hdac_quirks[i].unset); 3560 } 3561 3562 switch (id) { 3563 case HDA_CODEC_ALC260: 3564 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3565 w = hdac_widget_get(devinfo, i); 3566 if (w == NULL || w->enable == 0) 3567 continue; 3568 if (w->type != 3569 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3570 continue; 3571 if (w->nid != 5) 3572 w->enable = 0; 3573 } 3574 break; 3575 case HDA_CODEC_ALC861: 3576 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3577 if (ctl != NULL) 3578 ctl->muted = HDA_AMP_MUTE_ALL; 3579 break; 3580 case HDA_CODEC_ALC880: 3581 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3582 w = hdac_widget_get(devinfo, i); 3583 if (w == NULL || w->enable == 0) 3584 continue; 3585 if (w->type == 3586 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3587 w->nid != 9 && w->nid != 29) { 3588 w->enable = 0; 3589 } else if (w->type != 3590 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3591 w->nid == 29) { 3592 w->type = 3593 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3594 w->param.widget_cap &= 3595 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3596 w->param.widget_cap |= 3597 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3598 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3599 strlcpy(w->name, "beep widget", sizeof(w->name)); 3600 } 3601 } 3602 break; 3603 case HDA_CODEC_AD1981HD: 3604 w = hdac_widget_get(devinfo, 11); 3605 if (w != NULL && w->enable != 0 && w->nconns > 3) 3606 w->selconn = 3; 3607 if (subvendor == IBM_M52_SUBVENDOR) { 3608 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3609 if (ctl != NULL) 3610 ctl->ossmask = SOUND_MASK_SPEAKER; 3611 } 3612 break; 3613 case HDA_CODEC_AD1986A: 3614 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3615 w = hdac_widget_get(devinfo, i); 3616 if (w == NULL || w->enable == 0) 3617 continue; 3618 if (w->type != 3619 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3620 continue; 3621 if (w->nid != 3) 3622 w->enable = 0; 3623 } 3624 break; 3625 case HDA_CODEC_STAC9221: 3626 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3627 w = hdac_widget_get(devinfo, i); 3628 if (w == NULL || w->enable == 0) 3629 continue; 3630 if (w->type != 3631 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3632 continue; 3633 if (w->nid != 2) 3634 w->enable = 0; 3635 } 3636 break; 3637 case HDA_CODEC_STAC9221D: 3638 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3639 w = hdac_widget_get(devinfo, i); 3640 if (w == NULL || w->enable == 0) 3641 continue; 3642 if (w->type == 3643 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3644 w->nid != 6) 3645 w->enable = 0; 3646 3647 } 3648 break; 3649 default: 3650 break; 3651 } 3652 } 3653 3654 static int 3655 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3656 { 3657 int *dev = &devinfo->function.audio.ossidx; 3658 3659 while (*dev < SOUND_MIXER_NRDEVICES) { 3660 switch (*dev) { 3661 case SOUND_MIXER_VOLUME: 3662 case SOUND_MIXER_BASS: 3663 case SOUND_MIXER_TREBLE: 3664 case SOUND_MIXER_PCM: 3665 case SOUND_MIXER_SPEAKER: 3666 case SOUND_MIXER_LINE: 3667 case SOUND_MIXER_MIC: 3668 case SOUND_MIXER_CD: 3669 case SOUND_MIXER_RECLEV: 3670 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3671 (*dev)++; 3672 break; 3673 default: 3674 return (*dev)++; 3675 break; 3676 } 3677 } 3678 3679 return (-1); 3680 } 3681 3682 static int 3683 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3684 { 3685 struct hdac_widget *w; 3686 int i, ret = 0; 3687 3688 if (depth > HDA_PARSE_MAXDEPTH) 3689 return (0); 3690 w = hdac_widget_get(devinfo, nid); 3691 if (w == NULL || w->enable == 0) 3692 return (0); 3693 switch (w->type) { 3694 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3695 w->pflags |= HDA_DAC_PATH; 3696 ret = 1; 3697 break; 3698 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3699 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3700 for (i = 0; i < w->nconns; i++) { 3701 if (hdac_widget_find_dac_path(devinfo, 3702 w->conns[i], depth + 1) != 0) { 3703 if (w->selconn == -1) 3704 w->selconn = i; 3705 ret = 1; 3706 w->pflags |= HDA_DAC_PATH; 3707 } 3708 } 3709 break; 3710 default: 3711 break; 3712 } 3713 return (ret); 3714 } 3715 3716 static int 3717 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3718 { 3719 struct hdac_widget *w; 3720 int i, conndev, ret = 0; 3721 3722 if (depth > HDA_PARSE_MAXDEPTH) 3723 return (0); 3724 w = hdac_widget_get(devinfo, nid); 3725 if (w == NULL || w->enable == 0) 3726 return (0); 3727 switch (w->type) { 3728 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3729 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3730 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3731 for (i = 0; i < w->nconns; i++) { 3732 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3733 depth + 1) != 0) { 3734 if (w->selconn == -1) 3735 w->selconn = i; 3736 w->pflags |= HDA_ADC_PATH; 3737 ret = 1; 3738 } 3739 } 3740 break; 3741 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3742 conndev = w->wclass.pin.config & 3743 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3744 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3745 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3746 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3747 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3748 w->pflags |= HDA_ADC_PATH; 3749 ret = 1; 3750 } 3751 break; 3752 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3753 if (w->pflags & HDA_DAC_PATH) { 3754 w->pflags |= HDA_ADC_PATH; 3755 ret = 1; 3756 } 3757 break;*/ 3758 default: 3759 break; 3760 } 3761 return (ret); 3762 } 3763 3764 static uint32_t 3765 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3766 nid_t nid, nid_t pnid, int index, int depth) 3767 { 3768 struct hdac_widget *w, *pw; 3769 struct hdac_audio_ctl *ctl; 3770 uint32_t fl = 0; 3771 int i, ossdev, conndev, strategy; 3772 3773 if (depth > HDA_PARSE_MAXDEPTH) 3774 return (0); 3775 3776 w = hdac_widget_get(devinfo, nid); 3777 if (w == NULL || w->enable == 0) 3778 return (0); 3779 3780 pw = hdac_widget_get(devinfo, pnid); 3781 strategy = devinfo->function.audio.parsing_strategy; 3782 3783 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3784 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3785 for (i = 0; i < w->nconns; i++) { 3786 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3787 w->nid, i, depth + 1); 3788 } 3789 w->ctlflags |= fl; 3790 return (fl); 3791 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3792 (w->pflags & HDA_DAC_PATH)) { 3793 i = 0; 3794 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3795 if (ctl->enable == 0 || ctl->widget == NULL) 3796 continue; 3797 /* XXX This should be compressed! */ 3798 if ((ctl->widget->nid == w->nid) || 3799 (ctl->widget->nid == pnid && ctl->index == index && 3800 (ctl->dir & HDA_CTL_IN)) || 3801 (ctl->widget->nid == pnid && pw != NULL && 3802 pw->type == 3803 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3804 (pw->nconns < 2 || pw->selconn == index || 3805 pw->selconn == -1) && 3806 (ctl->dir & HDA_CTL_OUT)) || 3807 (strategy == HDA_PARSE_DIRECT && 3808 ctl->widget->nid == w->nid)) { 3809 /*if (pw != NULL && pw->selconn == -1) 3810 pw->selconn = index; 3811 fl |= SOUND_MASK_VOLUME; 3812 fl |= SOUND_MASK_PCM; 3813 ctl->ossmask |= SOUND_MASK_VOLUME; 3814 ctl->ossmask |= SOUND_MASK_PCM; 3815 ctl->ossdev = SOUND_MIXER_PCM;*/ 3816 if (!(w->ctlflags & SOUND_MASK_PCM) || 3817 (pw != NULL && 3818 !(pw->ctlflags & SOUND_MASK_PCM))) { 3819 fl |= SOUND_MASK_VOLUME; 3820 fl |= SOUND_MASK_PCM; 3821 ctl->ossmask |= SOUND_MASK_VOLUME; 3822 ctl->ossmask |= SOUND_MASK_PCM; 3823 ctl->ossdev = SOUND_MIXER_PCM; 3824 w->ctlflags |= SOUND_MASK_VOLUME; 3825 w->ctlflags |= SOUND_MASK_PCM; 3826 if (pw != NULL) { 3827 if (pw->selconn == -1) 3828 pw->selconn = index; 3829 pw->ctlflags |= 3830 SOUND_MASK_VOLUME; 3831 pw->ctlflags |= 3832 SOUND_MASK_PCM; 3833 } 3834 } 3835 } 3836 } 3837 w->ctlflags |= fl; 3838 return (fl); 3839 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3840 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3841 (w->pflags & HDA_ADC_PATH)) { 3842 conndev = w->wclass.pin.config & 3843 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3844 i = 0; 3845 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3846 if (ctl->enable == 0 || ctl->widget == NULL) 3847 continue; 3848 /* XXX This should be compressed! */ 3849 if (((ctl->widget->nid == pnid && ctl->index == index && 3850 (ctl->dir & HDA_CTL_IN)) || 3851 (ctl->widget->nid == pnid && pw != NULL && 3852 pw->type == 3853 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3854 (pw->nconns < 2 || pw->selconn == index || 3855 pw->selconn == -1) && 3856 (ctl->dir & HDA_CTL_OUT)) || 3857 (strategy == HDA_PARSE_DIRECT && 3858 ctl->widget->nid == w->nid)) && 3859 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3860 if (pw != NULL && pw->selconn == -1) 3861 pw->selconn = index; 3862 ossdev = 0; 3863 switch (conndev) { 3864 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3865 ossdev = SOUND_MIXER_MIC; 3866 break; 3867 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3868 ossdev = SOUND_MIXER_LINE; 3869 break; 3870 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3871 ossdev = SOUND_MIXER_CD; 3872 break; 3873 default: 3874 ossdev = 3875 hdac_audio_ctl_ossmixer_getnextdev( 3876 devinfo); 3877 if (ossdev < 0) 3878 ossdev = 0; 3879 break; 3880 } 3881 if (strategy == HDA_PARSE_MIXER) { 3882 fl |= SOUND_MASK_VOLUME; 3883 ctl->ossmask |= SOUND_MASK_VOLUME; 3884 } 3885 fl |= 1 << ossdev; 3886 ctl->ossmask |= 1 << ossdev; 3887 ctl->ossdev = ossdev; 3888 } 3889 } 3890 w->ctlflags |= fl; 3891 return (fl); 3892 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3893 i = 0; 3894 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3895 if (ctl->enable == 0 || ctl->widget == NULL) 3896 continue; 3897 /* XXX This should be compressed! */ 3898 if (((ctl->widget->nid == pnid && ctl->index == index && 3899 (ctl->dir & HDA_CTL_IN)) || 3900 (ctl->widget->nid == pnid && pw != NULL && 3901 pw->type == 3902 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3903 (pw->nconns < 2 || pw->selconn == index || 3904 pw->selconn == -1) && 3905 (ctl->dir & HDA_CTL_OUT)) || 3906 (strategy == HDA_PARSE_DIRECT && 3907 ctl->widget->nid == w->nid)) && 3908 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3909 if (pw != NULL && pw->selconn == -1) 3910 pw->selconn = index; 3911 fl |= SOUND_MASK_VOLUME; 3912 fl |= SOUND_MASK_SPEAKER; 3913 ctl->ossmask |= SOUND_MASK_VOLUME; 3914 ctl->ossmask |= SOUND_MASK_SPEAKER; 3915 ctl->ossdev = SOUND_MIXER_SPEAKER; 3916 } 3917 } 3918 w->ctlflags |= fl; 3919 return (fl); 3920 } 3921 return (0); 3922 } 3923 3924 static uint32_t 3925 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3926 { 3927 struct hdac_widget *w, *cw; 3928 struct hdac_audio_ctl *ctl; 3929 uint32_t fl; 3930 int i; 3931 3932 if (depth > HDA_PARSE_MAXDEPTH) 3933 return (0); 3934 3935 w = hdac_widget_get(devinfo, nid); 3936 if (w == NULL || w->enable == 0) 3937 return (0); 3938 /*if (!(w->pflags & HDA_ADC_PATH)) 3939 return (0); 3940 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3941 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3942 return (0);*/ 3943 i = 0; 3944 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3945 if (ctl->enable == 0 || ctl->widget == NULL) 3946 continue; 3947 if (ctl->widget->nid == nid) { 3948 ctl->ossmask |= SOUND_MASK_RECLEV; 3949 w->ctlflags |= SOUND_MASK_RECLEV; 3950 return (SOUND_MASK_RECLEV); 3951 } 3952 } 3953 for (i = 0; i < w->nconns; i++) { 3954 cw = hdac_widget_get(devinfo, w->conns[i]); 3955 if (cw == NULL || cw->enable == 0) 3956 continue; 3957 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3958 continue; 3959 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3960 if (fl != 0) { 3961 cw->ctlflags |= fl; 3962 w->ctlflags |= fl; 3963 return (fl); 3964 } 3965 } 3966 return (0); 3967 } 3968 3969 static int 3970 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3971 { 3972 struct hdac_widget *w, *cw; 3973 int i, child = 0; 3974 3975 if (depth > HDA_PARSE_MAXDEPTH) 3976 return (0); 3977 3978 w = hdac_widget_get(devinfo, nid); 3979 if (w == NULL || w->enable == 0) 3980 return (0); 3981 /*if (!(w->pflags & HDA_ADC_PATH)) 3982 return (0); 3983 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3984 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3985 return (0);*/ 3986 /* XXX weak! */ 3987 for (i = 0; i < w->nconns; i++) { 3988 cw = hdac_widget_get(devinfo, w->conns[i]); 3989 if (cw == NULL) 3990 continue; 3991 if (++child > 1) { 3992 w->pflags |= HDA_ADC_RECSEL; 3993 return (1); 3994 } 3995 } 3996 for (i = 0; i < w->nconns; i++) { 3997 if (hdac_audio_ctl_recsel_build(devinfo, 3998 w->conns[i], depth + 1) != 0) 3999 return (1); 4000 } 4001 return (0); 4002 } 4003 4004 static int 4005 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4006 { 4007 struct hdac_widget *w, *cw; 4008 int i, j, conndev, found_dac = 0; 4009 int strategy; 4010 4011 strategy = devinfo->function.audio.parsing_strategy; 4012 4013 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4014 w = hdac_widget_get(devinfo, i); 4015 if (w == NULL || w->enable == 0) 4016 continue; 4017 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4018 continue; 4019 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4020 continue; 4021 conndev = w->wclass.pin.config & 4022 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4023 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4024 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4025 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4026 continue; 4027 for (j = 0; j < w->nconns; j++) { 4028 cw = hdac_widget_get(devinfo, w->conns[j]); 4029 if (cw == NULL || cw->enable == 0) 4030 continue; 4031 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4032 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4033 cw->type == 4034 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4035 continue; 4036 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4037 != 0) { 4038 if (w->selconn == -1) 4039 w->selconn = j; 4040 w->pflags |= HDA_DAC_PATH; 4041 found_dac++; 4042 } 4043 } 4044 } 4045 4046 return (found_dac); 4047 } 4048 4049 static void 4050 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4051 { 4052 struct hdac_widget *w; 4053 struct hdac_audio_ctl *ctl; 4054 int i, j, dacs, strategy; 4055 4056 /* Construct DAC path */ 4057 strategy = HDA_PARSE_MIXER; 4058 devinfo->function.audio.parsing_strategy = strategy; 4059 HDA_BOOTVERBOSE( 4060 device_printf(devinfo->codec->sc->dev, 4061 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4062 HDA_WIDGET_PARSER_REV); 4063 ); 4064 dacs = hdac_audio_build_tree_strategy(devinfo); 4065 if (dacs == 0) { 4066 HDA_BOOTVERBOSE( 4067 device_printf(devinfo->codec->sc->dev, 4068 "HDA_DEBUG: HWiP: 0 DAC path found! " 4069 "Retrying parser " 4070 "using HDA_PARSE_DIRECT strategy.\n"); 4071 ); 4072 strategy = HDA_PARSE_DIRECT; 4073 devinfo->function.audio.parsing_strategy = strategy; 4074 dacs = hdac_audio_build_tree_strategy(devinfo); 4075 } 4076 4077 HDA_BOOTVERBOSE( 4078 device_printf(devinfo->codec->sc->dev, 4079 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4080 "strategy.\n", 4081 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4082 ); 4083 4084 /* Construct ADC path */ 4085 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4086 w = hdac_widget_get(devinfo, i); 4087 if (w == NULL || w->enable == 0) 4088 continue; 4089 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4090 continue; 4091 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4092 } 4093 4094 /* Output mixers */ 4095 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4096 w = hdac_widget_get(devinfo, i); 4097 if (w == NULL || w->enable == 0) 4098 continue; 4099 if ((strategy == HDA_PARSE_MIXER && 4100 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4101 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4102 && (w->pflags & HDA_DAC_PATH)) || 4103 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4104 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4105 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4106 w->nid, devinfo->startnode - 1, 0, 0); 4107 } else if (w->type == 4108 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4109 j = 0; 4110 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4111 NULL) { 4112 if (ctl->enable == 0 || ctl->widget == NULL) 4113 continue; 4114 if (ctl->widget->nid != w->nid) 4115 continue; 4116 ctl->ossmask |= SOUND_MASK_VOLUME; 4117 ctl->ossmask |= SOUND_MASK_SPEAKER; 4118 ctl->ossdev = SOUND_MIXER_SPEAKER; 4119 w->ctlflags |= SOUND_MASK_VOLUME; 4120 w->ctlflags |= SOUND_MASK_SPEAKER; 4121 } 4122 } 4123 } 4124 4125 /* Input mixers (rec) */ 4126 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4127 w = hdac_widget_get(devinfo, i); 4128 if (w == NULL || w->enable == 0) 4129 continue; 4130 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4131 w->pflags & HDA_ADC_PATH)) 4132 continue; 4133 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4134 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4135 } 4136 } 4137 4138 #define HDA_COMMIT_CONN (1 << 0) 4139 #define HDA_COMMIT_CTRL (1 << 1) 4140 #define HDA_COMMIT_EAPD (1 << 2) 4141 #define HDA_COMMIT_GPIO (1 << 3) 4142 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4143 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4144 4145 static void 4146 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4147 { 4148 struct hdac_softc *sc = devinfo->codec->sc; 4149 struct hdac_widget *w; 4150 nid_t cad; 4151 int i; 4152 4153 if (!(cfl & HDA_COMMIT_ALL)) 4154 return; 4155 4156 cad = devinfo->codec->cad; 4157 4158 if (cfl & HDA_COMMIT_GPIO) { 4159 uint32_t gdata, gmask, gdir; 4160 int commitgpio = 0; 4161 4162 gdata = 0; 4163 gmask = 0; 4164 gdir = 0; 4165 4166 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4167 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4168 0x7e7, 0), cad); 4169 4170 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4171 commitgpio = 1; 4172 else { 4173 for (i = 0; i < HDA_GPIO_MAX; i++) { 4174 if (!(devinfo->function.audio.quirks & 4175 (1 << i))) 4176 continue; 4177 if (commitgpio == 0) { 4178 commitgpio = 1; 4179 gdata = hdac_command(sc, 4180 HDA_CMD_GET_GPIO_DATA(cad, 4181 devinfo->nid), cad); 4182 gmask = hdac_command(sc, 4183 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4184 devinfo->nid), cad); 4185 gdir = hdac_command(sc, 4186 HDA_CMD_GET_GPIO_DIRECTION(cad, 4187 devinfo->nid), cad); 4188 HDA_BOOTVERBOSE( 4189 device_printf(sc->dev, 4190 "GPIO init: data=0x%08x " 4191 "mask=0x%08x dir=0x%08x\n", 4192 gdata, gmask, gdir); 4193 ); 4194 } 4195 gdata |= 1 << i; 4196 gmask |= 1 << i; 4197 gdir |= 1 << i; 4198 } 4199 } 4200 4201 if (commitgpio != 0) { 4202 HDA_BOOTVERBOSE( 4203 device_printf(sc->dev, 4204 "GPIO commit: data=0x%08x mask=0x%08x " 4205 "dir=0x%08x\n", 4206 gdata, gmask, gdir); 4207 ); 4208 hdac_command(sc, 4209 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4210 gmask), cad); 4211 hdac_command(sc, 4212 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4213 gdir), cad); 4214 hdac_command(sc, 4215 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4216 gdata), cad); 4217 } 4218 } 4219 4220 for (i = 0; i < devinfo->nodecnt; i++) { 4221 w = &devinfo->widget[i]; 4222 if (w == NULL || w->enable == 0) 4223 continue; 4224 if (cfl & HDA_COMMIT_CONN) { 4225 if (w->selconn == -1) 4226 w->selconn = 0; 4227 if (w->nconns > 0) 4228 hdac_widget_connection_select(w, w->selconn); 4229 } 4230 if ((cfl & HDA_COMMIT_CTRL) && 4231 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4232 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4233 (HDA_DAC_PATH | HDA_ADC_PATH)) 4234 device_printf(sc->dev, "WARNING: node %d " 4235 "participate both for DAC/ADC!\n", w->nid); 4236 if (w->pflags & HDA_DAC_PATH) { 4237 w->wclass.pin.ctrl &= 4238 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4239 if ((w->wclass.pin.config & 4240 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4241 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4242 w->wclass.pin.ctrl &= 4243 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4244 } else if (w->pflags & HDA_ADC_PATH) { 4245 w->wclass.pin.ctrl &= 4246 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4247 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4248 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4249 uint32_t pincap = w->wclass.pin.cap; 4250 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4251 w->wclass.pin.ctrl |= 4252 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4253 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4254 ); 4255 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4256 w->wclass.pin.ctrl |= 4257 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4258 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4259 ); 4260 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4261 w->wclass.pin.ctrl |= 4262 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4263 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4264 ); 4265 } 4266 } else 4267 w->wclass.pin.ctrl &= ~( 4268 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4269 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4270 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4271 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4272 hdac_command(sc, 4273 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4274 w->wclass.pin.ctrl), cad); 4275 } 4276 if ((cfl & HDA_COMMIT_EAPD) && 4277 w->param.eapdbtl != HDAC_INVALID) { 4278 uint32_t val; 4279 4280 val = w->param.eapdbtl; 4281 if (devinfo->function.audio.quirks & 4282 HDA_QUIRK_EAPDINV) 4283 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4284 hdac_command(sc, 4285 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4286 val), cad); 4287 4288 } 4289 DELAY(1000); 4290 } 4291 } 4292 4293 static void 4294 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4295 { 4296 struct hdac_softc *sc = devinfo->codec->sc; 4297 struct hdac_audio_ctl *ctl; 4298 int i; 4299 4300 devinfo->function.audio.mvol = 100 | (100 << 8); 4301 i = 0; 4302 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4303 if (ctl->enable == 0 || ctl->widget == NULL) { 4304 HDA_BOOTVERBOSE( 4305 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4306 i, (ctl->widget != NULL) ? 4307 ctl->widget->nid : -1); 4308 if (ctl->childwidget != NULL) 4309 printf(" childnid=%d", 4310 ctl->childwidget->nid); 4311 if (ctl->widget == NULL) 4312 printf(" NULL WIDGET!"); 4313 printf(" DISABLED\n"); 4314 ); 4315 continue; 4316 } 4317 HDA_BOOTVERBOSE( 4318 if (ctl->ossmask == 0) { 4319 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4320 i, ctl->widget->nid); 4321 if (ctl->childwidget != NULL) 4322 printf(" childnid=%d", 4323 ctl->childwidget->nid); 4324 printf(" Bind to NONE\n"); 4325 } 4326 ); 4327 if (ctl->step > 0) { 4328 ctl->ossval = (ctl->left * 100) / ctl->step; 4329 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4330 } else 4331 ctl->ossval = 0; 4332 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4333 ctl->left, ctl->right); 4334 } 4335 } 4336 4337 static int 4338 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4339 { 4340 struct hdac_chan *ch; 4341 struct hdac_widget *w; 4342 uint32_t cap, fmtcap, pcmcap, path; 4343 int i, type, ret, max; 4344 4345 if (dir == PCMDIR_PLAY) { 4346 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4347 ch = &devinfo->codec->sc->play; 4348 path = HDA_DAC_PATH; 4349 } else { 4350 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4351 ch = &devinfo->codec->sc->rec; 4352 path = HDA_ADC_PATH; 4353 } 4354 4355 ch->caps = hdac_caps; 4356 ch->caps.fmtlist = ch->fmtlist; 4357 ch->bit16 = 1; 4358 ch->bit32 = 0; 4359 ch->pcmrates[0] = 48000; 4360 ch->pcmrates[1] = 0; 4361 4362 ret = 0; 4363 fmtcap = devinfo->function.audio.supp_stream_formats; 4364 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4365 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4366 4367 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4368 w = hdac_widget_get(devinfo, i); 4369 if (w == NULL || w->enable == 0 || w->type != type || 4370 !(w->pflags & path)) 4371 continue; 4372 cap = w->param.widget_cap; 4373 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4374 continue;*/ 4375 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4376 continue; 4377 cap = w->param.supp_stream_formats; 4378 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4379 } 4380 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4381 }*/ 4382 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4383 continue; 4384 if (ret == 0) { 4385 fmtcap = w->param.supp_stream_formats; 4386 pcmcap = w->param.supp_pcm_size_rate; 4387 } else { 4388 fmtcap &= w->param.supp_stream_formats; 4389 pcmcap &= w->param.supp_pcm_size_rate; 4390 } 4391 ch->io[ret++] = i; 4392 } 4393 ch->io[ret] = -1; 4394 4395 ch->supp_stream_formats = fmtcap; 4396 ch->supp_pcm_size_rate = pcmcap; 4397 4398 /* 4399 * 8bit = 0 4400 * 16bit = 1 4401 * 20bit = 2 4402 * 24bit = 3 4403 * 32bit = 4 4404 */ 4405 if (ret > 0) { 4406 cap = pcmcap; 4407 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4408 ch->bit16 = 1; 4409 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4410 ch->bit16 = 0; 4411 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4412 ch->bit32 = 4; 4413 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4414 ch->bit32 = 3; 4415 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4416 ch->bit32 = 2; 4417 i = 0; 4418 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4419 ch->fmtlist[i++] = AFMT_S16_LE; 4420 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4421 if (ch->bit32 > 0) { 4422 if (!(devinfo->function.audio.quirks & 4423 HDA_QUIRK_FORCESTEREO)) 4424 ch->fmtlist[i++] = AFMT_S32_LE; 4425 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4426 } 4427 ch->fmtlist[i] = 0; 4428 i = 0; 4429 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4430 ch->pcmrates[i++] = 8000; 4431 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4432 ch->pcmrates[i++] = 11025; 4433 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4434 ch->pcmrates[i++] = 16000; 4435 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4436 ch->pcmrates[i++] = 22050; 4437 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4438 ch->pcmrates[i++] = 32000; 4439 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4440 ch->pcmrates[i++] = 44100; 4441 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4442 ch->pcmrates[i++] = 48000; 4443 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4444 ch->pcmrates[i++] = 88200; 4445 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4446 ch->pcmrates[i++] = 96000; 4447 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4448 ch->pcmrates[i++] = 176400; 4449 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4450 ch->pcmrates[i++] = 192000; 4451 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4452 ch->pcmrates[i] = 0; 4453 if (i > 0) { 4454 ch->caps.minspeed = ch->pcmrates[0]; 4455 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4456 } 4457 } 4458 4459 return (ret); 4460 } 4461 4462 static void 4463 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4464 { 4465 struct hdac_audio_ctl *ctl; 4466 struct hdac_softc *sc = devinfo->codec->sc; 4467 int i; 4468 uint32_t fl = 0; 4469 4470 4471 if (flag == 0) { 4472 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4473 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4474 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4475 } 4476 4477 i = 0; 4478 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4479 if (ctl->enable == 0 || ctl->widget == NULL || 4480 ctl->widget->enable == 0) 4481 continue; 4482 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4483 (flag != 0 && (ctl->ossmask & flag))) { 4484 if (banner != NULL) { 4485 device_printf(sc->dev, "\n"); 4486 device_printf(sc->dev, "%s\n", banner); 4487 } 4488 goto hdac_ctl_dump_it_all; 4489 } 4490 } 4491 4492 return; 4493 4494 hdac_ctl_dump_it_all: 4495 i = 0; 4496 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4497 if (ctl->enable == 0 || ctl->widget == NULL || 4498 ctl->widget->enable == 0) 4499 continue; 4500 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4501 (flag != 0 && (ctl->ossmask & flag)))) 4502 continue; 4503 if (flag == 0) { 4504 device_printf(sc->dev, "\n"); 4505 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4506 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4507 } 4508 device_printf(sc->dev, " |\n"); 4509 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4510 ctl->widget->nid, ctl->index); 4511 if (ctl->childwidget != NULL) 4512 printf("(nid: %2d) ", ctl->childwidget->nid); 4513 else 4514 printf(" "); 4515 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4516 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4517 ctl->ossmask); 4518 } 4519 } 4520 4521 static void 4522 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4523 { 4524 uint32_t cap; 4525 4526 cap = fcap; 4527 if (cap != 0) { 4528 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4529 device_printf(sc->dev, " Format:"); 4530 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4531 printf(" AC3"); 4532 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4533 printf(" FLOAT32"); 4534 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4535 printf(" PCM"); 4536 printf("\n"); 4537 } 4538 cap = pcmcap; 4539 if (cap != 0) { 4540 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4541 device_printf(sc->dev, " PCM size:"); 4542 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4543 printf(" 8"); 4544 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4545 printf(" 16"); 4546 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4547 printf(" 20"); 4548 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4549 printf(" 24"); 4550 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4551 printf(" 32"); 4552 printf("\n"); 4553 device_printf(sc->dev, " PCM rate:"); 4554 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4555 printf(" 8"); 4556 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4557 printf(" 11"); 4558 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4559 printf(" 16"); 4560 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4561 printf(" 22"); 4562 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4563 printf(" 32"); 4564 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4565 printf(" 44"); 4566 printf(" 48"); 4567 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4568 printf(" 88"); 4569 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4570 printf(" 96"); 4571 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4572 printf(" 176"); 4573 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4574 printf(" 192"); 4575 printf("\n"); 4576 } 4577 } 4578 4579 static void 4580 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4581 { 4582 uint32_t pincap, wcap; 4583 4584 pincap = w->wclass.pin.cap; 4585 wcap = w->param.widget_cap; 4586 4587 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4588 device_printf(sc->dev, " "); 4589 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4590 printf(" ISC"); 4591 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4592 printf(" TRQD"); 4593 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4594 printf(" PDC"); 4595 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4596 printf(" HP"); 4597 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4598 printf(" OUT"); 4599 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4600 printf(" IN"); 4601 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4602 printf(" BAL"); 4603 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4604 printf(" VREF["); 4605 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4606 printf(" 50"); 4607 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4608 printf(" 80"); 4609 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4610 printf(" 100"); 4611 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4612 printf(" GROUND"); 4613 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4614 printf(" HIZ"); 4615 printf(" ]"); 4616 } 4617 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4618 printf(" EAPD"); 4619 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4620 printf(" : UNSOL"); 4621 printf("\n"); 4622 device_printf(sc->dev, " Pin config: 0x%08x\n", 4623 w->wclass.pin.config); 4624 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4625 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4626 printf(" HP"); 4627 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4628 printf(" IN"); 4629 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4630 printf(" OUT"); 4631 printf("\n"); 4632 } 4633 4634 static void 4635 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4636 { 4637 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4638 device_printf(sc->dev, " " 4639 "mute=%d step=%d size=%d offset=%d\n", 4640 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4641 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4642 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4643 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4644 } 4645 4646 static void 4647 hdac_dump_nodes(struct hdac_devinfo *devinfo) 4648 { 4649 struct hdac_softc *sc = devinfo->codec->sc; 4650 struct hdac_widget *w, *cw; 4651 int i, j; 4652 4653 device_printf(sc->dev, "\n"); 4654 device_printf(sc->dev, "Default Parameter\n"); 4655 device_printf(sc->dev, "-----------------\n"); 4656 hdac_dump_audio_formats(sc, 4657 devinfo->function.audio.supp_stream_formats, 4658 devinfo->function.audio.supp_pcm_size_rate); 4659 device_printf(sc->dev, " IN amp: 0x%08x\n", 4660 devinfo->function.audio.inamp_cap); 4661 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4662 devinfo->function.audio.outamp_cap); 4663 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4664 w = hdac_widget_get(devinfo, i); 4665 if (w == NULL) { 4666 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4667 continue; 4668 } 4669 device_printf(sc->dev, "\n"); 4670 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4671 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4672 "DIGITAL" : "ANALOG", 4673 (w->enable == 0) ? " [DISABLED]" : ""); 4674 device_printf(sc->dev, " name: %s\n", w->name); 4675 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4676 w->param.widget_cap); 4677 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4678 w->pflags); 4679 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4680 w->ctlflags); 4681 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4682 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4683 hdac_dump_audio_formats(sc, 4684 w->param.supp_stream_formats, 4685 w->param.supp_pcm_size_rate); 4686 } else if (w->type == 4687 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4688 hdac_dump_pin(sc, w); 4689 if (w->param.eapdbtl != HDAC_INVALID) 4690 device_printf(sc->dev, " EAPD: 0x%08x\n", 4691 w->param.eapdbtl); 4692 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4693 w->param.outamp_cap != 0) 4694 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4695 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4696 w->param.inamp_cap != 0) 4697 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4698 device_printf(sc->dev, " connections: %d\n", w->nconns); 4699 for (j = 0; j < w->nconns; j++) { 4700 cw = hdac_widget_get(devinfo, w->conns[j]); 4701 device_printf(sc->dev, " |\n"); 4702 device_printf(sc->dev, " + <- nid=%d [%s]", 4703 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4704 if (cw == NULL) 4705 printf(" [UNKNOWN]"); 4706 else if (cw->enable == 0) 4707 printf(" [DISABLED]"); 4708 if (w->nconns > 1 && w->selconn == j && w->type != 4709 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4710 printf(" (selected)"); 4711 printf("\n"); 4712 } 4713 } 4714 4715 } 4716 4717 static int 4718 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4719 { 4720 struct hdac_widget *w, *cw; 4721 struct hdac_softc *sc = devinfo->codec->sc; 4722 int i; 4723 4724 if (depth > HDA_PARSE_MAXDEPTH) 4725 return (0); 4726 4727 w = hdac_widget_get(devinfo, nid); 4728 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4729 return (0); 4730 4731 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4732 device_printf(sc->dev, "\n"); 4733 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4734 device_printf(sc->dev, " ^\n"); 4735 device_printf(sc->dev, " |\n"); 4736 device_printf(sc->dev, " +-----<------+\n"); 4737 } else { 4738 device_printf(sc->dev, " ^\n"); 4739 device_printf(sc->dev, " |\n"); 4740 device_printf(sc->dev, " "); 4741 printf(" nid=%d [%s]\n", w->nid, w->name); 4742 } 4743 4744 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4745 return (1); 4746 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4747 for (i = 0; i < w->nconns; i++) { 4748 cw = hdac_widget_get(devinfo, w->conns[i]); 4749 if (cw == NULL || cw->enable == 0 || cw->type == 4750 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4751 continue; 4752 if (hdac_dump_dac_internal(devinfo, cw->nid, 4753 depth + 1) != 0) 4754 return (1); 4755 } 4756 } else if ((w->type == 4757 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4758 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4759 w->selconn > -1 && w->selconn < w->nconns) { 4760 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4761 depth + 1) != 0) 4762 return (1); 4763 } 4764 4765 return (0); 4766 } 4767 4768 static void 4769 hdac_dump_dac(struct hdac_devinfo *devinfo) 4770 { 4771 struct hdac_widget *w; 4772 struct hdac_softc *sc = devinfo->codec->sc; 4773 int i, printed = 0; 4774 4775 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4776 w = hdac_widget_get(devinfo, i); 4777 if (w == NULL || w->enable == 0) 4778 continue; 4779 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4780 !(w->pflags & HDA_DAC_PATH)) 4781 continue; 4782 if (printed == 0) { 4783 printed = 1; 4784 device_printf(sc->dev, "\n"); 4785 device_printf(sc->dev, "Playback path:\n"); 4786 } 4787 hdac_dump_dac_internal(devinfo, w->nid, 0); 4788 } 4789 } 4790 4791 static void 4792 hdac_dump_adc(struct hdac_devinfo *devinfo) 4793 { 4794 struct hdac_widget *w, *cw; 4795 struct hdac_softc *sc = devinfo->codec->sc; 4796 int i, j; 4797 int printed = 0; 4798 char ossdevs[256]; 4799 4800 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4801 w = hdac_widget_get(devinfo, i); 4802 if (w == NULL || w->enable == 0) 4803 continue; 4804 if (!(w->pflags & HDA_ADC_RECSEL)) 4805 continue; 4806 if (printed == 0) { 4807 printed = 1; 4808 device_printf(sc->dev, "\n"); 4809 device_printf(sc->dev, "Recording sources:\n"); 4810 } 4811 device_printf(sc->dev, "\n"); 4812 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4813 for (j = 0; j < w->nconns; j++) { 4814 cw = hdac_widget_get(devinfo, w->conns[j]); 4815 if (cw == NULL || cw->enable == 0) 4816 continue; 4817 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4818 ossdevs, sizeof(ossdevs)); 4819 device_printf(sc->dev, " |\n"); 4820 device_printf(sc->dev, " + <- nid=%d [%s]", 4821 cw->nid, cw->name); 4822 if (strlen(ossdevs) > 0) { 4823 printf(" [recsrc: %s]", ossdevs); 4824 } 4825 printf("\n"); 4826 } 4827 } 4828 } 4829 4830 static void 4831 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4832 { 4833 nid_t *nids; 4834 4835 if (pcnt > 0) { 4836 device_printf(sc->dev, "\n"); 4837 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4838 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4839 sc->play.supp_pcm_size_rate); 4840 device_printf(sc->dev, " DAC:"); 4841 for (nids = sc->play.io; *nids != -1; nids++) 4842 printf(" %d", *nids); 4843 printf("\n"); 4844 } 4845 4846 if (rcnt > 0) { 4847 device_printf(sc->dev, "\n"); 4848 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4849 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4850 sc->rec.supp_pcm_size_rate); 4851 device_printf(sc->dev, " ADC:"); 4852 for (nids = sc->rec.io; *nids != -1; nids++) 4853 printf(" %d", *nids); 4854 printf("\n"); 4855 } 4856 } 4857 4858 static void 4859 hdac_release_resources(struct hdac_softc *sc) 4860 { 4861 struct hdac_devinfo *devinfo = NULL; 4862 device_t *devlist = NULL; 4863 int i, devcount; 4864 4865 if (sc == NULL) 4866 return; 4867 4868 hdac_lock(sc); 4869 if (sc->polling != 0) 4870 callout_stop(&sc->poll_hdac); 4871 hdac_reset(sc); 4872 hdac_unlock(sc); 4873 snd_mtxfree(sc->lock); 4874 4875 device_get_children(sc->dev, &devlist, &devcount); 4876 for (i = 0; devlist != NULL && i < devcount; i++) { 4877 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4878 if (devinfo == NULL) 4879 continue; 4880 if (devinfo->widget != NULL) 4881 free(devinfo->widget, M_HDAC); 4882 if (devinfo->node_type == 4883 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4884 devinfo->function.audio.ctl != NULL) 4885 free(devinfo->function.audio.ctl, M_HDAC); 4886 free(devinfo, M_HDAC); 4887 device_delete_child(sc->dev, devlist[i]); 4888 } 4889 if (devlist != NULL) 4890 free(devlist, M_TEMP); 4891 4892 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4893 if (sc->codecs[i] != NULL) 4894 free(sc->codecs[i], M_HDAC); 4895 sc->codecs[i] = NULL; 4896 } 4897 4898 hdac_dma_free(&sc->rirb_dma); 4899 hdac_dma_free(&sc->corb_dma); 4900 if (sc->play.blkcnt > 0) 4901 hdac_dma_free(&sc->play.bdl_dma); 4902 if (sc->rec.blkcnt > 0) 4903 hdac_dma_free(&sc->rec.bdl_dma); 4904 hdac_irq_free(sc); 4905 hdac_mem_free(sc); 4906 free(sc, M_DEVBUF); 4907 4908 } 4909 4910 /* This function surely going to make its way into upper level someday. */ 4911 static void 4912 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4913 { 4914 const char *res = NULL; 4915 int i = 0, j, k, len, inv; 4916 4917 if (on != NULL) 4918 *on = 0; 4919 if (off != NULL) 4920 *off = 0; 4921 if (sc == NULL) 4922 return; 4923 if (resource_string_value(device_get_name(sc->dev), 4924 device_get_unit(sc->dev), "config", &res) != 0) 4925 return; 4926 if (!(res != NULL && strlen(res) > 0)) 4927 return; 4928 HDA_BOOTVERBOSE( 4929 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4930 ); 4931 for (;;) { 4932 while (res[i] != '\0' && 4933 (res[i] == ',' || isspace(res[i]) != 0)) 4934 i++; 4935 if (res[i] == '\0') { 4936 HDA_BOOTVERBOSE( 4937 printf("\n"); 4938 ); 4939 return; 4940 } 4941 j = i; 4942 while (res[j] != '\0' && 4943 !(res[j] == ',' || isspace(res[j]) != 0)) 4944 j++; 4945 len = j - i; 4946 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4947 inv = 2; 4948 else 4949 inv = 0; 4950 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4951 if (strncmp(res + i + inv, 4952 hdac_quirks_tab[k].key, len - inv) != 0) 4953 continue; 4954 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4955 break; 4956 HDA_BOOTVERBOSE( 4957 printf(" %s%s", (inv != 0) ? "no" : "", 4958 hdac_quirks_tab[k].key); 4959 ); 4960 if (inv == 0 && on != NULL) 4961 *on |= hdac_quirks_tab[k].value; 4962 else if (inv != 0 && off != NULL) 4963 *off |= hdac_quirks_tab[k].value; 4964 break; 4965 } 4966 i = j; 4967 } 4968 } 4969 4970 #ifdef SND_DYNSYSCTL 4971 static int 4972 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 4973 { 4974 struct hdac_softc *sc; 4975 struct hdac_devinfo *devinfo; 4976 device_t dev; 4977 uint32_t ctl; 4978 int err, val; 4979 4980 dev = oidp->oid_arg1; 4981 devinfo = pcm_getdevinfo(dev); 4982 if (devinfo == NULL || devinfo->codec == NULL || 4983 devinfo->codec->sc == NULL) 4984 return (EINVAL); 4985 sc = devinfo->codec->sc; 4986 hdac_lock(sc); 4987 val = sc->polling; 4988 hdac_unlock(sc); 4989 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 4990 4991 if (err || req->newptr == NULL) 4992 return (err); 4993 if (val < 0 || val > 1) 4994 return (EINVAL); 4995 4996 hdac_lock(sc); 4997 if (val != sc->polling) { 4998 if (hda_chan_active(sc) != 0) 4999 err = EBUSY; 5000 else if (val == 0) { 5001 callout_stop(&sc->poll_hdac); 5002 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5003 sc->rirb_size / 2); 5004 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5005 ctl |= HDAC_RIRBCTL_RINTCTL; 5006 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5007 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5008 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5009 sc->polling = 0; 5010 DELAY(1000); 5011 } else { 5012 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5013 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5014 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5015 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5016 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5017 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5018 sc); 5019 sc->polling = 1; 5020 DELAY(1000); 5021 } 5022 } 5023 hdac_unlock(sc); 5024 5025 return (err); 5026 } 5027 #endif 5028 5029 static void 5030 hdac_attach2(void *arg) 5031 { 5032 struct hdac_softc *sc; 5033 struct hdac_widget *w; 5034 struct hdac_audio_ctl *ctl; 5035 uint32_t quirks_on, quirks_off; 5036 int pcnt, rcnt; 5037 int i; 5038 char status[SND_STATUSLEN]; 5039 device_t *devlist = NULL; 5040 int devcount; 5041 struct hdac_devinfo *devinfo = NULL; 5042 5043 sc = (struct hdac_softc *)arg; 5044 5045 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5046 5047 HDA_BOOTVERBOSE( 5048 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5049 quirks_on, quirks_off); 5050 ); 5051 5052 hdac_lock(sc); 5053 5054 /* Remove ourselves from the config hooks */ 5055 if (sc->intrhook.ich_func != NULL) { 5056 config_intrhook_disestablish(&sc->intrhook); 5057 sc->intrhook.ich_func = NULL; 5058 } 5059 5060 /* Start the corb and rirb engines */ 5061 HDA_BOOTVERBOSE( 5062 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5063 ); 5064 hdac_corb_start(sc); 5065 HDA_BOOTVERBOSE( 5066 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5067 ); 5068 hdac_rirb_start(sc); 5069 5070 HDA_BOOTVERBOSE( 5071 device_printf(sc->dev, 5072 "HDA_DEBUG: Enabling controller interrupt...\n"); 5073 ); 5074 if (sc->polling == 0) 5075 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5076 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5077 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5078 HDAC_GCTL_UNSOL); 5079 5080 DELAY(1000); 5081 5082 HDA_BOOTVERBOSE( 5083 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5084 ); 5085 hdac_scan_codecs(sc); 5086 5087 device_get_children(sc->dev, &devlist, &devcount); 5088 for (i = 0; devlist != NULL && i < devcount; i++) { 5089 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5090 if (devinfo != NULL && devinfo->node_type == 5091 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5092 break; 5093 } else 5094 devinfo = NULL; 5095 } 5096 if (devlist != NULL) 5097 free(devlist, M_TEMP); 5098 5099 if (devinfo == NULL) { 5100 hdac_unlock(sc); 5101 device_printf(sc->dev, "Audio Function Group not found!\n"); 5102 hdac_release_resources(sc); 5103 return; 5104 } 5105 5106 HDA_BOOTVERBOSE( 5107 device_printf(sc->dev, 5108 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5109 devinfo->nid, devinfo->codec->cad); 5110 ); 5111 hdac_audio_parse(devinfo); 5112 HDA_BOOTVERBOSE( 5113 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5114 ); 5115 hdac_audio_ctl_parse(devinfo); 5116 HDA_BOOTVERBOSE( 5117 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5118 ); 5119 hdac_vendor_patch_parse(devinfo); 5120 if (quirks_on != 0) 5121 devinfo->function.audio.quirks |= quirks_on; 5122 if (quirks_off != 0) 5123 devinfo->function.audio.quirks &= ~quirks_off; 5124 5125 /* XXX Disable all DIGITAL path. */ 5126 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5127 w = hdac_widget_get(devinfo, i); 5128 if (w == NULL) 5129 continue; 5130 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5131 w->enable = 0; 5132 continue; 5133 } 5134 /* XXX Disable useless pin ? */ 5135 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5136 (w->wclass.pin.config & 5137 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5138 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5139 w->enable = 0; 5140 } 5141 i = 0; 5142 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5143 if (ctl->widget == NULL) 5144 continue; 5145 w = ctl->widget; 5146 if (w->enable == 0) 5147 ctl->enable = 0; 5148 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5149 ctl->enable = 0; 5150 w = ctl->childwidget; 5151 if (w == NULL) 5152 continue; 5153 if (w->enable == 0 || 5154 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5155 ctl->enable = 0; 5156 } 5157 5158 HDA_BOOTVERBOSE( 5159 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5160 ); 5161 hdac_audio_build_tree(devinfo); 5162 5163 HDA_BOOTVERBOSE( 5164 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5165 ); 5166 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5167 HDA_BOOTVERBOSE( 5168 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5169 ); 5170 hdac_audio_ctl_commit(devinfo); 5171 5172 HDA_BOOTVERBOSE( 5173 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5174 ); 5175 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5176 HDA_BOOTVERBOSE( 5177 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5178 ); 5179 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5180 5181 hdac_unlock(sc); 5182 HDA_BOOTVERBOSE( 5183 device_printf(sc->dev, 5184 "HDA_DEBUG: OSS mixer initialization...\n"); 5185 ); 5186 5187 /* 5188 * There is no point of return after this. If the driver failed, 5189 * so be it. Let the detach procedure do all the cleanup. 5190 */ 5191 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5192 device_printf(sc->dev, "Can't register mixer\n"); 5193 5194 if (pcnt > 0) 5195 pcnt = 1; 5196 if (rcnt > 0) 5197 rcnt = 1; 5198 5199 HDA_BOOTVERBOSE( 5200 device_printf(sc->dev, 5201 "HDA_DEBUG: Registering PCM channels...\n"); 5202 ); 5203 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5204 device_printf(sc->dev, "Can't register PCM\n"); 5205 5206 sc->registered++; 5207 5208 for (i = 0; i < pcnt; i++) 5209 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5210 for (i = 0; i < rcnt; i++) 5211 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5212 5213 #ifdef SND_DYNSYSCTL 5214 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5215 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5216 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5217 sysctl_hdac_polling, "I", "Enable polling mode"); 5218 #endif 5219 5220 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5221 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5222 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5223 pcm_setstatus(sc->dev, status); 5224 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5225 HDA_BOOTVERBOSE( 5226 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5227 hdac_codec_id(devinfo)); 5228 ); 5229 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5230 HDA_DRV_TEST_REV); 5231 5232 HDA_BOOTVERBOSE( 5233 if (devinfo->function.audio.quirks != 0) { 5234 device_printf(sc->dev, "\n"); 5235 device_printf(sc->dev, "HDA config/quirks:"); 5236 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5237 if (devinfo->function.audio.quirks & 5238 hdac_quirks_tab[i].value) 5239 printf(" %s", hdac_quirks_tab[i].key); 5240 } 5241 printf("\n"); 5242 } 5243 device_printf(sc->dev, "\n"); 5244 device_printf(sc->dev, "+-------------------+\n"); 5245 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5246 device_printf(sc->dev, "+-------------------+\n"); 5247 hdac_dump_nodes(devinfo); 5248 device_printf(sc->dev, "\n"); 5249 device_printf(sc->dev, "+------------------------+\n"); 5250 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5251 device_printf(sc->dev, "+------------------------+\n"); 5252 device_printf(sc->dev, "\n"); 5253 i = 0; 5254 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5255 device_printf(sc->dev, "%3d: nid=%d", i, 5256 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5257 if (ctl->childwidget != NULL) 5258 printf(" cnid=%d", ctl->childwidget->nid); 5259 printf(" dir=0x%x index=%d " 5260 "ossmask=0x%08x ossdev=%d%s\n", 5261 ctl->dir, ctl->index, 5262 ctl->ossmask, ctl->ossdev, 5263 (ctl->enable == 0) ? " [DISABLED]" : ""); 5264 } 5265 device_printf(sc->dev, "\n"); 5266 device_printf(sc->dev, "+-----------------------------------+\n"); 5267 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5268 device_printf(sc->dev, "+-----------------------------------+\n"); 5269 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5270 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5271 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5272 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5273 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5274 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5275 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5276 hdac_dump_ctls(devinfo, NULL, 0); 5277 hdac_dump_dac(devinfo); 5278 hdac_dump_adc(devinfo); 5279 device_printf(sc->dev, "\n"); 5280 device_printf(sc->dev, "+--------------------------------------+\n"); 5281 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5282 device_printf(sc->dev, "+--------------------------------------+\n"); 5283 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5284 ); 5285 5286 if (sc->polling != 0) { 5287 hdac_lock(sc); 5288 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5289 hdac_unlock(sc); 5290 } 5291 } 5292 5293 /**************************************************************************** 5294 * int hdac_detach(device_t) 5295 * 5296 * Detach and free up resources utilized by the hdac device. 5297 ****************************************************************************/ 5298 static int 5299 hdac_detach(device_t dev) 5300 { 5301 struct hdac_softc *sc = NULL; 5302 struct hdac_devinfo *devinfo = NULL; 5303 int err; 5304 5305 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5306 if (devinfo != NULL && devinfo->codec != NULL) 5307 sc = devinfo->codec->sc; 5308 if (sc == NULL) 5309 return (0); 5310 5311 if (sc->registered > 0) { 5312 err = pcm_unregister(dev); 5313 if (err != 0) 5314 return (err); 5315 } 5316 5317 hdac_release_resources(sc); 5318 5319 return (0); 5320 } 5321 5322 static device_method_t hdac_methods[] = { 5323 /* device interface */ 5324 DEVMETHOD(device_probe, hdac_probe), 5325 DEVMETHOD(device_attach, hdac_attach), 5326 DEVMETHOD(device_detach, hdac_detach), 5327 { 0, 0 } 5328 }; 5329 5330 static driver_t hdac_driver = { 5331 "pcm", 5332 hdac_methods, 5333 PCM_SOFTC_SIZE, 5334 }; 5335 5336 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5337 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5338 MODULE_VERSION(snd_hda, 1); 5339