1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _HDA_REG_H_ 30 #define _HDA_REG_H_ 31 32 /**************************************************************************** 33 * HDA Device Verbs 34 ****************************************************************************/ 35 36 /* HDA Command */ 37 #define HDA_CMD_VERB_MASK 0x000fffff 38 #define HDA_CMD_VERB_SHIFT 0 39 #define HDA_CMD_NID_MASK 0x0ff00000 40 #define HDA_CMD_NID_SHIFT 20 41 #define HDA_CMD_CAD_MASK 0xf0000000 42 #define HDA_CMD_CAD_SHIFT 28 43 44 #define HDA_CMD_VERB_4BIT_SHIFT 16 45 #define HDA_CMD_VERB_12BIT_SHIFT 8 46 47 #define HDA_CMD_VERB_4BIT(verb, payload) \ 48 (((verb) << HDA_CMD_VERB_4BIT_SHIFT) | (payload)) 49 #define HDA_CMD_4BIT(cad, nid, verb, payload) \ 50 (((cad) << HDA_CMD_CAD_SHIFT) | \ 51 ((nid) << HDA_CMD_NID_SHIFT) | \ 52 (HDA_CMD_VERB_4BIT((verb), (payload)))) 53 54 #define HDA_CMD_VERB_12BIT(verb, payload) \ 55 (((verb) << HDA_CMD_VERB_12BIT_SHIFT) | (payload)) 56 #define HDA_CMD_12BIT(cad, nid, verb, payload) \ 57 (((cad) << HDA_CMD_CAD_SHIFT) | \ 58 ((nid) << HDA_CMD_NID_SHIFT) | \ 59 (HDA_CMD_VERB_12BIT((verb), (payload)))) 60 61 /* Get Parameter */ 62 #define HDA_CMD_VERB_GET_PARAMETER 0xf00 63 64 #define HDA_CMD_GET_PARAMETER(cad, nid, payload) \ 65 (HDA_CMD_12BIT((cad), (nid), \ 66 HDA_CMD_VERB_GET_PARAMETER, (payload))) 67 68 /* Connection Select Control */ 69 #define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01 70 #define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701 71 72 #define HDA_CMD_GET_CONN_SELECT_CONTROL(cad, nid) \ 73 (HDA_CMD_12BIT((cad), (nid), \ 74 HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0)) 75 #define HDA_CMD_SET_CONNECTION_SELECT_CONTROL(cad, nid, payload) \ 76 (HDA_CMD_12BIT((cad), (nid), \ 77 HDA_CMD_VERB_SET_CONN_SELECT_CONTROL, (payload))) 78 79 /* Connection List Entry */ 80 #define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02 81 82 #define HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, payload) \ 83 (HDA_CMD_12BIT((cad), (nid), \ 84 HDA_CMD_VERB_GET_CONN_LIST_ENTRY, (payload))) 85 86 #define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_SHORT 1 87 #define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_LONG 2 88 89 /* Processing State */ 90 #define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03 91 #define HDA_CMD_VERB_SET_PROCESSING_STATE 0x703 92 93 #define HDA_CMD_GET_PROCESSING_STATE(cad, nid) \ 94 (HDA_CMD_12BIT((cad), (nid), \ 95 HDA_CMD_VERB_GET_PROCESSING_STATE, 0x0)) 96 #define HDA_CMD_SET_PROCESSING_STATE(cad, nid, payload) \ 97 (HDA_CMD_12BIT((cad), (nid), \ 98 HDA_CMD_VERB_SET_PROCESSING_STATE, (payload))) 99 100 #define HDA_CMD_GET_PROCESSING_STATE_STATE_OFF 0x00 101 #define HDA_CMD_GET_PROCESSING_STATE_STATE_ON 0x01 102 #define HDA_CMD_GET_PROCESSING_STATE_STATE_BENIGN 0x02 103 104 /* Coefficient Index */ 105 #define HDA_CMD_VERB_GET_COEFF_INDEX 0xd 106 #define HDA_CMD_VERB_SET_COEFF_INDEX 0x5 107 108 #define HDA_CMD_GET_COEFF_INDEX(cad, nid) \ 109 (HDA_CMD_4BIT((cad), (nid), \ 110 HDA_CMD_VERB_GET_COEFF_INDEX, 0x0)) 111 #define HDA_CMD_SET_COEFF_INDEX(cad, nid, payload) \ 112 (HDA_CMD_4BIT((cad), (nid), \ 113 HDA_CMD_VERB_SET_COEFF_INDEX, (payload))) 114 115 /* Processing Coefficient */ 116 #define HDA_CMD_VERB_GET_PROCESSING_COEFF 0xc 117 #define HDA_CMD_VERB_SET_PROCESSING_COEFF 0x4 118 119 #define HDA_CMD_GET_PROCESSING_COEFF(cad, nid) \ 120 (HDA_CMD_4BIT((cad), (nid), \ 121 HDA_CMD_VERB_GET_PROCESSING_COEFF, 0x0)) 122 #define HDA_CMD_SET_PROCESSING_COEFF(cad, nid, payload) \ 123 (HDA_CMD_4BIT((cad), (nid), \ 124 HDA_CMD_VERB_SET_PROCESSING_COEFF, (payload))) 125 126 /* Amplifier Gain/Mute */ 127 #define HDA_CMD_VERB_GET_AMP_GAIN_MUTE 0xb 128 #define HDA_CMD_VERB_SET_AMP_GAIN_MUTE 0x3 129 130 #define HDA_CMD_GET_AMP_GAIN_MUTE(cad, nid, payload) \ 131 (HDA_CMD_4BIT((cad), (nid), \ 132 HDA_CMD_VERB_GET_AMP_GAIN_MUTE, (payload))) 133 #define HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, payload) \ 134 (HDA_CMD_4BIT((cad), (nid), \ 135 HDA_CMD_VERB_SET_AMP_GAIN_MUTE, (payload))) 136 137 #define HDA_CMD_GET_AMP_GAIN_MUTE_INPUT 0x0000 138 #define HDA_CMD_GET_AMP_GAIN_MUTE_OUTPUT 0x8000 139 #define HDA_CMD_GET_AMP_GAIN_MUTE_RIGHT 0x0000 140 #define HDA_CMD_GET_AMP_GAIN_MUTE_LEFT 0x2000 141 142 #define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK 0x00000008 143 #define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT 7 144 #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK 0x00000007 145 #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT 0 146 147 #define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE(rsp) \ 148 (((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK) >> \ 149 HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT) 150 #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN(rsp) \ 151 (((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK) >> \ 152 HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT) 153 154 #define HDA_CMD_SET_AMP_GAIN_MUTE_OUTPUT 0x8000 155 #define HDA_CMD_SET_AMP_GAIN_MUTE_INPUT 0x4000 156 #define HDA_CMD_SET_AMP_GAIN_MUTE_LEFT 0x2000 157 #define HDA_CMD_SET_AMP_GAIN_MUTE_RIGHT 0x1000 158 #define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK 0x0f00 159 #define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT 8 160 #define HDA_CMD_SET_AMP_GAIN_MUTE_MUTE 0x0080 161 #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK 0x0007 162 #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT 0 163 164 #define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX(index) \ 165 (((index) << HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT) & \ 166 HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK) 167 #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN(index) \ 168 (((index) << HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT) & \ 169 HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK) 170 171 /* Converter format */ 172 #define HDA_CMD_VERB_GET_CONV_FMT 0xa 173 #define HDA_CMD_VERB_SET_CONV_FMT 0x2 174 175 #define HDA_CMD_GET_CONV_FMT(cad, nid) \ 176 (HDA_CMD_4BIT((cad), (nid), \ 177 HDA_CMD_VERB_GET_CONV_FMT, 0x0)) 178 #define HDA_CMD_SET_CONV_FMT(cad, nid, payload) \ 179 (HDA_CMD_4BIT((cad), (nid), \ 180 HDA_CMD_VERB_SET_CONV_FMT, (payload))) 181 182 /* Digital Converter Control */ 183 #define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT 0xf0d 184 #define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1 0x70d 185 #define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2 0x70e 186 187 #define HDA_CMD_GET_DIGITAL_CONV_FMT(cad, nid) \ 188 (HDA_CMD_12BIT((cad), (nid), \ 189 HDA_CMD_VERB_GET_DIGITAL_CONV_FMTT, 0x0)) 190 #define HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, nid, payload) \ 191 (HDA_CMD_12BIT((cad), (nid), \ 192 HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1, (payload))) 193 #define HDA_CMD_SET_DIGITAL_CONV_FMT2(cad, nid, payload) \ 194 (HDA_CMD_12BIT((cad), (nid), \ 195 HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2, (payload))) 196 197 #define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK 0x7f00 198 #define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT 8 199 #define HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK 0x0080 200 #define HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT 7 201 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK 0x0040 202 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT 6 203 #define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK 0x0020 204 #define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT 5 205 #define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK 0x0010 206 #define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT 4 207 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK 0x0008 208 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT 3 209 #define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK 0x0004 210 #define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT 2 211 #define HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK 0x0002 212 #define HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT 1 213 #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK 0x0001 214 #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT 0 215 216 #define HDA_CMD_GET_DIGITAL_CONV_FMT_CC(rsp) \ 217 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK) >> \ 218 HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT) 219 #define HDA_CMD_GET_DIGITAL_CONV_FMT_L(rsp) \ 220 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK) >> \ 221 HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT) 222 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO(rsp) \ 223 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK) >> \ 224 HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT) 225 #define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO(rsp) \ 226 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK) >> \ 227 HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT) 228 #define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY(rsp) \ 229 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK) >> \ 230 HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT) 231 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE(rsp) \ 232 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK) >> \ 233 HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT) 234 #define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG(rsp) \ 235 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK) >> \ 236 HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT) 237 #define HDA_CMD_GET_DIGITAL_CONV_FMT_V(rsp) \ 238 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK) >> \ 239 HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT) 240 #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN(rsp) \ 241 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK) >> \ 242 HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT) 243 244 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_L 0x80 245 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRO 0x40 246 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO 0x20 247 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_COPY 0x10 248 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRE 0x08 249 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_VCFG 0x04 250 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_V 0x02 251 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN 0x01 252 253 /* Power State */ 254 #define HDA_CMD_VERB_GET_POWER_STATE 0xf05 255 #define HDA_CMD_VERB_SET_POWER_STATE 0x705 256 257 #define HDA_CMD_GET_POWER_STATE(cad, nid) \ 258 (HDA_CMD_12BIT((cad), (nid), \ 259 HDA_CMD_VERB_GET_POWER_STATE, 0x0)) 260 #define HDA_CMD_SET_POWER_STATE(cad, nid, payload) \ 261 (HDA_CMD_12BIT((cad), (nid), \ 262 HDA_CMD_VERB_SET_POWER_STATE, (payload))) 263 264 #define HDA_CMD_POWER_STATE_D0 0x00 265 #define HDA_CMD_POWER_STATE_D1 0x01 266 #define HDA_CMD_POWER_STATE_D2 0x02 267 #define HDA_CMD_POWER_STATE_D3 0x03 268 269 #define HDA_CMD_POWER_STATE_ACT_MASK 0x000000f0 270 #define HDA_CMD_POWER_STATE_ACT_SHIFT 4 271 #define HDA_CMD_POWER_STATE_SET_MASK 0x0000000f 272 #define HDA_CMD_POWER_STATE_SET_SHIFT 0 273 274 #define HDA_CMD_GET_POWER_STATE_ACT(rsp) \ 275 (((rsp) & HDA_CMD_POWER_STATE_ACT_MASK) >> \ 276 HDA_CMD_POWER_STATE_ACT_SHIFT) 277 #define HDA_CMD_GET_POWER_STATE_SET(rsp) \ 278 (((rsp) & HDA_CMD_POWER_STATE_SET_MASK) >> \ 279 HDA_CMD_POWER_STATE_SET_SHIFT) 280 281 #define HDA_CMD_SET_POWER_STATE_ACT(ps) \ 282 (((ps) << HDA_CMD_POWER_STATE_ACT_SHIFT) & \ 283 HDA_CMD_POWER_STATE_ACT_MASK) 284 #define HDA_CMD_SET_POWER_STATE_SET(ps) \ 285 (((ps) << HDA_CMD_POWER_STATE_SET_SHIFT) & \ 286 HDA_CMD_POWER_STATE_ACT_MASK) 287 288 /* Converter Stream, Channel */ 289 #define HDA_CMD_VERB_GET_CONV_STREAM_CHAN 0xf06 290 #define HDA_CMD_VERB_SET_CONV_STREAM_CHAN 0x706 291 292 #define HDA_CMD_GET_CONV_STREAM_CHAN(cad, nid) \ 293 (HDA_CMD_12BIT((cad), (nid), \ 294 HDA_CMD_VERB_GET_CONV_STREAM_CHAN, 0x0)) 295 #define HDA_CMD_SET_CONV_STREAM_CHAN(cad, nid, payload) \ 296 (HDA_CMD_12BIT((cad), (nid), \ 297 HDA_CMD_VERB_SET_CONV_STREAM_CHAN, (payload))) 298 299 #define HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK 0x000000f0 300 #define HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT 4 301 #define HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK 0x0000000f 302 #define HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT 0 303 304 #define HDA_CMD_GET_CONV_STREAM_CHAN_STREAM(rsp) \ 305 (((rsp) & HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK) >> \ 306 HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT) 307 #define HDA_CMD_GET_CONV_STREAM_CHAN_CHAN(rsp) \ 308 (((rsp) & HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK) >> \ 309 HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT) 310 311 #define HDA_CMD_SET_CONV_STREAM_CHAN_STREAM(param) \ 312 (((param) << HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT) & \ 313 HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK) 314 #define HDA_CMD_SET_CONV_STREAM_CHAN_CHAN(param) \ 315 (((param) << HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT) & \ 316 HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK) 317 318 /* Input Converter SDI Select */ 319 #define HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT 0xf04 320 #define HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT 0x704 321 322 #define HDA_CMD_GET_INPUT_CONVERTER_SDI_SELECT(cad, nid) \ 323 (HDA_CMD_12BIT((cad), (nid), \ 324 HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT, 0x0)) 325 #define HDA_CMD_SET_INPUT_CONVERTER_SDI_SELECT(cad, nid, payload) \ 326 (HDA_CMD_12BIT((cad), (nid), \ 327 HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT, (payload))) 328 329 /* Pin Widget Control */ 330 #define HDA_CMD_VERB_GET_PIN_WIDGET_CTRL 0xf07 331 #define HDA_CMD_VERB_SET_PIN_WIDGET_CTRL 0x707 332 333 #define HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid) \ 334 (HDA_CMD_12BIT((cad), (nid), \ 335 HDA_CMD_VERB_GET_PIN_WIDGET_CTRL, 0x0)) 336 #define HDA_CMD_SET_PIN_WIDGET_CTRL(cad, nid, payload) \ 337 (HDA_CMD_12BIT((cad), (nid), \ 338 HDA_CMD_VERB_SET_PIN_WIDGET_CTRL, (payload))) 339 340 #define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK 0x00000080 341 #define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT 7 342 #define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK 0x00000040 343 #define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT 6 344 #define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK 0x00000020 345 #define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT 5 346 #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x00000007 347 #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0 348 349 #define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE(rsp) \ 350 (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK) >> \ 351 HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT) 352 #define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE(rsp) \ 353 (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK) >> \ 354 HDA_GET_CMD_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT) 355 #define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE(rsp) \ 356 (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK) >> \ 357 HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT) 358 #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE(rsp) \ 359 (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) >> \ 360 HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT) 361 362 #define HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE 0x80 363 #define HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE 0x40 364 #define HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE 0x20 365 #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x07 366 #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0 367 368 #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(param) \ 369 (((param) << HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT) & \ 370 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 371 372 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_HIZ 0 373 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 1 374 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_GROUND 2 375 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4 376 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 5 377 378 /* Unsolicited Response */ 379 #define HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE 0xf08 380 #define HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE 0x708 381 382 #define HDA_CMD_GET_UNSOLICITED_RESPONSE(cad, nid) \ 383 (HDA_CMD_12BIT((cad), (nid), \ 384 HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE, 0x0)) 385 #define HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, nid, payload) \ 386 (HDA_CMD_12BIT((cad), (nid), \ 387 HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE, (payload))) 388 389 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000080 390 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT 7 391 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK 0x0000001f 392 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT 0 393 394 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE(rsp) \ 395 (((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK) >> \ 396 HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT) 397 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG(rsp) \ 398 (((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK) >> \ 399 HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT) 400 401 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE 0x80 402 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK 0x1f 403 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT 0 404 405 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG(param) \ 406 (((param) << HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT) & \ 407 HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK) 408 409 /* Pin Sense */ 410 #define HDA_CMD_VERB_GET_PIN_SENSE 0xf09 411 #define HDA_CMD_VERB_SET_PIN_SENSE 0x709 412 413 #define HDA_CMD_GET_PIN_SENSE(cad, nid) \ 414 (HDA_CMD_12BIT((cad), (nid), \ 415 HDA_CMD_VERB_GET_PIN_SENSE, 0x0)) 416 #define HDA_CMD_SET_PIN_SENSE(cad, nid, payload) \ 417 (HDA_CMD_12BIT((cad), (nid), \ 418 HDA_CMD_VERB_SET_PIN_SENSE, (payload))) 419 420 #define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT_MASK 0x80000000 421 #define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT_SHIFT 31 422 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK 0x7fffffff 423 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT 0 424 425 #define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(rsp) \ 426 (((rsp) & HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT_MASK) >> \ 427 HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT_SHIFT) 428 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE(rsp) \ 429 (((rsp) & HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK) >> \ 430 HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT) 431 432 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_INVALID 0x7fffffff 433 434 #define HDA_CMD_SET_PIN_SENSE_LEFT_CHANNEL 0x00 435 #define HDA_CMD_SET_PIN_SENSE_RIGHT_CHANNEL 0x01 436 437 /* EAPD/BTL Enable */ 438 #define HDA_CMD_VERB_GET_EAPD_BTL_ENABLE 0xf0c 439 #define HDA_CMD_VERB_SET_EAPD_BTL_ENABLE 0x70c 440 441 #define HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid) \ 442 (HDA_CMD_12BIT((cad), (nid), \ 443 HDA_CMD_VERB_GET_EAPD_BTL_ENABLE, 0x0)) 444 #define HDA_CMD_SET_EAPD_BTL_ENABLE(cad, nid, payload) \ 445 (HDA_CMD_12BIT((cad), (nid), \ 446 HDA_CMD_VERB_SET_EAPD_BTL_ENABLE, (payload))) 447 448 #define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK 0x00000004 449 #define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT 2 450 #define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK 0x00000002 451 #define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT 1 452 #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK 0x00000001 453 #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT 0 454 455 #define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP(rsp) \ 456 (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK) >> \ 457 HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT) 458 #define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD(rsp) \ 459 (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK) >> \ 460 HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT) 461 #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL(rsp) \ 462 (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK) >> \ 463 HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT) 464 465 #define HDA_CMD_SET_EAPD_BTL_ENABLE_LR_SWAP 0x04 466 #define HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD 0x02 467 #define HDA_CMD_SET_EAPD_BTL_ENABLE_BTL 0x01 468 469 /* GPI Data */ 470 #define HDA_CMD_VERB_GET_GPI_DATA 0xf10 471 #define HDA_CMD_VERB_SET_GPI_DATA 0x710 472 473 #define HDA_CMD_GET_GPI_DATA(cad, nid) \ 474 (HDA_CMD_12BIT((cad), (nid), \ 475 HDA_CMD_VERB_GET_GPI_DATA, 0x0)) 476 #define HDA_CMD_SET_GPI_DATA(cad, nid) \ 477 (HDA_CMD_12BIT((cad), (nid), \ 478 HDA_CMD_VERB_SET_GPI_DATA, (payload))) 479 480 /* GPI Wake Enable Mask */ 481 #define HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK 0xf11 482 #define HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK 0x711 483 484 #define HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, nid) \ 485 (HDA_CMD_12BIT((cad), (nid), \ 486 HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK, 0x0)) 487 #define HDA_CMD_SET_GPI_WAKE_ENABLE_MASK(cad, nid, payload) \ 488 (HDA_CMD_12BIT((cad), (nid), \ 489 HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK, (payload))) 490 491 /* GPI Unsolicited Enable Mask */ 492 #define HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK 0xf12 493 #define HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK 0x712 494 495 #define HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid) \ 496 (HDA_CMD_12BIT((cad), (nid), \ 497 HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK, 0x0)) 498 #define HDA_CMD_SET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \ 499 (HDA_CMD_12BIT((cad), (nid), \ 500 HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK, (payload))) 501 502 /* GPI Sticky Mask */ 503 #define HDA_CMD_VERB_GET_GPI_STICKY_MASK 0xf13 504 #define HDA_CMD_VERB_SET_GPI_STICKY_MASK 0x713 505 506 #define HDA_CMD_GET_GPI_STICKY_MASK(cad, nid) \ 507 (HDA_CMD_12BIT((cad), (nid), \ 508 HDA_CMD_VERB_GET_GPI_STICKY_MASK, 0x0)) 509 #define HDA_CMD_SET_GPI_STICKY_MASK(cad, nid, payload) \ 510 (HDA_CMD_12BIT((cad), (nid), \ 511 HDA_CMD_VERB_SET_GPI_STICKY_MASK, (payload))) 512 513 /* GPO Data */ 514 #define HDA_CMD_VERB_GET_GPO_DATA 0xf14 515 #define HDA_CMD_VERB_SET_GPO_DATA 0x714 516 517 #define HDA_CMD_GET_GPO_DATA(cad, nid) \ 518 (HDA_CMD_12BIT((cad), (nid), \ 519 HDA_CMD_VERB_GET_GPO_DATA, 0x0)) 520 #define HDA_CMD_SET_GPO_DATA(cad, nid, payload) \ 521 (HDA_CMD_12BIT((cad), (nid), \ 522 HDA_CMD_VERB_SET_GPO_DATA, (payload))) 523 524 /* GPIO Data */ 525 #define HDA_CMD_VERB_GET_GPIO_DATA 0xf15 526 #define HDA_CMD_VERB_SET_GPIO_DATA 0x715 527 528 #define HDA_CMD_GET_GPIO_DATA(cad, nid) \ 529 (HDA_CMD_12BIT((cad), (nid), \ 530 HDA_CMD_VERB_GET_GPIO_DATA, 0x0)) 531 #define HDA_CMD_SET_GPIO_DATA(cad, nid, payload) \ 532 (HDA_CMD_12BIT((cad), (nid), \ 533 HDA_CMD_VERB_SET_GPIO_DATA, (payload))) 534 535 /* GPIO Enable Mask */ 536 #define HDA_CMD_VERB_GET_GPIO_ENABLE_MASK 0xf16 537 #define HDA_CMD_VERB_SET_GPIO_ENABLE_MASK 0x716 538 539 #define HDA_CMD_GET_GPIO_ENABLE_MASK(cad, nid) \ 540 (HDA_CMD_12BIT((cad), (nid), \ 541 HDA_CMD_VERB_GET_GPIO_ENABLE_MASK, 0x0)) 542 #define HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, payload) \ 543 (HDA_CMD_12BIT((cad), (nid), \ 544 HDA_CMD_VERB_SET_GPIO_ENABLE_MASK, (payload))) 545 546 /* GPIO Direction */ 547 #define HDA_CMD_VERB_GET_GPIO_DIRECTION 0xf17 548 #define HDA_CMD_VERB_SET_GPIO_DIRECTION 0x717 549 550 #define HDA_CMD_GET_GPIO_DIRECTION(cad, nid) \ 551 (HDA_CMD_12BIT((cad), (nid), \ 552 HDA_CMD_VERB_GET_GPIO_DIRECTION, 0x0)) 553 #define HDA_CMD_SET_GPIO_DIRECTION(cad, nid, payload) \ 554 (HDA_CMD_12BIT((cad), (nid), \ 555 HDA_CMD_VERB_SET_GPIO_DIRECTION, (payload))) 556 557 /* GPIO Wake Enable Mask */ 558 #define HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK 0xf18 559 #define HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK 0x718 560 561 #define HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, nid) \ 562 (HDA_CMD_12BIT((cad), (nid), \ 563 HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK, 0x0)) 564 #define HDA_CMD_SET_GPIO_WAKE_ENABLE_MASK(cad, nid, payload) \ 565 (HDA_CMD_12BIT((cad), (nid), \ 566 HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK, (payload))) 567 568 /* GPIO Unsolicited Enable Mask */ 569 #define HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK 0xf19 570 #define HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK 0x719 571 572 #define HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid) \ 573 (HDA_CMD_12BIT((cad), (nid), \ 574 HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK, 0x0)) 575 #define HDA_CMD_SET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \ 576 (HDA_CMD_12BIT((cad), (nid), \ 577 HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK, (payload))) 578 579 /* GPIO_STICKY_MASK */ 580 #define HDA_CMD_VERB_GET_GPIO_STICKY_MASK 0xf1a 581 #define HDA_CMD_VERB_SET_GPIO_STICKY_MASK 0x71a 582 583 #define HDA_CMD_GET_GPIO_STICKY_MASK(cad, nid) \ 584 (HDA_CMD_12BIT((cad), (nid), \ 585 HDA_CMD_VERB_GET_GPIO_STICKY_MASK, 0x0)) 586 #define HDA_CMD_SET_GPIO_STICKY_MASK(cad, nid, payload) \ 587 (HDA_CMD_12BIT((cad), (nid), \ 588 HDA_CMD_VERB_SET_GPIO_STICKY_MASK, (payload))) 589 590 /* Beep Generation */ 591 #define HDA_CMD_VERB_GET_BEEP_GENERATION 0xf0a 592 #define HDA_CMD_VERB_SET_BEEP_GENERATION 0x70a 593 594 #define HDA_CMD_GET_BEEP_GENERATION(cad, nid) \ 595 (HDA_CMD_12BIT((cad), (nid), \ 596 HDA_CMD_VERB_GET_BEEP_GENERATION, 0x0)) 597 #define HDA_CMD_SET_BEEP_GENERATION(cad, nid, payload) \ 598 (HDA_CMD_12BIT((cad), (nid), \ 599 HDA_CMD_VERB_SET_BEEP_GENERATION, (payload))) 600 601 /* Volume Knob */ 602 #define HDA_CMD_VERB_GET_VOLUME_KNOB 0xf0f 603 #define HDA_CMD_VERB_SET_VOLUME_KNOB 0x70f 604 605 #define HDA_CMD_GET_VOLUME_KNOB(cad, nid) \ 606 (HDA_CMD_12BIT((cad), (nid), \ 607 HDA_CMD_VERB_GET_VOLUME_KNOB, 0x0)) 608 #define HDA_CMD_SET_VOLUME_KNOB(cad, nid, payload) \ 609 (HDA_CMD_12BIT((cad), (nid), \ 610 HDA_CMD_VERB_SET_VOLUME_KNOB, (payload))) 611 612 /* Subsystem ID */ 613 #define HDA_CMD_VERB_GET_SUBSYSTEM_ID 0xf20 614 #define HDA_CMD_VERB_SET_SUSBYSTEM_ID1 0x720 615 #define HDA_CMD_VERB_SET_SUBSYSTEM_ID2 0x721 616 #define HDA_CMD_VERB_SET_SUBSYSTEM_ID3 0x722 617 #define HDA_CMD_VERB_SET_SUBSYSTEM_ID4 0x723 618 619 #define HDA_CMD_GET_SUBSYSTEM_ID(cad, nid) \ 620 (HDA_CMD_12BIT((cad), (nid), \ 621 HDA_CMD_VERB_GET_SUBSYSTEM_ID, 0x0)) 622 #define HDA_CMD_SET_SUBSYSTEM_ID1(cad, nid, payload) \ 623 (HDA_CMD_12BIT((cad), (nid), \ 624 HDA_CMD_VERB_SET_SUSBYSTEM_ID1, (payload))) 625 #define HDA_CMD_SET_SUBSYSTEM_ID2(cad, nid, payload) \ 626 (HDA_CMD_12BIT((cad), (nid), \ 627 HDA_CMD_VERB_SET_SUSBYSTEM_ID2, (payload))) 628 #define HDA_CMD_SET_SUBSYSTEM_ID3(cad, nid, payload) \ 629 (HDA_CMD_12BIT((cad), (nid), \ 630 HDA_CMD_VERB_SET_SUSBYSTEM_ID3, (payload))) 631 #define HDA_CMD_SET_SUBSYSTEM_ID4(cad, nid, payload) \ 632 (HDA_CMD_12BIT((cad), (nid), \ 633 HDA_CMD_VERB_SET_SUSBYSTEM_ID4, (payload))) 634 635 /* Configuration Default */ 636 #define HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT 0xf1c 637 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1 0x71c 638 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2 0x71d 639 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3 0x71e 640 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4 0x71f 641 642 #define HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid) \ 643 (HDA_CMD_12BIT((cad), (nid), \ 644 HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT, 0x0)) 645 #define HDA_CMD_SET_CONFIGURATION_DEFAULT1(cad, nid, payload) \ 646 (HDA_CMD_12BIT((cad), (nid), \ 647 HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1, (payload))) 648 #define HDA_CMD_SET_CONFIGURATION_DEFAULT2(cad, nid, payload) \ 649 (HDA_CMD_12BIT((cad), (nid), \ 650 HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2, (payload))) 651 #define HDA_CMD_SET_CONFIGURATION_DEFAULT3(cad, nid, payload) \ 652 (HDA_CMD_12BIT((cad), (nid), \ 653 HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3, (payload))) 654 #define HDA_CMD_SET_CONFIGURATION_DEFAULT4(cad, nid, payload) \ 655 (HDA_CMD_12BIT((cad), (nid), \ 656 HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4, (payload))) 657 658 /* Stripe Control */ 659 #define HDA_CMD_VERB_GET_STRIPE_CONTROL 0xf24 660 #define HDA_CMD_VERB_SET_STRIPE_CONTROL 0x724 661 662 #define HDA_CMD_SET_STRIPE_CONTROL(cad, nid) \ 663 (HDA_CMD_12BIT((cad), (nid), \ 664 HDA_CMD_VERB_GET_STRIPE_CONTROL, 0x0)) 665 #define HDA_CMD_GET_STRIPE_CONTROL(cad, nid, payload) \ 666 (HDA_CMD_12BIT((cad), (nid), \ 667 HDA_CMD_VERB_SET_STRIPE_CONTROL, (payload))) 668 669 /* Function Reset */ 670 #define HDA_CMD_VERB_FUNCTION_RESET 0x7ff 671 672 #define HDA_CMD_FUNCTION_RESET(cad, nid) \ 673 (HDA_CMD_12BIT((cad), (nid), \ 674 HDA_CMD_VERB_FUNCTION_RESET, 0x0)) 675 676 677 /**************************************************************************** 678 * HDA Device Parameters 679 ****************************************************************************/ 680 681 /* Vendor ID */ 682 #define HDA_PARAM_VENDOR_ID 0x00 683 684 #define HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK 0xffff0000 685 #define HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT 16 686 #define HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK 0x0000ffff 687 #define HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT 0 688 689 #define HDA_PARAM_VENDOR_ID_VENDOR_ID(param) \ 690 (((param) & HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK) >> \ 691 HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT) 692 #define HDA_PARAM_VENDOR_ID_DEVICE_ID(param) \ 693 (((param) & HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK) >> \ 694 HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT) 695 696 /* Revision ID */ 697 #define HDA_PARAM_REVISION_ID 0x02 698 699 #define HDA_PARAM_REVISION_ID_MAJREV_MASK 0x00f00000 700 #define HDA_PARAM_REVISION_ID_MAJREV_SHIFT 20 701 #define HDA_PARAM_REVISION_ID_MINREV_MASK 0x000f0000 702 #define HDA_PARAM_REVISION_ID_MINREV_SHIFT 16 703 #define HDA_PARAM_REVISION_ID_REVISION_ID_MASK 0x0000ff00 704 #define HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT 8 705 #define HDA_PARAM_REVISION_ID_STEPPING_ID_MASK 0x000000ff 706 #define HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT 0 707 708 #define HDA_PARAM_REVISION_ID_MAJREV(param) \ 709 (((param) & HDA_PARAM_REVISION_ID_MAJREV_MASK) >> \ 710 HDA_PARAM_REVISION_ID_MAJREV_SHIFT) 711 #define HDA_PARAM_REVISION_ID_MINREV(param) \ 712 (((param) & HDA_PARAM_REVISION_ID_MINREV_MASK) >> \ 713 HDA_PARAM_REVISION_ID_MINREV_SHIFT) 714 #define HDA_PARAM_REVISION_ID_REVISION_ID(param) \ 715 (((param) & HDA_PARAM_REVISION_ID_REVISION_ID_MASK) >> \ 716 HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT) 717 #define HDA_PARAM_REVISION_ID_STEPPING_ID(param) \ 718 (((param) & HDA_PARAM_REVISION_ID_STEPPING_ID_MASK) >> \ 719 HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT) 720 721 /* Subordinate Node Cound */ 722 #define HDA_PARAM_SUB_NODE_COUNT 0x04 723 724 #define HDA_PARAM_SUB_NODE_COUNT_START_MASK 0x00ff0000 725 #define HDA_PARAM_SUB_NODE_COUNT_START_SHIFT 16 726 #define HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK 0x000000ff 727 #define HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT 0 728 729 #define HDA_PARAM_SUB_NODE_COUNT_START(param) \ 730 (((param) & HDA_PARAM_SUB_NODE_COUNT_START_MASK) >> \ 731 HDA_PARAM_SUB_NODE_COUNT_START_SHIFT) 732 #define HDA_PARAM_SUB_NODE_COUNT_TOTAL(param) \ 733 (((param) & HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK) >> \ 734 HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT) 735 736 /* Function Group Type */ 737 #define HDA_PARAM_FCT_GRP_TYPE 0x05 738 739 #define HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK 0x00000100 740 #define HDA_PARAM_FCT_GRP_TYPE_UNSOL_SHIFT 8 741 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK 0x000000ff 742 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT 0 743 744 #define HDA_PARAM_FCT_GRP_TYPE_UNSOL(param) \ 745 (((param) & HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK) >> \ 746 HDA_PARAM_FCT_GROUP_TYPE_UNSOL_SHIFT) 747 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(param) \ 748 (((param) & HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK) >> \ 749 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT) 750 751 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO 0x01 752 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM 0x02 753 754 /* Audio Function Group Capabilities */ 755 #define HDA_PARAM_AUDIO_FCT_GRP_CAP 0x08 756 757 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK 0x00010000 758 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT 16 759 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK 0x00000f00 760 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT 8 761 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK 0x0000000f 762 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT 0 763 764 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN(param) \ 765 (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK) >> \ 766 HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT) 767 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY(param) \ 768 (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK) >> \ 769 HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT) 770 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY(param) \ 771 (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK) >> \ 772 HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT) 773 774 /* Audio Widget Capabilities */ 775 #define HDA_PARAM_AUDIO_WIDGET_CAP 0x09 776 777 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK 0x00f00000 778 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT 20 779 #define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK 0x000f0000 780 #define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT 16 781 #define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK 0x00000800 782 #define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT 11 783 #define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK 0x00000400 784 #define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT 10 785 #define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK 0x00000200 786 #define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT 9 787 #define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK 0x00000100 788 #define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT 8 789 #define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK 0x00000080 790 #define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT 7 791 #define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK 0x00000040 792 #define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT 6 793 #define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK 0x00000020 794 #define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT 5 795 #define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK 0x00000010 796 #define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT 4 797 #define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK 0x00000008 798 #define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT 3 799 #define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK 0x00000004 800 #define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT 2 801 #define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK 0x00000002 802 #define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT 1 803 #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK 0x00000001 804 #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT 0 805 806 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(param) \ 807 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK) >> \ 808 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT) 809 #define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY(param) \ 810 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK) >> \ 811 HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT) 812 #define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(param) \ 813 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK) >> \ 814 HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT) 815 #define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(param) \ 816 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK) >> \ 817 HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT) 818 #define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(param) \ 819 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK) >> \ 820 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT) 821 #define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST(param) \ 822 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK) >> \ 823 HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT) 824 #define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(param) \ 825 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK) >> \ 826 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT) 827 #define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(param) \ 828 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK) >> \ 829 HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT) 830 #define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(param) \ 831 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK) >> \ 832 HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT) 833 #define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(param) \ 834 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK) >> \ 835 HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT) 836 #define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(param) \ 837 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK) >> \ 838 HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT) 839 #define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(param) \ 840 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK) >> \ 841 HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT) 842 #define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(param) \ 843 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK) >> \ 844 HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT) 845 #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(param) \ 846 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \ 847 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT) 848 849 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT 0x0 850 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT 0x1 851 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 0x2 852 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR 0x3 853 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 0x4 854 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET 0x5 855 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET 0x6 856 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET 0x7 857 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET 0xf 858 859 /* Supported PCM Size, Rates */ 860 861 #define HDA_PARAM_SUPP_PCM_SIZE_RATE 0x0a 862 863 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK 0x00100000 864 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT 20 865 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK 0x00080000 866 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT 19 867 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK 0x00040000 868 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT 18 869 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK 0x00020000 870 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT 17 871 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK 0x00010000 872 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT 16 873 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK 0x00000001 874 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT 0 875 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK 0x00000002 876 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT 1 877 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK 0x00000004 878 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT 2 879 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK 0x00000008 880 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT 3 881 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK 0x00000010 882 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT 4 883 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK 0x00000020 884 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT 5 885 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK 0x00000040 886 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT 6 887 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK 0x00000080 888 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT 7 889 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK 0x00000100 890 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT 8 891 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK 0x00000200 892 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT 9 893 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK 0x00000400 894 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT 10 895 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK 0x00000800 896 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT 11 897 898 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(param) \ 899 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK) >> \ 900 HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT) 901 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(param) \ 902 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK) >> \ 903 HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT) 904 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(param) \ 905 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK) >> \ 906 HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT) 907 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(param) \ 908 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK) >> \ 909 HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT) 910 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(param) \ 911 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK) >> \ 912 HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT) 913 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(param) \ 914 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK) >> \ 915 HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT) 916 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(param) \ 917 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK) >> \ 918 HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT) 919 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(param) \ 920 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK) >> \ 921 HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT) 922 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(param) \ 923 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK) >> \ 924 HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT) 925 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(param) \ 926 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK) >> \ 927 HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT) 928 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(param) \ 929 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK) >> \ 930 HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT) 931 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(param) \ 932 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK) >> \ 933 HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT) 934 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(param) \ 935 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK) >> \ 936 HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT) 937 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(param) \ 938 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK) >> \ 939 HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT) 940 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(param) \ 941 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK) >> \ 942 HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT) 943 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(param) \ 944 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK) >> \ 945 HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT) 946 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(param) \ 947 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK) >> \ 948 HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT) 949 950 /* Supported Stream Formats */ 951 #define HDA_PARAM_SUPP_STREAM_FORMATS 0x0b 952 953 #define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK 0x00000004 954 #define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT 2 955 #define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK 0x00000002 956 #define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT 1 957 #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK 0x00000001 958 #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT 0 959 960 #define HDA_PARAM_SUPP_STREAM_FORMATS_AC3(param) \ 961 (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK) >> \ 962 HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT) 963 #define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(param) \ 964 (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK) >> \ 965 HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT) 966 #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM(param) \ 967 (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK) >> \ 968 HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT) 969 970 /* Pin Capabilities */ 971 #define HDA_PARAM_PIN_CAP 0x0c 972 973 #define HDA_PARAM_PIN_CAP_EAPD_CAP_MASK 0x00010000 974 #define HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT 16 975 #define HDA_PARAM_PIN_CAP_VREF_CTRL_MASK 0x0000ff00 976 #define HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT 8 977 #define HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK 0x00002000 978 #define HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT 13 979 #define HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK 0x00001000 980 #define HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT 12 981 #define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK 0x00000400 982 #define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT 10 983 #define HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK 0x00000200 984 #define HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT 9 985 #define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK 0x00000100 986 #define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT 8 987 #define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK 0x00000040 988 #define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT 6 989 #define HDA_PARAM_PIN_CAP_INPUT_CAP_MASK 0x00000020 990 #define HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT 5 991 #define HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK 0x00000010 992 #define HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT 4 993 #define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK 0x00000008 994 #define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT 3 995 #define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK 0x00000004 996 #define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT 2 997 #define HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK 0x00000002 998 #define HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT 1 999 #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK 0x00000001 1000 #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT 0 1001 1002 #define HDA_PARAM_PIN_CAP_EAPD_CAP(param) \ 1003 (((param) & HDA_PARAM_PIN_CAP_EAPD_CAP_MASK) >> \ 1004 HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT) 1005 #define HDA_PARAM_PIN_CAP_VREF_CTRL(param) \ 1006 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_MASK) >> \ 1007 HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT) 1008 #define HDA_PARAM_PIN_CAP_VREF_CTRL_100(param) \ 1009 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK) >> \ 1010 HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT) 1011 #define HDA_PARAM_PIN_CAP_VREF_CTRL_80(param) \ 1012 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK) >> \ 1013 HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT) 1014 #define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(param) \ 1015 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK) >> \ 1016 HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT) 1017 #define HDA_PARAM_PIN_CAP_VREF_CTRL_50(param) \ 1018 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK) >> \ 1019 HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT) 1020 #define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(param) \ 1021 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK) >> \ 1022 HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT) 1023 #define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(param) \ 1024 (((param) & HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK) >> \ 1025 HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT) 1026 #define HDA_PARAM_PIN_CAP_INPUT_CAP(param) \ 1027 (((param) & HDA_PARAM_PIN_CAP_INPUT_CAP_MASK) >> \ 1028 HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT) 1029 #define HDA_PARAM_PIN_CAP_OUTPUT_CAP(param) \ 1030 (((param) & HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK) >> \ 1031 HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT) 1032 #define HDA_PARAM_PIN_CAP_HEADPHONE_CAP(param) \ 1033 (((param) & HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK) >> \ 1034 HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT) 1035 #define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(param) \ 1036 (((param) & HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK) >> \ 1037 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK) 1038 #define HDA_PARAM_PIN_CAP_TRIGGER_REQD(param) \ 1039 (((param) & HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK) >> \ 1040 HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT) 1041 #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(param) \ 1042 (((param) & HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK) >> \ 1043 HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT) 1044 1045 /* Input Amplifier Capabilities */ 1046 #define HDA_PARAM_INPUT_AMP_CAP 0x0d 1047 1048 #define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000 1049 #define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT 31 1050 #define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000 1051 #define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT 16 1052 #define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00 1053 #define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT 8 1054 #define HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK 0x0000007f 1055 #define HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT 0 1056 1057 #define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(param) \ 1058 (((param) & HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK) >> \ 1059 HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT) 1060 #define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(param) \ 1061 (((param) & HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK) >> \ 1062 HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT) 1063 #define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(param) \ 1064 (((param) & HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK) >> \ 1065 HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT) 1066 #define HDA_PARAM_INPUT_AMP_CAP_OFFSET(param) \ 1067 (((param) & HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK) >> \ 1068 HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT) 1069 1070 /* Output Amplifier Capabilities */ 1071 #define HDA_PARAM_OUTPUT_AMP_CAP 0x12 1072 1073 #define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000 1074 #define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT 31 1075 #define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000 1076 #define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT 16 1077 #define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00 1078 #define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT 8 1079 #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK 0x0000007f 1080 #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT 0 1081 1082 #define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(param) \ 1083 (((param) & HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK) >> \ 1084 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT) 1085 #define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(param) \ 1086 (((param) & HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK) >> \ 1087 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT) 1088 #define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(param) \ 1089 (((param) & HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK) >> \ 1090 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT) 1091 #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(param) \ 1092 (((param) & HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK) >> \ 1093 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT) 1094 1095 /* Connection List Length */ 1096 #define HDA_PARAM_CONN_LIST_LENGTH 0x0e 1097 1098 #define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK 0x00000080 1099 #define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT 7 1100 #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK 0x0000007f 1101 #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT 0 1102 1103 #define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(param) \ 1104 (((param) & HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK) >> \ 1105 HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT) 1106 #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(param) \ 1107 (((param) & HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK) >> \ 1108 HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT) 1109 1110 /* Supported Power States */ 1111 #define HDA_PARAM_SUPP_POWER_STATES 0x0f 1112 1113 #define HDA_PARAM_SUPP_POWER_STATES_D3_MASK 0x00000008 1114 #define HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT 3 1115 #define HDA_PARAM_SUPP_POWER_STATES_D2_MASK 0x00000004 1116 #define HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT 2 1117 #define HDA_PARAM_SUPP_POWER_STATES_D1_MASK 0x00000002 1118 #define HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT 1 1119 #define HDA_PARAM_SUPP_POWER_STATES_D0_MASK 0x00000001 1120 #define HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT 0 1121 1122 #define HDA_PARAM_SUPP_POWER_STATES_D3(param) \ 1123 (((param) & HDA_PARAM_SUPP_POWER_STATES_D3_MASK) >> \ 1124 HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT) 1125 #define HDA_PARAM_SUPP_POWER_STATES_D2(param) \ 1126 (((param) & HDA_PARAM_SUPP_POWER_STATES_D2_MASK) >> \ 1127 HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT) 1128 #define HDA_PARAM_SUPP_POWER_STATES_D1(param) \ 1129 (((param) & HDA_PARAM_SUPP_POWER_STATES_D1_MASK) >> \ 1130 HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT) 1131 #define HDA_PARAM_SUPP_POWER_STATES_D0(param) \ 1132 (((param) & HDA_PARAM_SUPP_POWER_STATES_D0_MASK) >> \ 1133 HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT) 1134 1135 /* Processing Capabilities */ 1136 #define HDA_PARAM_PROCESSING_CAP 0x10 1137 1138 #define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK 0x0000ff00 1139 #define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT 8 1140 #define HDA_PARAM_PROCESSING_CAP_BENIGN_MASK 0x00000001 1141 #define HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT 0 1142 1143 #define HDA_PARAM_PROCESSING_CAP_NUMCOEFF(param) \ 1144 (((param) & HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK) >> \ 1145 HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT) 1146 #define HDA_PARAM_PROCESSING_CAP_BENIGN(param) \ 1147 (((param) & HDA_PARAM_PROCESSING_CAP_BENIGN_MASK) >> \ 1148 HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT) 1149 1150 /* GPIO Count */ 1151 #define HDA_PARAM_GPIO_COUNT 0x11 1152 1153 #define HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK 0x80000000 1154 #define HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT 31 1155 #define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK 0x40000000 1156 #define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT 30 1157 #define HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK 0x00ff0000 1158 #define HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT 16 1159 #define HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK 0x0000ff00 1160 #define HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT 8 1161 #define HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK 0x000000ff 1162 #define HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT 0 1163 1164 #define HDA_PARAM_GPIO_COUNT_GPI_WAKE(param) \ 1165 (((param) & HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK) >> \ 1166 HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT) 1167 #define HDA_PARAM_GPIO_COUNT_GPI_UNSOL(param) \ 1168 (((param) & HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK) >> \ 1169 HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT) 1170 #define HDA_PARAM_GPIO_COUNT_NUM_GPI(param) \ 1171 (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK) >> \ 1172 HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT) 1173 #define HDA_PARAM_GPIO_COUNT_NUM_GPO(param) \ 1174 (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK) >> \ 1175 HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT) 1176 #define HDA_PARAM_GPIO_COUNT_NUM_GPIO(param) \ 1177 (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK) >> \ 1178 HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT) 1179 1180 /* Volume Knob Capabilities */ 1181 #define HDA_PARAM_VOLUME_KNOB_CAP 0x13 1182 1183 #define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK 0x00000080 1184 #define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT 7 1185 #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK 0x0000007f 1186 #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT 0 1187 1188 #define HDA_PARAM_VOLUME_KNOB_CAP_DELTA(param) \ 1189 (((param) & HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK) >> \ 1190 HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT) 1191 #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS(param) \ 1192 (((param) & HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK) >> \ 1193 HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT) 1194 1195 1196 #define HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK 0x00000000f 1197 #define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK 0x0000000f0 1198 #define HDA_CONFIG_DEFAULTCONF_MISC_MASK 0x000000f00 1199 #define HDA_CONFIG_DEFAULTCONF_COLOR_MASK 0x00000f000 1200 #define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK 0x000f00000 1201 #define HDA_CONFIG_DEFAULTCONF_DEVICE_MASK 0x000f00000 1202 #define HDA_CONFIG_DEFAULTCONF_LOCATION_MASK 0x03f000000 1203 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK 0x0c0000000 1204 1205 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK (0<<30) 1206 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE (1<<30) 1207 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED (2<<30) 1208 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH (3<<30) 1209 1210 #define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT (0<<20) 1211 #define HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER (1<<20) 1212 #define HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT (2<<20) 1213 #define HDA_CONFIG_DEFAULTCONF_DEVICE_CD (3<<20) 1214 #define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT (4<<20) 1215 #define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT (5<<20) 1216 #define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE (6<<20) 1217 #define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET (7<<20) 1218 #define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN (8<<20) 1219 #define HDA_CONFIG_DEFAULTCONF_DEVICE_AUX (9<<20) 1220 #define HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN (10<<20) 1221 #define HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY (11<<20) 1222 #define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN (12<<20) 1223 #define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN (13<<20) 1224 #define HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER (15<<20) 1225 1226 #endif 1227