1 /*- 2 * Copyright (c) 1998 Joachim Kuebart <joachim.kuebart@gmx.net> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * $FreeBSD$ 15 */ 16 17 /* This supports the ENSONIQ AudioPCI board based on the ES1370. */ 18 19 #ifndef _ES1370_REG_H 20 #define _ES1370_REG_H 21 22 #define ES1370_REG_CONTROL 0x00 23 #define ES1370_REG_STATUS 0x04 24 #define ES1370_REG_UART_DATA 0x08 25 #define ES1370_REG_UART_STATUS 0x09 26 #define ES1370_REG_UART_CONTROL 0x09 27 #define ES1370_REG_UART_TEST 0x0a 28 #define ES1370_REG_MEMPAGE 0x0c 29 #define ES1370_REG_CODEC 0x10 30 #define CODEC_INDEX_SHIFT 8 31 #define ES1370_REG_SERIAL_CONTROL 0x20 32 #define ES1370_REG_DAC1_SCOUNT 0x24 33 #define ES1370_REG_DAC2_SCOUNT 0x28 34 #define ES1370_REG_ADC_SCOUNT 0x2c 35 36 #define ES1370_REG_DAC1_FRAMEADR 0xc30 37 #define ES1370_REG_DAC1_FRAMECNT 0xc34 38 #define ES1370_REG_DAC2_FRAMEADR 0xc38 39 #define ES1370_REG_DAC2_FRAMECNT 0xc3c 40 #define ES1370_REG_ADC_FRAMEADR 0xd30 41 #define ES1370_REG_ADC_FRAMECNT 0xd34 42 43 #define DAC2_SRTODIV(x) (((1411200 + (x) / 2) / (x) - 2) & 0x1fff) 44 #define DAC2_DIVTOSR(x) (1411200 / ((x) + 2)) 45 46 #define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */ 47 #define CTRL_XCTL1 0x40000000 /* SERR pin if enabled */ 48 #define CTRL_OPEN 0x20000000 /* no function, can be read and 49 * written */ 50 #define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */ 51 #define CTRL_SH_PCLKDIV 16 52 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 53 * = I2S */ 54 #define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */ 55 #define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025, 56 * 2=22050, 3=44100 */ 57 #define CTRL_SH_WTSRSEL 12 58 #define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */ 59 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */ 60 #define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 = 61 * MPEG */ 62 #define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */ 63 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */ 64 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */ 65 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */ 66 #define CTRL_ADC_EN 0x00000010 /* enable ADC */ 67 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */ 68 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably 69 * at address 0x200) */ 70 #define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */ 71 #define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */ 72 73 #define SCTRL_P2ENDINC 0x00380000 /* */ 74 #define SCTRL_SH_P2ENDINC 19 75 #define SCTRL_P2STINC 0x00070000 /* */ 76 #define SCTRL_SH_P2STINC 16 77 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */ 78 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */ 79 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */ 80 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */ 81 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */ 82 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */ 83 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */ 84 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */ 85 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for 86 * DAC1 */ 87 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample 88 * when disabled */ 89 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */ 90 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */ 91 #define SCTRL_R1FMT 0x00000030 /* format mask */ 92 #define SCTRL_SH_R1FMT 4 93 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */ 94 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */ 95 #define SCTRL_P2FMT 0x0000000c /* format mask */ 96 #define SCTRL_SH_P2FMT 2 97 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */ 98 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */ 99 #define SCTRL_P1FMT 0x00000003 /* format mask */ 100 #define SCTRL_SH_P1FMT 0 101 102 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */ 103 #define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in 104 * progress */ 105 #define STAT_CBUSY 0x00000200 /* 1 = codec busy */ 106 #define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */ 107 #define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 108 * 2=ADC, 3=undef */ 109 #define STAT_SH_VC 5 110 #define STAT_MCCB 0x00000010 /* CCB int pending */ 111 #define STAT_UART 0x00000008 /* UART int pending */ 112 #define STAT_DAC1 0x00000004 /* DAC1 int pending */ 113 #define STAT_DAC2 0x00000002 /* DAC2 int pending */ 114 #define STAT_ADC 0x00000001 /* ADC int pending */ 115 116 #define CODEC_OMIX1 0x10 117 #define CODEC_OMIX2 0x11 118 #define CODEC_LIMIX1 0x12 119 #define CODEC_RIMIX1 0x13 120 #define CODEC_LIMIX2 0x14 121 #define CODEC_RIMIX2 0x15 122 #define CODEC_RES_PD 0x16 123 #define CODEC_CSEL 0x17 124 #define CODEC_ADSEL 0x18 125 #define CODEC_MGAIN 0x19 126 127 /* ES1371 specific */ 128 129 #define CODEC_ID_SESHIFT 10 130 #define CODEC_ID_SEMASK 0x1f 131 132 #define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */ 133 #define CODEC_PIADD_MASK 0x007f0000 134 #define CODEC_PIADD_SHIFT 16 135 #define CODEC_PIDAT_MASK 0x0000ffff 136 #define CODEC_PIDAT_SHIFT 0 137 138 #define CODEC_PORD 0x00800000 /* 0 = write AC97 register */ 139 #define CODEC_POADD_MASK 0x007f0000 140 #define CODEC_POADD_SHIFT 16 141 #define CODEC_PODAT_MASK 0x0000ffff 142 #define CODEC_PODAT_SHIFT 0 143 144 #define CODEC_RDY 0x80000000 /* AC97 read data valid */ 145 #define CODEC_WIP 0x40000000 /* AC97 write in progress */ 146 147 #define ES1370_REG_CONTROL 0x00 148 #define ES1370_REG_SERIAL_CONTROL 0x20 149 #define ES1371_REG_CODEC 0x14 150 #define ES1371_REG_LEGACY 0x18 /* W/R: Legacy control/status register */ 151 #define ES1371_REG_SMPRATE 0x10 /* W/R: Codec rate converter interface register */ 152 153 #define ES1371_SYNC_RES (1<<14) /* Warm AC97 reset */ 154 #define ES1371_DIS_R1 (1<<19) /* record channel accumulator update disable */ 155 #define ES1371_DIS_P2 (1<<20) /* playback channel 2 accumulator update disable */ 156 #define ES1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */ 157 #define ES1371_DIS_SRC (1<<22) /* sample rate converter disable */ 158 #define ES1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */ 159 #define ES1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */ 160 #define ES1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25) /* address of the sample rate converter */ 161 #define ES1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0) /* current value of the sample rate converter */ 162 #define ES1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff) /* current value of the sample rate converter */ 163 164 /* 165 * S/PDIF specific 166 */ 167 168 /* Use ES1370_REG_CONTROL */ 169 #define RECEN_B 0x08000000 /* Used to control mixing of analog with digital data */ 170 #define SPDIFEN_B 0x04000000 /* Reset to switch digital output mux to "THRU" mode */ 171 /* Use ES1370_REG_STATUS */ 172 #define ENABLE_SPDIF 0x00040000 /* Used to enable the S/PDIF circuitry */ 173 #define TEST_SPDIF 0x00020000 /* Used to put the S/PDIF module in "test mode" */ 174 175 /* 176 * Sample rate converter addresses 177 */ 178 179 #define ES_SMPREG_DAC1 0x70 180 #define ES_SMPREG_DAC2 0x74 181 #define ES_SMPREG_ADC 0x78 182 #define ES_SMPREG_TRUNC_N 0x00 183 #define ES_SMPREG_INT_REGS 0x01 184 #define ES_SMPREG_VFREQ_FRAC 0x03 185 #define ES_SMPREG_VOL_ADC 0x6c 186 #define ES_SMPREG_VOL_DAC1 0x7c 187 #define ES_SMPREG_VOL_DAC2 0x7e 188 189 #endif 190